TWI880417B - Wiring board and method of manufacturing the same - Google Patents

Abstract

A wiring board includes an insulation layer and an embedded wiring layer. The insulation layer has a surface and a plurality of recesses formed in the surface. The embedded wiring layer embedded in the recesses includes a plurality of seed layers and a primary pattern layer. The seed layers are disposed individually in the recesses and directly touch the insulation layer. The primary pattern layer has a first surface, a second surface opposite to the first surface, a plurality of side surfaces located between the first surface and the second surface. The seed layers cover the first surface and the side surfaces, but do not cover the second surface. The primary pattern layer does not touch the insulation layer.

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a manufacturing method thereof, and in particular to a circuit board including an embedded wiring layer and a manufacturing method thereof.

Currently, there are circuit boards with embedded circuit layers, and the manufacturing method of such circuit boards generally includes the following steps. First, a circuit layer is formed, which is generally formed using a semi-additive process, wherein the step of forming the circuit layer includes an electroplating process. Afterwards, an insulating layer is pressed on the circuit layer so that the circuit layer is buried and embedded in the insulating layer, thereby forming an embedded circuit layer. However, due to the limitations of the electroplating process, the thickness uniformity of the above-mentioned circuit layer is difficult to further improve, so that the thickness difference of the existing embedded circuit layer, that is, the difference between the maximum thickness and the minimum thickness, is greater than 2 microns, which is not conducive to the development of fine circuits in current circuit boards.

At least one embodiment of the present invention provides a circuit board including an embedded circuit layer. Compared with the existing embedded circuit layer, the embedded circuit layer of at least one embodiment of the present invention has better thickness uniformity.

At least one embodiment of the present invention provides a method for manufacturing the above-mentioned circuit board.

The circuit board proposed in at least one embodiment of the present invention includes an insulating layer and an embedded circuit layer. The insulating layer has a surface and a plurality of grooves formed on the surface. The embedded circuit layer is buried in these grooves and includes a plurality of seed layers and a main pattern layer. These seed layers are respectively arranged in these grooves and directly contact the insulating layer. The main pattern layer has a first surface, a second surface opposite to the first surface, and a plurality of side surfaces between the first surface and the second surface. The seed layer covers the first surface and these side surfaces, but does not cover the second surface. The main pattern layer does not contact the insulating layer.

In at least one embodiment of the present invention, the thickness difference of the buried circuit layer is less than or equal to 1 micron.

In at least one embodiment of the present invention, the embedded circuit layer includes a plurality of traces and a plurality of pads, and the traces and the pads are exposed on the surface of the insulating layer.

In at least one embodiment of the present invention, the second surface of the main pattern layer is aligned with the surface of the insulating layer.

The manufacturing method of the circuit board proposed in at least one embodiment of the present invention includes forming a relief pattern layer on a carrier substrate. Then, an insulating layer is pressed on the carrier substrate, wherein the insulating layer covers the relief pattern layer, and the relief pattern layer is buried in the insulating layer. After pressing the insulating layer, the carrier substrate is removed to expose the relief pattern layer, wherein the relief pattern layer is exposed on the surface of the insulating layer. After removing the carrier substrate, the relief pattern layer is removed and the insulating layer is retained to form a plurality of grooves on the surface of the insulating layer. Then, an initial seed layer is formed on the insulating layer, wherein the initial seed layer covers the surface of the insulating layer and the grooves, but does not fill each of the grooves. Then, the initial seed layer is electroplated to form a metal layer on the surface and in the grooves, wherein the metal layer and the initial seed layer fill the grooves. Then, a portion of the metal layer and a portion of the initial seed layer outside the grooves are removed to expose the surface of the insulating layer.

In at least one embodiment of the present invention, the step of forming a relief pattern layer on a carrier substrate includes exposure and development.

In at least one embodiment of the present invention, the embossed pattern layer is removed using a photoresist.

In at least one embodiment of the present invention, the carrier substrate includes a main substrate and a metal foil formed on the main substrate, and the metal foil is bonded to the insulating layer. The step of removing the carrier substrate includes separating the metal foil from the main substrate to remove the main substrate. After removing the main substrate, the metal foil is etched.

In at least one embodiment of the present invention, the method of removing the portion of the metal layer and the portion of the initial seed layer outside the grooves comprises etching or grinding.

In at least one embodiment of the present invention, the step of pressing the insulating layer on the carrier substrate includes pressing a resin sheet on the carrier substrate.

Based on the above, compared with the circuit layer formed by the existing electroplating process, the embedded circuit layer disclosed in at least one embodiment of the present invention has better thickness uniformity, so that the circuit board disclosed in at least one embodiment of the present invention is conducive to the development of fine circuits.

In the following text, in order to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions, etc.) in the drawings will be enlarged in unequal proportions. Therefore, the description and explanation of the embodiments below are not limited to the dimensions and shapes presented by the elements in the drawings, but should cover the dimensions, shapes, and deviations therefrom caused by actual processes and/or tolerances. For example, the flat surface shown in the drawings may have rough and/or nonlinear features, and the sharp corners shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration, and are not intended to accurately depict the actual shapes of the elements, nor are they intended to limit the scope of the patent application of the present invention.

Secondly, the words "approximately", "approximately" or "substantially" used in the present case not only cover the numerical values and numerical ranges clearly recorded, but also cover the permissible deviation range that can be understood by a person of ordinary skill in the technical field to which the invention belongs, wherein the deviation range can be determined by the error generated during measurement, and such error is caused by the limitation of the measurement system or process conditions, for example. For example, two objects (such as the planes or traces of a substrate) are "substantially parallel" or "substantially perpendicular", wherein "substantially parallel" and "substantially perpendicular" respectively mean that the parallelism and perpendicularity between the two objects may include non-parallelism and non-perpendicularity caused by the permissible deviation range.

In addition, "approximately" may mean within one or more standard deviations of the above values, such as ±30%, ±20%, ±10% or ±5%. In this text, the words "approximately", "approximately" or "substantially" may be used to select acceptable deviation ranges or standard deviations according to the optical properties, etching properties, mechanical properties or other properties, and do not apply a single standard deviation to all the above optical properties, etching properties, mechanical properties and other properties.

FIG1 is a schematic cross-sectional view of a circuit board of at least one embodiment of the present invention. Referring to FIG1 , the circuit board 100 includes an insulating layer 110 and an embedded circuit layer 120, wherein the embedded circuit layer 120 is embedded in the insulating layer 110, and the insulating layer 110 exposes a portion of the embedded circuit layer 120. Taking FIG1 as an example, the insulating layer 110 has a surface 111 and a plurality of grooves R11 formed on the surface 111, wherein the surface 111 may be the lower surface of the insulating layer 110. The embedded circuit layer 120 is embedded in these grooves R11 and exposed on the surface 111 of the insulating layer 110.

The embedded circuit layer 120 includes a main pattern layer 121 and a plurality of seed layers 122, wherein the seed layers 122 are respectively disposed in the grooves R11 and directly contact the insulating layer 110. The seed layers 122 cover all surfaces of the grooves R11. In other words, the seed layers 122 cover the bottom surface and side walls of the grooves R11. Although the seed layers 122 are disposed in the grooves R11, each seed layer 122 does not fill any groove R11. Therefore, each seed layer 122 only occupies a portion of the space of one of the grooves R11 , and the main pattern layer 121 fills the remaining space of the groove R11 not occupied by the seed layer 122 .

In other words, the main pattern layer 121 and the seed layers 122 will fill the grooves R11, wherein the seed layers 122 can conformally cover all surfaces of the grooves R11. In other words, each seed layer 122 can extend along the surface of the groove R11 and form a groove (not shown) similar in shape to the groove R11, so as to be accommodated and filled by the main pattern layer 121, as shown in FIG. 1 .

The main pattern layer 121 can be a metal pattern layer, and can be made of a metal material with good conductivity such as copper, silver, gold, aluminum or aluminum-copper alloy. The main pattern layer 121 has a first surface 121a, a second surface 121b relative to the first surface 121a, and a plurality of side surfaces 121c located between the first surface 121a and the second surface 121b. The main pattern layer 121 can be a discontinuous film layer, so the first surface 121a and the second surface 121b can also be discontinuous surfaces. Specifically, the embedded circuit layer 120 includes a plurality of traces T12 and a plurality of pads P12, wherein these traces T12 and these pads P12 are exposed on the surface 111 of the insulating layer 110. At least two of the traces T12 and the pads P12 do not contact each other at all, so that the first surface 121a and the second surface 121b are discontinuous surfaces.

Since the seed layer 122 covers all surfaces of the groove R11, namely the bottom surface and the side walls of the groove R11, the seed layers 122 cover the first surface 121a and the side surfaces 121c of the main pattern layer 121 so that the main pattern layer 121 does not contact the insulating layer 110. In other words, the seed layers 122 separate the main pattern layer 121 from the insulating layer 110. In addition, although the seed layer 122 covers the first surface 121a and the side surfaces 121c, it does not cover the second surface 121b, so the second surface 121b is exposed to the surface 111 of the insulating layer 110, wherein the second surface 121b of the main pattern layer 121 can be aligned with the surface 111 of the insulating layer 110.

FIG. 2A to FIG. 2G are schematic cross-sectional views of the process of the circuit board in FIG. 1. Referring to FIG. 2A and FIG. 2B, a relief pattern layer MP2 is formed on a carrier substrate 20, wherein the relief pattern layer MP2 is depicted in FIG. 2B. Specifically, referring to FIG. 2A, first, a carrier substrate 20 is provided, wherein the carrier substrate 20 includes a main substrate 21 and a metal foil 22 formed on the main substrate 21, and the metal foil 22 can be an aluminum foil or a copper foil. Thereafter, a photoresist layer PS2 is formed on the carrier substrate 20, wherein the photoresist layer PS2 can be a dry film or a wet film.

The main substrate 21 includes a film layer 212 and a support layer 211, wherein the film layer 212 is disposed and fixed on the support layer 211. The support layer 211 may be an insulating layer, which may include resin and glass fiber, so that the support layer 211 can adhere to the film layer 212. In addition, the support layer 211 may also be a ceramic plate or a glass plate. The film layer 212 may be a metal layer, such as a copper metal layer or an aluminum metal layer, so that the film layer 212 and the metal foil 22 may be made of the same metal material (such as copper or aluminum). The metal foil 22 is disposed on the film layer 212 , and the film layer 212 is located between the metal foil 22 and the support layer 211 , wherein the metal foil 22 can be temporarily fixed on the film layer 212 and can be peeled off from the film layer 212 to separate the metal foil 22 from the main substrate 21 .

Referring to FIG. 2A and FIG. 2B , the photoresist layer PS2 is then patterned, that is, the photoresist layer PS2 is exposed and developed to form a relief pattern layer MP2 on the metal foil 22 of the carrier substrate 20. Therefore, the step of forming the relief pattern layer MP2 on the carrier substrate 20 includes exposure and development. The relief pattern layer MP2 can directly contact the metal foil 22 and partially cover the metal foil 22, so that the relief pattern layer MP2 has a plurality of openings H2 partially exposing the metal foil 22, wherein at least one opening H2 can be a trench.

Referring to FIG. 2C , an insulating layer 110 is then pressed onto the carrier substrate 20, wherein the insulating layer 110 covers the metal foil 22 and the embossed pattern layer MP2. The step of pressing the insulating layer 110 onto the carrier substrate 20 may include pressing a resin sheet (prepreg) onto the carrier substrate 20. In other words, the insulating layer 110 may be formed of a resin sheet and may directly contact the metal foil 22 and the embossed pattern layer MP2, so the insulating layer 110 will adhere to the metal foil 22 and the embossed pattern layer MP2, that is, the metal foil 22 is adhered to the insulating layer 110. Except for the surface of the embossed pattern layer MP2 contacting the metal foil 22 which is not covered by the insulating layer 110, the other surfaces of the embossed pattern layer MP2 are covered by the insulating layer 110. Secondly, the insulating layer 110 fills up the openings H2. Therefore, the embossed pattern layer MP2 is buried in the insulating layer 110.

Please refer to FIG. 2C and FIG. 2D. After the insulating layer 110 is pressed, the carrier substrate 20 is removed to expose the relief pattern layer MP2, wherein the relief pattern layer MP2 is exposed on the surface 111 of the insulating layer 110. The method for removing the carrier substrate 20 may include the following steps. The metal foil 22 is separated from the main substrate 21 to remove the main substrate 21. Since the metal foil 22 can be peeled off from the film layer 212 of the main substrate 21, the metal foil 22 and the main substrate 21 can be separated by peeling to remove the main substrate 21. After removing the main substrate 21, the metal foil 22 is etched. Since the metal foil 22 is bonded to the insulating layer 110, the metal foil 22 is suitable for being removed by etching.

Please refer to FIG. 2D and FIG. 2E. After removing the carrier substrate 20, the relief pattern layer MP2 is removed, and the insulating layer 110 is retained to form a plurality of grooves R11 on the surface 111 of the insulating layer 110. Since the relief pattern layer MP2 is formed by the photoresist layer PS2 after exposure and development, the relief pattern layer MP2 can be removed by removing the photoresist. In addition, from FIG. 2D and FIG. 2E, the thickness PT2 of the relief pattern layer MP2 is equivalent to the depth of these grooves R11, so the depth of these grooves R11 can be determined by the thickness PT2 of the relief pattern layer MP2.

Referring to FIG. 2F , an initial seed layer 122i is then formed on the insulating layer 110, wherein the initial seed layer 122i covers the surface 111 of the insulating layer 110 and the grooves R11, but does not fill each groove R11. The initial seed layer 122i may be a metal layer and may be formed by deposition. For example, the initial seed layer 122i may be formed by electroless plating or physical vapor deposition (PVD), and may be a copper metal layer.

Referring to FIG. 2G , the initial seed layer 122i is then electroplated to form a metal layer 121i on the surface 111 of the insulating layer 110 and in the grooves R11, so that the metal layer 121i and the initial seed layer 122i fill the grooves R11, as shown in FIG. 2G . In addition, the metal layer 121i can be a copper metal layer, so the initial seed layer 122i and the metal layer 121i can be made of the same metal material.

Referring to FIG. 1 and FIG. 2G , the portion of the metal layer 121i and the portion of the initial seed layer 122i outside the grooves R11 are then removed to expose the surface 111 of the insulating layer 110, and the remaining initial seed layer 122i and the remaining metal layer 121i in the grooves are retained to form a plurality of seed layers 122 and a main pattern layer 121, respectively, as shown in FIG. 1 . At this point, the circuit board 100 including the buried circuit layer 120 is substantially completed. The method of removing the portion of the metal layer 121i and the portion of the initial seed layer 122i outside the grooves R11 may include etching or grinding. When grinding is used to remove a portion of the metal layer 121i and a portion of the initial seed layer 122i, the second surface 121b of the main pattern layer 121 can be aligned with the surface 111 of the insulating layer 110.

From FIG. 1 and FIG. 2G , the thickness of the embedded circuit layer 120 is equivalent to the depth of the groove R11, and the depth of the groove R11 can be determined by the thickness PT2 of the embossed pattern layer MP2 (see FIG. 2D ). Therefore, the thickness of the embedded circuit layer 120 can be determined by the thickness PT2 of the embossed pattern layer MP2. Since the embossed pattern layer MP2 is formed by the photoresist layer PS2 (such as a dry film or a wet film) after exposure and development, the embossed pattern layer MP2 has better thickness uniformity than the circuit layer formed by the electroplating process, so that the thickness difference of the embedded circuit layer 120 can be less than 2 microns. The relief pattern layer MP2 formed by using a dry film has better thickness uniformity, so that the thickness difference of the embedded circuit layer 120 can be less than or equal to 1 micron. It should be noted that the aforementioned "thickness difference" refers to the difference between the maximum and minimum values of the thickness 120t of the embedded circuit layer 120.

In summary, compared with the circuit layer formed by the existing electroplating process, the embedded circuit layer disclosed in at least one embodiment of the present invention has better thickness uniformity, so that the circuit board disclosed in at least one embodiment of the present invention is conducive to the development of fine circuits, thereby meeting the development trend of existing electronic devices, such as mobile phones, tablets and computers, towards small size and thinness.

Although the present invention has been disclosed as above by way of embodiments, they are not intended to limit the present invention. A person having ordinary knowledge in the technical field to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

20: Carrier substrate

21: Main substrate

22: Metal foil

100: Circuit board

110: Insulation layer

111: Surface

120: Embedded circuit layer

120t, PT2: thickness

121: Main pattern layer

121a: first surface

121b: Second surface

121c: Side surface

121i:Metal layer

122: Seed layer

122i: Initial seed layer

211: Support layer

212: Membrane layer

H2: Opening

MP2: Embossed pattern layer

R11: Groove

T12: Routing

P12: pad

PS2: Photoresist layer

FIG. 1 is a schematic cross-sectional view of a circuit board of at least one embodiment of the present invention. FIG. 2A to FIG. 2G are schematic cross-sectional views of the process of the circuit board in FIG. 1 .

100: Circuit board

110: Insulation layer

111: Surface

120: Embedded circuit layer

120t:Thickness

121: Main pattern layer

121a: first surface

121b: Second surface

121c: Side surface

122: Seed layer

R11: Groove

T12: Routing

P12: pad

Claims (6)

A method for manufacturing a circuit board comprises: forming a relief pattern layer on a carrier substrate; pressing an insulating layer on the carrier substrate, wherein the insulating layer covers the relief pattern layer and the relief pattern layer is buried in the insulating layer; after pressing the insulating layer, removing the carrier substrate to expose the relief pattern layer, wherein the relief pattern layer is exposed on a surface of the insulating layer; after removing the carrier substrate, removing the relief pattern layer and retaining the insulating layer to expose the relief pattern layer on the insulating layer; A plurality of grooves are formed on the surface; an initial seed layer is formed on the insulating layer, wherein the initial seed layer covers the surface and the plurality of grooves but does not fill each of the plurality of grooves; the initial seed layer is electroplated to form a metal layer on the surface and in the plurality of grooves, wherein the metal layer and the initial seed layer fill the plurality of grooves; and a portion of the metal layer and a portion of the initial seed layer outside the grooves are removed to expose the surface of the insulating layer. The method for manufacturing a circuit board as described in claim 1, wherein the step of forming the embossed pattern layer on the carrier substrate includes exposure and development. A method for manufacturing a circuit board as described in claim 2, wherein the embossed pattern layer is removed using a photoresist. The manufacturing method of the circuit board as described in claim 1, wherein the carrier substrate includes a main substrate and a metal foil formed on the main substrate, and the metal foil is bonded to the insulating layer, and the step of removing the carrier substrate includes: separating the metal foil from the main substrate to remove the main substrate; and etching the metal foil after removing the main substrate. The method for manufacturing a circuit board as described in claim 1, wherein the method for removing the portion of the metal layer and the portion of the initial seed layer outside the groove includes etching or grinding. In the method for manufacturing a circuit board as described in claim 1, the step of pressing the insulating layer on the carrier substrate includes pressing a resin sheet on the carrier substrate.

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