TWI880338B - Multi-circuit control system and reading method for status informatiopn thereof - Google Patents

Abstract

A multi-circuit control system and a reading method for status information thereof are provided. The multi-circuit control system includes a first circuit and N second circuits. The second circuit is, for example a three dimensional NAND flash memory circuit, and the multi-circuit control system provides a storage media with high-performance and high-capacity. The first circuit provides a read clock signal. The second circuits are coupled in series, and coupled to the first circuit. Each of the second circuits has at least one first data shifter. The at least one data shifter is used to load status information of each of the second circuits., and shift out each of the status information to a prior stage second circuit or the first circuit, or the first chip obtains the status information of each of the second circuits through a parallel transmission scheme.

Description

Multi-circuit control system and method for reading its status information

The present invention relates to a multi-circuit control system and a method for reading its status information, and in particular to a multi-circuit control system of a memory circuit and a method for reading its status information.

In a multi-circuit system (such as a memory system), the master circuit often needs to monitor the working status of multiple slave circuits and thereby know whether each slave circuit is in a busy state. In the conventional technology, when the master circuit needs to read the status information of each slave circuit to know whether each slave circuit is in a busy state, it must send a read command for the status information one by one, and then receive the status information for each slave circuit one by one. When the number of slave circuits is too large, sending a read command for the status information for all slave circuits takes a lot of time, resulting in a waste of time and reducing the working efficiency of the system.

The present invention provides a multi-circuit control system and a method for reading state information thereof, which can improve the efficiency of reading the state information of the second circuit.

The multi-circuit control system of the present invention includes a first circuit and N second circuits. The first circuit provides a read clock signal. The second circuits are serially connected to each other in sequence and coupled to the first circuit. Each second circuit has at least one first data shifter. At least one first data shifter is used to load the state information of each second circuit, and shift out each state information to each second circuit or first circuit of the previous stage according to the read clock signal, or the first circuit obtains the state information of each second circuit through a parallel transmission mechanism.

The method for reading status information of the present invention includes: enabling the first circuit to provide a read clock signal; enabling N second circuits to be serially connected in sequence and coupled to the first circuit; providing at least one first data shifter in each second circuit, enabling at least one first data shifter to load the status information of each second circuit; and enabling each second circuit to shift out each status information to the second circuit or the first circuit at the previous stage according to the read clock signal, or enabling the first circuit to obtain the status information of each second circuit through a parallel transmission mechanism.

Based on the above, in the multi-circuit control system of the present invention, the first circuit can read the clock signal so that the status information of multiple second circuits can be read out in sequence along with the clock cycle of the read clock signal. In this way, the first circuit can avoid the time waste caused by issuing a read command for each second circuit, which can improve the working performance of the multi-circuit control system.

100, 200, 600, 700: Multi-circuit control system

110, 210, 610, 710: First circuit

120-1~120-N, 220-1~220-N, 300, 620-1~620-N, 720-1~720- A, 730-1~730-B: Second circuit

310, 320: Data shifter

311, 312, 321, 322: shift registers

ADD: address signal

CLK: clock signal

CMD: Command signal

IN[0], IN[1], IN[3], IN[4]: data input port

IO[7:0]: input and output signals

IOP, IOP1, IOP2: parallel input and output ports

LD: Load signal

OUT[0], OUT[1]: data output port

RE#: Read clock signal

RP, RP1, RP2: read signal transmission port

S410~S430, S810~S840: Steps

ST0[0], ST0[1], ST1[0], ST1[1], ST0[0]-0, ST0[1]-0, ST1[0]-0, ST1[1]-0, ST0[0]-1, ST0[1]-1, ST1[0]-1, ST1[1]-1, ST0[0]-2, ST0[1]-2, ST1[0]-2, ST1[1]-2: Status information

T1, T2: time interval

TP1~TP5: Time point

WE#: write signal

WP, WP1, WP2: write signal transmission port

FIG1 is a schematic diagram of a multi-circuit control system according to an embodiment of the present invention.

FIG2 is a schematic diagram of a multi-circuit control system of another embodiment of the present invention.

FIG3 is a schematic diagram showing the implementation of each second circuit in the multi-circuit control system of the embodiment of the present invention.

FIG4 is a flow chart showing a method for reading status information of a multi-circuit control system according to an embodiment of the present invention.

Figure 5 shows the action waveform of the multi-circuit control system of the embodiment of the present invention.

FIG6A shows an action waveform diagram of another implementation of the multi-circuit control system of the present invention.

FIG6B is a schematic diagram of a multi-circuit control system of another embodiment of the present invention.

FIG7 is a schematic diagram of a multi-circuit control system of another embodiment of the present invention.

FIG8 is a flow chart showing a method for reading status information of a multi-circuit control system according to an embodiment of the present invention.

Please refer to FIG. 1, which shows a schematic diagram of a multi-circuit control system according to an embodiment of the present invention. The multi-circuit control system 100 includes a first circuit 110 and a plurality of second circuits 120-1 to 120-N. The second circuits 120-1 to 120-N are coupled in series with each other, and the second circuits 120-1 to 120-N are coupled to the first circuit 110. The second circuit 120-1 of the first stage is coupled between the second circuit 120-2 of the second stage and the first circuit 110. The second circuits 120-2 to 120-N of the second stage to the Nth stage are sequentially coupled after the second circuit 120-1 of the first stage. Each of the second circuits 120-1 to 120-N has a data output port OUT[0] and a data input port IN[0], and the first circuit 110 has a data input port IN[0]. In detail, the data output port OUT[0] of the second circuit 120-1 of the first stage is coupled to the data input port IN[0] of the first circuit 110. The data input ports IN[0] of the second circuits 120-1 to 120-(N-1) of the first to N-1 stages are respectively coupled to the data output ports OUT[0] of the second circuits 120-2 to 120-N of the next stage (second to N-1 stages).

In addition, each of the first circuit 110 and the second circuits 120-1 to 120-N has a write signal transmission port WP and a read signal transmission port RP. The write signal transmission ports WP of the first circuit 110 and the second circuits 120-1 to 120-N are coupled to each other and used to transmit the write signal WE#. The read signal transmission ports RP of the first circuit 110 and the second circuits 120-1 to 120-N are coupled to each other, and the first circuit 110 can transmit the read clock signal RE# to the second circuits 120-1 to 120-N through the read signal transmission port RP. On the other hand, each of the first circuit 110 and the second circuits 120-1 to 120-N can also have a parallel input and output port IOP. The first circuit 110 and each of the second circuits 120-1 to 120-N can perform parallel data transmission via the parallel input and output port IOP.

In this embodiment, each second circuit 120-1~120-N may have a data shifter. The data shifter may be coupled between the data input port IN[0] and the data output port OUT[0] of the corresponding second circuit 120-1~120-N. Each second circuit 120-1~120-N may load its state information into the data shifter, and the data shifter may shift out the stored state information according to the clock cycle of the read clock signal RE# received by the corresponding second circuit 120-1~120-N.

In detail, when the first circuit 110 needs to read the status information of the second circuit 120-1~120-N, it can send the relevant command to the second circuit 120-1~120-N through the parallel input and output port IOP. Correspondingly, the second circuit 120-1~120-N can load its status information into the multiple data shifters therein. Then, the first circuit 110 can send the read clock signal RE# to the second circuit 120-1~120-N, and make the multiple data shifters in the second circuit 120-1~120-N shift out the stored status information to its data output port OUT[0] according to the clock cycle of the read clock signal RE#.

According to the coupling form of the multi-circuit control system 100, as the clock cycle of the read clock signal RE#, the state information of the second circuit 120-1 can be first shifted to the first circuit 110, and the state information of the second circuits 120-2 to 120-N of the subsequent stage can be shifted to the second circuits 120-1 to 120-(N-1) of the previous stage. Similarly, as the clock cycle of the read clock signal RE# increases, the state information of the second circuits 120-2 to 120-N can be sequentially shifted to the first circuit 110. In this way, the first circuit 110 can smoothly read the state information of all the second circuits 120-1 to 120-N.

Incidentally, the multi-circuit control system 100 of the present embodiment can be a memory system, and can be applied to a solid-state disk (SSD), for example. The first circuit 110 can be a memory controller, and can be set as a master circuit. The second circuits 120-1 to 120-N can be memory circuits, and can be set as slave circuits. The second circuits 120-1 to 120-N can be, for example, NAND, AND, or NOR flash memory circuits. In addition, the first circuit 110 can be set on a first chip, and the second circuits 120-1 to 120-N can be set on multiple different chips respectively.

On the other hand, in the embodiment of the present invention, when the first circuit 110 only needs to read the status information of one of the second circuits 120-1 to 120-N, the related command can be transmitted to the second circuits 120-1 to 120-N through the parallel input output port IOP. And through the transmitted data packet, the selected second circuit (one of the second circuits 120-1 to 120-N) is informed to transmit its status information to the first circuit 110 through the parallel input output port IOP. In addition, when the first circuit 110 reads the status information of the selected second circuit through its parallel input output port IOP, the shifting action of the status information of the second circuits 120-1 to 120-N can be performed at the same time. Under this mechanism, the data input port IN[0] of the first circuit 110 may be disconnected from the data output port OUT[0] of the second circuit 120-1.

Please refer to FIG. 2, which shows a schematic diagram of a multi-circuit control system of another embodiment of the present invention. The multi-circuit control system 200 includes a first circuit 210 and a plurality of second circuits 220-1 to 220-N. The second circuits 220-1 to 220-N are coupled in series with each other, and the second circuits 220-1 to 220-N are coupled to the first circuit 210.

Different from the embodiment of FIG. 1 , each second circuit 220-1 to 220-N in this embodiment has multiple data input ports IN[0], IN[1] and multiple data output ports OUT[0], OUT[1]. The first circuit 210 also has multiple data input ports IN[0], IN[1]. Among them, the data output ports OUT[0], OUT[1] of the first-level second circuit 220-1 are respectively coupled to the data input ports IN[0], IN[1] of the first circuit 210. The data input ports IN[0], IN[1] of the first-level to N-1-level second circuits 220-1 to 220-(N-1) are respectively coupled to the data output ports OUT[0], OUT[1] of the second circuits 220-2 to 220-N of the next level (second to N-level).

On the other hand, in this embodiment, each of the second circuits 220-1 to 220-N may have a plurality of data shifters. One of the data shifters may be coupled between the data input port IN[0] and the data output port OUT[0], and another data shifter may be coupled between the data input port IN[1] and the data output port OUT[1]. The data shifting operation of the second circuits 220-1 to 220-N in this embodiment is similar to that of the embodiment of FIG. 1, and will not be described in detail here.

In this embodiment, the multi-circuit control system 200 can speed up the reading of the status information of each second circuit 220-1 to 220-N by setting multiple data shifters in each second circuit 220-1 to 220-N.

It is worth mentioning that in the embodiment of the present invention, the number of data input ports, data output ports and corresponding data shifters in each second circuit 220-1 to 220-N can also be more than two. The two data input ports IN[0], IN[1] and the two data output ports OUT[0], OUT[1] shown in FIG. 2 are merely examples for illustration and are not intended to limit the scope of implementation of the present invention.

Please refer to Figure 3, which is a schematic diagram of the implementation method of each second circuit in the multi-circuit control system of an embodiment of the present invention. The second circuit 300 includes data shifters 310 and 320. The data shifter 310 is coupled between the data input port IN[0] and the data output port OUT[0], and the data shifter 320 is coupled between the data input port IN[1] and the data output port OUT[1]. The data shifters 310 and 320 are respectively composed of two shift register groups. The shift register group in the data shifter 310 includes a plurality of shift registers 311 and 312. The shift register group in the data shifter 320 includes a plurality of shift registers 321 and 322. It is worth mentioning that in the illustration of FIG. 3 , a single shift register group includes two shift registers, which is only an example for illustration. In the embodiment of the present invention, a single shift register group may include two or more registers without specific limitation. In addition, the number of data shifters in the second circuit 300 may also be more than two, and the illustration of FIG. 3 is not used to limit the number of data shifters.

In this embodiment, the shift registers 311 and 312 are sequentially coupled between the data input port IN[0] and the data output port OUT[0]. The shift registers 311 and 312 receive the load signal LD, the clock signal CLK, and the first part of the state information ST0[0] and ST0[1]. When the state information ST0[0] and ST0[1] of the second circuit 300 is to be read, the load signal LD can be enabled, and the state information ST0[0] and ST0[1] are loaded into the shift registers 311 and 312 respectively. Then, the load signal LD can be disabled, and the shift registers 311 and 312 can sequentially shift the status information ST0[0] and ST0[1] to the data output port OUT[0] according to the clock cycle of the clock signal CLK.

In addition, the shift registers 321 and 322 are coupled in sequence between the data input port IN[1] and the data output port OUT[1]. The shift registers 321 and 322 jointly receive the load signal LD, the clock signal CLK, and the second part of the state information ST1[0] and ST1[1]. When the load signal LD is enabled, a plurality of bits of the state information ST1[0] and ST1[1] can be loaded into the shift registers 321 and 322 respectively. Then, after the load signal LD is disabled, the shift registers 321 and 322 can shift the state information ST1[0] and ST1[1] in sequence to the data output port OUT[1] according to the clock cycle of the clock signal CLK. And through the data output ports OUT[0] and OUT[1], the status information ST0[0], ST0[1] and ST1[0], ST1[1] are respectively transmitted to the second circuit or the first circuit of the previous level.

In addition, as the clock signal CLK cycles, the shift registers 321 and 322 can receive the status information transmitted from the second circuit of the next stage through the data input ports IN[0] and IN[1], and then transmit the received status information to the second circuit or the first circuit of the previous stage through the data output ports OUT[0] and OUT[1].

It is worth mentioning that in this embodiment, the clock signal CLK can be generated according to the read clock signal RE# provided by the first circuit. The load signal LD can be disabled or enabled according to the write signal WE# provided by the first circuit. The relevant implementation details will be described in detail in the subsequent embodiments.

The above-mentioned shift registers 311, 312, 321, 322 can be implemented by using shift register circuits known to those skilled in the art without any special restrictions.

Please refer to FIG. 4, which shows a flow chart of a method for reading status information of a multi-circuit control system of an embodiment of the present invention. The multi-circuit control system includes a first circuit as a master circuit and a plurality of second circuits as slave circuits. In step S410, the plurality of second circuits as slave circuits receive a command to read status information sent by the first circuit as the master circuit. Then, in step S420, the second circuit can load its status information into a shift register. In step S430, the second circuit can shift the status information to the next shift register in each clock cycle of the read clock signal.

Please refer to FIG. 3 and FIG. 5 simultaneously, wherein FIG. 5 shows the action waveform diagram of the multi-circuit control system of the embodiment of the present invention. In FIG. 5, during the time interval T1, the first circuit, which is the main circuit, sends a read command of the state information to the second circuit 300 by pulling down the write signal WE#. Corresponding to the pull-down action of the write signal WE#, the second circuit 300 can pull up the load signal LD after the time interval T1 to enable the load signal LD, and load the state information ST0[0]-0, state information ST0[1]-0, state information ST1[0]-0 and state information ST1[1]-0 of the second circuit 300 into the shift registers 312, 311, 322 and 321 respectively.

In the time interval T2, the first circuit can send a dummy clock cycle by pulling down the write signal WE# again, and the second circuit 300 can disable the load signal LD by pulling down the load signal LD according to the dummy clock cycle. It is worth noting that the above dummy clock cycle is not necessary. The second circuit 300 can also pull down the load signal LD by itself after the load signal LD is maintained in the enabled state for a preset time.

At time point TP1, the data input ports IN[0] and IN[1] of the second circuit 300 can respectively receive the status information ST0[0]-1 and ST1[0]-1 of the second circuit of the next level, and the data output ports OUT[0] and OUT[1] of the second circuit 300 can respectively send the status information ST0[0]-0 and ST1[0]-0.

Then, after time point TP2, the first circuit may start to provide a continuously transitioning read clock signal RE#. Corresponding to the transition of the read clock signal RE#, the second circuit 300 may generate a clock signal CLK. In this embodiment, the second circuit 300 may detect the falling edge of the read clock signal RE# and activate the transition of the clock signal CLK according to the falling edge of the read clock signal RE#. After time point TP1, the clock signal CLK may be in phase with the read clock signal RE#. Of course, in other embodiments of the present invention, the clock signal CLK may also have a phase difference with the read clock signal RE#, and the transition action of the clock signal CLK may also be activated through other mechanisms based on the read clock signal RE#. For example, the second circuit 300 may be based on the rising edge of the read clock signal RE# or count the clock cycles of the read clock signal RE# to a certain number. The relevant details can be determined by the circuit designer without any restrictions.

After time point TP2, as the clock signal CLK cycles, the shift registers 311, 312, 321, 322 in the second circuit 300 can perform the shifting operation of the state information according to the rising edge of the clock signal CLK. Therefore, at time point TP3, the state information ST0[0]-1 and ST1[0]-1 of the second circuit of the next stage previously on the data input ports IN[0] and IN[1] are respectively shifted into the shift registers 311 and 321, and the state information ST0[1]-0 and ST1[1]-0 previously in the shift registers 311 and 321 are respectively shifted into the shift registers 312 and 322. Shift registers 312 and 322 and output the stored state information ST0[1]-0 and ST1[1]-0 to data output ports OUT[0] and OUT[1]. At this time, data input ports IN[0] and IN[1] receive the state information ST0[1]-1 and ST1[1]-1 of the second circuit of the next stage.

At time point TP4, the state information ST0[1]-1 and ST1[1]-1 of the second circuit of the next stage previously on the data input ports IN[0] and IN[1] are respectively shifted into the shift registers 311 and 321, and the state information ST0[0]-1 and ST1[0]-1 in the shift registers 311 and 321 are respectively shifted into the shift registers 312 and 322. The shift registers 312 and 322 output the stored state information ST0[0]-1 and ST1[0]-1 to the data output ports OUT[0] and OUT[1]. At this time, the data input ports IN[0] and IN[1] receive the state information ST0[0]-2 and ST1[0]-2 of the second circuit of the next stage.

At time point TP5, the state information ST0[0]-2 and ST1[0]-2 of the second circuit of the next two stages previously on the data input ports IN[0] and IN[1] are respectively shifted into the shift registers 311 and 321, and the state information ST0[1]-1 and ST1[1]-1 previously in the shift registers 311 and 321 are respectively shifted into the shift registers 312 and 322. The shift registers 312 and 322 output the stored state information ST0[1]-1 and ST1[1]-1 to the data output ports OUT[0] and OUT[1]. At this time, the data input ports IN[0] and IN[1] receive the state information ST0[1]-2 and ST1[1]-2 of the second circuit of the next two stages.

Please refer to FIG. 2 and FIG. 6A simultaneously, wherein FIG. 6A shows an operation waveform diagram of another embodiment of the multi-circuit control system of the present invention. In FIG. 6A, during the time interval T1, the first circuit 210 of the main circuit pulls down the write signal WE#, and transmits the input/output signal IO[7:0] of the command signal CMD to the second circuit 220-1~220-N through the parallel input/output port IOP. Then, during the time interval T2, the first circuit 210 pulls down the write signal WE# again, and transmits the input/output signal IO[7:0] of the address signal ADD to the second circuit 220-1~220-N through the parallel input/output port IOP. Among them, in this embodiment, the command signal CMD is used to convey the first circuit 210 to read the status information of one of the second circuits 220-1~220-N. The address signal ADD is used to indicate the address information of the selected second circuit (one of the second circuits 220-1~220-N) to be read.

Next, the first circuit 210 can provide a read clock signal RE#, and the selected second circuit (e.g., the second circuit 220-1) can sequentially transmit the input/output signal IO[7:0] as the state information ST[0]-0, ST[1]-0 to the first circuit 210 through the parallel input/output port IOP along with the clock cycle of the read clock signal RE#. After the state information ST[0]-0, ST[1]-0 of the second circuit 220-1 is output, the state information ST[0]-1, ST[1]-1 of the next-level second circuit 220-2 can be transmitted to the first circuit 210 through the input/output signal IO[7:0] along with the clock cycle of the read clock signal RE#.

In this embodiment, the first circuit 210 can perform a status reading operation on one of the required second circuits 220-1~220-N through the parallel input and output port IOP, and can quickly obtain the status information of each second circuit 220-1~220-N.

FIG6B is a schematic diagram of a multi-circuit control system of another embodiment of the present invention. The multi-circuit control system 600 includes a first circuit 610 and a plurality of second circuits 620-1 to 620-N. The second circuits 620-1 to 620-N are coupled in series with each other, and the second circuits 620-1 to 620-N are coupled with the first circuit 610 through the parallel input and output port IOP. Please note that in this embodiment, the data output ports OUT[0] and OUT[1] of the first-stage second circuit 620-1 are isolated from the first circuit 610. That is, the first circuit 610 of this embodiment can read the status information of each second circuit 620-1 to 620-N through the parallel input and output port IOP through the parallel transmission mechanism as shown in the waveform diagram of FIG6A.

Please refer to FIG. 7, which shows a schematic diagram of a multi-circuit control system of another embodiment of the present invention. The multi-circuit control system 700 includes a first circuit 710 and a plurality of second circuits 720-1~720-A and 730-1~730-B. The second circuits 720-1~720-A are coupled in series with each other, and the data output ports OUT[0] and OUT[1] of the first-stage second circuit 720-1 are respectively coupled to the data input ports IN[0] and IN[1] of the first circuit 710. In addition, the parallel input and output ports IOP of each second circuit 720-1~720-A are commonly coupled to the parallel input and output port IOP1 of the first circuit 710.

In addition, the second circuits 730-1 to 730-B are coupled in series with each other, and the data output ports OUT[0] and OUT[1] of the first-stage second circuit 730-1 are respectively coupled to the data input ports IN[2] and IN[3] of the first circuit 710. Furthermore, the parallel input/output ports IOP of each second circuit 730-1 to 730-B are commonly coupled to the parallel input/output port IOP2 of the first circuit 710.

In this embodiment, the first circuit 710 can transmit the read clock signal RE1# and the write signal WE1# to the second circuits 720-1~720-A through the read signal transmission port RP1 and the write signal transmission port WP1 to control the read action of the state information. The first circuit 710 can also transmit the read clock signal RE2# and the write signal WE2# to the second circuits 730-1~730-B through the read signal transmission port RP2 and the write signal transmission port WP2 to control the read action of the state information. Furthermore, the first circuit 710 can read the status information of any one of the second circuits 720-1~720-A through the parallel input/output port IOP1, and the first circuit 710 can also read the status information of any one of the second circuits 730-1~730-B through the parallel input/output port IOP2.

The details of the status information reading action have been described in detail in the aforementioned implementation examples, so I will not elaborate on them here.

It is worth mentioning that the number of second circuits 720-1~720-A in the series formed by the second circuits 720-1~720-A and the number of second circuits 730-1~730-B in the series formed by the second circuits 730-1~730-B may be the same or different. In addition, in other embodiments of the present invention, the multi-circuit system 700 may also have other second circuits to form another or more series. Specifically, in the multi-circuit system 700, the number of series formed by the second circuits may be one or more, without specific restrictions.

Please refer to FIG8, which shows a flow chart of a method for reading state information of a multi-circuit control system according to an embodiment of the present invention. In step S810, the first circuit provides a read clock signal. In step S820, N second circuits are connected in series in sequence, and the second circuits are coupled to the first circuit, wherein N is an integer greater than 1. In step S830, at least one first data shifter is provided in each second circuit, so that at least one first data shifter loads the state information of each second circuit. In step S840, each second circuit shifts out each state information to each second circuit or first circuit of the previous stage according to the read clock signal.

The implementation details of the above steps have been described in detail in the aforementioned embodiments, so I will not elaborate on them here.

In summary, in the multi-circuit control system of the present invention, by coupling the first circuit to multiple second circuits connected in series, and allowing the first circuit to provide a read clock signal, the status information of multiple second circuits can be read out in sequence along with the clock cycle of the read clock signal. The first circuit does not need to issue a read command to each second circuit one by one to read the status information of each second circuit, which effectively saves the time required for work.

100:Multi-circuit control system

110: First circuit

120-1~120-N: Second circuit

IN[0]: Data input port

IOP: parallel input and output port

OUT[0]: data output port

RE#: Read clock signal

RP: Read signal transmission port

WE#: write signal

WP: Write signal transmission port

Claims (17)

A multi-circuit control system includes: a first circuit, providing a read clock signal; and N second circuits, which are serially connected to each other in sequence and coupled to the first circuit, N is an integer greater than 1, wherein each second circuit has at least one first data shifter, the at least one first data shifter is used to load the state information of each second circuit, and according to the read clock signal, to shift out each state information to each second circuit or the first circuit of the previous stage, or the first circuit obtains the state information of each second circuit through a parallel transmission mechanism. A multi-circuit control system as described in claim 1, wherein each of the second circuits has at least one data output port and at least one data input port, and the at least one data output port and the at least one data input port are coupled to the at least one first data shifter. A multi-circuit control system as described in claim 2, wherein the at least one data output port of each of the second circuits of the Nth to the second stage is coupled to the at least one data input port of each of the second circuits of the previous stage, and the at least one data output port of the second circuit of the first stage is coupled to the first circuit or isolated from the first circuit. A multi-circuit control system as described in claim 2, wherein each of the at least one first data shifters is a shift register group, and the shift register group is coupled between each of the at least one data input port and each of the at least one data output port of the corresponding each of the second circuits. A multi-circuit control system as described in claim 4, wherein the shift register group includes: a plurality of shift registers, the shift registers are coupled in series with each other, wherein the shift registers jointly receive a load signal and the read clock signal, and respectively receive the corresponding state information. A multi-circuit control system as described in claim 5, wherein the shift registers store the bits of the state information into the shift registers respectively according to the load signal, and perform data shifting according to the read clock signal. A multi-circuit control system as described in claim 1, wherein the second circuits are respectively a plurality of memory circuits, and the first circuit is a memory control circuit. A multi-circuit control system as described in claim 1, wherein the first circuit further includes a first parallel input-output interface, and the second circuits each include a plurality of second parallel input-output interfaces, and the first parallel input-output interface and the second parallel input-output interfaces are coupled to each other. A multi-circuit control system as described in claim 8, wherein the first circuit reads the status information of one of the second circuits through the first parallel input/output interface. The multi-circuit control system as described in claim 1 further includes: N third circuits, which are serially connected to each other in sequence, and the third circuits are coupled to the first circuit, wherein each of the third circuits has at least one second data shifter, and the at least one second data shifter is used to load the state information of each of the third circuits, and according to the read clock signal, to shift out each of the state information to the third circuits or the first circuit of the previous stage. A multi-circuit control system as described in claim 1, wherein the first circuit is disposed on a first chip, and the second circuits are disposed on multiple second chips respectively. A method for reading state information includes: enabling a first circuit to provide a read clock signal; enabling N second circuits to be serially connected in sequence and coupled to the first circuit, wherein N is an integer greater than 1; providing at least one first data shifter in each of the second circuits, enabling the at least one first data shifter to load the state information of each of the second circuits; and enabling each of the second circuits to shift out the state information to the second circuit or the first circuit at the previous stage according to the read clock signal, or enabling the first circuit to obtain the state information of each of the second circuits through a parallel transmission mechanism. The reading method as described in claim 12 further includes: setting a shift register group in each of the at least one first data shifters, wherein each of the second circuits has at least one data output port and at least one data input port, and the shift register group is coupled between each of the at least one data input port and each of the at least one data output port of the corresponding second circuit. The reading method as described in claim 13, wherein the shift register group has a plurality of shift registers coupled in series, and the reading method further comprises: causing the shift registers to store the bits of the state information into the shift registers respectively according to a load signal; and causing the shift registers to perform data shifting according to the read clock signal. The reading method as described in claim 12 further includes: connecting a plurality of third circuits in series in sequence and coupling the third circuits to the first circuit; providing at least one second data shifter in each of the third circuits so that the at least one second data shifter loads the state information of each of the third circuits; and causing each of the third circuits to shift out the state information to the third circuits of the previous stage or the first circuit according to the reading clock signal. The reading method as described in claim 12 further includes: providing a first parallel input/output interface in the first circuit, and including a plurality of second parallel input/output interfaces in the second circuits respectively; coupling the first parallel input/output interface and the second parallel input/output interfaces to each other; and enabling the first circuit to read the status information of one of the second circuits through the first parallel input/output interface. The reading method as described in claim 12 further includes: setting the first circuit on a first chip, and setting the second circuits on multiple second chips respectively, wherein the first circuit is a memory control circuit, and the second circuits are multiple memory circuits respectively.

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