TWI880169B - Memory device - Google Patents

Abstract

The embodiment of the present invention provides a memory device that can reduce erroneous reading. The memory device of the embodiment includes: a first memory cell, a second memory cell, a first circuit for supplying write current to the first memory cell and the second memory cell, a first wiring connected to the first circuit, a first plug electrically connecting the first memory cell and the first wiring, and a second plug electrically connecting the second memory cell and the first wiring. The length of the first wiring from the first circuit to the first plug is shorter than the length of the first wiring from the first circuit to the second plug. The resistance value of the first plug is higher than the resistance value of the second plug.

Description

Memory device

An embodiment of the present invention relates to a memory device.

A memory device using a variable resistance element as a memory element is known. A magnetic memory device using a magnetoresistive effect element as a variable resistance element is known (MRAM: Magnetoresistive Random Access Memory).

The problem that the present invention aims to solve is to provide a memory device that can reduce erroneous reading.

The memory device of the embodiment includes: a first memory cell, a second memory cell, a first circuit for supplying write current to the first memory cell and the second memory cell, a first wiring connected to the first circuit, a first plug electrically connecting the first memory cell and the first wiring, and a second plug electrically connecting the second memory cell and the first wiring. The length of the first wiring from the first circuit to the first plug is shorter than the length of the first wiring from the first circuit to the second plug. The resistance value of the first plug is higher than the resistance value of the second plug.

1: Memory device

10: Memory cell array

11: Input and output circuits

12: Control circuit

13: Decoding circuit

14: Column selection circuit/1st circuit

15: Row selection circuit

16: Voltage generating circuit

17: Write circuit

18: Read out the circuit

19: Write to drive

30:Semiconductor substrate

31: Insulation layer

32,33a,33b,33b1~33b4,36,37a,37b,38: Conductor

34,35: Components

39: Ferromagnetic

40: Non-magnetic material

41: Ferromagnetic

42: Insulation layer

43,44: Anti-corrosion agent mask

A1,A2: Arrow

ADD: address

AP: Antiparallel

BL, BL<0>~BL<N>: bit line

CP1, CP2: contact plug

CNT: control signal

CMD: Command

dm0~dm4: diameter

D10a~D12a: Concentration

D11b~D14b: Concentration

DAT: data (write data) (read data)

G0,G1: Group

I-I,II-II: line

MC,MC<0,0>~MC<0,N>,MC<1,0>~MC<1,N>,MC<M,0>~MC<M,N>: memory cells

MTJ: Magnetic Tunnel Junction

MTJ<0,0>: magnetoresistance element

P: Parallel

R0b~R4b,R0w~R4w: Area

RL: Reference layer

SEL,SEL<0,0>: switch element

SL: Memory layer

TB: Tunneling barrier layer

WL, WL<0>, WL<1>~WL<M>: character line

X,Y,:direction

Z: Direction/Axis

FIG1 is a block diagram showing the structure of the memory device of the first embodiment.

FIG2 is a circuit diagram showing an example of the circuit structure of the memory cell array contained in the memory device of the first embodiment.

FIG3 is a top view showing an example of the planar structure of the memory cell array contained in the memory device of the first embodiment.

FIG4 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array contained in the memory device of the first embodiment.

FIG5 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array contained in the memory device of the first embodiment.

FIG6 is a three-dimensional diagram of a portion of the memory cell array contained in the memory device of the first embodiment.

FIG7 is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element included in the memory device of the first embodiment.

FIG8 is a flow chart showing an example of a method for manufacturing a memory device according to the first embodiment.

FIG9 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device of the first embodiment.

FIG10 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device of the first embodiment.

FIG11 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device of the first embodiment.

FIG12 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device of the first embodiment.

FIG13 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device of the first embodiment.

FIG14 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device of the first embodiment.

FIG15 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in the memory device of the first variation of the first embodiment.

FIG16 is a flow chart showing an example of a method for manufacturing a memory device according to the second variation of the first embodiment.

FIG17 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device of the second variation of the first embodiment.

FIG18 is a cross-sectional view showing an example of a cross-sectional structure in the manufacturing steps of the memory device of the second variation of the first embodiment.

FIG19 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in the memory device of the third variation of the first embodiment.

FIG20 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in the memory device of the fourth variation of the first embodiment.

FIG21 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in the memory device of the second embodiment.

FIG22 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a memory device of a variation of the second embodiment.

FIG23 is a top view showing an example of the planar structure of the memory cell array contained in the memory device of the third embodiment.

FIG24 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in the memory device of the third embodiment.

FIG25 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in the memory device of the third embodiment.

FIG26 is a three-dimensional diagram of a portion of the memory cell array contained in the memory device of the third embodiment.

FIG27 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in the memory device of the fourth embodiment.

FIG28 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device of the fifth embodiment.

FIG29 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device of the fifth embodiment.

FIG30 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in the memory device of the sixth embodiment.

FIG31 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in the memory device of the sixth embodiment.

The following is a description of the implementation form with reference to the drawings. In addition, in the following description, the same symbols are given to the components with roughly the same function and structure. When the components with the same structure are not particularly distinguished from each other, different characters or numbers are sometimes added to the end of the same symbol.

1. The first implementation form

The memory device of the first embodiment is described. The memory device of the first embodiment is, for example, a magnetic memory device that uses an element having a magnetoresistance effect (Magnetoresistance effect) through a magnetic tunnel junction (MTJ) (referred to as an MTJ element or a magnetoresistance effect element) as a variable resistance element. In this embodiment, and the embodiments and variations described below, the description is based on the case of using an MTJ element as a variable resistance element, and the description is based on the magnetoresistance effect element MTJ.

1.1 Composition

1.1.1 Composition of memory device

The structure of the memory device of the first embodiment is described using FIG1. FIG1 is a block diagram showing the structure of the memory device. The memory device 1 includes: a memory cell array 10, an input/output circuit 11, a control circuit 12, a decoding circuit 13, a column selection circuit 14, a row selection circuit 15, a voltage generation circuit 16, a write circuit 17, and a read circuit 18.

The memory cell array 10 is a non-volatile memory. The memory cell array 10 includes a plurality of memory cells MC each corresponding to a row and a column. The memory cells MC store data non-volatilely. For example, the memory cells MC in the same row are connected to the same word line WL. The memory cells MC in the same row are connected to the same bit line BL.

The input-output circuit 11 is a circuit for sending and receiving data. The input-output circuit 11 receives the control signal CNT, the command CMD, the bit address ADD, and the data (write data) DAT from the outside of the memory device 1. The input-output circuit 11 sends the control signal CNT and the command CMD to the control circuit 12. The input-output circuit 11 sends the bit address ADD to the decoding circuit 13. The input-output circuit 11 sends the data (write data) DAT to the write circuit 17. The input-output circuit 11 receives the data (read data) DAT from the read circuit 18. The input-output circuit 11 sends the data (read data) DAT to the outside of the memory device 1.

The control circuit 12 is a circuit for controlling the overall operation of the memory device 1. The control circuit 12 controls the operation of the input/output circuit 11, the decoding circuit 13, the column selection circuit 14, the row selection circuit 15, the voltage generation circuit 16, the write circuit 17, and the read circuit 18 based on the control signal CNT and the command CMD.

The decoding circuit 13 is a circuit for decoding the bit address ADD. The decoding circuit 13 receives the bit address ADD from the input/output circuit 11. The decoding circuit 13 decodes the bit address ADD. The decoding circuit 13 sends the decoding result of the bit address ADD to the column selection circuit 14 and the row selection circuit 15. The address ADD includes a column address and a row address.

The column selection circuit 14 is a circuit for selecting the word line WL corresponding to the column of the memory cell array 10. The column selection circuit 14 is connected to the memory cell array 10 via the word line WL. The column selection circuit 14 receives the decoding result (column address) of the bit address ADD from the decoding circuit 13. The column selection circuit 14 selects the word line WL corresponding to the column based on the decoding result of the bit address ADD.

The row selection circuit 15 is a circuit for selecting the bit line BL corresponding to the row of the memory cell array 10. The row selection circuit 15 is connected to the memory cell array 10 via the bit line BL. The row selection circuit 15 receives the decoding result (row address) of the bit address ADD from the decoding circuit 13. The row selection circuit 15 selects the bit line BL corresponding to the row based on the decoding result of the bit address ADD.

The voltage generating circuit 16 is a circuit that uses the power supply voltage applied from the outside of the memory device 1 to generate voltages used for various operations of the memory cell array 10. For example, the voltage generating circuit 16 generates a voltage used by a write operation (hereinafter also described as a "write voltage"). The voltage generating circuit 16 supplies the write voltage to the write circuit 17. In addition, the voltage generating circuit 16 generates a voltage used by a read operation (hereinafter also described as a "read voltage"). The voltage generating circuit 16 supplies the read voltage to the read circuit 18.

The write circuit 17 is a circuit for writing data to the memory cell MC. The write circuit 17 includes a write driver 19. The write circuit 17 receives the write data DAT from the input/output circuit 11. The write circuit 17 applies a write voltage from the voltage generating circuit 16. The write driver 19 is, for example, a constant current driver circuit. The write driver 19 supplies a current based on the write voltage (current used by the write action. Hereinafter, it is also described as "write current") to the column selection circuit 14 and the row selection circuit 15. The column selection circuit 14 and the row selection circuit 15 supply the write current to the memory cell array 10 via the selected word line WL and the bit line BL.

The read circuit 18 is a circuit for reading data from the memory cell MC. The read circuit 18 includes a sense amplifier not shown. The read circuit 18 applies a read voltage from the voltage generating circuit 16. The read circuit 18 supplies the read voltage to the row selection circuit 15. The row selection circuit 15 supplies the read voltage to the memory cell array 10 via the selected bit line BL. The read circuit 18 applies the voltage of the bit line BL to the self-selection circuit 15. The sense amplifier calculates the data stored in the memory cell MC based on the voltage of the bit line BL. The read circuit 18 sends the calculated data as read data DAT to the input-output circuit 11.

1.1.2 Circuit structure of memory cell array

The circuit structure of the memory cell array 10 is described using FIG2. FIG2 is a circuit diagram showing an example of the circuit structure of the memory cell array 10. In FIG2, the memory cell MC, the word line WL, and the bit line BL are classified and displayed by a suffix including an index ""<>"".

As shown in FIG2 , the memory cells MC are arranged in a matrix in the memory cell array 10, and a correspondence is established between one of a plurality of word lines WL (WL<0>, WL<1>, ..., WL<M>) and one of a plurality of bit lines BL (BL<0>, BL<1>, ..., BL<N>) (M and N are arbitrary integers). That is, the memory cell MC<i,j> (0≦i≦M, 0≦j≦N) is connected between the word line WL<i> and the bit line BL<j>. The memory cell MC<i,j> includes a switch element SEL<i,j> and a magnetoresistive effect element MTJ<i,j> connected in series.

The switch element SEL has the function of serving as a selector for controlling the supply of current to the magnetoresistive effect element MTJ when writing and reading data of the corresponding magnetoresistive effect element MTJ.

The switch element SEL of this embodiment is explained as having two terminals. When the voltage applied between the two terminals does not reach a certain first critical value, the switch element SEL is in a high resistance state, such as an electrically non-conductive state (off state). When the voltage applied between the two terminals rises and is above the first critical value, the switch element SEL is in a low resistance state, such as an electrically conductive state (on state). When the voltage applied between the two terminals of the switch element SEL in the low resistance state decreases and is below the second critical value, the switch element SEL is in a high resistance state. The switch element SEL also has the same function of switching between the high resistance state and the low resistance state based on the magnitude of the voltage applied in the first direction for the second direction opposite to the first direction. That is, the switch element SEL is a bidirectional switch element. By turning the switch element SEL on or off, it is possible to control whether or not current is supplied to the TJ element MTJ connected to the switch element SEL, that is, whether the MTJ element MTJ is selected or not.

In this embodiment, a switch element having the following characteristics can be used, namely: the resistance value drops sharply at a certain voltage, and along with it, the applied voltage drops sharply and the current increases (reverse).

Furthermore, for example, a switch element substantially formed of a composition containing a specific element selected from silicon (Si), oxygen (O), arsenic (As), phosphorus (P), indium (Sb), sulfur (S), selenium (Se) and tellurium (Te) (for example, silicon oxide (SiOx) containing the above-mentioned specific elements) can also be used.

In addition, the inclusion of "substantially" records (e.g., substantially formed) and similar records means that substantially formed materials (compositions) are allowed to contain unintentional impurities.

The magnetoresistive element MTJ can switch between a low resistance state and a high resistance state by controlling the current supplied by the switch element SEL. The magnetoresistive element MTJ functions as a memory element that can write data according to the change of the resistance state and can store and read the written data in a non-volatile manner.

1.1.3 Structure of memory cell array

An example of the structure of the memory cell array 10 is described. In addition, in the following referenced figures, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the vertical direction of the front surface of the semiconductor substrate used for forming the memory device 1.

(Plane structure)

FIG3 is used to explain the planar structure of the memory cell array 10. FIG3 is a top view showing an example of the planar structure of the memory cell array 10. FIG3 shows the word lines WL between the plurality of memory cells MC and the column selection circuit 14 in the memory cell array 10, and the bit lines BL between the plurality of memory cells MC and the row selection circuit 15. In addition, in FIG3, the word lines WL<5>~WL<M>, the bit lines BL<5>~BL<N>, and the plurality of memory cells MC corresponding thereto are omitted.

In addition, the plane structure here means that in the Z direction, the memory cell MC can select a structure (1-layer structure) of a memory cell MC through a combination of a word line WL and a bit line BL, just like the structure in Figure 6. The description of the plane structure in the following is also assumed to be used with the same meaning.

As shown in FIG. 3 , in the memory cell array 10 , for example, the memory cell MC is arranged above the word line WL. The bit line BL is arranged above the memory cell MC.

Each word line WL is connected to a column selection circuit 14 and a plurality of memory cells MC arranged in the X direction. The column selection circuit 14 supplies a write current to the memory cells MC via the word lines WL. Hereinafter, regions including a plurality of memory cells MC connected to each of the word lines WL<0>~WL<4> are described as regions R0w~R4w. Region R0w includes memory cells MC<0,0>~ MC<0,N>. Region R1w includes memory cells MC<1,0>~MC<1,N>. Region R2w includes memory cells MC<2,0>~MC<2,N>. Region R3w includes memory cells MC<3,0>~MC<3,N>. Region R4w contains memory cells MC<4,0>~MC<4,N>.

Regions R0w~R4w are arranged in the order of region R4w, region R3w, region R2w, region R1w, and region R0w on the side of the self-selection circuit 15. The length of the bit line BL between the memory cell MC and the row selection circuit 15 is shorter for the memory cell MC in the region closer to the row selection circuit 15 (e.g., region R4w) (hereinafter also referred to as "the cell close to the row selection circuit 15"). In other words, the length of the bit line BL between the memory cell MC and the row selection circuit 15 is longer for the memory cell MC in the region farther from the row selection circuit 15 (e.g., region R0w) (hereinafter also referred to as "the cell far from the row selection circuit 15"). Therefore, the resistance value of the bit line BL between the memory cell MC and the row selection circuit 15 is lower as the cell is closer to the row selection circuit 15.

Each bit line BL is connected to a row selection circuit 15 and a plurality of memory cells MC arranged in the Y direction. The row selection circuit 15 supplies a write current to the memory cells MC via the bit lines BL. Hereinafter, regions including a plurality of memory cells MC connected to each of the bit lines BL<0>~BL<4> are respectively described as regions R0b~R4b. Region R0b includes memory cells MC<0,0>~MC<M,0>. Region R1b includes memory cells MC<0,1>~MC<M,1>. Region R2b includes memory cells MC<0,2>~MC<M,2>. Region R3b includes memory cells MC<0,3>~MC<M,3>. Region R4b includes memory cells MC<0,4>~MC<M,4>.

Regions R0b to R4b are arranged in the order of region R0b, region R1b, region R2b, region R3b, and region R4b from the column selection circuit 14 side. The length of the word line WL between the memory cell MC and the column selection circuit 14 is shorter for the memory cell MC in the region (e.g., region R0b) closer to the column selection circuit 14 (hereinafter referred to as "cell close to the column selection circuit 14"). In other words, the length of the word line WL between the memory cell MC and the column selection circuit 14 is longer for the memory cell MC in the region (e.g., region R4b) farther from the column selection circuit 14 (hereinafter also referred to as "cell far from the column selection circuit 14"). Therefore, the resistance value of the word line WL between the memory cell MC and the column selection circuit 14 is lower the closer the cell is to the column selection circuit 14.

(Section structure)

The cross-sectional structure of the memory cell array 10 is described using Figures 4 to 6. Figure 4 is a cross-sectional view along the I-I line of Figure 3. Figure 5 is a cross-sectional view along the II-II line of Figure 3. Figure 6 is a three-dimensional view of a portion of the memory cell array 10. In addition, in the examples shown in Figures 4 to 6, the insulating layer is omitted.

As shown in FIGS. 4 to 6 , the memory cell array 10 is disposed above the semiconductor substrate 30.

A plurality of conductors 32 are disposed above the semiconductor substrate 30, for example, via an insulating layer 31. The plurality of conductors 32 are made of conductive material and function as word lines WL. The plurality of conductors 32 are arranged, for example, in the Y direction, and each extends in the X direction. In addition, the semiconductor substrate 30 and the insulating layer 31 are omitted in FIG. 6 .

A plurality of contact plugs CP1 (hereinafter also referred to as "first electrode" or upper electrode) are provided on the upper surface of a conductor 32. The contact plugs CP1 electrically connect the memory cell MC and the conductor 32. The plurality of contact plugs CP1 provided on the upper surface of a conductor 32 are arranged, for example, in the X direction.

The contact plug CP1 of the region R0b includes a conductor 33a. The contact plug CP1 of each of the regions R1b to R4b includes conductors 33a and 33b. The conductors 33a and 33b are made of conductive materials. The conductor 33b includes a material having a lower resistivity than the conductor 33a. The conductors 33a and 33b may include, for example, carbon, boron nitride (BN), metal oxide, metal nitride, polycrystalline silicon (poly-Si), tungsten, titanium, aluminum, copper, etc. For example, two materials are selected from these materials, and among the selected two materials, the conductor 33a includes a material having a relatively high resistivity (hereinafter also described as a "high resistance material"). The conductor 33b includes a material having a relatively low resistivity (hereinafter also described as a "low resistance material"). In addition, the conductors 33a and 33b are not limited to these materials as long as the resistivity of the conductor 33a is higher than the resistivity of the conductor 33b.

The high resistance material used for the conductor 33a and the low resistance material used for the conductor 33b can be selected, for example, as follows. When at least one of copper and aluminum is selected as the low resistance material, at least one of tungsten, tungsten nitride (WN), titanium, titanium nitride (TiN), carbon, and polysilicon can be selected as the high resistance material. When at least one of tungsten, tungsten nitride, titanium, and titanium nitride is selected as the low resistance material, at least one of carbon and polysilicon can be selected as the high resistance material. When carbon is selected as the low resistance material, polysilicon can be selected as the high resistance material.

The diameter of the contact plug CP1 in each of the regions R0b~R4b is roughly the same. In addition, the shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circle. For example, the cross section of the contact plug CP1 can be an ellipse or a rectangle. Regardless of the cross section of the contact plug CP1, the area (contact area) of the contact plug CP1 in each of the regions R0b~R4b contacting the word line WL is roughly the same.

The ratio of the conductive body 33b contained in the contact plug CP1 of each region R1b~R4b is lower as the contact plug CP1 is disposed in a region close to the column selection circuit 14. The height of the conductive body 33b contained in the contact plug CP1 of each region R1b~R4b is lower as the contact plug CP1 is disposed in a region close to the column selection circuit 14. Therefore, the resistance value of the contact plug CP1 is higher as the contact plug CP1 is disposed in a region close to the column selection circuit 14.

The length of the word line WL from the column selection circuit 14 to the contact plug CP1 set in the region R0b is shorter than the length of the word line WL from the column selection circuit 14 to the contact plug CP1 set in the region R1b. The length of the word line WL from the column selection circuit 14 to the contact plug CP1 set in the region R1b is shorter than the length of the word line WL from the column selection circuit 14 to the contact plug CP1 set in the region R2b. The same applies to the following.

The conductor 33b is disposed on the conductor 33a. In addition, the conductor 33a can be disposed on the conductor 33b. Furthermore, the contact plug CP1 of each of the regions R1b to R4b can be composed of three or more conductors having different resistivities.

The conductors 33a and 33b may include more than two materials. For example, when the conductors 33a and 33b each include two materials A and B having different resistance values, the ratio of material A to material B contained in the conductor 33a and the ratio of material A to material B contained in the conductor 33b may be different. Thus, the resistivity of the conductor 33a and the resistivity of the conductor 33b may be different.

An element 34 that functions as a switch element SEL is disposed on the upper surface of the contact plug CP1.

Element 35 is provided on the upper surface of element 34 to function as a magnetoresistive element MTJ. Details of the structure of element 35 will be described later.

A conductor 36 is disposed on the upper surface of the component 35. The conductor 36 is made of a conductive material and functions as a hard mask when processing the component 35.

A contact plug CP2 (hereinafter also referred to as the "second electrode" or the lower electrode) is provided on the upper surface of the conductor 36. The contact plug CP2 electrically connects the memory cell MC and the conductor 38 described later via the conductor 36. The contact plug CP2 includes a conductor 37a. The conductor 37a is made of a conductive material.

A conductor 38 is provided on the upper surface of the contact plug CP2. The plurality of conductors 38 are made of a conductive material and function as a bit line BL. The plurality of conductors 38 are arranged in the X direction, for example, and each extends in the Y direction. For example, the plurality of contact plugs CP2 arranged in the Y direction are connected to one conductor 38.

As shown in FIG6 , a memory cell MC is provided at each intersection of the conductor 32 and the conductor 38.

In addition, element 34 and element 35 may be arranged to be connected to each other. For example, element 34 and element 35 may be electrically connected via a conductor (not shown). In addition, FIG. 4 to FIG. 6 are used to illustrate the case where element 35 and conductor 36 are arranged on element 34, but the present invention is not limited thereto. For example, element 34 may be arranged on element 35 and conductor 36.

By being constructed as described above, the memory cell array 10 has a structure in which the memory cell MC is disposed between the corresponding word line WL and the bit line BL.

Using FIG. 3 to FIG. 6, a structure (referred to as a single-layer structure) in which a memory cell MC can be selected by a combination of a word line WL and a bit line BL is described, but the present invention is not limited to this. For example, any array structure such as an array structure in which a plurality of such structures are stacked in the Z direction can be applied.

In FIG. 6, as an example, the structure in which the diameters of CP1 and CP2 are smaller than the diameter of MC is described, but it is not limited to this structure. In the case of a structure in which the diameters of CP1 and CP2 are substantially the same as the diameter of MC, the same effect can be obtained.

1.1.4 Structure of magnetoresistance effect element

The structure of the magnetoresistive effect element MTJ is described using FIG7. FIG7 is a cross-sectional view showing an example of the cross-sectional structure of the magnetoresistive effect element MTJ.

As shown in FIG. 7 , the element 35 (magnetoresistive element MTJ) includes: a ferromagnetic material 39 that functions as a reference layer RL (Reference layer), a non-magnetic material 40 that functions as a tunnel barrier layer TB (Tunnel barrier layer), and a ferromagnetic material 41 that functions as a storage layer SL (Storage layer).

The magnetoresistive effect element MTJ, for example, is a layer of multiple materials from the word line WL side to the bit line BL side (along the Z-axis direction) in the order of ferromagnetic material 39, non-magnetic material 40, and ferromagnetic material 41. The magnetoresistive effect element MTJ, for example, functions as a perpendicular magnetization type magnetoresistive effect element MTJ in which the magnetization direction of the magnetic material constituting the magnetoresistive effect element MTJ is perpendicular to the film surface.

The ferromagnetic body 39 has ferromagnetism and has an easy magnetization axis in a direction perpendicular to the film surface. The ferromagnetic body 39 has a magnetization direction in any direction toward the bit line BL side or the word line WL side. The ferromagnetic body 39 includes, for example, cobalt iron boron (CoFeB) or iron boride (FeB). The magnetization direction of the ferromagnetic body 39 is fixed, and in the example of FIG. 7, it is toward the opposite side relative to the side where the non-magnetic body 40 is provided. In addition, "the magnetization direction is fixed" means that the magnetization direction will not change due to a current (spin torque) of a magnitude that can reverse the magnetization direction of the ferromagnetic body 41.

The non-magnetic body 40 is a non-magnetic insulating film, for example, containing magnesium oxide (MgO). The non-magnetic body 40 is disposed between the ferromagnetic body 39 and the ferromagnetic body 41. Thus, the ferromagnetic body 39, the non-magnetic body 40, and the ferromagnetic body 41 form a magnetic tunnel junction.

The ferromagnetic body 41 has ferromagnetism and has an easy axis of magnetization in a direction perpendicular to the film surface. The ferromagnetic body 41 has a magnetization direction in any direction toward the bit line BL side or the word line WL side. The ferromagnetic body 41 may include, for example, cobalt iron boron (CoFeB) or iron boride (FeB) and has a body-centered cubic (bcc) crystal structure.

The memory device 1, for example, directly flows a write current through the magnetoresistive element MTJ constructed as described above, and injects spin torque into the memory layer SL and the reference layer RL by the write current to control the magnetization direction of the memory layer SL and the magnetization direction of the reference layer RL. This writing method is also called a spin injection writing method. The magnetoresistive element MTJ can obtain either a low resistance state or a high resistance state according to whether the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL is parallel or antiparallel.

If a write current Iw0 of a certain magnitude flows in the magnetoresistive element MTJ in the direction of arrow A1 in FIG. 7 , that is, from the memory layer SL toward the reference layer RL, the magnetization directions of the memory layer SL and the reference layer RL are parallel to each other. In the case of the parallel state, the resistance value of the magnetoresistive element MTJ is the lowest, and the magnetoresistive element MTJ is set to a low resistance state. The low resistance state is called the "P (Parallel) state" and is defined as, for example, the state of data "0".

Furthermore, if a write current Iw1 greater than the write current Iw0 flows in the direction of arrow A2 in FIG. 7 , that is, from the reference layer RL toward the memory layer SL, in the magnetoresistive element MTJ, the relative relationship between the magnetization directions of the memory layer SL and the reference layer RL is antiparallel. In the case of the antiparallel state, the resistance value of the magnetoresistive element MTJ is the highest, and the magnetoresistive element MTJ is set to a high resistance state. The high resistance state is called the "AP (Anti-Parallel) state", which is defined as, for example, the state of data "1".

In addition, the method of defining data "1" and data "0" is not limited to the above example. For example, the P state can be defined as data "1" and the AP state can be defined as data "0".

1.2 Manufacturing method of memory device

The manufacturing method of the memory device 1 of the first embodiment is described using FIGS. 8 to 14. FIG. 8 is a flow chart showing an example of the manufacturing method of the contact plug CP1 in the memory device 1. FIGS. 9 to 14 are cross-sectional views showing an example of the cross-sectional structure in the manufacturing steps of the memory device 1. The following is described by taking the case of forming the contact plug CP1 of the region R0b to R2b in FIG. 4 as an example. The contact plug CP1 of the region R0b to R2b in FIG. 4 is shown in FIGS. 9 to 14. In addition, the semiconductor substrate 30, the insulating layer 31, the element 34, the element 35, the conductor 36, the contact plug CP2, and the conductor 38 are omitted in FIGS. 9 to 14.

As shown in FIG8 , in the manufacturing steps of the contact plug CP1, the processes S100 to S105 are performed in sequence. Below, referring to FIG8 , an example of the manufacturing steps of the contact plug CP1 is described.

First, as shown in FIG. 9 , a conductor 33a is formed that penetrates the insulating layer 42 and whose bottom surface reaches the conductor 32 (S100). More specifically, first, a hole is formed that penetrates the insulating layer 42 and whose bottom surface reaches the conductor 32. The hole corresponds to the contact plug CP1. Next, the conductor 33a is formed into a film in a manner of burying the hole. After that, the conductor 33a on the insulating layer 42 is removed by CMP (Chemical Mechanical Polishing) or the like.

Next, as shown in FIG. 10 , an anti-etching mask 43 for processing the conductor 33a of the region R2b is formed on the conductor 33a and the insulating layer 42 by photolithography or the like (S101). The opening of the anti-etching mask 43 is set in the region R2b. Therefore, the upper surface of the conductor 33a set in the region R2b is exposed (not covered by the anti-etching mask 43). The upper surface of the conductor 33a set in the regions R0b and R1b is covered by the anti-etching mask 43.

Next, as shown in FIG. 11 , the conductor 33a is processed by, for example, RIE (reactive ion etching) (S102). By S102, the upper portion of the conductor 33a in the region R2b is removed. The upper surface of the conductor 33a in the region R2b is located below the upper surface of the insulating layer 42. In addition, the conductor 33a can be processed by wet etching. After the conductor 33a is processed, the anti-etching agent mask 43 is peeled off.

Next, as shown in FIG. 12 , an anti-etching mask 44 for processing the conductor 33a in the region R2b and the conductor 33a in the region R1b is formed on the conductor 33a and the insulating layer 42 by photolithography or the like (S103). The opening of the anti-etching mask 44 is set in the regions R1b and R2b. Therefore, the upper surface of the conductor 33a set in the regions R1b and R2b is exposed (not covered by the anti-etching mask 44). The upper surface of the conductor 33a set in the region R0b is covered by the anti-etching mask 44.

Next, as shown in FIG. 13 , for example, the conductor 33a is processed by RIE (S104). By S104, the upper portion of each of the conductor 33a in the region R2b and the conductor 33a in the region R1b is removed. The upper surface of the conductor 33a in the region R1b is located below the upper surface of the insulating layer 42. The upper surface of the conductor 33a in the region R2b is located below the upper surface of the conductor 33a in the region R1b. That is, by S102 and S104, the conductor 33a in the region R2b is cut deeper than the conductor 33a in the region R1b. In addition, the conductor 33a can be processed by wet etching. After the conductor 33a is processed, the anti-etching agent mask 44 is peeled off.

Next, as shown in FIG. 14 , a conductor 33b is formed on the conductor 33a in the region R2b and the conductor 33a in the region R1b (S105). More specifically, the conductor 33b is formed into a film in such a manner as to bury the region where the conductor 33a is removed by S102 and S104. Thereafter, the conductor 33b on the insulating layer 42 is removed by CMP or the like.

In addition, generally speaking, since materials with lower resistivity are more compatible with RIE than materials with higher resistivity, the conductor 33a is preferably disposed below the conductor 33b.

When there are k bit lines BL (k is an integer greater than 1), photolithography and RIE for changing the ratio of the conductor 33b are repeated (k-1) times.

The contact plug CP1 is formed by the manufacturing steps described above. In addition, the manufacturing steps described above are ultimately just an example and are not limited to this. For example, other processes can be inserted between each manufacturing step, and some steps can be omitted or integrated. In addition, each manufacturing step can be replaced within a possible range.

1.3 Effects of this implementation form

According to the first implementation form, misreading can be reduced. This effect is described below.

As described above, the resistance value of the word line WL between the memory cell MC and the column selection circuit 14 is lower as the cell is closer to the column selection circuit 14. It is assumed that the resistance values of the plurality of contact plugs CP1 connected to the word line WL are the same. In this case, the resistance value of the wiring path formed by the word line WL and the contact plug CP1 from the column selection circuit 14 to the memory cell MC (hereinafter also described as "column selection circuit-inter-cell wiring path") changes according to the length of the word line WL from the column selection circuit 14 to the contact plug CP1. The time from when the write driver 19 starts to drive until the element 34 (switching element SEL) of the memory cell MC is turned on varies according to the resistance value of the column selection circuit-inter-cell wiring path. Therefore, the length of the time that the write driver 19 supplies the write current to the memory cell MC (hereinafter also referred to as "current supply time") varies according to the length of the word line WL.

The current supply time is longer for cells closer to the column selection circuit 14, and shorter for cells farther from the column selection circuit 14. In memory cells MC with shorter current supply time, i.e., cells farther from the column selection circuit 14, sometimes write failures due to insufficient current supply time occur. On the other hand, in memory cells MC with longer current supply time, i.e., cells closer to the column selection circuit 14, sometimes magnetoresistive element MTJ damage failures due to excessive current supply time occur.

To this end, in this embodiment, the resistance value of the contact plug CP1 is changed in accordance with the length of the word line WL from the column selection circuit 14 to the contact plug CP1. In other words, the resistance value of the contact plug CP1 is different in accordance with the configuration of the column selection circuit 14 and the memory cell MC.

More specifically, the contact plug CP1 of the region R0b includes the conductor 33a. The contact plug CP1 of each of the regions R1b to R4b includes the conductor 33a and the conductor 33b having a lower resistivity than the conductor 33a. The closer the contact plug CP1 is to the column selection circuit 14, the lower the ratio of the conductor 33b contained in the contact plug CP1. Thus, the closer the contact plug CP1 is to the column selection circuit 14, the higher the resistance value of the contact plug CP1 becomes. Therefore, in the region close to the column selection circuit 14, the resistance value of the word line WL becomes lower and the resistance value of the contact plug CP1 becomes higher than that of the region farther away. On the other hand, in the area far from the column selection circuit 14, the resistance value of the word line WL becomes higher and the resistance value of the contact plug CP1 becomes lower than that of the closer area. In this way, by combining the resistance value of the above-mentioned word line WL with the resistance value of the contact plug CP1, the change of the resistance value of the column selection circuit-inter-cell wiring path caused by the length of the word line WL can be suppressed. Therefore, the misreading of data can be reduced.

1.4 Variation 1

A memory device of the first variation of the first embodiment is described. In the memory device 1 of the first variation of the first embodiment, the distribution method of the ratio of the conductive body 33b contained in the contact plug CP1 is different from that of the first embodiment. In the following description, the description of the same structure as the first embodiment is omitted, and the description is mainly focused on the structure different from the first embodiment.

1.4.1 Structure of memory cell array

The structure of the memory cell array 10 is the same as that of the first embodiment.

The cross-sectional structure of the memory cell array 10 is described using FIG15 . FIG15 is a cross-sectional view along the I-I line of FIG3 . In addition, the insulating layer is omitted in the example shown in FIG15 .

As shown in FIG. 15 , the diameters of the contact plugs CP1 in each of the regions R0b to R4b are roughly the same. In addition, the cross-sectional shape of the contact plugs CP1 is not limited to a circle. Regardless of the cross-sectional shape of the contact plugs CP1, the contact areas of the contact plugs CP1 in each of the regions R0b to R4b and the word lines WL are roughly the same.

The regions R1b to R4b are divided into a group G0 including two adjacent regions R1b and R2b, and a group G1 including two adjacent regions R3b and R4b. The ratio of the conductive body 33b contained in the contact plug CP1 of each region R1b and R2b is the same. The ratio of the conductive body 33b contained in the contact plug CP1 of each region R3b and R4b is the same. The ratio of the conductive body 33b contained in the contact plug CP1 of each region R1b and R2b is lower than the ratio of the conductive body 33b contained in the contact plug CP1 of each region R3b and R4b. Thus, the ratio of the conductive body 33b contained in the contact plug CP1 of each of the groups G0 and G1 is lower as the contact plug CP1 of the group is closer to the column selection circuit 14. The height of the conductive body 33b contained in the contact plug CP1 of each of the groups G0 and G1 is lower as the contact plug CP1 of the group is closer to the column selection circuit 14. Therefore, the resistance value of the contact plug CP1 is higher as the contact plug CP1 of the group is closer to the column selection circuit 14. In addition, FIG. 15 is used to illustrate the case where each group includes two adjacent regions, but it is not limited to this. For example, each group may include more than three adjacent regions. In addition, the number of regions contained in the group may be different.

The rest of the cross-sectional structure of the memory cell array 10 is the same as that of the first embodiment.

1.4.2 Effect of this variation

According to this variation, the same effect as the first implementation form is achieved.

Furthermore, according to this variation, the ratio of the conductive body 33b contained in the contact plug CP1 is different for each group. Therefore, the ratio of the conductive body 33b contained in the contact plug CP1 does not need to be changed for each region R1b~R4b. Thus, compared with the case where the ratio of the conductive body 33b contained in the contact plug CP1 is changed individually, the types of contact plugs CP1 with different ratios of the conductive body 33b are reduced. Therefore, the number of repetitions of photolithography and RIE for changing the ratio of the conductive body 33b can be reduced. Therefore, the process cost can be reduced.

1.5 Variation 2

A memory device of the second variation of the first embodiment is described. In the memory device 1 of the second variation of the first embodiment, the material of the conductive bodies 33a and 33b contained in the contact plug CP1 is different from that of the first embodiment. In the following description, the description of the same structure as the first embodiment is omitted, and the description of the structure different from the first embodiment is mainly carried out.

1.5.1 Structure of memory cell array

The planar structure and cross-sectional structure of the memory cell array 10 are the same as those of the first embodiment.

In FIG. 4 , the conductors 33a and 33b are, for example, n-type semiconductors or p-type semiconductors. The conductors 33a and 33b include, for example, at least one of silicon and germanium. The conductors 33a and 33b include impurities (doping). The impurities are, for example, boron, phosphorus, arsenic, and indium. The concentration of impurities in the conductor 33b is higher than that in the conductor 33a. That is, the resistivity of the conductor 33b is lower than that of the conductor 33a. Therefore, the resistance value of the contact plug CP1 is higher as the contact plug CP1 is disposed closer to the column selection circuit 14.

1.5.2 Manufacturing method of memory device

The manufacturing method of the memory device 1 of the second variation of the first embodiment is explained using FIGS. 16 to 18. FIG. 16 is a flow chart showing an example of the manufacturing method of the contact plug CP1 in the memory device 1. FIGS. 17 and 18 are cross-sectional views showing an example of the cross-sectional structure in the manufacturing steps of the memory device 1. In the manufacturing method of the contact plug CP1 in the memory device 1 of the second variation of the first embodiment, S102 and S104 of FIG. 8 of the first embodiment are replaced with S106 and S107. Furthermore, S105 of FIG. 8 of the first embodiment is eliminated. S100, S101, and S103 are the same as the first embodiment. The following explanation focuses on S106 and S107.

Below, it is appropriate to refer to Figure 16 to explain an example of the manufacturing steps of the contact plug CP1.

A conductor 33a with a lower impurity concentration is formed in S100, and an anti-etching agent mask 43 is formed in S101. Thereafter, as shown in FIG. 17, ion implantation of impurities is performed into the conductor 33a of the region R2b (S106). Thus, a conductor 33b with a higher impurity concentration than the conductor 33a is formed on the upper portion of the conductor 33a of the region R2b. If the impurity concentration of the conductor 33a of each region R0b~R2b is set to concentration D10a~D12a respectively, the concentrations D10a~D12a are the same. After the ion implantation, the anti-etching agent mask 43 is peeled off.

In S103, an anti-etching agent mask 44 is formed. Thereafter, as shown in FIG. 18, ion implantation of impurities is performed into each of the conductor 33a in the region R2b and the conductor 33a in the region R1b (S107). At this time, the acceleration voltage used for the ion implantation is lower than the acceleration voltage used for the ion implantation in S106. As a result, the depth of the ion implantation into the conductor 33a in the region R1b is shallower than the depth of the ion implantation into the conductor 33a in the region R2b in S106. As a result, a conductor 33b having a higher impurity concentration than the conductor 33a is formed on the upper portion of each of the conductor 33a in the region R2b and the conductor 33a in the region R1b. If the concentration of impurities in the conductor 33b of the region R2b is set to D12b, the concentration D12b is higher than the concentration D12a. If the concentration of impurities in the conductor 33b of the region R1b is set to D11b, the concentration D11b is higher than the concentration D11a. In addition, the concentration D12b may be the same as the concentration D11b or may be different. After the ion implantation, the anti-etching agent mask 44 is peeled off.

Through S106 and S107, the closer the contact plug CP1 is to the column selection circuit 14, the lower the ratio of the conductive body 33b contained in the contact plug CP1. The closer the contact plug CP1 is to the column selection circuit 14, the lower the height of the conductive body 33b contained in the contact plug CP1.

1.5.3 Effect of this variation

According to this variation, the same effect as the first embodiment is achieved. Of course, the first variation of the first embodiment can also be applied to the contact plug CP1 included in the memory device 1 of this variation.

1.6 Variation 3

The memory device of the third variation of the first embodiment is described. In the memory device 1 of the third variation of the first embodiment, the structure of the contact plug CP1 is different from that of the second variation of the first embodiment. In the following description, the description of the same structure as the second variation of the first embodiment is omitted, and the description is mainly focused on the structure that is different from the second variation of the first embodiment.

1.6.1 Structure of memory cell array

The planar structure of the memory cell array 10 is the same as the second variation of the first embodiment.

The cross-sectional structure of the memory cell array 10 is described using FIG19 . FIG19 is a cross-sectional view along the I-I line of FIG3 . In addition, the insulating layer is omitted in the example shown in FIG19 .

As shown in FIG. 19, the contact plug CP1 of the region R0b includes a conductor 33a. The contact plug CP1 of the region R1b includes a conductor 33b1. The contact plug CP1 of the region R2b includes a conductor 33b2. The contact plug CP1 of the region R3b includes a conductor 33b3. The contact plug CP1 of the region R4b includes a conductor 33b4. The conductors 33a and 33b1 to 33b4 are made of the same material as the second variation of the first embodiment. The conductors 33a and 33b1 to 33b4 are, for example, n-type semiconductors or p-type semiconductors. The conductors 33a and 33b1 to 33b4 include, for example, at least one of silicon and germanium. Conductors 33a and 33b1 to 33b4 contain impurities (dopings). The impurities are made of the same material as the second variation of the first embodiment.

The diameters of the contact plugs CP1 in each of the regions R0b~R4b are roughly the same. In addition, the cross-sectional shape of the contact plugs CP1 is not limited to a circle. Regardless of the cross-sectional shape of the contact plugs CP1, the contact areas of the contact plugs CP1 in each of the regions R0b~R4b and the word lines WL are roughly the same.

If the concentration of impurities in the contact plugs CP1 (conductors 33a, and 33b1-33b4) of each region R0b-R4b is set to concentrations D10a and D11b-D14b, respectively, then concentration D10a is lower than concentration D11b. Concentration D11b is lower than concentration D12b. Concentration D12b is lower than concentration D13b. Concentration D13b is lower than concentration D14b. Thus, the concentration of impurities in the contact plugs CP1 of each region R0b-R4b is lower as the contact plugs CP1 are located closer to the column selection circuit 14. For example, for the contact plugs CP1 (conductors 33b1~33b4) of each region R1b~R4b, the acceleration voltage used for ion injection is set to the same voltage. The closer the contact plug CP1 is to the column selection circuit 14, the less ion injection amount can be reduced. Therefore, the resistance value of the contact plug CP1 is higher when the contact plug CP1 is located closer to the column selection circuit 14.

The rest of the cross-sectional structure of the memory cell array 10 is the same as the second variation of the first embodiment.

When there are k bit lines BL (k is an integer greater than 1), ion implantation for changing the impurity concentration is repeated (k-1) times.

1.6.2 Effect of this variation

According to this variation, the same effect as the first implementation form is achieved.

1.7 Variation 4

The memory device of the fourth variation of the first embodiment is described. In the memory device 1 of the fourth variation of the first embodiment, the method of distributing the concentration of impurities in the contact plug CP1 is different from that in the third variation of the first embodiment. In the following description, the description of the same structure as the third variation of the first embodiment is omitted, and the description is mainly focused on the structure different from the third variation of the first embodiment.

1.7.1 Structure of memory cell array

The planar structure of the memory cell array 10 is the same as the third variation of the first embodiment.

The cross-sectional structure of the memory cell array 10 is described using FIG20 . FIG20 is a cross-sectional view along the I-I line of FIG3 . In addition, the insulating layer is omitted in the example shown in FIG20 .

As shown in FIG. 20 , the diameters of the contact plugs CP1 in each of the regions R0b to R4b are roughly the same. In addition, the cross-sectional shape of the contact plugs CP1 is not limited to a circle. Regardless of the cross-sectional shape of the contact plugs CP1, the contact areas of the contact plugs CP1 in each of the regions R0b to R4b and the word lines WL are roughly the same.

The regions R1b to R4b are divided into a group G0 including two adjacent regions R1b and R2b, and a group G1 including two adjacent regions R3b and R4b. The impurity concentrations D11b and D12b of the contact plugs CP1 (conductors 33b1 and 33b2) of the regions R1b and R2b are the same. The impurity concentrations D13b and D14b of the contact plugs CP1 (conductors 33b3 and 33b4) of the regions R3b and R4b are the same. The concentration D10a is lower than the concentrations D11b and D12b. The concentrations D11b and D12b are lower than the concentrations D13b and D14b. Thus, the concentration of impurities in the contact plugs CP1 in the groups G0 and G1 is lower as the contact plugs CP1 of the groups are closer to the column selection circuit 14. Therefore, the resistance value of the contact plugs CP1 is higher as the contact plugs CP1 of the groups are closer to the column selection circuit 14. In addition, FIG. 20 is used to illustrate the case where each group includes two adjacent regions, but it is not limited to this. For example, each group may include more than three adjacent regions. In addition, the number of regions contained in the groups may be different.

The rest of the cross-sectional structure of the memory cell array 10 is the same as the third variation of the first embodiment.

1.7.2 Effect of this variation

According to this variation, the same effect as the first implementation form is achieved.

Furthermore, according to this variation, the concentration of impurities in the contact plug CP1 is different for each group. Therefore, the concentration of impurities in the contact plug CP1 does not need to be changed for each region R1b~R4b. Thus, compared with the case where the concentration of impurities in the contact plug CP1 is changed individually, the types of contact plugs CP1 with different impurity concentrations are reduced. Therefore, the number of repetitions of ion implantation for changing the concentration of impurities can be reduced. Therefore, the process cost can be reduced.

2. Second implementation form

The memory device of the second embodiment is described. In the memory device 1 of the second embodiment, the structure of the contact plug CP1 is different from that of the first embodiment. In the following description, the description of the same structure as the first embodiment is omitted, and the description is mainly focused on the structure different from the first embodiment.

2.1 Structure of memory cell array

The planar structure of the memory cell array 10 is the same as that of the first embodiment.

The cross-sectional structure of the memory cell array 10 is described using FIG21. FIG21 is a cross-sectional view along the I-I line of FIG3. In addition, the insulating layer is omitted in the example shown in FIG21.

As shown in FIG. 21 , the contact plug CP1 of each of the regions R0b to R4b includes a conductor 33a. The conductor 33a is made of the same material as that of the first embodiment.

If the diameters of the contact plugs CP1 of the regions R0b to R4b are set to diameters dm0 to dm4, respectively, the diameter dm0 is smaller than the diameter dm1. The diameter dm1 is smaller than the diameter dm2. The diameter dm2 is smaller than the diameter dm3. The diameter dm3 is smaller than the diameter dm4. In addition, the shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circle. For example, the shape of the cross section of the contact plug CP1 may be an ellipse or a rectangle. Regardless of the cross-sectional shape of the contact plug CP1, the contact area of the contact plug CP1 in each region R0b~R4b and the word line WL is smaller the closer the contact plug CP1 is to the column selection circuit 14. Therefore, the resistance value of the contact plug CP1 is higher the closer the contact plug CP1 is to the column selection circuit 14.

The length of the word line WL from the column selection circuit 14 to the contact plug CP1 set in the region R0b is shorter than the length of the word line WL from the column selection circuit 14 to the contact plug CP1 set in the region R1b. The length of the word line WL from the column selection circuit 14 to the contact plug CP1 set in the region R1b is shorter than the length of the word line WL from the column selection circuit 14 to the contact plug CP1 set in the region R2b. The same applies to the following.

The rest of the cross-sectional structure of the memory cell array 10 is the same as that of the first embodiment.

2.2 Effects of this implementation form

According to the second implementation form, the same effect as the first implementation form is achieved.

2.3 Variations

A memory device of a variation of the second embodiment is described. In the memory device 1 of the variation of the second embodiment, the method of allocating the diameter of the contact plug CP1 is different from that of the second embodiment. In the following description, the description of the same structure as the second embodiment is omitted, and the description is mainly focused on the structure different from the second embodiment.

2.3.1 Structure of memory cell array

The planar structure of the memory cell array 10 is the same as that of the second embodiment.

The cross-sectional structure of the memory cell array 10 is described using FIG22. FIG22 is a cross-sectional view along the I-I line of FIG3. In addition, the insulating layer is omitted in the example shown in FIG22.

As shown in FIG. 22 , regions R1b to R4b are divided into a group G0 including two adjacent regions R1b and R2b, and a group G1 including two adjacent regions R3b and R4b. The diameters dm1 and dm2 of the contact plugs CP1 of each region R1b and R2b are the same. The diameters dm3 and dm4 of the contact plugs CP1 of each region R3b and R4b are the same. The diameter dm0 is smaller than the diameters dm1 and dm2. The diameters dm1 and dm2 are smaller than the diameters dm3 and dm4. Thus, the diameters of the contact plugs CP1 of each group G0 and G1 are smaller as the contact plugs CP1 of the group are closer to the column selection circuit 14. In addition, the cross-sectional shape of the contact plug CP1 is not limited to a circle. Regardless of the cross-sectional shape of the contact plug CP1, the contact area of each of the groups G0 and G1 that contacts the word line WL is smaller the closer the contact plug CP1 of the group is to the column selection circuit 14. Therefore, the resistance value of the contact plug CP1 is higher the closer the contact plug CP1 of the group is to the column selection circuit 14. In addition, FIG. 22 is used to illustrate the situation where each group includes two adjacent regions, but it is not limited to this. For example, each group may include more than three adjacent regions. In addition, the number of regions contained in the group may be different.

The rest of the cross-sectional structure of the memory cell array 10 is the same as that of the second embodiment.

2.3.2 Effect of this change

According to this variation, the same effect as the first implementation form is achieved.

Furthermore, according to this variation, the diameter of the contact plug CP1 is different for each group. The structure in which all contact plugs CP1 have different diameters may complicate the manufacturing steps, but according to this variation, this concern is eliminated.

3. The third implementation form

A memory device of the third embodiment is described. In the memory device 1 of the third embodiment, the configuration of the word line WL, the contact plugs CP1 and CP2, and the bit line BL is different from that of the first embodiment. In the following description, the description of the same structure as the first embodiment is omitted, and the description is mainly focused on the structure different from the first embodiment.

3.1 Structure of memory cell array

An example of the structure of the memory cell array 10 is described.

(Plane structure)

FIG. 23 is used to explain the planar structure of the memory cell array 10. FIG. 23 is a top view showing an example of the planar structure of the memory cell array 10. FIG. 23 shows the word lines WL between the plurality of memory cells MC and the column selection circuit 14 in the memory cell array 10, and the bit lines BL between the plurality of memory cells MC and the row selection circuit 15. In addition, in FIG. 23, the word lines WL<5>~WL<M>, the bit lines BL<5>~BL<N>, and the plurality of memory cells MC corresponding thereto are omitted.

As shown in FIG. 23 , in the memory cell array 10, for example, the memory cell MC is arranged above the bit line BL. The word line WL is arranged above the memory cell MC.

(Section structure)

The cross-sectional structure of the memory cell array 10 is described using Figures 24 to 26. Figure 24 is a cross-sectional view along the I-I line of Figure 23. Figure 25 is a cross-sectional view along the II-II line of Figure 23. Figure 26 is a three-dimensional view of a portion of the memory cell array 10. In addition, in the examples shown in Figures 24 to 26, the insulating layer is omitted.

As shown in FIGS. 24 to 26 , a plurality of conductors 38 are disposed on the semiconductor substrate 30, for example, via an insulating layer 31. The plurality of conductors 38 are arranged, for example, in the X direction, and each extends in the Y direction. In addition, the semiconductor substrate 30 and the insulating layer 31 are omitted in FIG. 26 .

A plurality of contact plugs CP2 are provided on the upper surface of a conductor 38. The plurality of contact plugs CP2 provided on the upper surface of a conductor 38 are arranged, for example, in the Y direction. The contact plug CP2 includes a conductor 37a.

Component 34 is disposed on the upper surface of contact plug CP2.

A contact plug CP1 is provided on the upper surface of the conductor 36. The contact plug CP1 of the region R0b includes the conductor 33a. The contact plug CP1 of each of the regions R1b to R4b includes conductors 33a and 33b. The conductors 33a and 33b are made of the same material as the first embodiment.

The diameter of the contact plug CP1 in each of the regions R0b~R4b is roughly the same. In addition, the shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circle. For example, the cross section of the contact plug CP1 may be an ellipse or a rectangle. Regardless of the cross section of the contact plug CP1, the contact area of the contact plug CP1 in each of the regions R0b~R4b and the word line WL is roughly the same.

The ratio of the conductive body 33b contained in the contact plug CP1 of each region R1b~R4b is lower as the contact plug CP1 is disposed in a region closer to the column selection circuit 14. The height of the conductive body 33b contained in the contact plug CP1 of each region R1b~R4b is lower as the contact plug CP1 is disposed in a region closer to the column selection circuit 14. The conductive body 33b is disposed on the conductive body 33a. In addition, the conductive body 33a may be disposed on the conductive body 33b. Furthermore, the contact plug CP1 of each region R1b~R4b may be composed of three or more conductive bodies having different resistivities. The conductive bodies 33a and 33b may include two or more materials.

A conductor 32 is provided on the upper surface of the contact plug CP1. For example, a plurality of conductors 32 are arranged in the Y direction and each extends in the X direction. For example, a plurality of contact plugs CP1 arranged in the X direction are connected to one conductor 32.

As shown in FIG26 , a memory cell MC is provided at each intersection of the conductor 32 and the conductor 38.

3.2 Effects of this implementation form

According to the third embodiment, the same effect as the first embodiment is achieved. Of course, the first to fourth variations of the first embodiment can be applied to the contact plug CP1 included in the memory device 1 of this embodiment.

4. Implementation form 4

The memory device of the fourth embodiment is described. In the memory device 1 of the fourth embodiment, the structure of the contact plug CP1 is different from that of the third embodiment. In the following description, the description of the same structure as the third embodiment is omitted, and the description is mainly focused on the structure different from the third embodiment.

4.1 Structure of memory cell array

The planar structure of the memory cell array 10 is the same as that of the third embodiment.

The cross-sectional structure of the memory cell array 10 is described using FIG27. FIG27 is a cross-sectional view along the I-I line of FIG23. In addition, the insulating layer is omitted in the example shown in FIG27.

As shown in FIG. 27 , the contact plug CP1 of each of the regions R0b to R4b includes a conductor 33a. The conductor 33a is made of the same material as that of the second embodiment.

The diameter dm0 is smaller than the diameter dm1. The diameter dm1 is smaller than the diameter dm2. The diameter dm2 is smaller than the diameter dm3. The diameter dm3 is smaller than the diameter dm4. In addition, the shape of the cross section (XY cross section) of the contact plug CP1 is not limited to a circle. For example, the cross section of the contact plug CP1 may be an ellipse or a rectangle. Regardless of the cross section of the contact plug CP1, the area of contact between the contact plug CP1 and the word line WL in each of the regions R0b~R4b is smaller the closer the contact plug CP1 is to the column selection circuit 14.

The rest of the cross-sectional structure of the memory cell array 10 is the same as that of the third embodiment.

4.2 Effects of this implementation form

According to the fourth embodiment, the same effect as the first embodiment is achieved. Of course, the variation of the second embodiment can also be applied to the contact plug CP1 included in the memory device 1 of this embodiment.

5. Fifth implementation form

The memory device of the fifth embodiment is described. In the memory device 1 of the fifth embodiment, the structure of the contact plug CP2 is different from that of the first embodiment. In the following description, the description of the same structure as the first embodiment is omitted, and the description is mainly focused on the structure different from the first embodiment.

5.1 Structure of memory cell array

The planar structure of the memory cell array 10 is the same as that of the first embodiment.

The cross-sectional structure of the memory cell array 10 is described using FIG. 28 and FIG. 29 . FIG. 28 is a cross-sectional view along the I-I line of FIG. 3 . FIG. 29 is a cross-sectional view along the II-II line of FIG. 3 . In addition, in the examples shown in FIG. 28 and FIG. 29 , the insulating layer is omitted.

As shown in FIG. 28 and FIG. 29, the contact plug CP2 of the region R4w includes a conductor 37a. The contact plug CP2 of each of the regions R0w to R3w includes conductors 37a and 37b. The conductor 37a is made of the same material as the conductor 33a. The conductor 37b is made of the same material as the conductor 33b.

The diameter of the contact plug CP2 in each region R0w~R4w is roughly the same. In addition, the shape of the cross section (XY cross section) of the contact plug CP2 is not limited to a circle. For example, the cross section of the contact plug CP2 can be an ellipse or a rectangle. Regardless of the shape of the cross section of the contact plug CP2, the area of contact between the contact plug CP2 in each region R0w~R4w and the word line WL is roughly the same.

The ratio of the conductive body 37b contained in the contact plug CP2 of each region R0w~R3w is lower as the contact plug CP2 is disposed in a region closer to the row selection circuit 15. The height of the conductive body 37b contained in the contact plug CP2 of each region R0w~R3 is lower as the contact plug CP2 is disposed in a region closer to the row selection circuit 15. Therefore, the resistance value of the contact plug CP2 is higher as the contact plug CP2 is disposed in a region closer to the row selection circuit 15. The conductive body 37b is disposed on the conductive body 37a. In addition, the conductive body 37a may be disposed on the conductive body 37b. Furthermore, the contact plug CP2 of each region R0w~R3w can be composed of three or more conductors with different resistivity. The conductors 37a and 37b can include two or more materials.

The length of the bit line BL from the self-selection circuit 15 to the contact plug CP2 set in the region R4w is shorter than the length of the bit line BL from the self-selection circuit 15 to the contact plug CP2 set in the region R3w. The length of the bit line BL from the self-selection circuit 15 to the contact plug CP2 set in the region R3w is shorter than the length of the bit line BL from the self-selection circuit 15 to the contact plug CP2 set in the region R2w. The same applies to the following.

The rest of the cross-sectional structure of the memory cell array 10 is the same as that of the first embodiment.

5.2 Effects of this implementation form

According to the fifth implementation form, the same effect as the first implementation form is achieved.

Furthermore, as described in the first embodiment, the resistance value of the bit line BL between the memory cell MC and the row selection circuit 15 is lower as the cell is closer to the row selection circuit 15. It is assumed that the resistance values of the plurality of contact plugs CP2 connected to the bit line BL are the same. In this case, the resistance value of the wiring path formed by the bit line BL and the contact plug CP2 from the self-selection circuit 15 to the memory cell MC (hereinafter also described as "row selection circuit-inter-cell wiring path") changes according to the length of the bit line BL from the self-selection circuit 15 to the contact plug CP2.

According to this embodiment, by combining the resistance value of the bit line BL and the resistance value of the contact plug CP2, the change in the resistance value of the row selection circuit-inter-cell wiring path caused by the length of the bit line BL can be suppressed.

Of course, the first to fourth variations of the first embodiment, as well as the second embodiment and variations of the second embodiment can also be applied to the contact plugs CP1 and CP2 included in the memory device 1 of this embodiment.

6. Implementation form of Article 6

The memory device of the sixth embodiment is described. In the memory device 1 of the sixth embodiment, the structure of the contact plug CP2 is different from that of the third embodiment. In the following description, the description of the same structure as the third embodiment is omitted, and the description is mainly focused on the structure different from the third embodiment.

6.1 Structure of memory cell array

The planar structure of the memory cell array 10 is the same as that of the third embodiment.

The cross-sectional structure of the memory cell array 10 is described using FIG. 30 and FIG. 31 . FIG. 30 is a cross-sectional view along the I-I line of FIG. 23 . FIG. 31 is a cross-sectional view along the II-II line of FIG. 23 . In addition, in the examples shown in FIG. 30 and FIG. 31 , the insulating layer is omitted.

As shown in FIG. 30 and FIG. 31 , the contact plug CP2 of the region R4w includes a conductor 37a. The contact plug CP2 of each of the regions R0w to R3w includes conductors 37a and 37b. The conductor 37a is made of the same material as the conductor 33a. The conductor 37b is made of the same material as the conductor 33b.

The diameter of the contact plug CP2 of each region R0w~R4w is roughly the same. In addition, the shape of the cross section (XY cross section) of the contact plug CP2 is not limited to a circle. For example, the cross section of the contact plug CP2 can be an ellipse or a rectangle. Regardless of the cross section of the contact plug CP2, the area of contact between the contact plug CP2 of each region R0w~R4w and the word line WL is roughly the same.

The ratio of the conductive body 37b contained in the contact plug CP2 of each region R0w~R3w is lower when the contact plug CP2 is disposed in a region close to the row selection circuit 15. The height of the conductive body 37b contained in the contact plug CP2 of each region R0w~R3w is lower when the contact plug CP2 is disposed in a region close to the row selection circuit 15. The conductive body 37b is disposed on the conductive body 37a. In addition, the conductive body 37a can be disposed on the conductive body 37b. In addition, the contact plug CP2 of each region R0w~R3w can be composed of three or more conductive bodies with different resistivities. The conductive bodies 37a and 37b can include two or more materials.

The length of the bit line BL from the self-selection circuit 15 to the contact plug CP2 set in the region R4w is shorter than the length of the bit line BL from the self-selection circuit 15 to the contact plug CP2 set in the region R3w. The length of the bit line BL from the self-selection circuit 15 to the contact plug CP2 set in the region R3w is shorter than the length of the bit line BL from the self-selection circuit 15 to the contact plug CP2 set in the region R2w. The same applies to the following.

The rest of the cross-sectional structure of the memory cell array 10 is the same as that of the third embodiment.

6.2 Effects of this implementation form

According to the sixth embodiment, the same effect as the first embodiment is achieved. Furthermore, according to this embodiment, the same effect as the fifth embodiment is achieved. Of course, the first to fourth variations of the first embodiment, as well as the second embodiment and the variation of the second embodiment can also be applied to the contact plugs CP1 and CP2 included in the memory device 1 of this embodiment.

7. Variations, etc.

As described above, the memory device of the embodiment comprises: a first memory cell (MC), a second memory cell (MC), a first circuit (14) for supplying write current to the first memory cell and the second memory cell, a first wiring (WL) connected to the first circuit, a first plug (CP1) electrically connecting the first memory cell and the first wiring, and a second plug (CP1) electrically connecting the second memory cell and the first wiring. The length of the first wiring (WL) from the first circuit to the first plug is shorter than the length of the first wiring (WL) from the first circuit to the second plug. The resistance value of the first plug (CP1) is higher than the resistance value of the second plug (CP1).

In addition, the implementation form is not limited to the form described above, and various changes can be made.

Furthermore, the flowchart described in the above embodiment may change the order of the processing as much as possible.

In addition, in each of the above-mentioned embodiments, the structure (referred to as a single-layer structure) in which a memory cell MC can be selected by a combination of a word line WL and a bit line BL is mainly described, but the present invention is not limited to this. For example, any array structure such as an array structure in which a plurality of such structures are stacked in the Z direction can be applied.

Several embodiments of the present invention are described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms and can be omitted, replaced, and changed in various ways without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the scope of the invention described in the patent application and its equivalents.

[References to related applications]

This invention application enjoys the priority of Japanese Patent Application No. 2022-044000 (filing date: March 18, 2022) and U.S. Patent Application No. 17/843084 (filing date: June 17, 2022) as the basic application. This invention application includes all the contents of the basic application by reference to the basic application.

10: Memory cell array

30:Semiconductor substrate

31: Insulation layer

32,33a,33b,36,37a,38: Conductor

34,35: Components

BL<0>~BL<4>: bit line

CP1, CP2: contact plug

MC: Memory Cell

MTJ: Magnetic Tunnel Junction

R0b~R4b: Area

SEL: Switching element

WL<0>: character line

X,Y: direction

Z: Direction/Axis

Claims (20)

A memory device, comprising: a first memory cell; a second memory cell; a first circuit, which supplies a write current to the first memory cell and the second memory cell; a first wiring, which is connected to the first circuit; a first plug, which electrically connects the first memory cell and the first wiring and is disposed between the first memory cell and the first wiring; and a second plug, which electrically connects the second memory cell and the first wiring and is disposed between the second memory cell and the first wiring; and the length of the first wiring from the first circuit to the first plug is shorter than the length of the first wiring from the first circuit to the second plug; and the resistance value of the first plug is higher than the resistance value of the second plug. A memory device as claimed in claim 1, wherein the first plug comprises a first conductor and a second conductor; the second plug comprises a third conductor and a fourth conductor; the resistivity of the second conductor is lower than the resistivity of the first conductor; the resistivity of the fourth conductor is lower than the resistivity of the third conductor; the ratio of the second conductor contained in the first plug is lower than the ratio of the fourth conductor contained in the second plug. A memory device as claimed in claim 2, wherein the first conductor and the third conductor include at least one of tungsten, tungsten nitride, titanium, titanium nitride, carbon, and polycrystalline silicon; and the second conductor and the fourth conductor include at least one of copper and aluminum. A memory device as claimed in claim 2, wherein the first conductor and the third conductor include at least one of carbon and polysilicon; and the second conductor and the fourth conductor include at least one of tungsten, tungsten nitride, titanium, and titanium nitride. A memory device as claimed in claim 2, wherein the first conductor and the third conductor include a first semiconductor; and the second conductor and the fourth conductor include a second semiconductor; and the impurity concentration of the first semiconductor is lower than the impurity concentration of the second semiconductor. A memory device as claimed in claim 2, wherein the second conductor is disposed on the first conductor; and the fourth conductor is disposed on the third conductor. A memory device as claimed in claim 1, wherein the first plug comprises a first semiconductor; and the second plug comprises a second semiconductor; and the impurity concentration of the first semiconductor is lower than the impurity concentration of the second semiconductor. A memory device as claimed in claim 1, wherein the area of contact between the first plug and the first wiring is smaller than the area of contact between the second plug and the first wiring. A memory device as claimed in claim 8, wherein the cross-sectional shape of the first plug and the second plug is circular. A memory device as claimed in claim 9, wherein the diameter of the first plug is smaller than the diameter of the second plug. A memory device as claimed in claim 1, wherein the first memory cell and the second memory cell are arranged above the first wiring. A memory device as claimed in claim 1, wherein the first wiring is arranged above the first memory cell and the second memory cell. The memory device of claim 1 further comprises: a third memory cell; a fourth memory cell; a third plug electrically connecting the third memory cell to the first wiring; and a fourth plug electrically connecting the fourth memory cell to the first wiring; and the length of the first wiring from the first circuit to the third plug is greater than the length of the first wiring from the first circuit to the first plug. The length of the first wiring from the first circuit to the second plug is longer and shorter than the length of the first wiring from the first circuit to the fourth plug; the length of the first wiring from the first circuit to the fourth plug is longer than the length of the first wiring from the first circuit to the second plug; The resistance value of the third plug is equal to the resistance value of the first plug; the resistance value of the fourth plug is equal to the resistance value of the second plug. A memory device as claimed in claim 13, wherein the first plug comprises a first conductor and a second conductor; the second plug comprises a third conductor and a fourth conductor; the third plug comprises a fifth conductor and a sixth conductor; the fourth plug comprises a seventh conductor and an eighth conductor; the resistivity of the second conductor is lower than the resistivity of the first conductor; the resistivity of the fourth conductor is lower than the resistivity of the third conductor; the ratio of the second conductor contained in the first plug is lower than the ratio of the fourth conductor contained in the second plug; The resistivity of the fifth conductor is equal to the resistivity of the first conductor; the resistivity of the sixth conductor is equal to the resistivity of the second conductor; the resistivity of the seventh conductor is equal to the resistivity of the third conductor; the resistivity of the eighth conductor is equal to the resistivity of the fourth conductor; the ratio of the sixth conductor contained in the third plug is equal to the ratio of the second conductor contained in the first plug; the ratio of the eighth conductor contained in the fourth plug is equal to the ratio of the fourth conductor contained in the second plug. A memory device as claimed in claim 13, wherein the area of the first plug contacting the first wiring is smaller than the area of the second plug contacting the first wiring; and the area of the third plug contacting the first wiring is equal to the area of the first plug contacting the first wiring; and the area of the fourth plug contacting the first wiring is equal to the area of the second plug contacting the first wiring. The memory device of claim 1 further comprises: a fifth memory cell; a sixth memory cell; a second circuit for supplying write current to the fifth memory cell and the sixth memory cell; a second wiring connected to the second circuit; a fifth plug for electrically connecting the fifth memory cell and the second wiring; and a sixth plug for electrically connecting the sixth memory cell and the second wiring; and the length of the second wiring from the second circuit to the fifth plug is shorter than the length of the second wiring from the second circuit to the sixth plug; and the resistance value of the fifth plug is higher than the resistance value of the sixth plug. A memory device as claimed in claim 16, wherein the second wiring is arranged above the fifth memory cell and the sixth memory cell. A memory device as claimed in claim 16, wherein the fifth memory cell and the sixth memory cell are arranged above the second wiring. A memory device as claimed in claim 1, wherein the first memory cell and the second memory cell comprise variable resistance elements. A memory device as claimed in claim 19, wherein the variable resistance element is a magnetoresistive element.