TWI879865B - Manufacturing method for metal filled microstructure - Google Patents

Abstract

The present invention provides a method for manufacturing a metal-filled microstructure, which suppresses metal filling defects in a plurality of fine pores when metal is filled into the plurality of fine pores. The method for manufacturing a metal-filled microstructure comprises: a process of providing an insulating film having a plurality of fine pores on the surface of a metal component to obtain a structure having a metal component and an insulating film; and a plating process, in which metal plating is performed on a surface of at least one side of the structure having the insulating film in a supercritical state or a subcritical state to fill the plurality of fine pores with metal. At the start of the plating process, a metal layer other than the valve metal exists at the bottom of the pores of the structure, and the metal layer other than the valve metal is formed in an area of more than 80% of the area of the bottom of the pores.

Description

Method for manufacturing metal-filled microstructure

The present invention relates to a method for manufacturing a metal-filled microstructure, wherein a plurality of pores of an oxide film are filled with metal, and more particularly, to a method for manufacturing a metal-filled microstructure, wherein metal plating is performed under a supercritical state or a subcritical state, thereby filling the plurality of pores with metal.

Metal-filled microstructures, which are multiple through holes that penetrate the thickness direction of an insulating substrate such as an oxide film and are filled with metal, are one of the areas that have received attention in nanotechnology in recent years. Metal-filled microstructures are expected to be used in battery electrodes, breathable films, sensors, and anisotropic conductive components. Anisotropic conductive components are inserted between electronic parts such as semiconductor elements and circuit boards, and electrical connections between electronic parts and circuit boards are obtained simply by applying pressure. Therefore, they are widely used as electrical connection components for electronic parts such as semiconductor elements and connectors for inspection during functional inspections. In particular, the miniaturization of electronic parts such as semiconductor elements is remarkable. In conventional methods of directly connecting wiring substrates such as wire bonding, flip chip bonding, and thermocompression bonding, the stability of the electrical connection of electronic parts cannot be sufficiently guaranteed. Therefore, anisotropic conductive members have attracted much attention as electronic connection members.

In the manufacturing method of the above-mentioned metal-filled microstructure, a plating method is used when metal is filled into a plurality of through holes. As the plating method, electroplating or electroless plating is used. In addition, for example, as described in Patent Document 1, there is an electroplating method as follows: a plating solution and a surfactant are added to and dispersed in an amount greater than that of insoluble metal powder, including at least one of carbon dioxide and an inert gas, and electroplating is performed in a supercritical state or a subcritical state using an induced eutectoid phenomenon. In addition, the metal powder is the same type of metal as the metal substrate and at least one of the metal films obtained by electroplating. Furthermore, as described in Patent Document 2, there is also a method in which, when filling the pores with magnetic material, a supercritical fluid or subcritical fluid containing magnetic particles is used, and the supercritical fluid or subcritical fluid is made to flow into the pores to fill the pores with magnetic material.

[Patent document 1] Japanese Patent No. 4163728 [Patent document 2] Japanese Patent Publication No. 2008-305443

In the metal-filled microstructure, the possibility of filling defects such as failure to fully fill all pores with metal needs to be considered. In the above-mentioned patent documents 1 and 2, although the supercritical state or subcritical state is used, it may not be possible to fully fill all pores with metal only by using the supercritical state or subcritical state.

An object of the present invention is to provide a method for manufacturing a metal-filled microstructure, which method can suppress metal filling defects in a plurality of fine pores when metal is filled in the plurality of fine pores.

In order to achieve the above-mentioned purpose, the first aspect of the present invention provides a method for manufacturing a metal-filled microstructure, which comprises: a process of providing an insulating film having a plurality of pores on the surface of a metal component to obtain a structure having a metal component and an insulating film; and a plating process, in which metal plating is performed on a surface of at least one side of the structure having the insulating film under a supercritical state or a subcritical state to fill a plurality of pores with metal, and at the beginning of the plating process, a metal layer other than the valve metal exists at the bottom of the pores of the structure, and a metal layer other than the valve metal is formed in an area of more than 80% of the area at the bottom of the pores.

Between the process of obtaining the structure and the plating process, there is a process of forming a metal layer other than the valve metal at the bottom of the pores. The plating process is preferably carried out in a state where a metal layer other than the valve metal is formed on an area of more than 80% of the area at the bottom of the pores at the start of the plating process. The metal component is made of a metal other than the valve metal, and the metal component is preferably exposed at the bottom of the pores. The average diameter of the plurality of pores is preferably 1 μm or less. The insulating film is preferably an oxide film. The oxide film is preferably an anodic oxide film of aluminum. The metal layer other than the valve metal is preferably made of a metal having a higher potential than aluminum. The metal component is preferably made of a noble metal or a valve metal. [Effect of the invention]

According to the present invention, when metal is filled into a plurality of fine holes, metal filling defects in the plurality of fine holes can be suppressed.

Hereinafter, the manufacturing method of the metal-filled microstructure of the present invention will be described in detail according to the preferred embodiment shown in the drawings. In addition, the figures described below are exemplary figures used to illustrate the present invention, and the present invention is not limited to the figures shown below. In addition, the "～" indicating the range of numerical values below means that the numerical values recorded on both sides are included. For example, ε is the numerical value α～the numerical value β means that the range of ε includes the range of the numerical value α and the numerical value β, and if expressed in mathematical symbols, it is α≦ε≦β. Regarding angles such as "orthogonal", temperature and pressure, if there is no special description, it is included in the error range generally allowed in the corresponding technical field. In addition, "same" means that it is included in the error range generally allowed in the corresponding technical field. Furthermore, “the entire surface” etc. includes the error range that is generally allowed in the corresponding technical field.

It is often required to fill metal into the through-holes of an insulating substrate such as an anodic oxide film of aluminum having very fine through-holes. However, local filling defects will occur. If the filling defects are for experimental purposes, they will not be a problem, but if the area of the metal-filled microstructure is increased for use in battery electrodes, breathable membranes, sensors, etc., the above-mentioned filling defects will cause poor bonding and other effects. The following is a specific description of the manufacturing method of the metal-filled microstructure. The manufactured metal-filled microstructure has an insulating substrate composed of an insulating film. The insulating film is composed of an oxide film, for example. The oxide film is not particularly limited, but is composed of an anodic oxide film of aluminum. The following description will be given of an example in which the oxide film is composed of an anodic oxide film of aluminum. In this case, an aluminum member is used as the metal member.

<First Aspect> Figures 1 to 5 are schematic cross-sectional views of the first aspect of the method for manufacturing a metal-filled microstructure in the embodiment of the present invention in the order of the process. Figure 6 is an enlarged schematic cross-sectional view of a process of the first aspect of the method for manufacturing a metal-filled microstructure in the embodiment of the present invention. First, as a metal component, for example, an aluminum component 10 shown in Figure 1 is prepared. The aluminum component 10 is appropriately determined in size and thickness according to the thickness of the aluminum anodic oxide film 14 of the metal-filled microstructure 20 (see Figure 5) to be finally obtained, that is, the thickness of the insulating substrate, the device to be processed, etc. The aluminum component 10 is, for example, a rectangular plate.

Next, the surface 10a (see FIG. 1) of one side of the aluminum member 10 is subjected to an anodic oxidation treatment. Thus, the surface 10a (see FIG. 1) of one side of the aluminum member 10 is anodic oxidized, and as shown in FIG. 2, an anodic oxide film 14 having a barrier layer 13 is formed, and the barrier layer 13 exists at the bottom of a plurality of through holes 12 extending in the thickness direction Dt of the aluminum member 10. The process of performing the above-mentioned anodic oxidation is called an anodic oxidation treatment process. For example, by an anodic oxidation treatment, an oxide film having a plurality of fine pores is provided on the surface of the metal member, thereby obtaining a structure having the metal member and the oxide film. That is, the surface 10a of one side of the aluminum member 10 is anodized, and an aluminum anodic oxide film 14 having a plurality of through holes 12 is provided on the surface 10a of the aluminum member 10, thereby obtaining a structure 17 having the aluminum member 10 and the anodic oxide film 14. In addition, the structure 17 is not limited to that obtained by anodizing the aluminum member 10. As described later, the structure 17 can also be obtained by providing a metal member on an oxide film.

In the anodic oxide film 14 having a plurality of through holes 12, as described above, the blocking layer 13 exists at the bottom of the through hole 12, but the blocking layer 13 is removed as shown in FIG. 3. The process of removing the blocking layer 13 is called a blocking layer removal process. In the blocking layer removal process, by using an alkaline aqueous solution containing ions of a metal M1 having a higher hydrogen overvoltage than aluminum, a metal layer 15a composed of a metal (metal M1) is formed at the bottom 12c of the through hole 12 of the structure 17 while removing the blocking layer 13 of the anodic oxide film 14. Thus, the metal layer 15a other than the valve metal is exposed at the bottom 12c of the through hole 12 of the structure 17. Specifically, as shown in FIG6 , the metal layer 15a is formed on the surface 10a of the aluminum member 10 at the bottom 12c of the through hole 12 of the structure 17. In this case, in the bottom 12c of the through hole 12 in the structure 17, more than 80% of the area is formed by the metal layer 15a other than the valve metal. The ratio of the metal layer other than the valve metal formed in the bottom area of the pore is called the area ratio. If the metal layer 15a is formed on a region covering 80% or more of the area of the bottom 12c of the through hole 12 in the structure 17, the area ratio of the metal layer 15a is 80%.

In addition, it is preferred to form the metal layer 15a on an area of more than 80% of the area in the bottom 12c of the through hole 12, and it is more preferred to form the metal layer 15a on an area of more than 95% of the area in the surface 12d of the bottom 12c of the through hole 12, and it is best to form the metal layer 15a on 100% of the area in the bottom 12c of the through hole 12. The above-mentioned barrier layer removal process also serves as a process for forming a metal layer composed of metal other than the valve metal at the bottom of the fine hole. The process for forming the above-mentioned metal layer is a process implemented between the process for obtaining the structure and the plating process.

The plating process is that at the beginning of the plating process, a metal layer other than the valve metal exists at the bottom 12c of the through hole 12, and a metal layer 15a is formed on the surface 10a of the aluminum member 10 located at the bottom 12c of the through hole 12 for an area of more than 80% of the area. Thus, when the through hole 12 is filled with metal by metal plating, plating is easy to perform, and insufficient metal filling can be suppressed, and metal can be suppressed from not being filled in the through hole 12, etc. In addition, in the surface 10a of the aluminum component 10 in the structure 17, the anodic oxide film was cut in the thickness direction by FIB (Focused Ion Beam), and the surface photos (50,000 times magnification) of the cross section were taken by FE-SEM for 10 fields of view, and the area ratio of the metal layer formed on the surface of the component where the pores were exposed in each field of view was measured, and the proportion covered by the metal layer 15a was calculated as the average value. As long as a metal layer other than the valve metal is formed on an area of more than 80% of the area of the bottom 12c of the through hole 12 of the structure 17, it is not limited to the structure in which more than 80% of the area of the surface 10a of the aluminum member 10 in the structure 17 is covered with the metal layer 15a as shown in FIG. 6 .

Next, for the structure 17, on at least one side of the surface having an oxide film, that is, on one side of the surface having an anodic oxide film 14, by performing a plating process of metal plating in a supercritical state or a subcritical state, as shown in FIG. 4, the metal 15b is filled inside the through hole 12 of the anodic oxide film 14. By filling the metal 15b inside the through hole 12, a conductive path 16 is formed. In this case, the metal layer 15a composed of the metal (metal M1) can be used as an electrode during metal plating. The plating process of filling the metal 15b inside the through hole 12 will be described in detail later. In addition, the metal layer 15a and the metal 15b are collectively referred to as the filling metal 15. After the plating process, as shown in FIG5, the aluminum component 10 is removed. In this way, a metal-filled microstructure 20 is obtained. The process of removing the aluminum component 10 is called a substrate removal process.

In the barrier layer removal process before the plating process, an alkaline aqueous solution containing metal M1 ions with a higher hydrogen overvoltage than the metal component (such as aluminum) is used to remove the barrier layer, thereby not only removing the barrier layer 13, but also forming a metal layer 15a of the metal M1 that is less likely to generate hydrogen than aluminum on the aluminum component 10 exposed at the bottom 12c of the through hole 12. As a result, the in-plane uniformity of the metal filling becomes good. It can be considered that the generation of hydrogen by the plating solution can be suppressed, and the metal filling can be easily performed by electroplating. The detailed mechanism is not clear, but it is believed that the reason is that in the barrier layer removal process, by using an alkaline aqueous solution containing metal M1 ions, a metal M1 layer is formed under the barrier layer, thereby suppressing damage to the interface between the aluminum component and the anodic oxide film, and improving the dissolution uniformity of the barrier layer. In this case, more than 80% of the area of the surface 10a of the aluminum component 10 in the structure 17 is also covered by the metal layer 15a.

In addition, in the blocking layer removal process, a metal layer 15a composed of metal (metal M1) is formed at the bottom 12c of the through hole 12, but it is not limited to this. The blocking layer 13 is only removed to expose the aluminum member 10 at the bottom of the through hole 12. On the surface 10a of the aluminum member 10 exposed at the bottom of the through hole 12, the metal layer 15a is formed as a coating material by evaporation or plating. In the above-mentioned first embodiment, a metal protrusion process or a resin layer formation process may be included. The metal protrusion process and the resin layer formation process will be described later.

<Second Aspect> Figures 7 to 10 are schematic cross-sectional views showing the second aspect of the method for manufacturing a metal-filled microstructure according to the process sequence of the present invention. Figure 11 is a schematic cross-sectional view showing an enlarged process of the second aspect of the method for manufacturing a metal-filled microstructure according to the present invention. In addition, with respect to Figures 7 to 11, the same symbols are attached to the components having the same structure as those shown in Figures 1 to 5, and their detailed description is omitted.

Compared with the first embodiment, the second embodiment is different in that, as a metal member, instead of the aluminum member 10, a metal member 24 is used (see FIG. 9 and FIG. 11). In addition, compared with the first embodiment, the second embodiment is different in the following process. In the first embodiment, the structure 17 having the aluminum member 10 and the anodic oxide film 14 shown in FIG. 2 is removed from the aluminum member 10 in the second embodiment to obtain the anodic oxide film 14 shown in FIG. 7. Since the removal of the aluminum member 10 can utilize the substrate removal process, the detailed description is omitted.

Next, the through hole 12 of the anodic oxide film 14 shown in FIG. 7 is enlarged and the blocking layer 13 is removed, thereby forming a through hole 12 penetrating in the thickness direction Dt on the anodic oxide film 14 as shown in FIG. 8. In the expansion of the through hole 12 (fine hole), for example, a hole expansion process is used. The pore expansion treatment is a treatment for expanding the pore diameter of the through hole 12 (pore) by immersing the anodic oxide film in an acidic aqueous solution or an alkaline aqueous solution to dissolve the anodic oxide film. In the pore expansion treatment, an aqueous solution of an inorganic acid such as sulfuric acid, phosphorus, nitric acid, hydrochloric acid, or a mixture thereof, or an aqueous solution of sodium hydroxide, potassium hydroxide, lithium hydroxide, or the like can be used.

Next, a metal member 24 is formed on the entire surface of the back side 14b of the anodic oxide film 14 shown in FIG8, for example, as shown in FIG9. Thus, a structure 17 is obtained, which has an anodic oxide film 14 having a plurality of through holes 12 provided on the surface 24a of the metal member 24, and has the metal member 24 and the anodic oxide film 14. The process of forming the metal member 24 is called a metal member forming process. In the metal member forming process, the metal member 24 is formed by, for example, evaporation, sputtering, or electroless plating. The metal member 24 is preferably formed of a metal other than the valve metal, for example, a precious metal such as Au (gold). The metal member 24 may be the same as the above-mentioned metal layer 15a. Here, as shown in FIG. 11 , a metal member 24 is provided on the back side 14b of the anodic oxide film 14. The metal member 24 covers the entire opening on the back side 14b of the anodic oxide film 14 of the through hole 12. The metal member 24 is made of, for example, Au, and in the surface 24a of the metal member 24, 100% of the surface 24a is made of metal other than the valve metal. By providing the metal member 24 on the back side 14b of the anodic oxide film 14, a metal layer other than the valve metal is exposed on the surface 12d of the bottom 12c of the through hole 12 of the structure 17. In addition, 100% of the surface 12d of the bottom 12c of the through hole 12 can be set to non-valve metal. Thereby, when the through hole 12 is filled with metal by metal plating, plating can be easily performed, and insufficient filling of the metal can be suppressed, and the through hole 12 can be suppressed from not being filled with metal.

Next, as shown in FIG. 10 , in a state where the metal component 24 is formed in the anodic oxide film 14 , similarly to the first state, inside the through hole 12 of the anodic oxide film 14 , the metal 15b is filled in a plurality of through holes 12 by a plating process in a supercritical state or a subcritical state, thereby forming a conductive path 16. Next, the metal component 24 is removed to obtain the metal-filled microstructure 20 shown in FIG. 5 . The method of removing the metal component 24 is not particularly limited as long as the metal component 24 can be removed, and etching or grinding can be cited.

<Other aspects> As a manufacturing method, for example, the above-mentioned anodic oxidation process, retention process, barrier layer removal process, plating process, surface metal protrusion process, resin layer formation process, substrate removal process and back metal protrusion process can be combined. In addition, a mask layer of a desired shape can be used to perform anodic oxidation treatment on a portion of the surface of the aluminum component. In the above-mentioned method for manufacturing a metal-filled microstructure, it is possible to suppress the occurrence of local filling defects in a plurality of through holes 12 (pores), and it is possible to obtain a metal-filled microstructure with fewer filling defects in the through holes 12. Therefore, when using metal-filled microstructures to manufacture heterogeneous conductive components, the density of conductive paths can be significantly increased. As high integration continues to develop, they can also be used as electrical connection components for electronic parts such as semiconductor elements or inspection connectors.

[Insulating substrate] The insulating substrate is composed of an inorganic material and is not particularly limited as long as it has a resistivity (about 10 ¹⁴ Ω·cm) of the same degree as that of an insulating substrate constituting a conventionally known anisotropic conductive film or the like. In addition, "composed of an inorganic material" is a stipulation used to distinguish it from a polymer material constituting the resin layer described later, and does not mean that the insulating substrate is not limited to being composed of an inorganic material alone, but is a stipulation that the inorganic material is the main component (50% by mass or more).

As described above, the insulating substrate is composed of an oxide film. As the oxide film, an anodic oxide film of a valve metal is more preferable because a through hole having a desired average diameter is formed and a conductive path described later is easily formed. For example, as described above, the oxide film is an anodic oxide film of aluminum. Therefore, it is preferable that the metal component is a valve metal. Here, as the valve metal, specifically, for example, aluminum, tantalum, niobium, titanium, tungsten, bismuth, zirconium, zinc, tungsten, bismuth, and antimony can be cited. Among them, an anodic oxide film of aluminum is more preferable because of good dimensional stability and low price. Therefore, it is preferable to use an aluminum component to manufacture a metal-filled microstructure.

[Metal Components] Metal components are used to manufacture metal-filled microstructures. As described above, it is preferred that the metal components be capable of forming an anodic oxide film, and it is preferred that the metal components be formed of the valve metal described above. As described above, aluminum components are used as metal components. In addition, as in the second embodiment, when a metal component is provided on an anodic oxide film, in addition to the valve metal, for example, a noble metal may be used. Examples of noble metals include Au (gold), Ag (silver), and platinum group (Ru, Rh, Pd, Os, Ir, Pt).

<Aluminum components> Aluminum components are not particularly limited. Specific examples include: pure aluminum plates; alloy plates with aluminum as the main component and containing trace amounts of foreign elements; substrates with high-purity aluminum deposited on low-purity aluminum (such as recycled materials); substrates with high-purity aluminum coated on the surface of silicon wafers, quartz, glass, etc. by evaporation, sputtering, etc.; resin substrates laminated with aluminum; etc.

In the aluminum component, the surface of the anodic oxide film formed by the anodic oxidation process preferably has an aluminum purity of 99.5 mass % or more, more preferably 99.9 mass % or more, and even more preferably 99.99 mass % or more. If the aluminum purity is within the above range, the regularity of the through hole arrangement becomes sufficient.

In addition, it is preferred that the surface of one side of the aluminum component that is subjected to the anodic oxidation process is previously subjected to heat treatment, degreasing treatment, and mirror finishing treatment. Here, regarding the heat treatment, degreasing treatment, and mirror finishing treatment, the same treatment as that described in paragraphs [0044] to [0054] of Japanese Patent Publication No. 2008-270158 can be performed.

[Anodic oxidation process] The anodic oxidation process is a process for forming an anodic oxide film having a through hole penetrating in the thickness direction and a barrier layer at the bottom of the through hole on one side of the aluminum member by performing an anodic oxidation process on one side of the aluminum member. The anodic oxidation process can utilize a conventionally known method, but from the perspective of improving the regularity of the through hole arrangement and ensuring the anisotropic conductivity of the metal-filled microstructure, it is preferable to use a self-regularization method or a constant pressure process. Here, regarding the self-regularization method and constant pressure treatment of the anodic oxidation treatment, the same treatment as that described in paragraphs [0056] to [0108] and [FIG. 3] of Japanese Patent Application Laid-Open No. 2008-270158 can be implemented.

<Anodic oxidation treatment> The average flow rate of the electrolyte in the anodic oxidation treatment is preferably 0.5 to 20.0 m/min, more preferably 1.0 to 15.0 m/min, and even more preferably 2.0 to 10.0 m/min. The method of causing the electrolyte to flow under the above conditions is not particularly limited, and for example, a method using a conventional stirring device such as a stirrer can be used. In particular, if a stirrer capable of controlling the stirring speed by digital display is used, the average flow rate can be controlled, which is preferred. As such a stirring device, for example, "Magnetic Stirrer HS-50D (manufactured by AS ONE CORPORATION.)" can be cited.

Anodic oxidation treatment can be performed by, for example, applying electricity to the aluminum member as an anode in a solution having an acid concentration of 1 to 10 mass%. As the solution used in the anodic oxidation treatment, an acid solution is preferred, and sulfuric acid, phosphoric acid, chromic acid, oxalic acid, benzenesulfonic acid, aminosulfonic acid, glycolic acid, tartaric acid, apple acid, citric acid, etc. are more preferred, among which sulfuric acid, phosphoric acid and oxalic acid are particularly preferred. These acids can be used alone or in combination of two or more.

The conditions for anodic oxidation treatment vary depending on the electrolyte used, so they cannot be generalized. However, generally, the electrolyte concentration is 0.1-20 mass%, the liquid temperature is -10-30°C, the current density is 0.01-20A/dm ² , the voltage is 3-300V, and the electrolysis time is 0.5-30 hours. The electrolyte concentration is 0.5-15 mass%, the liquid temperature is -5-25°C, the current density is 0.05-15A/dm ² , the voltage is 5-250V, and the electrolysis time is 1-25 hours. The electrolyte concentration is 1-10 mass%, the liquid temperature is 0-20°C, and the current density is 0.1-10A/dm ² It is further preferred that the voltage is 10-200V and the electrolysis time is 2-20 hours.

From the perspective of supplying the metal-filled microstructure 20 in a shape wound on a winding core, the average thickness of the anodic oxide film formed by the anodic oxide treatment in the above-mentioned anodic oxide treatment process is preferably 30 μm or less, and more preferably 5 to 20 μm. In addition, the anodic oxide film is cut in the thickness direction by a focused ion beam (FIB), and the surface photograph of its cross section is taken by a field emission scanning electron microscope (FE-SEM) (magnification is 50,000 times), and the average thickness is calculated as the average value of 10 measurement points.

[Holding process] The method for manufacturing a metal-filled microstructure may include a holding process. The holding process is a process in which, after the above-mentioned anodic oxidation process, the electrode is held at a voltage of 95% to 105% of a holding voltage selected from a range of 1V to 30% of the voltage in the above-mentioned anodic oxidation process for a total of 5 minutes or more. In other words, the holding process is a process in which, after the above-mentioned anodic oxidation process, an electrolytic treatment is performed at a voltage of 95% to 105% of a holding voltage selected from a range of 1V to 30% of the voltage in the above-mentioned anodic oxidation process for a total of 5 minutes or more. By means of the holding process, the uniformity of metal filling during the plating process is greatly improved. Here, "voltage during anodic oxidation treatment" refers to the voltage applied between aluminum and the counter electrode. For example, if the electrolysis time based on anodic oxidation treatment is 30 minutes, it is the average value of the voltage maintained during the 30-minute period.

From the perspective of controlling the thickness of the side wall of the anodic oxide film, that is, the thickness of the barrier layer relative to the depth of the through hole to be appropriately thick, it is preferred to maintain the voltage during the process at 5% or more and 25% or less of the voltage during the anodic oxidation treatment, and more preferably at 5% or more and 20% or less.

In order to further improve the uniformity of the surface, the total holding time in the holding process is preferably 5 minutes or more and 20 minutes or less, more preferably 5 minutes or more and 15 minutes or less, and even more preferably 5 minutes or more and 10 minutes or less. In addition, the holding time in the holding process is 5 minutes or more in total, and preferably 5 minutes or more continuously.

In addition, the voltage in the holding process can be set to decrease continuously or stepwise (step-like) from the voltage in the anodic oxidation process to the voltage in the holding process, but in order to further improve the in-plane uniformity, it is better to set the voltage to more than 95% and less than 105% of the above holding voltage within 1 second after the end of the anodic oxidation process.

The holding process can also be performed continuously with the anodic oxidation process, for example, by lowering the electrolytic potential at the end of the anodic oxidation process. With regard to conditions other than the electrolytic potential, the holding process can use the same electrolyte and treatment conditions as the above-mentioned conventionally known anodic oxidation process. In particular, when the holding process and the anodic oxidation process are performed continuously, it is preferable to use the same electrolyte for the treatment.

[Blocking layer removal process] The blocking layer removal process is a process for removing the blocking layer of the anodic oxide film, for example, using an alkaline aqueous solution containing metal M1 ions having a higher hydrogen overvoltage than aluminum. By the above-mentioned blocking layer removal process, the blocking layer is removed, and as shown in FIG. 3 , a metal layer 15a composed of metal M1 is formed at the bottom 12c of the through hole 12. Here, hydrogen overvoltage refers to the voltage required to generate hydrogen, for example, the hydrogen overvoltage of aluminum (Al) is -1.66V (Journal of the Chemical Society of Japan, 1982, (8), p1305-1313). In addition, the following shows an example of a metal M1 having a higher hydrogen overvoltage than aluminum and its hydrogen overvoltage value. <Metal M1 and hydrogen (1N H ₂ SO ₄ ) overvoltage> ・Platinum (Pt): 0.00V ・Gold (Au): 0.02V ・Silver (Ag): 0.08V ・Nickel (Ni): 0.21V ・Copper (Cu): 0.23V ・Tin (Sn): 0.53V ・Zinc (Zn): 0.70V

The metal M1 used in the above-mentioned barrier layer removal process is preferably a metal having a higher ionization tendency than the metal M2 used in the later-mentioned plating process, because it causes a substitution reaction with the metal M2 filled in the later-mentioned anodic oxidation process and reduces the influence on the electrical characteristics of the metal filled in the through hole. Specifically, when copper (Cu) is used as the metal M2 in the plating process, a metal other than the valve metal is used as the metal M1 used in the above-mentioned barrier layer removal process, and the metal other than the valve metal is preferably a metal having a higher potential than aluminum. In addition, a metal having a higher potential than aluminum means a metal that is less likely to be ionized than aluminum. Metals with higher potential than aluminum include, for example, Zn, Cr, Fe, Co, Ni, Sn, Pb, Cu, Ag, and Au. As the metal M1, for example, Zn, Fe, Ni, and Sn can be cited, among which Zn and Ni are preferably used, and Zn is more preferably used. In addition, when Ni is used as the metal M2 of the plating process, as the metal M1 used in the barrier layer removal process, for example, Zn, Fe, and the like can be cited, among which Zn is more preferably used.

The method of removing the barrier layer using the alkaline aqueous solution containing the metal M1 ions is not particularly limited, and for example, the same method as the conventionally known chemical etching process can be cited.

<Chemical etching> The barrier layer is removed by chemical etching, for example, by immersing the structure after the anodic oxidation process in an alkaline aqueous solution, filling the inside of the through hole with the alkaline aqueous solution, and then contacting the opening side surface of the through hole of the anodic oxide film with a pH (hydrogen ion index) buffer solution, so that only the barrier layer can be selectively dissolved.

Here, as the alkaline aqueous solution containing the above-mentioned metal M1 ions, it is preferred to use at least one alkaline aqueous solution selected from the group consisting of sodium hydroxide, potassium hydroxide and lithium hydroxide. In addition, the concentration of the alkaline aqueous solution is preferably 0.1 to 5 mass %. The temperature of the alkaline aqueous solution is preferably 10 to 60°C, more preferably 15 to 45°C, and further preferably 20 to 35°C. Specifically, for example, it is preferred to use a 50g/L, 40°C phosphoric acid aqueous solution, a 0.5g/L, 30°C sodium hydroxide aqueous solution, a 0.5g/L, 30°C potassium hydroxide aqueous solution, etc. In addition, as the pH buffer, a buffer corresponding to the above-mentioned alkaline aqueous solution can be appropriately used.

The immersion time in the alkaline aqueous solution is preferably 5 to 120 minutes, more preferably 8 to 120 minutes, further preferably 8 to 90 minutes, and particularly preferably 10 to 90 minutes, preferably 10 to 60 minutes, and more preferably 15 to 60 minutes.

[Other examples of barrier layer removal process] In addition to the above, the barrier layer removal process can also be a process for removing the barrier layer of the anodic oxide film and exposing a portion of the aluminum component at the bottom of the through hole. In this case, the method of removing the barrier layer is not particularly limited, and examples thereof include: a method of electrochemically dissolving the barrier layer at a potential lower than the potential in the anodic oxidation treatment of the anodic oxidation treatment process (hereinafter also referred to as "electrolytic removal treatment"); a method of removing the barrier layer by etching (hereinafter also referred to as "etching removal treatment"); and a combination of these methods (in particular, a method of removing the remaining barrier layer by etching removal treatment after performing the electrolytic removal treatment), etc.

<Electrolytic removal treatment> The electrolytic removal treatment is not particularly limited as long as it is an electrolytic treatment performed at a potential lower than the potential (electrolytic potential) in the anodic oxidation treatment of the anodic oxidation treatment process. The electrolytic removal treatment can be performed continuously with the anodic oxidation treatment, for example, by lowering the electrolytic potential at the end of the anodic oxidation treatment process.

Regarding conditions other than the electrolytic potential, the electrolytic removal treatment can use the same electrolyte and treatment conditions as the above-mentioned conventionally known anodic oxidation treatment. In particular, as described above, when the electrolytic removal treatment and the anodic oxidation treatment are performed continuously, it is preferable to use the same electrolyte for the treatment.

(Electrolytic Potential) The electrolytic potential in the electrolytic removal treatment is preferably continuously or stepwise (stepwise) lowered to a potential lower than the electrolytic potential in the anodic oxidation treatment. Here, from the perspective of the withstand voltage of the barrier layer, it is preferred that the reduction amplitude (step width) when the electrolytic potential is reduced stepwise is 10V or less, 5V or less is more preferred, and 2V or less is further preferred. In addition, from the perspective of productivity, the voltage reduction rate when the electrolytic potential is reduced continuously or stepwise is preferably 1V/second or less, 0.5V/second or less is more preferred, and 0.2V/second or less is further preferred.

〈Etching removal treatment〉 The etching removal treatment is not particularly limited and can be a chemical etching treatment using an acidic aqueous solution or an alkaline aqueous solution for dissolution, or a dry etching treatment.

(Chemical etching treatment) Blocking layers are removed by chemical etching treatment, for example, by immersing the structure after the anodic oxidation process in an acidic aqueous solution or an alkaline aqueous solution, and after the inside of the pores are filled with the acidic aqueous solution or the alkaline aqueous solution, the surface of the opening side of the pores of the anodic oxide film is brought into contact with a pH (hydrogen ion index) buffer solution, etc., so that only the blocking layer can be selectively dissolved.

Here, when an acidic aqueous solution is used, it is preferred to use an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or a mixture thereof. In addition, the concentration of the acidic aqueous solution is preferably 1 mass% to 10 mass%. The temperature of the acidic aqueous solution is preferably 15°C to 80°C, more preferably 20°C to 60°C, and more preferably 30°C to 50°C. On the other hand, when an alkaline aqueous solution is used, it is preferred to use at least one alkaline aqueous solution selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide. In addition, the concentration of the alkaline aqueous solution is preferably 0.1 mass% to 5 mass%. The temperature of the alkaline aqueous solution is preferably 10°C to 60°C, more preferably 15°C to 45°C, and more preferably 20°C to 35°C. In addition, the alkaline aqueous solution may contain zinc and other metals. Specifically, for example, it is preferred to use a 50 g/L, 40°C phosphoric acid aqueous solution, a 0.5 g/L, 30°C sodium hydroxide aqueous solution, a 0.5 g/L, 30°C potassium hydroxide aqueous solution, etc. In addition, as a pH buffer, a buffer corresponding to the above-mentioned acidic aqueous solution or alkaline aqueous solution can be appropriately used.

Furthermore, the immersion time in the acidic aqueous solution or the alkaline aqueous solution is preferably 8 minutes to 120 minutes, more preferably 10 minutes to 90 minutes, and even more preferably 15 minutes to 60 minutes.

(Dry Etching Process) For dry etching process, it is preferable to use a gas type such as Cl ₂ /Ar mixed gas.

[Plating process] The plating process is a process in which metal plating is performed in a supercritical state or a subcritical state after the barrier layer removal process, and the metal M2 is filled inside a plurality of through holes (pores) of the anodic oxide film. As described above, at the beginning of the plating process, a metal layer other than the valve metal exists at the bottom of the pores of the structure, and a metal layer other than the valve metal is formed in an area of more than 80% of the area at the bottom of the pores. In the plating process, metal plating can be either electroplating or electroless plating, but electroplating is preferred because it can be processed in a short time. Here, FIG. 12 is a schematic diagram showing an electroplating device used in a plating process in a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention.

The plating device 28 shown in FIG. 12 has a plating tank 29, an oven 30 surrounding the plating tank 29, a counter electrode 31, a power supply unit 32, and a control unit 33. In the plating tank 29, the above-mentioned structure 17 is arranged opposite to the counter electrode 31. In addition, the plating solution AQ is filled in the plating tank 29, and the structure 17 and the counter electrode 31 are immersed. As described above, the structure 17 has a metal component and an anodic oxide film 14 having a plurality of through holes 12. The power supply unit 32 is electrically connected to the structure 17 and the counter electrode 31, and applies a current to the structure 17. When metal plating is performed, the current is applied to the metal layer or metal component of the structure 17. The control unit 33 is connected to the power supply unit 32 and controls the power supply unit 32. The current value, time and period of the current applied by the power supply unit 32 are controlled by the control unit 33. For example, a plurality of current patterns of applied currents are stored in the control unit 33, and the current is applied to the structure 17 from the power supply unit 32 in an arbitrary current pattern. In addition, the power supply unit 32 can be made to have the function of the control unit 33, in which case the control unit 33 is not required. In addition, the current pattern of the applied current is also called the current control mode. The oven 30 is used to adjust the temperature of the plating solution AQ in the coating tank 29. As long as the oven 30 can adjust the temperature of the plating solution AQ in the coating tank 29, it is not particularly limited, and a known heater can be used. The temperature of the plating solution AQ is maintained at a desired supercritical or subcritical temperature by the oven 30.

The coating device 28 has a supply unit 34, a pump 35 and a valve 36. The supply pipe 37 is provided on the cover 29a of the coating tank 29, and high-pressure carbon dioxide is supplied into the coating tank 29. In addition, the pressure adjustment unit 38 is connected to the coating tank 29 via the discharge pipe 39 provided on the cover 29a of the coating tank 29. The pressure in the coating tank 29 is maintained at the required supercritical or subcritical pressure by the pressure adjustment unit 38. The supply unit 34 is for storing supercritical or subcritical substances. When the supercritical substance is carbon dioxide, the supply unit 34 is a carbon dioxide bottle. The pump 35 is used to pressurize the supercritical or subcritical substance and supply it to the coating tank 29, and a known pressurizing pump is used. The valve 36 is used to control the supply of the supercritical or subcritical substance to the coating tank 29. As described above, the pressure adjustment part 38 is used to maintain the pressure in the coating tank 29, and to reduce or release the pressure in the coating tank 29. The pressure adjustment part 38 uses a valve, for example.

As a supercritical medium, for example, carbon dioxide is used. The critical point of carbon dioxide (the point at which it becomes a supercritical state) is 31.0°C and 7.38MPa, and at a temperature and pressure above the critical point, carbon dioxide becomes a supercritical state. Therefore, the temperature in the coating tank 29 is set to be above 31.0°C, and the pressure is set to be above 7.38MPa. At this time, if the supercritical medium is stirred at the same time, the coating can be effectively performed. Therefore, it is better to set a stirrer (not shown) for stirring in the coating tank 29. In addition, the sub-supercritical medium can use the same one as the above-mentioned supercritical medium.

In the coating tank 29 shown in FIG. 12 , the structure 17 and the counter electrode 31 are arranged opposite to each other. Then, the inside of the coating tank 29 is filled with the plating solution AQ. The temperature of the plating solution AQ in the coating tank 29 is set to, for example, 40°C by the oven 30. Next, carbon dioxide is supplied to the pump 35 from, for example, the supply unit 34, and the pump 35 is pressurized to pass through the valve 36 and supplied to the coating tank 29 through the supply pipe 37, and pressurized so that the pressure in the coating tank 29 becomes, for example, 10 MPa. At this time, it is better to stir the plating solution AQ. As described above, since carbon dioxide becomes a supercritical state in an environment of a temperature of 31.0°C and a pressure of 7.38 MPa, the interior of the plating groove 29 is substantially in a supercritical state, and the plating solution AQ is substantially in an emulsion state. The plating treatment is performed by the plating solution AQ in an emulsion state, and the interior of the through hole in the anodic oxide film is filled with metal M2, thereby forming a conductive conductive path 16. In the plating process, metal plating is performed in a supercritical state using a supercritical medium. In addition, the pressure and temperature can also be adjusted so that, for example, carbon dioxide is set in a subcritical state, thereby performing metal plating in a subsupercritical state using a subcritical medium.

<Supercritical medium> As a supercritical medium, in addition to carbon dioxide, oxygen, argon, krypton, xenon, ammonia, methane, ethane, methanol, ethanol, isopropyl alcohol, dimethyl ketone, sulfur hexafluoride, carbon monoxide, nitrous oxide, a mixed gas of 95% nitrogen and 5% hydrogen, hydrogen, and a mixture of two or more thereof can be used. In addition, water can also be used. Among them, carbon dioxide is preferred. In addition, water becomes a supercritical medium in an environment with a temperature of 374.2°C or more and a pressure of 22.1MPa or more. Methanol becomes a supercritical medium in an environment with a temperature of 239.4°C or more and a pressure of 8.1MPa or more. Ethanol becomes a supercritical medium in an environment with a temperature of 243°C or higher and a pressure of 6.4 MPa or higher. ＜Subsupercritical medium＞ Here, the supercritical state refers to a state where the temperature is higher than the critical point (critical temperature) and the pressure is higher than the critical point (critical pressure). The subcritical state refers to a state where the temperature near the critical point is slightly lower than the critical temperature or the pressure is slightly lower than the critical pressure. The subcritical medium can be the same as the supercritical medium. As described above in the subcritical state, the subcritical medium is a state where the temperature is slightly lower than the critical state or the pressure is slightly lower than the critical state compared to the supercritical medium.

<Metal M2> The metal M2 is preferably a material having a resistivity of 10 ³ Ω·cm or less, and specific examples thereof preferably include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni), zinc (Zn), etc. Among them, from the viewpoint of conductivity, Cu, Au, Al and Ni are preferred, Cu and Au are more preferred, and Cu is further preferred.

<Filling method> As a method of plating the metal M2 into the through hole, an electroplating method is used. In addition, in the electroless plating method, it takes a long time to completely fill the metal into the hole composed of through holes with a high aspect ratio. Here, in the conventionally known electroplating method used in coloring, it is difficult to selectively precipitate (grow) the metal in the hole with a high aspect ratio. It is believed that the reason is that even if the precipitated metal is consumed in the hole and electrolysis is performed for a constant time or more, the plating layer will not grow.

Therefore, when filling the metal by electroplating, a pause time needs to be set during pulse electrolysis or constant potential electrolysis. The pause time needs to be more than 10 seconds, and 30 to 60 seconds is preferred. In addition, in order to promote the stirring of the electrolyte, it is also desirable to apply ultrasound. In addition, the electrolysis voltage is usually below 20V, and it is desirable to be below 10V, but it is better to pre-measure the deposition potential of the target metal in the electrolyte used, and perform constant potential electrolysis within +1V of the potential. In addition, when performing constant potential electrolysis, it is desirable to use cyclic voltammetry in combination, and constant potential meter devices such as Solartron, BAS Inc., HOKUTO DENKO CORP., and IVIUM can be used.

(Plating solution) The plating solution contains metal ions, and a conventionally known plating solution corresponding to the metal to be filled is used. As the plating solution, it is preferable that the main component of the solid component is copper sulfate, for example, a mixed aqueous solution of copper sulfate, sulfuric acid and hydrochloric acid is used. Specifically, when copper is precipitated, a copper sulfate aqueous solution is usually used, but the concentration of copper sulfate is preferably 1 to 300 g/L, and more preferably 100 to 200 g/L. In addition, if hydrochloric acid is added to the plating solution, precipitation can be promoted. In this case, the hydrochloric acid concentration is preferably 10 to 20 g/L. In addition, the main component of the solid component refers to a component whose proportion in the solid component of the electrolyte is 20 mass % or more, for example, copper sulfate is contained in the solid component of the electrolyte at 20 mass % or more. In addition, when gold is precipitated, it is desirable to use a sulfuric acid solution of tetrachlorogold and perform plating by alternating current electrolysis.

The plating solution preferably contains a surfactant. As the surfactant, a known surfactant can be used. Sodium dodecyl sulfate, which is known as a surfactant added to the conventional plating solution, can also be used directly. The hydrophilic part can be ionic (cationic, anionic, and amphoteric) or nonionic (nonionic), but cationic surfactants are preferred from the viewpoint of avoiding the generation of bubbles on the surface of the object to be plated. The concentration of the surfactant in the plating solution composition is preferably 1 mass % or less.

<Pore expansion treatment> The pore expansion treatment is a treatment in which the anodic oxide film is dissolved by immersing the aluminum member in an acidic aqueous solution or an alkaline aqueous solution to expand the diameter of the through hole 12. Thereby, the arrangement regularity of the through holes 12 and the deviation of the diameter are easily controlled. In addition, the barrier film at the bottom of the plurality of through holes 12 that dissolves the anodic oxide film is selectively deposited inside the through hole 12 and the diameter is expanded, thereby significantly increasing the surface area of the electrode.

When an acidic aqueous solution is used in the pore expansion treatment, it is preferred to use an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or a mixture thereof. The concentration of the acidic aqueous solution is preferably 1 to 10% by mass. The temperature of the acidic aqueous solution is preferably 25 to 40°C. In addition, when an alkaline aqueous solution is used in the pore expansion treatment, it is preferred to use at least one alkaline aqueous solution selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1 to 5% by mass. The temperature of the alkaline aqueous solution is preferably 20 to 35°C. Specifically, for example, it is preferred to use a 50 g/L, 40°C phosphoric acid aqueous solution, a 0.5 g/L, 30°C sodium hydroxide aqueous solution, or a 0.5 g/L, 30°C potassium hydroxide aqueous solution. The immersion time for the acidic aqueous solution or the alkaline aqueous solution is preferably 8 to 60 minutes, more preferably 10 to 50 minutes, and even more preferably 15 to 30 minutes.

[Substrate Removal Process] The substrate removal process is a process for removing the above-mentioned aluminum components after the coating process. The method of removing the aluminum components is not particularly limited, and for example, a method of removing by dissolution can be preferably cited.

<Dissolution of aluminum components> In the above-mentioned dissolution of aluminum components, it is preferred to use a treatment liquid that is not easy to dissolve the anodic oxide film but is easy to dissolve aluminum. The dissolution rate of aluminum in such treatment liquid is preferably 1μm/minute or more, more preferably 3μm/minute or more, and more preferably 5μm/minute or more. Similarly, the dissolution rate of the anodic oxide film is preferably 0.1nm/minute or less, more preferably 0.05nm/minute or less, and more preferably 0.01nm/minute or less. Specifically, a treatment liquid containing at least one metal compound having a lower ionization tendency than aluminum and having a pH of 4 or less or 8 or more is preferred, and its pH is more preferably 3 or less or 9 or more, and more preferably 2 or less or 10 or more.

As a treatment solution for dissolving aluminum, an acid or alkaline aqueous solution is used as a base, for example, a compound of manganese, zinc, chromium, iron, cadmium, cobalt, nickel, tin, lead, antimony, bismuth, copper, mercury, silver, palladium, platinum, gold (such as chloroplatinic acid), a fluoride of these, a chloride of these, etc. is preferably used. Among them, an acidic aqueous solution base is preferred, and a mixed chloride is preferred. In particular, from the perspective of the treatment range, a treatment solution in which mercuric chloride is mixed in a hydrochloric acid aqueous solution (hydrochloric acid/mercuric chloride) and a treatment solution in which copper chloride is mixed in a hydrochloric acid aqueous solution (hydrochloric acid/copper chloride) are preferred. In addition, the composition of the treatment solution for dissolving aluminum is not particularly limited, and for example, a bromine/methanol mixture, a bromine/ethanol mixture, aqua regia, etc. can be used.

Furthermore, the acid or alkaline concentration of the treatment solution for dissolving aluminum is preferably 0.01 to 10 mol/L, and more preferably 0.05 to 5 mol/L. In addition, the treatment temperature of the treatment solution for dissolving aluminum is preferably -10°C to 80°C, and more preferably 0°C to 60°C.

Furthermore, the aluminum component is dissolved by contacting the aluminum component after the coating process with the treatment solution. The contact method is not particularly limited, and examples thereof include immersion and spraying. Among them, immersion is preferred. The contact time at this time is preferably 10 seconds to 5 hours, and more preferably 1 minute to 3 hours.

[Metal protrusion process] Based on the reason that the metal bonding of the produced metal-filled microstructure is improved, at least one of the surface metal protrusion process and the back metal protrusion process can be included. Here, the surface metal protrusion process is a process in which, after the above-mentioned plating process and before the above-mentioned substrate removal process, a portion of the surface of one side of the above-mentioned anodic oxide film on which the above-mentioned aluminum component is not provided is removed in the thickness direction, so that the above-mentioned metal M2 filled in the above-mentioned plating process protrudes more than the surface of the above-mentioned anodic oxide film. In addition, the back metal protrusion process is a process in which, after the above-mentioned substrate removal process, a portion of the surface of one side of the above-mentioned anodic oxide film on which the above-mentioned aluminum component is provided is removed in the thickness direction, so that the above-mentioned metal M2 filled in the above-mentioned plating process protrudes more than the surface of the above-mentioned anodic oxide film.

Removing a portion of the anodic oxide film in the metal protrusion process can be performed, for example, by not dissolving the above-mentioned metal M1 and metal M2 (especially metal M2), but by contacting the anodic oxide film, that is, the anodic oxide film having the through hole filled with metal, with an acidic aqueous solution or an alkaline aqueous solution that dissolves aluminum oxide. The contact method is not particularly limited, and for example, an immersion method and a spray method can be cited. Among them, the immersion method is preferred.

When using an acidic aqueous solution, it is preferred to use an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or a mixture thereof. Among them, an aqueous solution that does not contain chromic acid is preferred from the perspective of superior safety. The concentration of the acidic aqueous solution is preferably 1 to 10% by mass. The temperature of the acidic aqueous solution is preferably 25 to 60°C. In addition, when using an alkaline aqueous solution, it is preferred to use at least one alkaline aqueous solution selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1 to 5% by mass. The temperature of the alkaline aqueous solution is preferably 20 to 35°C. Specifically, for example, it is preferable to use a 50 g/L, 40°C phosphoric acid aqueous solution, a 0.5 g/L, 30°C sodium hydroxide aqueous solution, or a 0.5 g/L, 30°C potassium hydroxide aqueous solution. The immersion time for the acidic aqueous solution or the alkaline aqueous solution is preferably 8 to 120 minutes, more preferably 10 to 90 minutes, and even more preferably 15 to 60 minutes. Here, the immersion time refers to the total of each immersion time when a short-time immersion treatment is repeated. In addition, a cleaning treatment can be performed between each immersion treatment.

Furthermore, when the produced metal-filled microstructure is used as an anisotropic conductive component, in order to improve the compression bonding between the surface metal protrusion process and the back metal protrusion process, at least one of the surface metal protrusion process and the back metal protrusion process is preferably a process in which the metal M2 protrudes 10 to 1000 nm beyond the surface of the anodic oxide film, and a process in which the metal M2 protrudes 50 to 500 nm is even more preferably.

Furthermore, when the metal-filled microstructure and the electrode are connected (joined) by methods such as pressing, the aspect ratio (height of the protrusion/diameter of the protrusion) of the protrusion formed by at least one of the above-mentioned surface metal protrusion process and the back metal protrusion process is preferably greater than 0.01 and less than 20, and more preferably 6 to 20, for the reason that the insulation in the planar direction when the protrusion is flattened can be fully ensured.

The conductive path composed of metal formed by the above-mentioned plating process, substrate removal process and any metal protrusion process is preferably columnar. The diameter of the conductive path is roughly the same as the diameter of the through hole filled with metal. The average diameter of the conductive path is the average diameter of the through hole, preferably less than 1μm, more preferably 5 to 500nm, more preferably 20 to 400nm, more preferably 40 to 200nm, and most preferably 50 to 100nm.

Furthermore, the above-mentioned conductive paths exist in a state of mutual insulation through the anodic oxide film of the aluminum member, but the density is preferably 20,000 or more/ ^mm2 , more preferably 2,000,000 or more/ ^mm2 , further preferably 10,000,000 or more/ ^mm2 , particularly preferably 50,000,000 or more/ ^mm2 , and most preferably 100,000,000 or more/ ^mm2 .

In addition, the center distance between adjacent conductive paths is preferably 20nm to 500nm, more preferably 40nm to 200nm, and even more preferably 50nm to 140nm.

[Resin layer forming process] Based on the reason that the transportability of the produced metal-filled microstructure is improved, a resin layer forming process may be provided as described above. Here, the resin layer forming process is a process in which a resin layer is provided on the surface of one side of the anodic oxide film on which the aluminum member is not provided after the above-mentioned plating process (after the surface metal protrusion process in the case of the above-mentioned surface metal protrusion process) and before the above-mentioned substrate removal process.

Specifically, the resin material constituting the resin layer includes, for example, ethylene copolymers, polyamide resins, polyester resins, polyurethane resins, polyolefin resins, acrylic resins and cellulose resins, but from the perspective of transportability and ease of use as an anisotropic conductive component, the resin layer is preferably a peelable adhesive film, and a peelable adhesive film whose adhesiveness is weakened by heat treatment or ultraviolet exposure treatment is even more preferred.

The above-mentioned adhesive layer film is not particularly limited, and examples thereof include a heat-peelable resin layer and an ultraviolet (UV)-peelable resin layer. Here, the heat-peelable resin layer has adhesive force at room temperature and can be easily peeled off only by heating, so foaming microcapsules are mainly used. In addition, as an adhesive constituting the adhesive layer, specifically, for example, rubber adhesives, acrylic adhesives, vinyl alkyl ether adhesives, silicone adhesives, polyester adhesives, polyamide adhesives, amine adhesives, styrene-diene block copolymer adhesives, etc. can be cited.

In addition, the UV peelable resin layer refers to a layer having a UV curable adhesive layer, and can be peeled off by losing adhesion due to curing. As the UV curable adhesive layer, there can be cited a polymer in which a carbon-carbon double bond is introduced into the polymer side chain or the main chain or the end of the main chain. As the base polymer having a carbon-carbon double bond, it is preferable to use an acrylic polymer as the basic skeleton. In addition, for crosslinking, the acrylic polymer can also contain a multifunctional monomer as a copolymer monomer component as needed. The base polymer having a carbon-carbon double bond can be used alone, but can also be combined with a UV curable monomer or oligomer. In order to cure the UV curing type adhesive layer by UV irradiation, it is better to use a photopolymerization initiator. As the photopolymerization initiator, benzoin ether compounds; ketal compounds; aromatic sulfonyl chloride compounds; photosensitive oxime compounds; benzophenone compounds; thioxanone compounds; camphorquinone; halogenated ketones; acylphosphine oxides; acylphosphonates, etc. can be cited.

As commercially available products of heat-peelable resin layers, for example, Intellimer (registered trademark) tapes such as WS5130C02 and WS5130C10 (NITTA Corporation); Somatac〔Registered Trademark〕TE Series (SOMAR Corporation); No.3198, No.3198LS, No.3198M, No.3198MS, No.3198H, No.3195, No.3196, No.3195M, No.3195MS, No.3195H, No.3195HS, No.3195V, No.3195VS, No.319Y-4L, No.319Y-4LS, No.319Y-4M, No.319Y-4MS, No.319Y-4H, No.319Y-4HS, No.319Y-4LSC, No.31935MS, No.31935HS, No.3193M, No.3193MS, etc. Riva Alpha〔Registered Trademark〕series（Made by NITTO DENKO CORPORATION.）；etc.

As commercially available products of UV peelable resin layers, for example, ELP DU-300, ELP DU-2385KS, ELP DU-2187G, ELP NBD-3190K, ELP UE-2091J and other ELEPH HOLDER [registered trademark] (manufactured by NITTO DENKO CORPORATION); Adwill D-210, Adwill D-203, Adwill D-202, Adwill D-175, Adwill D-675 (all manufactured by Lintec Corporation); SUMILITE [registered trademark] FLS N8000 series (manufactured by Sumitomo Bakelite Co., Ltd.); UC353EP-110 (manufactured by FURUKAWA ELECTRIC CO., LTD.); cutting tapes, ELP RF-7232DB, ELP UB-5133D (all manufactured by NITTO DENKO CORPORATION); SP-575B-150, SP-541B-205, SP-537T-160, SP-537T-230 (all manufactured by FURUKAWA ELECTRIC CO., LTD.); back grinding rubber belts.

Furthermore, the method of sticking the above-mentioned adhesive layer film is not particularly limited, and it can be stuck using a conventionally known surface protection tape sticking device and a laminating press.

[Rolling process] In order to further improve the transportability of the produced metal-filled microstructure, after any of the above-mentioned resin layer forming processes, a winding process may be provided, in which the metal-filled microstructure is wound into a roll while having the above-mentioned resin layer. Here, the winding method in the above-mentioned winding process is not particularly limited, and for example, a method of winding on a winding core of a specific diameter and a specific width can be cited.

Furthermore, from the perspective of the ease of winding in the above-mentioned winding process, the average thickness of the metal-filled microstructure excluding the resin layer (not shown) is preferably 30 μm or less, and more preferably 5 to 20 μm. In addition, the metal-filled microstructure excluding the resin layer is cut along the thickness direction by FIB, and the surface photograph of its cross section is taken by FE-SEM (magnification 50,000 times), and the average thickness is calculated as the average value of 10 measurement points.

[Other processing steps] In addition to the above-mentioned processes, the manufacturing method of the present invention may also include the polishing process, surface smoothing process, protective film forming process and water washing process described in paragraphs [0049] to [0057] of International Publication No. 2015/029881. In addition, from the perspective of the processing properties in manufacturing and the use of metal-filled microstructures as anisotropic conductive components, various steps and forms as shown below can be applied.

<Example of steps using temporary bonding materials> The following process may be used: After obtaining the metal-filled microstructure by the above-mentioned substrate removal process, the metal-filled microstructure is fixed on the silicon wafer using a temporary bonding material and thinned by grinding. Secondly, after the thinning process and after the surface is fully cleaned, the above-mentioned surface metal protrusion process can be performed. Next, after a temporary adhesive having a stronger adhesive force than the aforementioned temporary adhesive is applied on the surface of the metal protrusion and fixed on the silicon wafer, the silicon wafer bonded with the aforementioned temporary adhesive is peeled off, and the above-mentioned back metal protrusion process can be performed on the side surface of the peeled metal-filled microstructure.

<Example of steps using wax> The following process may be used: After obtaining the metal-filled microstructure by the above-mentioned substrate removal process, the metal-filled microstructure is fixed on the silicon wafer using wax and thinned by grinding. Secondly, after the thinning process and after the surface is fully cleaned, the above-mentioned surface metal protrusion process can be performed. Secondly, after a temporary adhesive is applied on the surface of the metal protrusion and fixed on the silicon wafer, the above-mentioned wax is dissolved by heating and the silicon wafer is peeled off, and the above-mentioned back metal protrusion process can be performed on the side surface of the peeled metal-filled microstructure. In addition, solid wax can be used, but if liquid wax such as SKYCOAT (manufactured by NIKKA SEIKO CO., LTD.) is used, the uniformity of coating thickness can be improved.

<Example of steps to be performed after substrate removal> The following process may be provided: after the above-mentioned coating process and before the above-mentioned substrate removal process, the aluminum component is fixed to a rigid substrate (such as a silicon wafer, a glass substrate, etc.) using a temporary adhesive, wax or a functional adsorption film, and then thinning is performed by grinding the surface of the above-mentioned anodic oxide film on one side where the above-mentioned aluminum component is not provided. Secondly, after the thinning process and after the surface is fully cleaned, the above-mentioned surface metal protrusion process can be performed. Secondly, after an insulating material, i.e., a resin material (such as an epoxy resin, a polyimide resin, etc.) is coated on the surface where the metal is protruded, a rigid substrate is bonded on the surface by the same method as described above. The bonding system based on the resin material is performed by selecting a bonding force greater than that based on the temporary adhesive, etc., peeling off the rigid substrate initially bonded after bonding with the resin material, and sequentially performing the above-mentioned substrate removal process, grinding process, and back metal protrusion treatment process. In addition, as a functional adsorption film, Q-chuck (registered trademark) (manufactured by MARUISHI SANGYO CO., LTD.) etc. can be used.

The metal-filled fine structure is preferably provided as a product in a state where it is adhered to a rigid substrate (such as a silicon wafer, a glass substrate, etc.) via a removable layer. In this supply form, when the metal-filled fine structure is used as a bonding member, the surface of the metal-filled fine structure is temporarily bonded to the surface of the device, and after the rigid substrate is peeled off, the device to be connected is set at an appropriate position and heated and pressed, thereby enabling the upper and lower devices to be bonded via the metal-filled fine structure. In addition, the removable layer can use a heat-peelable layer, and can also use a light-peelable layer by combining with a glass substrate.

Furthermore, each of the above processes can be performed as a single piece, or the aluminum coil can be used as the original coil for continuous processing. In the case of continuous processing, it is better to set up appropriate cleaning and drying processes between each process.

A metal-filled microstructure is obtained by a manufacturing method having the above-mentioned processing steps to obtain a metal-filled through-hole, wherein the through-hole originates from a through-hole provided on an insulating substrate composed of an anodic oxide film of an aluminum component. Specifically, by the above-mentioned manufacturing method, it is possible to obtain an anisotropic conductive component described in, for example, Japanese Patent Publication No. 2008-270158, that is, an anisotropic conductive component arranged in the following state: in an insulating substrate (anodic oxide film of an aluminum component having a through hole), a plurality of conductive paths composed of a conductive component (metal) penetrate the insulating substrate in the thickness direction in a state of being insulated from each other, and one end of each conductive path is exposed on one side of the insulating substrate, and the other end of each conductive path is exposed on the other side of the insulating substrate.

An example of a metal-filled microstructure 20 manufactured by the above-mentioned manufacturing method is described below. FIG. 13 is a top view showing an example of a metal-filled microstructure of an embodiment of the present invention, and FIG. 14 is a schematic cross-sectional view showing an example of a metal-filled microstructure of an embodiment of the present invention. FIG. 14 is a cross-sectional view taken along the section line IB-IB of FIG. 13. FIG. 15 is a schematic cross-sectional view showing an example of a structure of an anisotropic conductive material using a metal-filled microstructure of an embodiment of the present invention.

As shown in FIG. 13 and FIG. 14 , the metal-filled microstructure 20 manufactured as described above is, for example, a component having an insulating substrate 40 and a plurality of conductive paths 16. The insulating substrate 40 is composed of an aluminum anodic oxide film 14 (see FIG. 5 ). The plurality of conductive paths 16 are connected in the thickness direction Dt (see FIG. 14 ) of the insulating substrate 40 and are arranged in an electrically insulated state. The metal-filled microstructure 20 also has a resin layer 44 arranged on the surface 40a and the back surface 40b of the insulating substrate 40. Here, "a state of being electrically insulated from each other" refers to a state in which the conductivity between each conductive path existing inside the insulating substrate is sufficiently low. The metal-filled microstructure 20 is a component as follows: the conductive paths 16 are electrically insulated from each other, the conductivity is sufficiently low in the direction x orthogonal to the thickness direction Dt (see FIG. 14) of the insulating substrate 40, and the conductivity is in the thickness direction Dt (see FIG. 14). In this way, the metal-filled microstructure 20 is a component showing anisotropic conductivity. For example, the metal-filled microstructure 20 is configured so that the thickness direction Dt (see FIG. 14) coincides with the stacking direction Ds of the stacking device 60.

As shown in FIG. 13 and FIG. 14 , the conductive path 16 is arranged to penetrate the insulating substrate 40 in the thickness direction Dt in a state of being electrically insulated from each other. In addition, as shown in FIG. 14 , the conductive path 16 may have a protrusion 16a and a protrusion 16b protruding from the surface 40a and the back surface 40b of the insulating substrate 40. The metal-filled microstructure 20 may also have a resin layer 44 arranged on the surface 40a and the back surface 40b of the insulating substrate 40. The resin layer 44 has adhesiveness and also imparts bonding properties. The length of the protrusion 16a and the protrusion 16b is preferably 6nm or more, and more preferably 30nm to 500nm.

In addition, FIG. 15 and FIG. 14 show that the insulating substrate 40 has a resin layer 44 on the surface 40a and the back surface 40b, but the present invention is not limited to this, and the insulating substrate 40 may have a resin layer 44 on at least one surface. Similarly, the conductive path 16 of FIG. 15 and FIG. 14 has a protruding portion 16a and a protruding portion 16b at both ends, but the present invention is not limited to this, and the insulating substrate 40 may have a protruding portion on the surface of at least one side having the resin layer 44.

The thickness h of the metal-filled microstructure 20 shown in FIG. 14 is, for example, 30 μm or less. Moreover, the TTV (Total Thickness Variation) of the metal-filled microstructure 20 is preferably 10 μm or less. Here, the thickness h of the metal-filled microstructure 20 is obtained by observing the metal-filled microstructure 20 at a magnification of 200,000 times using an electrolytic emission scanning electron microscope to obtain the contour shape of the metal-filled microstructure 20, and measuring the average value of 10 points in the area equivalent to the thickness h. The total thickness variation (TTV) of the metal-filled microstructure 20 is a value obtained by cutting the metal-filled microstructure 20 together with the support 46 and observing the cross-sectional shape of the metal-filled microstructure 20 .

The metal-filled microstructure 20 is placed on a support 46 as shown in FIG15 for transportation, delivery, handling, storage, etc. A peeling layer 47 is placed between the support 46 and the metal-filled microstructure 20. The support 46 and the metal-filled microstructure 20 are bonded to each other through the peeling layer 47 so as to be separable. As described above, the metal-filled microstructure 20 placed on the support 46 via the peeling layer 47 is called an anisotropic conductive material 50. The support 46 supports the metal-filled microstructure 20 and is composed of, for example, a silicon substrate. As the support body 46, in addition to the silicon substrate, for example, a ceramic substrate such as SiC, SiN, GaN, and alumina ( _Al2O3 ), a glass substrate, a fiber-reinforced plastic substrate, and a metal substrate can be _used . The fiber-reinforced plastic substrate also includes a printed wiring substrate, that is, a FR-4 (Flame Retardant Type 4) substrate.

Furthermore, as the support body 46, a flexible and transparent one can be used. As the flexible and transparent support body 46, for example, plastic films such as PET (polyethylene terephthalate), polyethylene, polycarbonate, acrylic resin, PEN (polyethylene naphthalate), PE (polyethylene), PP (polypropylene), polystyrene, polyvinyl chloride, polyvinylidene chloride and TAC (cellulose triacetate) can be cited. Here, transparency means that the transmittance is 80% or more in the wavelength light used for alignment. Therefore, the transmittance in the entire visible light range of 400 to 800nm can be low, but it is better to have a transmittance of 80% or more in the entire visible light range of 400 to 800nm. The transmittance is measured by a spectrophotometer.

The peeling layer 47 is preferably laminated with the support layer 48 and the peeling agent 49. The peeling agent 49 contacts the metal-filled microstructure 20, and the support 46 and the metal-filled microstructure 20 are separated starting from the peeling layer 47. In the anisotropic conductive material 50, for example, by heating to a predetermined temperature, the adhesion of the peeling agent 49 is weakened, and the support 46 can be removed from the metal-filled microstructure 20. As the peeling agent 49, for example, REVALPHA (registered trademark) manufactured by Nitto Denko Corporation, SOMATAC (registered trademark) manufactured by SOMAR Corporation, or the like can be used.

In addition, a protective layer (not shown) can be provided on the resin layer 44. The protective layer is used to protect the surface of the structure from scratches, etc., so an easily peelable tape is preferred. As the protective layer, for example, an adhesive film can be used. As the adhesive layer film, commercial products sold under the following series names can be used, for example: SUNYTECT (registered trademark) having an adhesive layer formed on the surface of a polyethylene resin film (manufactured by Sun A.Kaken Co., Ltd.), E-MASK (registered trademark) having an adhesive layer formed on the surface of a polyethylene terephthalate resin film (manufactured by Nitto Denko Corporation), MASTACK (registered trademark) having an adhesive layer formed on the surface of a polyethylene terephthalate resin film (manufactured by FUJIMORI KOGYO CO., LTD), etc. In addition, the method of sticking the adhesive layer film is not particularly limited, and can be stuck using a conventionally known surface protection tape sticking device and a laminating press.

The following is a more detailed description of the structure of the metal-filled microstructure 20. [Insulating substrate] The physical properties and composition of the insulating substrate are as described above. The thickness ht of the insulating substrate 40 is preferably in the range of 1 to 1000 μm, more preferably in the range of 5 to 500 μm, and even more preferably in the range of 10 to 300 μm. If the thickness of the insulating substrate is within this range, the operability of the insulating substrate becomes good. The thickness ht of the insulating substrate 40 is obtained by cutting the insulating substrate 40 in the thickness direction Dt using a focused ion beam (FIB), observing its cross section with a magnification of 200,000 times using an electrochemical emission scanning electron microscope to obtain the contour shape of the insulating substrate 40, and measuring the average value of 10 points in an area equivalent to the thickness ht.

The spacing between each through hole in the insulating substrate is preferably 5nm to 800nm, more preferably 10nm to 200nm, and even more preferably 50nm to 140nm. If the spacing between each through hole in the insulating substrate is within this range, the insulating substrate fully functions as an insulating partition. The spacing between the through holes is the same as the spacing between the conductive paths. Here, the spacing of through holes, that is, the spacing of conductive paths refers to the width w between adjacent conductive paths (see Figure 14), and refers to the average value of the width between adjacent conductive paths measured at 10 points by observing the cross section of the anisotropic conductive component with a field emission scanning electron microscope at a magnification of 200,000 times.

<Average diameter of fine holes> The average diameter of the fine holes, i.e., the average diameter d of the through hole 12 (see FIG. 14 ), is preferably 1 μm or less, 5 to 500 nm is more preferred, 20 to 400 nm is further preferred, 40 to 200 nm is further preferred, and 50 to 100 nm is the best. If the average diameter d of the through hole 12 is 1 μm or less and within the above range, when the electrical signal passes through the resulting conductive path 16, it can be fully responded to, so it can be better used as a connector for inspection of electronic components. The average diameter d of the through hole 12 is obtained by photographing the surface of the anodic oxide film 14 from above with a scanning electron microscope at a magnification of 100 to 10,000 times, and measuring the diameters of at least 20 through holes connected in a ring shape in advance in the photographic image and setting them as the opening diameters, and calculating the average value of the opening diameters as the average diameter of the through holes. In addition, the magnification can be appropriately selected within the above range so that a photographic image that can extract more than 20 through holes can be obtained. In addition, the opening diameter is measured as the maximum value of the distance between the ends of the through hole portion. That is, since the shape of the opening of the through hole is not limited to a substantially circular shape, when the shape of the opening is non-circular, the maximum value of the distance between the ends of the through hole portion is set as the opening diameter. Therefore, in the case of a through hole having a shape of two or more through holes integrated, it is also regarded as one through hole, and the maximum value of the distance between the ends of the through hole portion is set as the opening diameter.

[Conductive path] The conductive path is made of metal. Specific examples of the metal include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), and nickel (Ni). From the perspective of electrical conductivity, copper, gold, aluminum, and nickel are preferred, and copper and gold are more preferred.

<Protrusion> When the anisotropic conductive member is electrically connected or physically joined to the electrode by crimping or the like, the aspect ratio (height of the protrusion/diameter of the protrusion) of the protrusion of the conductive path is preferably 0.5 or more and less than 50, more preferably 0.8 to 20, and even more preferably 1 to 10, in order to ensure sufficient insulation in the planar direction when the protrusion is flattened.

Furthermore, from the viewpoint of following the surface shape of the semiconductor component to be connected, as described above, the height of the protruding portion of the conductive path is preferably 20 nm or more, and more preferably 100 nm to 500 nm. The height of the protruding portion of the conductive path refers to the average value of the height of the protruding portion of the conductive path measured at 10 points by observing the cross section of the metal-filled microstructure with an electrochemical emission scanning electron microscope at a magnification of 20,000 times. The diameter of the protruding portion of the conductive path refers to the average value of the diameter of the protruding portion of the conductive path measured at 10 points by observing the cross section of the metal-filled microstructure with an electrochemical emission scanning electron microscope.

As described above, the conducting paths 16 exist in a state of being electrically insulated from each other by the insulating substrate 40, but the density is preferably 20,000 or more/ ^mm2 , more preferably 2,000,000 or more/ ^mm2 , more preferably 10,000,000 or more/ ^mm2 , more preferably 50,000,000 or more/ ^mm2 , and most preferably 100,000,000 or more/ ^mm2 . In addition, the center distance p (see FIG. 13) between adjacent conducting paths 16 is preferably 20nm to 500nm, more preferably 40nm to 200nm, and even more preferably 50nm to 140nm.

[Resin layer] As described above, the resin layer is provided on the surface and back of the insulating substrate, and as described above, the protruding portion of the conductive path is buried. That is, the resin layer covers the end of the conductive path protruding from the insulating substrate and protects the protruding portion. The resin layer is formed by the above-mentioned resin layer forming process. The resin layer exhibits fluidity in a temperature range of 50°C to 200°C, for example, and preferably hardens at a temperature above 200°C. The resin layer is formed by the above-mentioned resin layer forming process, but the composition of the resin agent shown below can also be used. The composition of the resin layer is described below. The resin layer contains a polymer material. The resin layer may contain an antioxidant material.

<Polymer material> The polymer material contained in the resin layer is not particularly limited, but thermosetting resin is preferred because it can effectively fill the gap between the semiconductor chip or semiconductor wafer and the anisotropic conductive component and further improve the adhesion with the semiconductor chip or semiconductor wafer. Specific examples of thermosetting resins include epoxy resins, phenol resins, polyimide resins, polyester resins, polyurethane resins, dimaleimide resins, melamine resins, and isocyanate resins. Among them, polyimide resin and/or epoxy resin is preferably used because of further improving insulation reliability and excellent chemical resistance.

<Antioxidant material> Specific examples of the antioxidant material contained in the resin layer include 1,2,3,4-tetrazole, 5-amino-1,2,3,4-tetrazole, 5-methyl-1,2,3,4-tetrazole, 1H-tetrazole-5-acetic acid, 1H-tetrazole-5-succinic acid, 1,2,3-triazole, 4-amino-1,2,3-triazole, 4,5-diamino-1,2,3-triazole, 4-carboxyl-1H-1,2,3-triazole, 4,5-dicarboxyl-1H-1,2,3-triazole, 1H-1,2,3-triazole-4-acetic acid, 4-carboxyl- -5-carboxymethyl-1H-1,2,3-triazole, 1,2,4-triazole, 3-amino-1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-carboxy-1,2,4-triazole, 3,5-dicarboxy-1,2,4-triazole, 1,2,4-triazole-3-acetic acid, 1H-benzotriazole, 1H-benzotriazole-5-carboxylic acid, benzofuran, 2,1,3-benzothiazole, o-phenylenediamine, m-phenylenediamine, catechol, o-aminophenol, 2-phenylbenzothiazole, 2-phenylbenzimidazole, 2-phenylbenzoxazole, melamine and their derivatives. Among them, benzotriazole and its derivatives are preferred. Examples of benzotriazole derivatives include substituted benzotriazoles having a hydroxyl group, an alkoxy group (e.g., methoxy group, ethoxy group, etc.), an amino group, a nitro group, an alkyl group (e.g., methyl group, ethyl group, butyl group, etc.), a halogen atom (e.g., fluorine, chlorine, bromine, iodine, etc.) on the benzene ring of benzotriazole. Also, similarly to naphthalenetriazole and naphthalenebistriazole, substituted naphthalenetriazoles and substituted naphthalenebistriazoles can be mentioned.

Furthermore, as other examples of the antioxidant material contained in the resin layer, there can be cited conventional antioxidants, that is, higher fatty acids, higher fatty acid copper, phenol compounds, alkanolamines, hydroquinones, copper chelating agents, organic amines, and organic ammonium salts.

The content of the antioxidant material contained in the resin layer is not particularly limited, but from the viewpoint of the anti-corrosion effect, it is preferably 0.0001 mass % or more, and more preferably 0.001 mass % or more, relative to the total mass of the resin layer. In addition, for the reason of obtaining an appropriate resistance in the formal bonding step, it is preferably 5.0 mass % or less, and more preferably 2.5 mass % or less.

<Migration prevention material> For the reason that the insulation reliability can be further improved by capturing metal ions, halogen ions that may be contained in the resin layer, and metal ions originating from the semiconductor chip and the semiconductor wafer, it is preferable that the resin layer contains a migration prevention material.

As the migration prevention material, for example, only an ion exchanger can be used, specifically, a mixture of a cation exchanger and an anion exchanger or a cation exchanger. Here, the cation exchanger and the anion exchanger can be appropriately selected from, for example, the inorganic ion exchangers and organic ion exchangers described later.

(Inorganic ion exchanger) As an inorganic ion exchanger, for example, a metal hydroxide represented by zirconium hydroxide can be cited. As the type of metal, for example, in addition to zirconium, iron, aluminum, tin, titanium, antimony, magnesium, curium, indium, chromium and bismuth are also known. Among them, zirconium metals have the ability to exchange cations Cu ²⁺ and Al ³⁺ . In addition, iron metals also have the ability to exchange Ag ⁺ and Cu ²⁺ . Similarly, tin, titanium and antimony metals are cation exchangers. On the other hand, bismuth metals have the ability to exchange anions Cl ^- . Furthermore, zirconium-based metals show anion exchange ability depending on the manufacturing conditions. The same is true for aluminum-based and tin-based metals. As other inorganic ion exchangers, acid salts of polyvalent metals represented by zirconium phosphate, polyacid salts represented by ammonium molybdenum phosphate, insoluble ferrocyanide and other synthetic products are known. Some of these inorganic ion exchangers are commercially available, for example, various grades of the product name "IXE" of TOAGOSEI CO., LTD. are known. In addition to synthetic products, inorganic ion exchanger powders such as natural products such as zeolite or montmorillonite can also be used.

(Organic ion exchanger) As an organic ion exchanger, cross-linked polystyrene having a sulfonic acid group as a cation exchanger can be cited, and those having a carboxylic acid group, a phosphonic acid group or a phosphinic acid group can also be cited. Also, cross-linked polystyrene having a quaternary ammonium group, a quaternary phosphonium group or a tertiary coronium group can be cited as an anion exchanger.

The inorganic ion exchangers and organic ion exchangers can be appropriately selected by considering the types of cations and anions to be captured and the exchange capacity of the aforementioned ions. Of course, inorganic ion exchangers and organic ion exchangers can also be mixed and used. The manufacturing process of electronic components includes a heating step, so inorganic ion exchangers are preferred.

Furthermore, for example, from the viewpoint of mechanical strength, the mixing ratio of the migration prevention material to the polymer material is preferably 10% by mass or less, more preferably 5% by mass or less, and further preferably 2.5% by mass or less. Furthermore, from the viewpoint of suppressing migration when bonding a semiconductor chip or a semiconductor wafer to an anisotropic conductive member, the migration prevention material is preferably 0.01% by mass or more.

<Inorganic filler> The resin layer preferably contains an inorganic filler. The inorganic filler is not particularly limited and can be appropriately selected from known ones. For example, kaolin, barium sulfate, barium titanate, silica powder, fine powder silica, fumed silica, amorphous silica, crystalline silica, fused silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica, aluminum nitride, zirconium oxide, yttrium oxide, silicon carbide, and silicon nitride can be cited.

In order to prevent the inorganic filler from entering between the conductive paths and further improve the conduction reliability, the average particle size of the inorganic filler is preferably larger than the interval between each conductive path. The average particle size of the inorganic filler is preferably 30nm to 10μm, and more preferably 80nm to 1μm. Here, regarding the average particle size, the primary particle size measured by a laser diffraction scattering particle size measuring device (Microtrac MT3300 manufactured by NIKKISO CO., LTD.) is set as the average particle size.

<Hardener> The resin layer may contain a hardener. When a hardener is contained, it is more preferable to contain a hardener that is liquid at room temperature instead of a hardener that is solid at room temperature from the viewpoint of suppressing poor bonding with the surface shape of a semiconductor chip or semiconductor wafer to be connected. Here, "solid at room temperature" means a substance that is solid at 25°C, for example, a substance with a melting point higher than 25°C.

Specific examples of the curing agent include aromatic amines such as diaminodiphenylmethane and diaminodiphenylsulfone, aliphatic amines, imidazole derivatives such as 4-methylimidazole, cyanamide, tetramethylguanidine, thiourea addition amines, carboxylic anhydrides such as methylhexahydrophthalic anhydride, carboxylic acid hydrazides, carboxylic acid amides, polyphenol compounds, novolac resins, and polythiol, and a liquid at 25° C. can be appropriately selected from these curing agents. The curing agent may be used alone or in combination of two or more.

The resin layer may contain various additives within the range that does not impair its properties, such as dispersants, buffers, viscosity adjusters, etc., which are commonly added to resin insulation films for semiconductor packaging.

<Shape> For the purpose of protecting the conductive path, the thickness of the resin layer is greater than the height of the protruding portion of the conductive path and is preferably 1μm to 5μm.

As an example of application of the metal-filled microstructure 20, an example of using the metal-filled microstructure 20 in an anisotropic conductive member 22 (see FIG. 16, etc.) is described below. FIG. 16 is a schematic diagram showing a first example of a laminated device using a metal-filled microstructure in an embodiment of the present invention, FIG. 17 is a schematic diagram showing a second example of a laminated device using a metal-filled microstructure in an embodiment of the present invention, FIG. 18 is a schematic diagram showing a third example of a laminated device using a metal-filled microstructure in an embodiment of the present invention, and FIG. 19 is a schematic diagram showing a fourth example of a laminated device using a metal-filled microstructure in an embodiment of the present invention.

In addition, as shown in FIG16 , the stacked device 60 can be electrically connected by bonding the semiconductor element 62 and the semiconductor element 64 in the stacking direction Ds via the anisotropic conductive member 22 showing anisotropic conductivity. The anisotropic conductive member 22 has the same structure as the metal-filled microstructure 20 described above, and has a conductive path 16 (see FIG5 ) that conducts in the stacking direction Ds, and performs the function of TSV (Through Silicon Via). In addition, the anisotropic conductive member 22 can also be used as an interposer.

In addition to the configuration shown in FIG. 16 , for example, the following configuration may be used: as shown in FIG. 17 , a stacked device 60 is formed by stacking and bonding semiconductor elements 62, 64, and 66 in a stacking direction Ds via an anisotropic conductive member 22, and electrically connecting them. In addition, the following configuration may be used: as shown in FIG. 18 , a stacked device 60 is formed by stacking and bonding semiconductor elements 62, 64, and 66 in a stacking direction Ds using an intermediate layer 23 and an anisotropic conductive member 22, and electrically connecting them.

Alternatively, the device may function as an optical sensor as shown in FIG19 , such as the multilayer device 60. The multilayer device 60 shown in FIG19 has a semiconductor element 72 and a sensor chip 74 stacked in the stacking direction Ds via an anisotropic conductive member 22. A lens 76 is provided on the sensor chip 74. The semiconductor element 72 is formed with a logic circuit, and its structure is not particularly limited as long as it can process the signal obtained by the sensor chip 74. The sensor chip 74 is a photo sensor that detects light. The photo sensor is not particularly limited as long as it can detect light. For example, a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor can be used. In addition, in the multilayer device 60 shown in FIG. 19 , the semiconductor element 72 and the sensor chip 74 are connected via the anisotropic conductive member 22, but this is not limited to this. The semiconductor element 72 and the sensor chip 74 can also be directly bonded. The lens 76 is not particularly limited as long as it can focus light on the sensor chip 74. For example, a so-called micro lens can be used.

In addition, the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 have an element region (not shown). The element region is a region where various elements such as capacitors, resistors, and coils that function as electronic elements are formed to form circuits. In the element region, for example, there are regions where memory circuits such as flash memories, microprocessors, and logic circuits such as FPGAs (field-programmable gate arrays) are formed; and regions where communication modules and wiring such as wireless tags are formed. In addition, in the element region, a transmission circuit or MEMS (Micro Electro Mechanical Systems) can also be formed. MEMS are, for example, sensors, actuators, and antennas. Among sensors, for example, there are various sensors such as acceleration sensors, sound sensors, and light sensors.

As described above, the element region is formed with an element constituting circuit, etc., and in the semiconductor element, for example, a redistribution layer (not shown) is provided. In the multilayer device, for example, it is possible to set it as a combination of a semiconductor element having a logic circuit and a semiconductor element having a memory circuit. In addition, the semiconductor elements can all be set to have a memory circuit, and in addition, they can all be set to have a logic circuit. In addition, as a combination of semiconductor elements in the multilayer device 60, it can be a combination of sensors, actuators, antennas, etc., and memory circuits and logic circuits, which can be appropriately determined according to the purpose of the multilayer device 60, etc.

The semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 may be, in addition to the above, logic integrated circuits such as ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), and ASSP (Application Specific Standard Product). In addition, microprocessors such as CPU (Central Processing Unit) and GPU (Graphics Processing Unit) may be cited. In addition, for example, memories such as DRAM (Dynamic Random Access Memory), HMC (Hybrid Memory Cube), MRAM (Magnetoresistive Random Access Memory), PCM (Phase-Change Memory), ReRAM (Resistance Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and flash memory can be cited. In addition, analog integrated circuits such as LED (Light Emitting Diode), power devices, DC (Direct Current)-DC (Direct Current) converters, and insulated gate bipolar transistors (IGBT) can be cited. In addition, as semiconductor components, there are wireless components such as GPS (Global Positioning System), FM (Frequency Modulation), NFC (Near Field Communication), RFEM (RF Expansion Module), MMIC (Monolithic Microwave Integrated Circuit), WLAN (Wireless Local Area Network), discrete components, passive devices, SAW (Surface Acoustic Wave) filters, RF (Radio Frequency) filters, IPD (Integrated Passive Devices), etc.

Next, the first example of the method for manufacturing a laminated device using a metal-filled microstructure is described. The first example of the method for manufacturing a laminated device using a metal-filled microstructure is related to a chip stacking wafer, and shows a method for manufacturing a laminated device 60 shown in FIG. 16. FIGS. 20 to 22 are schematic diagrams showing the first example of the method for manufacturing a laminated device using a metal-filled microstructure in the embodiment of the present invention in the order of the process. In the first example of the method for manufacturing a laminated device using a metal-filled microstructure, first, a semiconductor element 64 having an anisotropic conductive member 22 provided on a surface 64a is prepared. Next, the semiconductor element 64 is arranged so that the anisotropic conductive member 22 faces the first semiconductor wafer 80. Next, the semiconductor element 64 is aligned with respect to the first semiconductor wafer 80 using the alignment mark of the semiconductor element 64 and the alignment mark of the first semiconductor wafer 80. In addition, regarding the alignment, if digital image data can be obtained from the image or reflection image of the alignment mark of the first semiconductor wafer 80 and the image or reflection image of the alignment mark of the semiconductor element 64, the configuration is not particularly limited, and a known camera device can be appropriately used.

Next, the semiconductor element 64 is placed on the element region of the first semiconductor wafer 80 via the anisotropic conductive member 22, for example, a predetermined pressure is applied, heated to a predetermined temperature and maintained for a predetermined time, and a resin layer 44 (see FIG. 14 ) is used for temporary bonding. The aforementioned treatment is performed on all semiconductor elements 64, and as shown in FIG. 21 , all semiconductor elements 64 are temporarily bonded to the element region of the first semiconductor wafer 80. Using the resin layer 44 for temporary bonding is one method, and the following method may also be used. For example, a sealing resin or the like can be supplied to the first semiconductor wafer 80 using a glue dispenser or the like, thereby temporarily bonding the semiconductor element 64 to the element region of the first semiconductor wafer 80. Alternatively, the semiconductor element 64 can be temporarily bonded to the element region on the first semiconductor wafer 80 using a pre-supplied insulating resin film (NCF (Non-conductive Film)).

Next, while all semiconductor elements 64 are temporarily bonded to the element region of the first semiconductor wafer 80, a predetermined pressure is applied to the semiconductor element 64, and the temperature is heated to a predetermined temperature and maintained for a predetermined time, thereby bonding all the multiple semiconductor elements 64 to the element region of the first semiconductor wafer 80. This bonding is called formal bonding. Thus, the terminal (not shown) of the semiconductor element 64 is bonded to the anisotropic conductive member 22, and the terminal (not shown) of the first semiconductor wafer 80 is bonded to the anisotropic conductive member 22. Next, as shown in Fig. 22, the first semiconductor wafer 80 to which the semiconductor element 64 is bonded via the anisotropic conductive member 22 is singulated in each element region by dicing or laser scribing, etc. Thus, a multilayer device 60 to which the semiconductor element 62, the anisotropic conductive member 22, and the semiconductor element 64 are bonded can be obtained.

In addition, when temporary bonding is performed, if the temporary bonding strength is weak, it will cause positional deviation in the conveying process and the process until bonding, so the temporary bonding strength becomes important. In addition, the temperature conditions in the temporary bonding step are not particularly limited, and 0℃～300℃ is preferred, 10℃～200℃ is more preferred, and room temperature (23℃)～100℃ is particularly preferred. Similarly, the pressurization conditions in the temporary bonding step are not particularly limited, and 10MPa or less is preferred, 5MPa or less is more preferred, and 1MPa or less is particularly preferred.

The temperature conditions in the formal bonding are not particularly limited, and a temperature higher than the temperature of the temporary bonding is preferred. Specifically, 150°C to 350°C is more preferred, and 200°C to 300°C is particularly preferred. In addition, the pressurization conditions in the formal bonding are not particularly limited, and 30 MPa or less is preferred, and 0.1 MPa to 20 MPa is more preferred. In addition, the time of the formal bonding is not particularly limited, and 1 second to 60 minutes is preferred, and 5 seconds to 10 minutes is more preferred. By performing the formal bonding under the above conditions, the resin layer flows between the electrodes of the semiconductor element 64 and is less likely to remain in the bonding portion. As described above, by performing bonding of a plurality of semiconductor elements 64 at once in the final bonding, the production time can be shortened and the productivity can be improved.

A second example of a method for manufacturing a laminated device using a metal-filled microstructure is described. FIGS. 23 to 25 are schematic diagrams showing the second example of a method for manufacturing a laminated device using a metal-filled microstructure in accordance with the process sequence. Compared with the first example of a method for manufacturing a laminated device using a metal-filled microstructure, the second example of a method for manufacturing a laminated device using a metal-filled microstructure is the same as the first example of a method for manufacturing a laminated device using a metal-filled microstructure except that three semiconductor elements 62, 64, and 66 are laminated and bonded via an anisotropic conductive member 22. Therefore, detailed description of the manufacturing method common to the second example of the manufacturing method of the multilayer device is omitted. The semiconductor element 64 is provided with an alignment mark (not shown) on the back surface 64b and a terminal (not shown). In addition, an anisotropic conductive component 22 is provided on the surface 64a of the semiconductor element 64. In addition, the semiconductor element 66 is also provided with an anisotropic conductive component 22 on the surface 66a.

As shown in FIG. 23 , when all semiconductor elements 64 are temporarily bonded to the element region of the first semiconductor wafer 80 via the anisotropic conductive member 22 , the semiconductor element 66 is aligned relative to the semiconductor element 64 using the alignment mark on the back surface 64 b of the semiconductor element 64 and the alignment mark on the semiconductor element 66 .

Next, as shown in FIG. 24 , the semiconductor element 66 is provisionally bonded to the back surface 64b of the semiconductor element 64 via the anisotropic conductive member 22. Next, all the semiconductor elements 64 are provisionally bonded to the element region of the first semiconductor wafer 80 via the anisotropic conductive member 22, and in a state where the semiconductor elements 66 are provisionally bonded to all the semiconductor elements 64 via the anisotropic conductive member 22, formal bonding is performed under predetermined conditions. Thus, the semiconductor element 64 and the semiconductor element 66 are bonded via the anisotropic conductive member 22, and the semiconductor element 64 and the first semiconductor wafer 80 are bonded via the anisotropic conductive member 22. The semiconductor element 64, the semiconductor element 66, and the terminals (not shown) of the first semiconductor wafer 80 are bonded to the anisotropic conductive member 22. Next, as shown in FIG. 25, the first semiconductor wafer 80 to which the semiconductor element 64 and the semiconductor element 66 are bonded via the anisotropic conductive member 22 is singulated in each element region, for example, by dicing or laser scribing. In this way, a multilayer device 60 in which the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 are bonded via the anisotropic conductive member 22 can be obtained.

The third example of the method for manufacturing a laminated device using a metal-filled microstructure is described. The third example of the method for manufacturing a laminated device using a metal-filled microstructure is related to stacking wafers, and shows a method for manufacturing a laminated device 60 shown in FIG. 16. FIGS. 26 and 27 are schematic diagrams showing the third example of the method for manufacturing a laminated device using a metal-filled microstructure in the embodiment of the present invention in the order of the manufacturing process. Compared with the first example of the method for manufacturing a multilayer device, the third example of the method for manufacturing a multilayer device using a metal-filled microstructure is the same as the third example of the method for manufacturing a multilayer device except that the first semiconductor wafer 80 and the second semiconductor wafer 82 are bonded via the anisotropic conductive member 22. Therefore, the detailed description of the manufacturing method common to the first example of the method for manufacturing a multilayer device is omitted. In addition, the anisotropic conductive member 22 is the same as described above, so the detailed description thereof is omitted.

First, prepare the first semiconductor wafer 80 and the second semiconductor wafer 82. An anisotropic conductive component 22 is provided on the surface 80a of the first semiconductor wafer 80 or the surface 82a of the second semiconductor wafer 82. Second, the surface 80a of the first semiconductor wafer 80 and the surface 82a of the second semiconductor wafer 82 are made to face each other. Then, the alignment mark of the first semiconductor wafer 80 and the alignment mark of the second semiconductor wafer 82 are used to align the second semiconductor wafer 82 with respect to the first semiconductor wafer 80. Next, the surface 80a of the first semiconductor wafer 80 and the surface 82a of the second semiconductor wafer 82 are made to face each other, and the first semiconductor wafer 80 and the second semiconductor wafer 82 are bonded via the anisotropic conductive member 22 using the above method as shown in FIG26. In this case, the formal bonding may be performed after the temporary bonding, or only the formal bonding may be performed.

Next, as shown in FIG. 27 , in a state where the first semiconductor wafer 80 and the second semiconductor wafer 82 are bonded via the anisotropic conductive member 22, singulation is performed in each element region, for example, by dicing or laser scribing. In this way, a multilayer device 60 can be obtained in which the semiconductor element 62 and the semiconductor element 64 are bonded via the anisotropic conductive member 22. In this way, the multilayer device 60 can be obtained even when stacked wafers are used. In addition, as described above, detailed description of singulation is omitted. Furthermore, as shown in FIG. 27 , when the first semiconductor wafer 80 and the second semiconductor wafer 82 are bonded, if there is a semiconductor wafer that needs to be thinned between the first semiconductor wafer 80 and the second semiconductor wafer 82 , the thinning can be performed by chemical mechanical polishing (CMP) or the like.

In the third example of the method for manufacturing a multilayer device using a metal-filled microstructure, a double-layer structure in which the semiconductor element 62 and the semiconductor element 64 are stacked is described as an example, but the invention is not limited thereto and, as mentioned above, it can be three or more layers. In this case, as in the second example of the method for manufacturing the multilayer device 60, by providing an alignment mark (not shown) and a terminal (not shown) on the back surface 82b of the second semiconductor wafer 82, a multilayer device 60 having three or more layers can be obtained.

As described above, by providing the anisotropic conductive member 22 in the multilayer device 60, even if there are bumps on the semiconductor element, the bumps can be absorbed by using the protrusions 16a and 16b as a buffer layer. Since the protrusions 16a and 16b function as a buffer layer, high surface quality is not required for the element region in the semiconductor element. Therefore, smoothing treatment such as grinding is not required, production costs can be suppressed, and production time can be shortened. Furthermore, since the multilayer device 60 can be manufactured using a chip stacking wafer, productivity can be maintained and manufacturing losses can be reduced by bonding only the qualified semiconductor chips to the qualified parts in the semiconductor wafer. In addition, as described above, the resin layer 44 has adhesiveness and can be used as a temporary bonding agent during temporary bonding and can be used together with the formal bonding.

The semiconductor device 64 provided with the anisotropic conductive member 22 can be formed using the anisotropic conductive member 22 and a semiconductor wafer having a plurality of device regions (not shown). In the device region, an alignment mark (not shown) and a terminal (not shown) for alignment as described above are provided. In the anisotropic conductive material 50 (see FIG. 15 ), the anisotropic conductive member 22 is formed in a pattern matching the device region.

First, a predetermined pressure is applied, heated to a predetermined temperature and maintained for a predetermined time, and the anisotropic conductive member 22 of the anisotropic conductive material 50 is bonded to the device region of the semiconductor wafer. Second, the support 46 of the anisotropic conductive material 50 is removed, leaving only the anisotropic conductive member 22 bonded to the semiconductor wafer. In this case, in the anisotropic conductive material 50, the peeling agent 49 of the peeling layer 47 is heated to a predetermined temperature, so that the bonding force is reduced, thereby removing the support 46 starting from the peeling layer 47 of the anisotropic conductive material 50. Next, the semiconductor wafer is singulated in each device region to obtain a plurality of semiconductor devices 64. Also, the semiconductor device 64 provided with the anisotropic conductive component 22 is used as an example for explanation, but the semiconductor device 66 provided with the anisotropic conductive component 22 and the second semiconductor wafer 82 provided with the anisotropic conductive component 22 can also be provided with the anisotropic conductive component 22 in the same manner as the semiconductor device 64 provided with the anisotropic conductive component 22.

Regarding the bonding of semiconductor devices, the bonding of a semiconductor element to another semiconductor element is described, but it is not limited to this. It can also be a bonding of multiple semiconductor elements to one semiconductor element, that is, a one-to-multiple bonding. In addition, it can also be a bonding of multiple semiconductor elements to multiple semiconductor elements, that is, a multiple-to-multiple bonding. Figure 28 is a schematic diagram showing the 5th example of a multilayer device in the implementation form of the present invention, Figure 29 is a schematic diagram showing the 6th example of a multilayer device in the implementation form of the present invention, Figure 30 is a schematic diagram showing the 7th example of a multilayer device in the implementation form of the present invention, Figure 31 is a schematic diagram showing the 8th example of a multilayer device in the implementation form of the present invention, and Figure 32 is a schematic diagram showing the 9th example of a multilayer device in the implementation form of the present invention.

As a pair of multiple forms, as shown in FIG. 28, for example, a multilayer device 83 is illustrated, which is a form in which semiconductor element 62, semiconductor element 64, and semiconductor element 66 are bonded and electrically connected using anisotropic conductive members 22, respectively. In addition, semiconductor element 62 may be one having an interlayer function. In multilayer device 83, semiconductor element 62, semiconductor element 64, and semiconductor element 66 may be replaced by a semiconductor element wafer. Also, as a multiple-to-multiple form, as shown in FIG. 29, for example, a multilayer device 84 is illustrated, which is a form in which semiconductor element 64 and semiconductor element 66 are bonded and electrically connected to one semiconductor element 62 using anisotropic conductive members 22. Semiconductor element 62 may be one having an interlayer function.

Moreover, for example, on a device having an interposer function, multiple devices such as a logic chip and a memory chip having a logic circuit can be stacked. Moreover, in this case, even if the electrode sizes are different, they can be bonded to each device. In the stacked device 85 shown in FIG. 30, the size of the electrode 88 is different, and although there are mixed electrodes of different sizes, the semiconductor element 64 and the semiconductor element 66 are bonded and electrically connected to one semiconductor element 62 using an anisotropic conductive member 22. In addition, the semiconductor element 86 is bonded and electrically connected to the semiconductor element 64 using the anisotropic conductive member 22. The semiconductor element 87 is bonded and electrically connected to the semiconductor element 64 and the semiconductor element 66 using the anisotropic conductive member 22.

31, semiconductor element 64 and semiconductor element 66 are bonded to and electrically connected to one semiconductor element 62 using anisotropic conductive member 22. In addition, semiconductor element 86 and semiconductor element 87 are bonded to semiconductor element 64 using anisotropic conductive member 22, and semiconductor element 91 is bonded to semiconductor element 66 using anisotropic conductive member 22 and electrically connected.

In the case of the above-described configuration, by stacking light-emitting elements such as VCSEL (Vertical Cavity Surface Emitting Laser) and light-receiving elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors on the surface of a device such as an optical waveguide, it is possible to cope with silicon photons assumed to be high frequencies. For example, as in the stacked device 89a shown in FIG. 32 , the semiconductor element 64 and the semiconductor element 66 are bonded and electrically connected to one semiconductor element 62 using an anisotropic conductive member 22. In addition, semiconductor element 86 and semiconductor element 87 are bonded to semiconductor element 64 using anisotropic conductive member 22, and semiconductor element 91 is bonded to semiconductor element 66 using anisotropic conductive member 22 and electrically connected. An optical waveguide 81 is provided on semiconductor element 62. A light-emitting element 95 is provided on semiconductor element 66, and a light-receiving element 96 is provided on semiconductor element 64. Light Lo output from light-emitting element 95 of semiconductor element 66 passes through optical waveguide 81 of semiconductor element 62 and is emitted as emitted light Ld to light-receiving element 96 of semiconductor element 64. In this way, the above-mentioned silicon photon can be handled. In addition, a hole 27 is formed on anisotropic conductive member 22 at a position corresponding to the optical path of light Lo and emitted light Ld.

The specific assembly process in three-dimensional stacking using stacked bodies is explained. In order to realize three-dimensional stacking, wiring that supports electrical connection in the stacking direction needs to be formed in the stacked device. The wiring that supports the connection in the stacking direction is called TSV (Through Silicon Via). Devices with TSV are classified into three types: first drill (Via-first), middle drill (Vias-middle) and last drill (Via-last) according to the stage at which TSV is formed. TSV formed before forming the transistor of the device is called first drill. TSV formed after forming the transistor and before forming the redistribution layer is called middle drill. The formation of TSV after the redistribution layer is called post-drilling. Forming TSV by either method requires thinning the silicon substrate to perform the through-hole process.

The following describes the bonding method of semiconductor chips or wafers using TSV, along with examples of the use of laminated bodies. As a representative example of pre-drilling or mid-drilling, laminated memory chips called HBM (High Bandwidth Memory) or HMC (Hybrid Memory Cube) can be cited. In these examples, the TSV region is formed while the memory region is formed in the same mold shape, and the base wafer is thinned to form the TSV, and electrodes called microbumps are formed on the surface of the through hole, and laminated and bonded. As an example of post-drilling, the following process can be cited: a semiconductor chip or wafer without metal bumps is bonded by an insulating adhesive or an insulating oxide, and then TSV is formed.

In the past, after forming the interlayer joint, a hole was formed by a method such as the BOSCH method or the laser drilling method, a plating core was formed on the wall surface by sputtering, and metal was filled by plating to electrically connect to the wiring part of each layer. However, since the filling metal is formed by the growth of the plating core, the connection between the filling metal and the wiring part is not necessarily guaranteed. In contrast, when an anisotropic conductive member is used to connect the bumps, the conductive path of the anisotropic conductive member is directly formed to the bump, so the electrical connection is strengthened and the signal connection becomes better. At this time, an electrode that does not contribute to signal transmission is set on the surface of the semiconductor chip or the surface of the wafer, thereby increasing the area of the joint and improving the resistance to each shear stress. In addition, the heat conduction between the layers becomes good, so the heat can be easily diffused to the entire laminate. According to these mechanisms, the connection strength and heat dissipation are further improved.

Examples of bonding methods applicable to any of the pre-drilling, mid-drilling, and post-drilling methods include metal diffusion bonding, oxide film direct bonding, metal bump bonding, and eutectic bonding. Metal diffusion bonding or oxide film direct bonding has good bonding properties under low pressure and low temperature conditions. On the other hand, as a high degree of cleanliness of the bonding surface, for example, a level equal to that just after surface cleaning by Ar etching is required. Furthermore, as flatness, for example, the arithmetic mean roughness Ra is required to be 1 nm or less, so strict environmental control and parallelism control are required during bonding. Furthermore, product groups of semiconductor devices manufactured by different companies or even in the same company but in different factories may have different types of semiconductor devices or wiring rules. When these product groups of semiconductor devices are three-dimensionally stacked, the strictest precision or control is required.

On the other hand, metal bump bonding or eutectic bonding also has good bonding properties when there are some defects or when the steps are lengthy. In addition, due to the deformation or flow of bumps or solder, the cleanliness or flatness of the device surface when bonding different types of devices can sometimes be lower than that of metal diffusion bonding or oxide film direct bonding. Among these bonding methods, the following issues can be cited as issues: the bonding strength is lower than that of metal diffusion bonding and oxide film direct bonding; and each time the lamination is repeated, the bonded part is reheated, which may cause device failure. In the literature (National Institute of Advanced Industrial Science and Technology (AIST) Research Results Report March 8, 2013: "Multifunctional High-Density Three-Dimensional Integration Technology (2) Research and Development of Evaluation and Analysis Technology for Next-Generation Three-Dimensional Integration <(2)-B Research and Development of Heat/Laminar Bonding Technology>"), the following method is proposed: Temporary fixation during lamination is performed using an organic resin, and after lamination, all layers are heated and bonded together to avoid the influence of temperature history. By forming an electrode that does not contribute to signal transmission, heat dissipation is improved, so the application of laminated bodies is particularly useful for the use of organic resin layers with low thermal conductivity.

Next, the case where the anisotropic conductive member constituting the laminate is used in the above-mentioned bonding is described. The anisotropic conductive member used in the laminate preferably has a resin layer formed on at least one surface, and more preferably on both surfaces. Furthermore, the resin layer 44 of the anisotropic conductive member preferably includes a thermosetting resin. The above-mentioned resin layer is formed as a temporary bonding layer to suppress positional deviation after lamination. Since temporary bonding can be performed at a low temperature and in a short time, adverse effects on the device can be reduced. From the viewpoint of suppressing positional deviation caused by heat in the step, the thickness of the above-mentioned resin layer is preferably 100nm to 1000nm, the thermal conductivity of the anisotropic conductive member in the thickness direction is preferably 20 to 100W/(m·K), and the coefficient of thermal expansion (CTE) of the anisotropic conductive member is preferably 5ppm to 10ppm.

The anisotropic conductive member is preferably supplied in the form of being held on a support body via a removable adhesive layer. The material of the support body is not particularly limited, but materials such as silicon or glass are preferred from the viewpoint of being less prone to bending and being able to ensure constant flatness. The removable adhesive layer may be an adhesive layer with low adhesion, but an adhesive layer whose adhesion is reduced by heating or light irradiation is preferred. As an example of an adhesive layer whose adhesion is reduced by heating, REVALPHA (registered trademark) manufactured by Nitto Denko Corporation or SOMATAC (registered trademark) manufactured by SOMAR Corporation can be cited. As the adhesive layer whose adhesiveness is reduced by light irradiation, in addition to materials used for ordinary dicing tapes, a photo-peelable layer manufactured by 3M Company can also be used.

In an anisotropic conductive member, a pattern can be formed while being held on a support. Examples of pattern formation include concave-convex pattern formation, monolithicization, and hydrophilic-hydrophobic pattern formation. It is preferred to form a hydrophilic-hydrophobic pattern, and it is more preferred to monolithicize the hydrophilic-hydrophobic pattern. Since the anisotropic conductive member contains a conductive material, it is sufficient to form an electrode on the surface of the object to be bonded for bonding, and no special technology is required, such as special metal protrusions such as fine conical gold protrusions, or MONSTER PAC Core technology based on CONNECTEC JAPAN, Tohoku MicroTec Co., Ltd., and the Masahiro Aoyagi research group of the National Institute of Advanced Industrial Science and Technology (AIST). In particular, since bonding can be performed even when the surface flatness of the bonding object is low, it is preferable that the anisotropic conductive member has protrusions on the surface, and as described above, it is more preferable that the protrusion 16a, i.e., the protrusion includes a protrusion composed of a conductive material. In addition, since the thermal conductivity between layers of the laminate having the terminal having the area ratio of the present invention is good, heat is easily diffused to the entire laminate, and thus the heat dissipation is particularly good.

Next, the stacking method of stacking devices is explained. Among the methods of stacking different semiconductor chips, the COC (Chip on Chip) method, the COW (Chip on Wafer) method, and the WOW (Wafer on Wafer) method can be cited. The COC method is a method of stacking semiconductor chips on a semiconductor chip fixed to a substrate. It has the advantages of being able to stack semiconductor chips of different sizes and being able to screen qualified semiconductor chips before bonding. When stacking multiple semiconductor chips, the cost is high because alignment is required each time. The COW method is a method of stacking semiconductor chips on a substrate wafer. When stacking multiple semiconductor chips, the cost is high because alignment is required each time, just like the COC method. The WOW method is a method of bonding wafers together. It has advantages such as shortening the bonding time and facilitating alignment. However, since it is impossible to screen qualified semiconductor chips, the productivity of multiple-layer stacking is likely to decrease.

In order to shorten the alignment time, a method called self-alignment for performing simultaneous alignment on a wafer has been developed, and the technology is disclosed in Japanese Patent Publication No. 2005-150385 or Japanese Patent Publication No. 2014-57019. However, these documents only disclose the technology of aligning the positions of the fixed semiconductor chips. In order to electrically connect the layers, it is necessary to further perform any of the above-mentioned bonding methods. In order to apply metal diffusion bonding or oxide film direct bonding, it is necessary to accurately control the height of all arranged semiconductor chips, which is costly. On the other hand, when metal bump bonding or eutectic bonding is applied, a method of heating each time before bonding requires a countermeasure for reheating the bonded portion, and a method of heating all layers at once before bonding requires research to prevent the semiconductor chip from deviating during the stacking and a heat dissipation countermeasure.

For the above-mentioned subject, a three-dimensional stack using an anisotropic conductive member is useful. Therefore, it is preferable to use an anisotropic conductive member in each joint of the stack, but the stack may also include a joint based on a known method. As an example of a joint based on a known method, a stack having a joint based on an anisotropic conductive member having a hybrid bonding state between an optical semiconductor and an ASIC (Application Specific Integrated Circuit), and a surface activated bonding state between a memory and an ASIC can be cited. The joint based on a known method has the advantage that devices manufactured by different rules can be easily stacked on each other.

As an example of three-dimensional stacking using an anisotropic conductive member, the following can be cited. First, the first semiconductor chip set is inspected and singulated, and the first qualified semiconductor chip set is screened. The first qualified semiconductor chip set is arranged on the first substrate via the first anisotropic conductive member and temporarily bonded. The temporary bonding can be performed by a device such as a flip chip bonder. The first substrate is not particularly limited, and a device having a transistor or a substrate having a wiring layer and a through electrode can be cited as an example. After the stacked semiconductor chip set is inspected, it is singulated, and the stacked qualified semiconductor chip set is screened. The stacked semiconductor chip set is not particularly limited, and examples thereof include a state with a through electrode, or a state in which the back side of a semiconductor chip with a buried through hole is removed. As a method for removing the back side, back grinding, CMP, and chemical etching methods can be cited. In particular, removal methods such as chemical etching with less lateral stress are preferred.

Arrange the stacked qualified semiconductor chip set at a position on the second substrate corresponding to the arrangement of the first qualified semiconductor chip set on the first substrate. After the first substrate and the second substrate are aligned, a second anisotropic conductive member is sandwiched between the first substrate and the second substrate, and the first qualified semiconductor chip set and the stacked qualified semiconductor chip set are temporarily bonded via the second anisotropic conductive member. Next, the second substrate is peeled off from the stacked qualified semiconductor chip set and removed. The structure composed of the first qualified semiconductor chip set, the second anisotropic conductive component and the stacked qualified semiconductor chip set is set as a new first qualified semiconductor chip set, and the second anisotropic conductive component and the stacked semiconductor chip set are repeatedly stacked until a predetermined hierarchical structure is formed. After the predetermined hierarchical structure is formed, the hierarchical layers are formally bonded by heating and pressing at the same time, thereby obtaining a three-dimensional bonded structure. The obtained three-dimensional bonded structure is sealed by compression bonding and the like, and the target element is obtained by singulation. In addition, before singulation, thinning, rewiring, electrode formation and other processes can be performed.

As other examples, the following aspects can be cited: a aspect in which a stacked semiconductor chip set is singulated after being bonded to a first qualified semiconductor chip set via a second anisotropic conductive component; a aspect in which a patterned anisotropic conductive component is used as a first anisotropic conductive component or a second anisotropic conductive component; and a aspect in which a patterned anisotropic conductive component is used as an adhesive for arranging a stacked semiconductor chip set on a second substrate and is peeled off at the interface between the second substrate and the anisotropic conductive component.

As another example, the following aspects can be cited. First, a first anisotropic conductive member is provided on the surface of a first substrate. As the first substrate, a MOS (Metal Oxide Semiconductor) may be present or absent. The first semiconductor chip set is inspected and singulated, and a first qualified semiconductor chip set is selected. A second anisotropic conductive member is provided on the surface of a support through a temporary bonding layer whose adhesion is reduced by processing. The material of the support is not particularly limited, but silicon or glass is preferred. As the temporary bonding layer whose adhesiveness is reduced by treatment, a temporary bonding layer whose adhesiveness is reduced by heating or a temporary bonding layer whose adhesiveness is reduced by light irradiation is preferred.

A pattern is provided on the second anisotropic conductive member. As the pattern, a hydrophilic and hydrophobic pattern that has been singulated is more preferred. When the hydrophilic and hydrophobic pattern is singulated, it is easy to transfer the anisotropic conductive member to the first qualified semiconductor chip set in the subsequent process. The singulation method is not particularly limited, and examples thereof include dicing, laser irradiation, stealth dicing, wet etching, and dry etching.

By using a self-assembly technique using a pattern, a first qualified semiconductor chip group is arranged on a support body via a second anisotropic conductive member and temporarily bonded. As a self-assembly technique, for example, the following method can be cited: a droplet containing an active agent is formed on an assembly area of a substrate, a semiconductor chip group is placed on the droplet, a component is positioned in the assembly area and the droplet is dried, the component and the assembly substrate are bonded via a curable resin layer, and the active agent is washed off. Such techniques are disclosed in Japanese Patent Publication No. 2005-150385 or Japanese Patent Publication No. 2014-57019. When performing self-assembly, an electrode can also be used as an alignment mark.

The first substrate and the first qualified semiconductor chip set are temporarily bonded via the first anisotropic conductive member. Next, the bonding property of the temporary bonding layer is reduced, and the second anisotropic conductive member is peeled off at the interface between the second anisotropic conductive member and the support. The structure composed of the first substrate, the first anisotropic conductive member and the first qualified semiconductor chip set is set as a new first substrate, and the second anisotropic conductive member is set as a new first anisotropic conductive member, and the first qualified semiconductor chip set and the second anisotropic conductive member are repeatedly laminated until a predetermined hierarchical structure is formed.

After forming a structure with predetermined layers, the layers are formally bonded by processing them together under conditions of higher pressure and higher temperature than those used in the temporary bonding, thereby obtaining a three-dimensional bonding structure. Since the temporary bonding layer remains in the laminate, it is better to use a material that undergoes a hardening reaction under formal bonding conditions as a temporary bonding layer. The obtained three-dimensional bonding structure is sealed by compression bonding and the target laminated device is obtained by singulation. In addition, thinning, rewiring, and electrode formation can be performed before singulation. As described above, by using an anisotropic conductive member, temporary bonding and formal bonding can be separated, so that it is not necessary to perform multiple high-temperature steps such as reflow soldering, and the risk of device failure can be reduced. Also, as described above, in the case of using an anisotropic conductive member having a resin layer on the surface, the resin layer can alleviate the influence on the bonding portion caused by the step conditions. Also, in the case of using an anisotropic conductive member having protrusions on the surface, bonding is possible even when the surface flatness of the bonding object is low, so the flattening step can be simplified.

Hereinafter, regarding the three-dimensional stacking using the stacked body, FIG. 33 to FIG. 48 are used to provide a more specific description. FIG. 33 to FIG. 43 are schematic diagrams showing the fourth example of the method for manufacturing a stacked device using a metal-filled microstructure in the embodiment of the present invention in the process sequence. FIG. 44 to FIG. 46 are schematic diagrams showing the method for manufacturing a stacked body used in the fourth example of the method for manufacturing a stacked device using a metal-filled microstructure in the embodiment of the present invention in the process sequence. FIG. 47 and FIG. 48 are schematic diagrams showing the method for manufacturing a stacked body used in the fourth example of the method for manufacturing a stacked device using a metal-filled microstructure in the embodiment of the present invention in the process sequence. The fourth example of the method for manufacturing a laminated device using a metal-filled microstructure is related to three-dimensional lamination, and uses an anisotropic conductive member like the second example of the method for manufacturing a laminated device using a metal-filled microstructure. Therefore, the detailed description of the manufacturing method common to the second example of the method for manufacturing a laminated device using a metal-filled microstructure is omitted.

First, as shown in FIG. 33 , a first multilayer substrate 90 is prepared in which an anisotropic conductive component 22 is provided on the entire surface 92a of a semiconductor wafer 92. The semiconductor wafer 92 can be configured to have the same structure as the first semiconductor wafer 80 having a plurality of element regions (not shown), for example. In addition, the semiconductor wafer 92 can also be configured as the above-mentioned intermediate layer 23. Furthermore, as shown in FIG. 34 , a second multilayer substrate 100 is prepared in which a plurality of semiconductor elements 64 are provided. The second multilayer substrate 100 has a peeling functional layer 104 and an anisotropic conductive component 22 laminated on the surface 102a of the second substrate 102. A plurality of semiconductor elements 64 are provided on the anisotropic conductive member 22. A hydrophilic/hydrophobic film 105 is provided on the anisotropic conductive member 22 in the region where the semiconductor element 64 is not provided. In the second laminate substrate 100, the back surface 64b of the semiconductor element 64 is the surface on the second substrate 102 side, and the surface 64a is the surface on the opposite side. The semiconductor element 64 is, for example, a qualified semiconductor element that has been screened after inspection.

The peeling functional layer 104 is composed of, for example, an adhesive layer whose adhesiveness is reduced by heating or light irradiation. As an example of an adhesive layer whose adhesiveness is reduced by heating, REVALPHA (registered trademark) manufactured by Nitto Denko Corporation or SOMATAC (registered trademark) manufactured by SOMAR Corporation can be cited. As an adhesive layer whose adhesiveness is reduced by light irradiation, in addition to being able to use materials such as those used for ordinary dicing tapes, a photo-peelable layer manufactured by 3M Company can also be cited.

Next, as shown in FIG. 35 , the first multilayer substrate 90 and the second multilayer substrate 100 are temporarily bonded. In addition, the method of temporary bonding is as described above. In addition, a flip chip bonder or the like is used for temporary bonding. Next, as shown in FIG. 36 , the second substrate 102 of the second multilayer substrate 100 is removed. In this case, the semiconductor element 64 is in a state of temporary bonding with the anisotropic conductive component 22 of the semiconductor wafer 92, and the anisotropic conductive component 22 is transferred to the surface 64a of the semiconductor element 64. The second substrate 102 is removed by reducing the adhesion of the peeling functional layer 104, for example, by heating or light irradiation.

Next, as shown in FIG. 37, another second multilayer substrate 100 is temporarily bonded to the anisotropic conductive member 22 on the surface 64a side of the semiconductor element 64, aligning the positions of the semiconductor elements 64. In this case, the back surface 64b of the semiconductor element 64 of the other second multilayer substrate 100 and the anisotropic conductive member 22 on the surface 64a side of the semiconductor element 64 temporarily bonded to the semiconductor wafer 92 are temporarily bonded. The method of temporary bonding is as described above. Next, as shown in FIG. 38, the second substrate 102 of the other second multilayer substrate 100 is removed. The method of removing the second substrate 102 is as described above. As shown in FIG38, the semiconductor element 64 is in a state of being temporarily bonded to the anisotropic conductive member 22 of the semiconductor element 64 on the semiconductor wafer 92 side, and the anisotropic conductive member 22 is transferred to the surface 64a of the semiconductor element 64. FIG38 shows that the semiconductor element 64 has a two-layer structure. In this way, by repeatedly performing the temporary bonding of the second laminate substrate 100, the number of layers of the semiconductor element 64 can be controlled.

Here, the third composite laminate 106 shown in FIG. 39 is prepared. The third composite laminate 106 has a third substrate 108, and a hydrophilic and hydrophobic film 109 is formed on its surface 108a in a specific pattern. In addition, the semiconductor element 64 is provided on the surface 108a where the third substrate 108 is not provided, that is, the area where the hydrophilic and hydrophobic film 109 is provided. In this case, the semiconductor element 64 can use, for example, a qualified semiconductor element that has been inspected and screened. The hydrophilic and hydrophobic film 109 is coated with a hydrophobic material through a mask, for example, and is provided in a desired pattern, thereby obtaining a specific pattern. As the hydrophobic material, compounds such as alkylsilane or fluoroalkylsilane can be used. As the water-repellent material, a material showing a water-repellent effect based on shape, such as a phase separation structure of isomeric polypropylene (i-PP), etc. can be used.

Next, as shown in FIG. 40 , for the first multilayer substrate 90 having two layers of semiconductor elements 64, the third composite laminate 106 is temporarily bonded on the anisotropic conductive member 22 on the surface 64a side of the semiconductor element 64 by aligning the positions of the semiconductor elements 64. Thus, the semiconductor element 64 is provided with three layers. Next, as shown in FIG. 41 , the third substrate 108 of the third composite laminate 106 is removed. The method of removing the third substrate 108 is the same as the method of removing the second substrate 102 described above. Next, by performing a combined process under higher pressure and higher temperature conditions than those used in the temporary bonding, the semiconductor element 64, the anisotropic conductive member 22, and the semiconductor wafer 92 are formally bonded to obtain a three-dimensional bonded structure 94 as shown in Fig. 42. In addition, the three-dimensional bonded structure 94 may be subjected to processes such as thinning, rewiring, and electrode formation.

Next, the semiconductor wafer 92 and the anisotropic conductive member 22 of the three-dimensionally bonded structure 94 are cut and singulated as shown in Fig. 43. Thus, a multilayer device 60 can be obtained in which three semiconductor elements 64 are bonded via the anisotropic conductive member 22. The singulation method can appropriately utilize the above-mentioned method.

As shown in FIG. 44, the second laminated substrate 100 shown in FIG. 34 is formed by laminating the peeling functional layer 104 and the anisotropic conductive member 22 on the surface 102a of the second substrate 102. Next, as shown in FIG. 45, a hydrophilic and hydrophobic film 105 is formed on the anisotropic conductive member 22 in a specific pattern. The hydrophilic and hydrophobic film 105 is formed on the anisotropic conductive member 22 in a pattern by, for example, a lithography method or a self-organization method. In the hydrophilic and hydrophobic film 105, as an example of a hydrophilic material forming a hydrophilic pattern, a hydrophilic polymer such as polyvinyl alcohol can be cited. In addition, the hydrophilic and hydrophobic film 105 can also be formed by the material used for the above-mentioned hydrophilic and hydrophobic film 109. The hydrophilic and hydrophobic film 105 can also be made of, for example, a resist material containing a fluorine compound, and a specific pattern can be formed by exposure and development.

Next, as shown in FIG. 46 , a semiconductor element 64 is provided in an area where the hydrophilic and hydrophobic film 105 is not provided. Thus, the second laminated substrate 100 shown in FIG. 34 is obtained. As a method for providing the semiconductor element 64, for example, the following method can be used: a droplet containing an active agent is formed in an area where the hydrophilic and hydrophobic film 105 is not provided, the semiconductor element 64 is placed on the droplet for positioning and drying, the semiconductor element 64 and the second substrate 102 are bonded via a curable resin layer, and the active agent is washed off.

As shown in FIG. 47 , the third composite laminate 106 shown in FIG. 39 prepares the third substrate 108. Next, as shown in FIG. 48 , a hydrophilic/hydrophobic film 109 is formed in a specific pattern on the surface 108a of the third substrate 108. The hydrophilic/hydrophobic film 109 has the same structure as the above-mentioned hydrophilic/hydrophobic film 105 and can be formed in the same way. Next, a semiconductor element 64 is provided in an area where the hydrophilic/hydrophobic film 109 is not provided. As a method for providing the semiconductor element 64, for example, the following method can be used: a droplet containing an active agent is formed in an area where the hydrophilic/hydrophobic film 109 is not provided, a semiconductor element 64 is placed on the droplet for positioning and the droplet is dried, the semiconductor element 64 and the third substrate 108 are bonded via a curable resin layer, and the active agent is washed off. In this way, the third composite laminate 106 shown in FIG. 39 is obtained.

In addition, new methods that do not use TSV can also be used. In three-dimensional assembly, as mentioned above, it is sometimes required to bond a pair of multiple shapes or multiple to multiple shapes. At this time, it is usually necessary to pre-assign the function of an interposer to any device. However, considering the heterogeneous bonding environment, it is not preferable to pre-design in order to aggregate each device. As a method to solve this problem, a method of using a redistribution layer (RDL: Re-Distribution Layer) alone has been proposed. By bonding a redistribution layer that has an interposer function for connecting various devices and embedding it in an anisotropic conductive film, it is possible to achieve thinness and no TSV without being constrained by the design of each device. A stack of multiple devices can also be provided in an organic substrate with the same specifications. Examples of such assembly are shown in FIGS. 49 to 66. In addition, as a specific assembly method, it is of course not limited to those shown in FIGS. 49 to 66. FIGS. 49 to 61 are schematic diagrams showing the fifth example of a method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention in a process sequence, and FIGS. 62 to 66 are schematic diagrams showing the sixth example of a method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention in a process sequence. 49 to 66, the same symbols are used for the same components as the anisotropic conductive material 50 and the multilayer device 60 shown in FIG. 13, and their detailed description is omitted.

First, an anisotropic conductive material 50 having a support 46 and an anisotropic conductive member 22, and a wafer 112 provided with a redistribution layer 110 are prepared. In addition, the redistribution layer 110 has the above-mentioned intermediate layer function. As shown in FIG. 49, the redistribution layer 110 is arranged opposite to the anisotropic conductive member 22, and as shown in FIG. 50, the anisotropic conductive member 22 and the redistribution layer 110 are bonded and electrically connected. Next, as shown in FIG. 51, the wafer 112 is separated from the redistribution layer 110.

Next, as shown in FIG. 52, an anisotropic conductive material 50 is arranged on the redistribution layer 110 opposite to the anisotropic conductive member 22. Next, as shown in FIG. 53, the redistribution layer 110 and the anisotropic conductive member 22 are joined, and as shown in FIG. 54, a support 46 is separated. Next, as shown in FIG. 55, a semiconductor element 62 is arranged opposite to the anisotropic conductive member 22 from which a support 46 is separated. Next, as shown in FIG. 56, the anisotropic conductive member 22 and the semiconductor element 62 are joined and electrically connected. Next, as shown in FIG. 57, the remaining support 46 is separated. Next, as shown in FIG. 58, a semiconductor element 64 is disposed opposite to the anisotropic conductive member 22 separated from the remaining support body 46 on the side where the semiconductor element 62 is not disposed.

Next, as shown in FIG. 59, the anisotropic conductive member 22 and the semiconductor element 64 are joined and electrically connected. Thus, the semiconductor element 62 and the semiconductor element 64 can be stacked without using TSV. In addition, the semiconductor element 64 is configured in FIG. 58, but it is not limited to this. As shown in FIG. 60, the semiconductor element 64 and the semiconductor element 66 can also be configured on one semiconductor element 62. In this case, as shown in FIG. 61, a plurality of semiconductor elements 64 and semiconductor elements 66 are configured on one semiconductor element 62. In this case, the semiconductor element 64 and the semiconductor element 66 can also be stacked on the semiconductor element 62 without using TSV.

Furthermore, the redistribution layer 110 is not limited to being used alone, but can also be embedded in an organic substrate for use. In this case, as shown in FIG. 62, an organic substrate 120 is disposed opposite to the redistribution layer 110 and on an anisotropic conductive material 50 provided with the redistribution layer 110. The organic substrate 120 functions as an intermediate layer, for example. Next, as shown in FIG. 63, the organic substrate 120 is electrically connected to the redistribution layer 110, for example, by soldering. In this case, the redistribution layer 110 can also be embedded in the organic substrate 120. Next, as shown in FIG. 64, the support body 46 is separated. Next, as shown in FIG. 65, a semiconductor element 62 is disposed opposite to the anisotropic conductive member 22. Next, as shown in FIG. 66, the semiconductor element 62 is bonded and electrically connected to the anisotropic conductive member 22. In this way, a laminated structure with a redistribution layer 110 and a semiconductor element 62 can be obtained. In addition, the semiconductor element is used as an example in the above description, but it is not limited to this, and a semiconductor wafer can also be used instead of a semiconductor element. In addition, the structure of the semiconductor element is not particularly limited, and the above example can be appropriately used.

Here, temporary bonding refers to fixing a semiconductor element or a semiconductor wafer to an object to be bonded in a state of being aligned with the object to be bonded. Formal bonding refers to bonding the objects to each other under predetermined conditions in a state of temporary bonding. Formal bonding refers to a state in which the bonding state is permanently not released as long as no special external force is applied. Since formal bonding is performed at the same time as described above, production time can be shortened and productivity can be improved.

The bonding method is not particularly limited to the above method, and DBI (Direct Bond Interconnect) and SAB (Surface Activated Bond) can be used. For example, in the case of bonding an anisotropic conductive component and a semiconductor wafer, the above DBI deposits a silicon oxide film on the anisotropic conductive component and the semiconductor wafer, and performs chemical mechanical polishing. Then, the silicon oxide film interface is activated by plasma treatment, and the anisotropic conductive component and the semiconductor wafer are bonded by contacting the two. For example, in the case of bonding an anisotropic conductive component and a semiconductor wafer, the above SAB performs surface treatment and activation on each bonding surface of the anisotropic conductive component and the semiconductor wafer in a vacuum. In this state, the anisotropic conductive member and the semiconductor wafer are brought into contact with each other at room temperature to bond the two. In the surface treatment, ion irradiation of an inert gas such as argon or irradiation of a neutral atom beam is used.

Furthermore, when performing temporary bonding, when bonding the anisotropic conductive member and the semiconductor wafer, the semiconductor wafer and the semiconductor element are inspected to separate good and bad products in advance, and only good semiconductor elements are bonded to the good parts of the semiconductor wafer via the anisotropic conductive member, thereby reducing manufacturing losses. The semiconductor element with guaranteed quality is called KGD (Known Good Die: high-quality chip).

Furthermore, in the process of bonding a semiconductor element to an element region, multiple semiconductor elements are temporarily bonded and then all of them are bonded together, but this is not limited to this. Depending on the bonding method, there are also cases where temporary bonding is not possible. In this case, temporary bonding of the semiconductor element can be omitted. In addition, the semiconductor elements can be bonded one by one to the element region of the semiconductor wafer. The transportation and pickup of semiconductor elements and semiconductor wafers, as well as temporary bonding and formal bonding, can be achieved by using known semiconductor manufacturing equipment.

In the case of the above-mentioned temporary bonding, equipment from TORAY ENGINEERING Co., Ltd., SHIBUYA CORPORATION, SHINKAWA LTD., and Yamaha Motor Co., Ltd. can be used. As equipment used for the above-mentioned formal bonding, for example, wafer bonding equipment from MITSUBISHI HEAVY INDUSTRIES MACHINE TOOL CO., LTD., Bondtech Co., Ltd., PMT CORPORATION, AYUMI INDUSTRY Co., Ltd., Tokyo Electron Limited. (TEL), EVG, SÜSS MICROTEC SE. (SUSS), MUSASHINO ENGINEERING CO., LTD. can be used. When performing various types of bonding such as temporary bonding and formal bonding, the bonding environment, heating temperature, pressure (load), and processing time can be cited as control factors, but conditions suitable for devices such as semiconductor elements used can be selected.

As the environment for bonding, you can choose from an inert environment such as a nitrogen environment and a vacuum state, starting with the atmosphere. The heating temperature can be selected from various temperatures from 100°C to 400°C, and the heating rate can be selected from 10°C/minute to 10°C/second according to the performance of the heating stage or the heating method. The same applies to cooling. In addition, you can heat in steps, or you can bond by increasing the heating temperature in multiple stages. Regarding pressure (load), you can also choose to pressurize rapidly or pressurize in steps according to the characteristics of the resin sealant.

The holding time and change time of the environment, heating and pressurization during bonding can be appropriately set. In addition, the sequence can also be appropriately changed. For example, the following sequence can be combined: after becoming a vacuum state, the first stage of pressurization is performed, and then when the temperature is raised by heating, the second stage of pressurization is performed and maintained for a constant time, and cooling is performed while unloading, and the temperature is returned to the atmosphere at a stage below a constant temperature. These sequences can be reorganized in various ways. After pressurization in the atmosphere, it can be set to a vacuum state and heated, or vacuumization, pressurization and heating can be performed at the same time. Examples of these combinations are shown in Figures 67 to 73. Furthermore, if a mechanism is used to independently control the pressure distribution and heat distribution within the surface during bonding, the yield of bonding can be improved. The same changes can be made to temporary bonding, for example, by performing it in an inert environment, it is possible to suppress the oxidation of the electrode surface of the semiconductor element. In addition, bonding can also be performed while adding ultrasound.

Figures 67 to 73 are graphs showing the first to seventh examples of formal bonding conditions. Figures 67 to 73 show the environment, heating temperature, pressure (load) and processing time during bonding, with symbol V representing the vacuum degree, symbol L representing the load, and symbol T representing the temperature. In Figures 67 to 73, a high vacuum degree means a lower pressure. In Figures 67 to 73, the lower the vacuum degree, the closer it is to atmospheric pressure. Regarding the environment, heating temperature and load during bonding, for example, as shown in Figures 67 to 69, after applying a load in a state of reducing pressure, the temperature can be increased. In addition, as shown in Figures 70, 72 and 73, the moment of applying the load can be matched with the moment of increasing the temperature. As shown in Figure 71, the load can also be applied after the temperature is increased. Furthermore, as shown in Figs. 70 and 71, the timing of reducing the pressure can be matched with the timing of increasing the temperature. The temperature rise can also be stepped as shown in Figs. 67, 68 and 72, or can be heated in two stages as shown in Fig. 73. As shown in Figs. 69 and 72, the load can also be applied in a stepped manner. Furthermore, the timing of reducing the pressure can be applied after the pressure is reduced as shown in Figs. 67, 69, 71, 72 and 73, or the timing of reducing the pressure can be matched with the timing of applying the load as shown in Figs. 68 and 70. In this case, the pressure is reduced and joined simultaneously.

The present invention is basically constructed as described above. The above is a detailed description of the method for manufacturing the metal-filled microstructure of the present invention, but the present invention is not limited to the above-mentioned implementation form, and various improvements or changes can be made without departing from the scope of the present invention. [Example]

Hereinafter, examples are given to explain the features of the present invention in more detail. The materials, reagents, mass ratios and operations shown in the following examples can be appropriately changed as long as they do not deviate from the main purpose of the present invention. Therefore, the scope of the present invention is not limited to the following examples. In this example, metal-filled microstructures of Examples 1 and 2 and metal-filled microstructures of Comparative Examples 1 to 3 were prepared. The number of micro-defects and the nano-defect rate of the metal-filled microstructures of Examples 1 and 2 and the metal-filled microstructures of Comparative Examples 1 to 3 were evaluated. The evaluation results of the number of micro-defects and the nano-defect rate are shown in Table 2 below. The following is an explanation of the number of micro defects and the nano defect rate.

The evaluation of the number of micro defects is explained. ＜Evaluation of the number of micro defects＞ After polishing one side of the manufactured metal-filled microstructure, the polished surface is observed by an optical microscope to try to find defects. Then, the number of defects is counted, the number of defects per unit area is calculated, and the number of defects is evaluated according to the evaluation criteria shown in Table 1 below. In the evaluation, both the evaluation criteria of 20 to 50 μm in diameter and the evaluation criteria of more than 50 μm in diameter need to be met. For example, the evaluation AA is set to satisfy 0.001 to 0.1 for 20 to 50 μm in diameter and no diameter exceeding 50 μm is detected. In addition, the above-mentioned single-sided polishing was carried out as follows. First, the manufactured metal-filled microstructure was attached to a 4-inch wafer using a Q-chuck (registered trademark) (manufactured by MARUISHI SANGYO CO., LTD.), and the metal-filled microstructure was polished using a polishing device manufactured by MAT Inc. until the arithmetic mean roughness (JIS (Japanese Industrial Standards) B0601: 2001) became 0.02 μm. Abrasive particles containing aluminum oxide were used for polishing.

[Table 1] Defect size Evaluation Criteria AA A B C Number of defects (/mm ² ) Diameter: 20～50μm 0.01~0.1 More than 0.1 and less than 1 More than 1 and less than 5 More than 5 and less than 10 Diameter over 50μm Not detected Not detected 0.01~0.1 More than 0.1 and less than 1 Number of defects (/mm ² ) Defect size D E F Diameter: 20～50μm More than 10 and less than 50 More than 50 and less than 100 More than 100 Diameter over 50μm More than 1 and less than 5 More than 5 and less than 10 More than 10

The evaluation of the nano defect rate is explained. ＜Evaluation of the nano defect rate＞ Regarding the manufactured metal-filled microstructure, 10 fields of view were observed by taking 10,000-fold FE-SEM (Field Emission Scanning Electron Microscope) images, and the total number of pores and the number of unfilled pores in each field of view were counted. Using the average value of the total number of pores in 10 fields of view and the average value of the number of unfilled pores in 10 fields of view, the nano defect rate (%) = ((average number of unfilled pores) / (average number of total pores)) × 100 (%). The results are shown in Table 2 below. In addition, the cross section was obtained by cutting using a focused ion beam (FIB).

Hereinafter, Example 1, Example 2, and Comparative Examples 1 to 3 will be described. (Example 1) The metal-filled microstructure of Example 1 will be described. [Metal-filled microstructure] <Production of aluminum components> Molten metal was prepared using an aluminum alloy containing Si: 0.06 mass%, Fe: 0.30 mass%, Cu: 0.005 mass%, Mn: 0.001 mass%, Mg: 0.001 mass%, Zn: 0.001 mass%, Ti: 0.03 mass%, and the remainder being Al and inevitable impurities. After molten metal treatment and filtration, a casting with a thickness of 500 mm and a width of 1200 mm was produced by the DC (Direct Chill) casting method. Next, the surface was milled with a flat milling cutter to an average thickness of 10 mm, then kept at 550°C for about 5 hours, and when the temperature dropped to 400°C, a hot rolling machine was used to roll the plate to a thickness of 2.7 mm. In addition, after heat treatment at 500°C using a continuous annealing machine, it was finished to a thickness of 1.0 mm by cold rolling to obtain an aluminum member of JIS (Japanese Industrial Standard) 1050 material. After the aluminum member was formed into a wafer with a diameter of 200 mm (8 inches), the following treatments were performed.

<Electrolytic polishing> The aluminum component was subjected to electrolytic polishing using the electrolytic polishing liquid of the following composition at a voltage of 25 V, a liquid temperature of 65°C, and a liquid flow rate of 3.0 m/min. The cathode was a carbon electrode, and the power source was GP0110-30R (manufactured by TAKASAGO LTD.). The flow rate of the electrolyte was measured using a vortex flow monitor FLM22-10PCW (manufactured by AS ONE Corporation.). (Electrolytic polishing liquid composition) ・85 mass% phosphoric acid (Wako Pure Chemical, Ltd. reagent) 660 mL ・Pure water 160 mL ・Sulfuric acid 150 mL ・Ethylene glycol 30 mL

<Anodic oxidation process> Next, the aluminum components after electrolytic polishing were subjected to anodic oxidation by the self-regularization method according to the procedure described in Japanese Patent Publication No. 2007-204802. The aluminum components after electrolytic polishing were subjected to pre-anodic oxidation for 5 hours using 0.50 mol/L oxalic acid electrolyte at a voltage of 40 V, a liquid temperature of 16°C, and a liquid flow rate of 3.0 m/min. Then, the aluminum components after pre-anodic oxidation were subjected to a stripping treatment by immersing in a mixed aqueous solution of 0.2 mol/L chromic anhydride and 0.6 mol/L phosphoric acid (liquid temperature: 50°C) for 12 hours. Then, a re-anodization treatment was carried out for 3 hours and 45 minutes using an electrolyte solution of 0.50 mol/L oxalic acid at a voltage of 40 V, a liquid temperature of 16°C, and a liquid flow rate of 3.0 m/min, to obtain an anodic oxide film with a film thickness of 30 μm. In addition, in both the pre-anodization treatment and the re-anodization treatment, the cathode was a stainless steel electrode, and the power source used was GP0110-30R (manufactured by TAKASAGO LTD.). In addition, the cooling device used was NeoCool BD36 (manufactured by Yamato Scientific Co., Ltd.), and the stirring and heating device used was a counter stirrer PS-100 (manufactured by EYELATOKYO RIKAKIKAI CO, LTD.). In addition, the flow rate of the electrolyte was measured using a vortex flow monitor FLM22-10PCW (manufactured by AS ONE Corporation.).

<Barrier layer removal process> Secondly, under the same treatment solution and treatment conditions as the above-mentioned anodic oxidation treatment, an electrolytic treatment (electrolytic removal treatment) was performed while the voltage was continuously reduced from 40V to 0V at a voltage reduction rate of 0.2V/sec. Then, an etching treatment (etching removal treatment) was performed by immersion in a 5 mass% phosphoric acid aqueous solution at 30°C for 30 minutes to remove the barrier layer existing at the bottom of the pores of the anodic oxide film, so that the aluminum component was exposed through the pores.

Here, the through holes, i.e., the average diameter of the pores, existing in the anodic oxide film after the barrier layer removal process is 60nm. In addition, the surface photograph (50,000 times magnification) was taken by FE-SEM (Field emission - Scanning Electron Microscope), and the average diameter was calculated as the average value of 50 points. In addition, the average thickness of the anodic oxide film after the barrier layer removal process is 80μm. In addition, the anodic oxide film was cut in the thickness direction by FIB (Focused Ion Beam), and the surface photograph (50,000 times magnification) of its cross section was taken by FE-SEM, and the average thickness was calculated as the average value of 10 points. The density of through holes in the anodic oxide film is about 100 million/ ^mm2 . The density of through holes is measured and calculated by the method described in paragraphs <0168> and <0169> of Japanese Patent Publication No. 2008-270158. The regularity of through holes in the anodic oxide film is 92%. The regularity is measured and calculated by taking a surface photograph (20,000 times magnification) by FE-SEM and by the method described in paragraphs [0024] to [0027] of Japanese Patent Publication No. 2008-270158.

Next, a metal layer is formed on the exposed aluminum member at the bottom of the pore using Zn (zinc). In addition, in the barrier layer removal process, a metal layer composed of Zn is formed at the bottom of the pore while removing the barrier layer using an alkaline aqueous solution containing Zn ions. In Example 1, a metal layer other than the valve metal is formed in an area of more than 80% of the area of the bottom of the pore, which is the area ratio of the metal layer composed of Zn. In addition, the area ratio of the metal layer other than the valve metal is recorded as "area ratio other than the valve metal" in Table 2. In addition, the area ratio other than the valve metal is calculated as the average value by cutting the anodic oxide film in the thickness direction using FIB (Focused Ion Beam) and taking surface photographs of 10 fields of view (50,000 times magnification) of the cross section using FE-SEM, measuring the area ratio of the Zn layer formed on the surface of the aluminum member where the pores are exposed in each field of view.

<Metal filling process> Next, the aluminum member with the anodic oxide film formed thereon was plated in a supercritical state with the aluminum member as the cathode and platinum as the positive electrode. The copper plating solution shown below was used for the metal plating. In addition, a supercritical state was achieved by using carbon dioxide and setting the temperature to 35°C and the pressure to 15 MPa. The metal plating was performed in a supercritical state. In addition, the electroplating device shown in FIG. 12 was used for the metal plating.

(Copper plating solution composition and conditions) ・Copper sulfate 100g/L ・Sulfuric acid 10g/L ・Hydrochloric acid 5g/L ・Non-ionic surfactant 1 mass% ・Current density 3A/ ^dm2・Plating solution temperature 35℃ ・Pressure 15Mpa ・Counter electrode (positive electrode) Pt

<Substrate removal process> Secondly, the aluminum components were dissolved and removed by immersion in a 20 mass % mercuric chloride aqueous solution (mercuric chloride) at 20°C for 3 hours, thereby producing a metal-filled microstructure.

(Example 2) Compared with Example 1, in Example 2, after the anodic oxide film is formed, the aluminum member (metal part) is removed. Then, the pore expansion and barrier layer removal are performed. Thus, the anodic oxide film 14 is provided as a single body (see FIG8). The pore expansion and barrier layer removal are performed by immersing in a 50 g/L, 40°C phosphorus aqueous solution for 15 minutes. Second, an Au (gold) film is formed on the back surface 14b of the anodic oxide film 14 by electroless plating, and a metal member 24 is provided on the back surface 14b of the anodic oxide film 14 (see FIG10). In addition, the metal component covers the entire opening of the fine hole, and the metal component 24 other than the valve metal is exposed at the bottom of the fine hole (see Figure 10). In Example 2, 100% of the area at the bottom of the fine hole is composed of the metal component 24 other than the valve metal (see Figure 10), and the area ratio other than the valve metal is 100%. Secondly, the anodic oxide film 14 provided with the metal component 24 is metal-plated in a supercritical state under the same conditions as in Example 1. After metal plating, the metal component is polished and removed, thereby producing a metal-filled microstructure. Similar to Example 1, the average diameter of the pores in Example 2 is 60 nm, and the regularity of the pores is 92%.

(Comparative Example 1) Comparative Example 1 is different from Example 1 in that the plating reaction field is set to a liquid phase and metal plating is performed under atmospheric pressure during the plating process, and other than that, it is the same as Example 1. Comparative Example 1 does not perform metal plating in a supercritical state. (Comparative Example 2) Comparative Example 2 is different from Example 2 in that the plating reaction field is set to a liquid phase and metal plating is performed under atmospheric pressure during the plating process, and other than that, it is the same as Example 2. Comparative Example 2 does not perform metal plating in a supercritical state. (Comparative Example 3) Compared with Example 1, Comparative Example 3 is the same as Example 1 except that the area ratio of the metal layer composed of Zn is set to 50%. In Comparative Example 3, the etching treatment time in the above-mentioned barrier layer removal process is shortened to adjust the area ratio.

[Table 2] Metal components Area ratio excluding valve metal Plating reaction field temperature pressure Reviews Number of micro defects Nano defect rate Embodiment 1 Al 80% Supercritical 35℃ 15MPa AA Less than 1% Embodiment 2 Au 100% Supercritical 35℃ 15MPa AA Less than 1% Comparison Example 1 Al 80% Liquid Phase 35℃ Atmospheric pressure D 10% Comparison Example 2 Au 100% Liquid Phase 35℃ Atmospheric pressure D 10% Comparison Example 3 Al 50% Supercritical 35℃ 15MPa D 10%

As shown in Table 2, compared with Comparative Examples 1 to 3, Examples 1 and 2 have fewer micro defects and fewer and better pores. Since Comparative Examples 1 and 2 do not perform metal plating in a supercritical state, the metal does not fully fill the pores, the number of micro defects is large, and the nano defect rate is also large. In Comparative Example 3, the area ratio of materials other than the valve metal is small, the metal does not fully fill the pores, the number of micro defects is large, and the nano defect rate is also large.

10: Aluminum component 10a: Surface 12: Through hole 12c: Bottom 12d: Surface 13: Barrier layer 14: Anode oxide film 15: Metal 15a: Metal layer 15b: Metal 16: Conductive path 17: Structure 20: Metal-filled microstructure 22: Anisotropic conductive component 23: Intermediate layer 27: Hole 28: Plating device 29: Plating groove 30: Oven 31: Counter electrode 32: Power supply unit 33: Control unit 34: Supply unit 35: Pump 36: Valve 37: Supply pipe 38: Pressure adjustment unit 39: Discharge pipe 40: Insulating substrate 40a: Surface 40b: Back 16a, 16b: Protrusion 44: Resin layer 46: Support body 47: Release layer 48: Support layer 49: Release agent 50: Anisotropic conductive material 60: Multilayer device 62: Semiconductor element 64: Semiconductor element 64a, 66a, 80 a: Surface 64b, 82b: Back 66, 72, 86, 87: Semiconductor element 74: Sensor chip 76: Lens 80: First semiconductor wafer 81: Optical waveguide 82: Second semiconductor wafer 83, 84, 85, 89, 89a: Multilayer device 88: Electrode 90: First multilayer substrate 91: Semiconductor element 92: Semiconductor wafer 92a, 102a, 108a: Surface 94: Three-dimensional bonding structure 95 : Light-emitting element 96: Light-receiving element 100: Second laminate substrate 102: Second substrate 104: Stripping functional layer 105: Hydrophilic/hydrophobic film 106: Third composite laminate 108: Third substrate 109: Hydrophilic/hydrophobic film 110: Rewiring layer 112: Wafer 120: Organic substrate AQ: Plating solution Ds: Lamination direction Dt: Thickness direction d: Average diameter Ld: Emitted light Lo: Light h, ht: Thickness x: Direction

FIG. 1 is a schematic cross-sectional view showing a process of a first embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing a process of a first embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing a process of a first embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing a process of a first embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a process of a first embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing an enlarged view of a process of a first embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view showing a process of a second embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 8 is a schematic cross-sectional view showing a process of a second embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 9 is a schematic cross-sectional view showing a process of a second embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 10 is a schematic cross-sectional view showing a process of a second embodiment of a method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 11 is a schematic cross-sectional view showing an enlarged view of a process of the second embodiment of the method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 12 is a schematic view showing an electroplating device used in a plating process in the method for manufacturing a metal-filled microstructure according to an embodiment of the present invention. FIG. 13 is a top view showing an example of a metal-filled microstructure according to an embodiment of the present invention. FIG. 14 is a schematic cross-sectional view showing an example of a metal-filled microstructure according to an embodiment of the present invention. FIG. 15 is a schematic cross-sectional view showing an example of a structure of an anisotropic conductive material using a metal-filled microstructure according to an embodiment of the present invention. FIG. 16 is a schematic diagram showing a first example of a laminated device using a metal-filled microstructure in an embodiment of the present invention. FIG. 17 is a schematic diagram showing a second example of a laminated device using a metal-filled microstructure in an embodiment of the present invention. FIG. 18 is a schematic diagram showing a third example of a laminated device using a metal-filled microstructure in an embodiment of the present invention. FIG. 19 is a schematic diagram showing a fourth example of a laminated device using a metal-filled microstructure in an embodiment of the present invention. FIG. 20 is a schematic diagram showing a process of a first example of a method for manufacturing a laminated device using a metal-filled microstructure in an embodiment of the present invention. FIG. 21 is a schematic diagram showing a process of the first example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 22 is a schematic diagram showing a process of the first example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 23 is a schematic diagram showing a process of the second example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 24 is a schematic diagram showing a process of the second example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 25 is a schematic diagram showing a process of the second example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 26 is a schematic diagram showing a process of the third example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 27 is a schematic diagram showing a process of the third example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 28 is a schematic diagram showing a fifth example of a laminated device of an embodiment of the present invention. FIG. 29 is a schematic diagram showing a sixth example of a laminated device of an embodiment of the present invention. FIG. 30 is a schematic diagram showing a seventh example of a laminated device of an embodiment of the present invention. FIG. 31 is a schematic diagram showing an eighth example of a laminated device in an embodiment of the present invention. FIG. 32 is a schematic diagram showing a ninth example of a laminated device in an embodiment of the present invention. FIG. 33 is a schematic diagram showing a process of a fourth example of a method for manufacturing a laminated device using a metal-filled microstructure in an embodiment of the present invention. FIG. 34 is a schematic diagram showing a process of a fourth example of a method for manufacturing a laminated device using a metal-filled microstructure in an embodiment of the present invention. FIG. 35 is a schematic diagram showing a process of a fourth example of a method for manufacturing a laminated device using a metal-filled microstructure in an embodiment of the present invention. FIG. 36 is a schematic diagram showing a process of the fourth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 37 is a schematic diagram showing a process of the fourth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 38 is a schematic diagram showing a process of the fourth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 39 is a schematic diagram showing a process of the fourth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 40 is a schematic diagram showing a process of the fourth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 41 is a schematic diagram showing a process of the fourth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 42 is a schematic diagram showing a process of the fourth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 43 is a schematic diagram showing a process of the fourth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 44 is a schematic diagram showing a process of a method for manufacturing a laminated body used in the fourth example of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention. FIG. 45 is a schematic diagram showing a process of a method for manufacturing a laminated body used in the fourth example of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention. FIG. 46 is a schematic diagram showing a process of a method for manufacturing a laminated body used in the fourth example of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention. FIG. 47 is a schematic diagram showing a process of a method for manufacturing a laminated body used in the fourth example of the method for manufacturing a laminated device using a metal-filled microstructure in the embodiment of the present invention. FIG. 48 is a schematic diagram showing a process of a method for manufacturing a laminated body used in the fourth example of the method for manufacturing a laminated device using a metal-filled microstructure in the embodiment of the present invention. FIG. 49 is a schematic diagram showing a process of a fifth example of the method for manufacturing a laminated device using a metal-filled microstructure in the embodiment of the present invention. FIG. 50 is a schematic diagram showing a process of a fifth example of the method for manufacturing a laminated device using a metal-filled microstructure in the embodiment of the present invention. FIG. 51 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 52 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 53 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 54 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 55 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 56 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 57 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 58 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 59 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 60 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 61 is a schematic diagram showing a process of the fifth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 62 is a schematic diagram showing a process of the sixth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 63 is a schematic diagram showing a process of the sixth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 64 is a schematic diagram showing a process of the sixth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 65 is a schematic diagram showing a process of the sixth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 66 is a schematic diagram showing a process of the sixth example of the method for manufacturing a laminated device of a metal-filled microstructure using an embodiment of the present invention. FIG. 67 is a graph showing the first example of the formal bonding condition. FIG. 68 is a graph showing the second example of the formal bonding condition. FIG. 69 is a graph showing the third example of the formal bonding condition. FIG. 70 is a graph showing the fourth example of the formal bonding condition. FIG. 71 is a graph showing the fifth example of the formal bonding condition. FIG. 72 is a graph showing the sixth example of the formal bonding condition. FIG. 73 is a graph showing the seventh example of the formal bonding condition.

Claims (12)

A method for manufacturing a metal-filled microstructure comprises: a process of providing an insulating film having a plurality of pores on the surface of a metal component to obtain a structure having the metal component and the insulating film; and a plating process of plating the structure under a supercritical state or a subcritical state on a surface having at least one side of the insulating film to form a metal layer on the surface of the plurality of pores. The metal is filled in the fine holes, and the metal includes gold, silver, copper, aluminum, magnesium, nickel or zinc. When the plating process starts, a metal layer other than the valve metal exists at the bottom of the fine holes of the structure. The metal layer other than the valve metal is formed in an area of more than 80% of the area of the bottom of the fine holes. The average diameter of the plurality of fine holes is less than 1μm. The method for manufacturing a metal-filled microstructure as described in claim 1, wherein between the process of obtaining the structure and the plating process, there is a process of forming the metal layer other than the valve metal at the bottom of the fine hole, and the plating process is implemented in a state where the metal layer other than the valve metal is formed on an area of more than 80% of the area of the bottom of the fine hole at the start of the plating process. A method for manufacturing a metal-filled microstructure as described in claim 1, wherein the metal component is made of a metal other than the valve metal, and the metal component is exposed at the bottom of the fine hole. A method for manufacturing a metal-filled microstructure as described in any one of claim 1 to claim 3, wherein the insulating film is an oxide film. A method for manufacturing a metal-filled microstructure as described in claim 4, wherein the oxide film is an anodic oxide film of aluminum. A method for manufacturing a metal-filled microstructure as described in any one of claims 1 to 3, wherein the metal layer other than the valve metal is composed of a metal having a higher potential than aluminum. A method for manufacturing a metal-filled microstructure as described in claim 4, wherein the metal layer other than the valve metal is composed of a metal having a higher potential than aluminum. A method for manufacturing a metal-filled microstructure as described in claim 5, wherein the metal layer other than the valve metal is composed of a metal having a higher potential than aluminum. A method for manufacturing a metal-filled microstructure as described in any one of claim 1 to claim 3, wherein the aforementioned metal component is composed of a precious metal or a valve metal. The method for manufacturing a metal-filled microstructure as described in claim 4, wherein the aforementioned metal component is composed of a precious metal or a valve metal. The method for manufacturing a metal-filled microstructure as described in claim 5, wherein the aforementioned metal component is composed of a precious metal or a valve metal. The method for manufacturing a metal-filled microstructure as described in claim 6, wherein the aforementioned metal component is composed of a precious metal or a valve metal.

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