TWI879406B - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing semiconductor device includes forming a first oxide layer on a substrate; doping the first oxide layer; forming a stacked structure on the doped first oxide layer; etching the stacked structure and the doped first oxide layer by a first composition gas and forming openings, in which the first composition gas is alkaline; and filling the openings by a filling layer.

Description

Method for manufacturing semiconductor device

The present disclosure relates to a method for manufacturing a semiconductor device.

Etching process is an indispensable part of semiconductor manufacturing process. Etching process can form the desired etching pattern by performing single or composite etching methods with different characteristics (such as dry etching or wet etching, selective etching or non-selective etching, etc.). With the increasing miniaturization of semiconductor components, the requirements for etching process are also increasing. For example, the production of capacitor structures with higher aspect ratios than in the past. However, according to the etching limit of existing dry etching, it is impossible to form openings or grooves with high aspect ratios.

Therefore, how to come up with a method for manufacturing semiconductor devices that can solve the above problems is one of the problems that the industry is eager to invest research and development resources to solve.

In view of this, one purpose of the present disclosure is to provide a method for manufacturing a semiconductor device that can effectively solve the above-mentioned problem.

The present disclosure relates to a method for manufacturing a semiconductor device, comprising: forming a first oxide layer on a substrate; doping the first oxide layer; forming a stacked structure on the doped first oxide layer; performing a selective etching process, wherein the selective etching process comprises etching the stacked structure and a portion of the doped first oxide layer using a first formula liquid to form an opening, so that the opening has a first hole area away from the substrate, and has a second hole area at the junction of the stacked structure and the first oxide layer, wherein the first hole area is larger than the second hole area; and filling the opening with a filling layer.

In some current embodiments, the step of doping the first oxide layer further comprises: doping the first oxide layer with at least one of boron and phosphorus, wherein the doped first oxide layer further comprises silicon.

In some current implementations, the selective etching process is performed by reacting a first liquid formulation with silicon adjacent to the dopant to form a first compound to etch the doped first oxide layer.

In some current embodiments, the step of forming a stacked structure on the doped first oxide layer further includes: forming a bottom layer on the doped first oxide layer; forming a second oxide layer on the bottom layer; and forming an overlying layer on the second oxide layer.

In some current embodiments, the method of manufacturing a semiconductor device further includes: performing a non-selective etching process before performing a selective etching process, the non-selective etching process including etching the stacked structure using a second gas recipe to form an opening, wherein the opening is expanded after performing the selective etching process.

In some current implementations, the selective etching process and the non-selective etching process are plasma etching processes.

In some current embodiments, the first liquid formulation is alkaline.

In some current implementations, the step of performing the selective etching process is to make the opening have a third hole area adjacent to the substrate, and the second hole area is equal to the third hole area.

In some current implementations, the step of performing a selective etching process is to form an opening exposing a portion of the substrate.

In some current embodiments, the step of filling the opening with a filling layer is to make the filling layer contact a portion of the substrate and be flush with the upper surface of the stacked structure.

In summary, in the manufacturing method of the semiconductor device disclosed in the present invention, an opening with a high aspect ratio can be obtained through a selective etching process performed by doping the first oxide layer and the first formula liquid. Applying it to the existing semiconductor process can eventually manufacture, for example, a capacitor structure with a high aspect ratio. The capacitor structure with a high aspect ratio can increase the contact area between the opening and the capacitor filling material, and further improve the capacitor performance.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat component symbols and/or letters in various examples. This repetition is for simplification and clarity purposes, and does not itself represent the relationship between the various embodiments and/or configurations discussed.

Additionally, for simplicity of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (additional) element or feature as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, "approximately", "about", "approximately" or "substantially" generally means falling within 20%, or within 10%, or within 5% of a given value or range. The numerical values given herein are approximate values, indicating that the terms used, such as "approximately", "about", "approximately" or "substantially" can be inferred when not explicitly stated.

FIG. 1 is a flow chart of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1, the present disclosure provides a method M1 for manufacturing a semiconductor device, comprising: forming a first oxide layer on a substrate (step S110); doping the first oxide layer (step S120); forming a stacked structure on the doped first oxide layer (step S130); etching the stacked structure and the doped first oxide layer using a first liquid formulation to form an opening, wherein the first liquid formulation is alkaline (step S140); and filling the opening with a filling layer (step S150).

FIG. 2A is a schematic diagram of one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2A, in step S110, a first oxide layer 120 is formed on a substrate 110. In some embodiments, the materials of the substrate 110 and the first oxide layer 120 both include silicon, for example, the substrate 110 is SiN and the first oxide layer 120 is SiO ₂ , but the present disclosure is not limited thereto.

FIG. 2B is a schematic diagram of another stage of the method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2B, in step S120, the first oxide layer 120 is doped. In some embodiments, step S120 further includes doping the first oxide layer 120 with at least one of boron (B) and phosphorus (P), wherein the doped first oxide layer 120 further includes silicon. Specifically, when the first oxide layer 120 is _SiO2 , the first oxide layer 120 can be doped with one of boron and phosphorus or both of them at the same time. For example, doping SiO ₂ (the first oxide layer 120 ) with boron and phosphorus simultaneously will make it boro-phospho-silicate glass (BPSG).

FIG. 3A is a schematic diagram of the reaction between the first formula liquid and the second oxide layer according to some embodiments of the present disclosure. FIG. 3B is a schematic diagram of the reaction between the first formula liquid and the first oxide layer according to some embodiments of the present disclosure. Referring to FIG. 2B, FIG. 3A and FIG. 3B, the first oxide layer 120 can change its internal bonding structure by an appropriate amount of doping. For example, when boron is used to dope with _SiO2 , boron will replace the position of Si in _SiO2 and form a bond with O, but boron can only bond with up to three O atoms, leaving one unbonded electron in the Si atom adjacent to boron. Similarly, if phosphorus is used to dope with _SiO2 , phosphorus will replace the position of Si in _SiO2 . Unlike boron, phosphorus will bond with four O atoms and form a double bond with one of the O atoms, so that the Si atom adjacent to phosphorus will also have an unbonded electron. In step S120, changing the bonding structure of the first oxide layer 120 will facilitate the execution of the subsequent etching process (e.g., step S140 in FIG. 1 ), the details of which will be described below.

FIG. 2C is a schematic diagram of another stage of the method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2C, in step S130, a stacked structure 130 is formed on the doped first oxide layer 120. In some embodiments, step S130 further includes: forming a bottom layer on the doped first oxide layer (step S131); forming a second oxide layer on the bottom layer (step S132); and forming an overlying layer on the second oxide layer (step S133). For example, in the illustrated embodiment, the stacked structure 130 includes a bottom layer 132, a second oxide layer 134, and an overlying layer 136, but the present disclosure is not limited thereto. The stacked structure 130 can be formed on the first oxide layer 120 by any multiple layers of the same or different materials in a suitable method. In some embodiments, the material composition of the bottom layer 132 and the upper cover layer 136 is the same as that of the substrate 110. In some embodiments, the materials of the bottom layer 132, the second oxide layer 134 and the upper cover layer 136 all include silicon. In some embodiments, the stacked structure 130 can be an independent component. However, in other embodiments, the stacked structure 130 can form a component or a part of a component together with the substrate 110 and the first oxide layer 120.

FIG. 2D is a schematic diagram of another stage of the method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2E is a schematic diagram of another stage of the method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1, FIG. 2D and FIG. 2E, in step S140, a first liquid formulation is introduced to etch a portion of the stacked structure 130 and the doped first oxide layer 120 to form an opening 140, wherein the first liquid formulation is alkaline. Specifically, in some embodiments, step S140 further includes: performing a first etching process, the first etching process includes etching the stacked structure using a second recipe gas (step S141); and performing a second etching process, the second etching process includes etching the doped first oxide layer using a first recipe liquid, wherein the first recipe liquid is different from the second recipe gas (step S142).

In step S141 and step S142, a first liquid formulation and a second gas formulation are used respectively, wherein the first liquid formulation is an alkaline liquid. In the 2D diagram, step S141 uses the second gas formulation to perform a first etching process, and a plurality of openings 140 are formed in the stacked structure 130 in the first etching process. These openings 140 will penetrate the doped first oxide layer 120 and expose a portion of the substrate 110. In some embodiments, the first etching process is a plasma etching process, but the present disclosure is not limited thereto, and other suitable etching processes may also be used. In some embodiments, the second gas formulation is an acidic gas.

Please refer to FIG. 2D , specifically, in the first etching process, the opening 140 will have a narrower opening size as it goes deeper into the first oxide layer 120. In some embodiments, step S140 is to make the opening 140 have a first hole area A1 far from the substrate 110, and the opening 140 has a second hole area A2 at the interface between the stacked structure 130 and the first oxide layer 120, wherein the first hole area A1 is larger than the second hole area A2. Specifically, after the first etching process is completed, the first hole area A1 of the opening 140 is located on the upper surface of the stacked structure (i.e., the upper surface of the upper cover layer 136), and the second hole area A2 of the opening 140 is located at the interface between the stacked structure 130 and the first oxide layer 120. The opening 140 formed after the first etching process (as shown in FIG. 2D ) will present a morphology that is wide at the top and narrow at the bottom. The reason is that the ionized gas ions will not easily reach the deep part of the opening for etching, and the produced opening will have a lower aspect ratio, so the first hole area A1 will be larger than the second hole area A2. However, since it is a non-selective etching, the first etching process may etch through different types of materials (eg, the bottom layer 132, the second oxide layer 134, and the upper cover layer 136 in the stacked structure 130).

Referring to FIG. 2E , step S142 uses the first liquid formula to perform a second etching process, and the opening 140 is formed deep into the doped first oxide layer 120 by the second etching process. Further, in some embodiments, step S140 (including step S141 and step S142) is to make the opening 140 expose a portion of the substrate 110. The opening 140 is extended through the doped first oxide layer 120 by step S142, and the opening 140 in the doped first oxide layer 120 is enlarged at the same time, and a larger area of the substrate 110 located below the doped first oxide layer 120 is exposed. In some embodiments, the second etching process is a wet etching process, but the present disclosure is not limited thereto, and other suitable etching processes may also be used.

Please refer to FIG. 2E, FIG. 3A and FIG. 3B. In step S142, the first liquid formula can be any gas having a hydroxyl group (OH ^- ). Because the first liquid formula has a hydroxyl group, it is easy to etch the doped first oxide layer 120. In other words, in some embodiments, the second etching process can be a selective etching process. For example, the undoped first oxide layer 120 is SiO ₂ , and its structure is shown in FIG. 3A. When the hydroxyl groups in the first liquid formula approach the undoped first oxide layer 120, because Si in the _SiO2 structure does not have unbonded electrons to react with the hydroxyl groups, the first liquid formula will not be able to etch the undoped first oxide layer 120. On the other hand, the first oxide layer 120 doped with boron and phosphorus is BPSG, and its structure is shown in FIG. 3B. When the hydroxyl groups in the first liquid formula approach the doped first oxide layer 120, because Si atoms adjacent to boron or phosphorus have unbonded electrons, these Si atoms tend to bond with the hydroxyl groups.

Furthermore, in some embodiments, step S140 is to make the first liquid formula react with the adjacent doped silicon to form a first compound to etch the doped first oxide layer 120. Referring to FIG. 3B , the reaction formula of Si and hydroxyl bonding is described as follows: The free electrons obtained after the reaction will react with water molecules in the air to produce hydrogen: . Combining the first two reaction equations, we finally get the overall reaction equation: Si reacts with the hydroxyl group of the first liquid formula to obtain Si(OH) ₄ (ie, the first compound), so that the doped first oxide layer 120 is etched. However, the above discussion is only an embodiment of the present disclosure and is not intended to limit the content of the present disclosure.

Please refer to FIG. 2E , in some embodiments, step S140 is to make the opening 140 have a third hole area A3 adjacent to the substrate 110, and the second hole area A2 is equal to the third hole area A3. Specifically, the third hole area A3 of the opening 140 is located at the interface between the first oxide layer 120 and the substrate 110. Since the second etching process is a selective etching, it has a higher aspect ratio than the first etching process, and the opening 140 can be extended into the first oxide layer 120 according to the size of the second hole area A2, so that the second hole area A2 of the opening 140 is equal to the third hole area A3.

FIG. 2F is a schematic diagram of another stage of the method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 2F , in step S150, the opening 140 is filled with a filling layer 150. In some embodiments, the material of the filling layer 150 includes a metal. In some embodiments, step S150 is used so that the filling layer 150 contacts a portion of the substrate 110 and is flush with the upper surface of the stacked structure 130. Specifically, in some embodiments, the filling layer 150 will completely fill the opening 140 to have a maximum contact area with the inner surface of the opening 140. Compared to the opening formed by non-selective etching, the opening 140 etched in step S140 has a higher aspect ratio, so the contact area between the filling layer 150 and the inner surface of the opening 140 is increased. When applied to a semiconductor capacitor structure, when the contact area between the opening 140 and the filling layer 150 is increased, the performance of the capacitor can be effectively optimized. However, the application scope of the present disclosure is not limited to this, and any etching process in the field of semiconductor manufacturing can use the method M1 provided by the present disclosure.

From the above detailed description of the specific implementation of the present disclosure, it can be clearly seen that in the manufacturing method of the semiconductor element disclosed in the present disclosure, an opening with a high aspect ratio can be obtained through the selective etching process performed by doping the first oxide layer and the first formula liquid. Applying it in the existing semiconductor process can manufacture a capacitor structure with a high aspect ratio. The capacitor structure with a high aspect ratio can increase the contact area between the opening and the capacitor filling material, and further improve the capacitor performance.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and replacements herein without departing from the spirit and scope of the present disclosure.

110: substrate 120: first oxide layer 130: stacking structure 132: bottom layer 134: second oxide layer 136: overlying layer 140: opening 150: filling layer A1: first hole area A2: second hole area A3: third hole area S110, S120, S130, S131, S132, S133, S140, S141, S142, S150: steps M1: method

The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2A is a schematic diagram of one stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2B is a schematic diagram of another stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2C is a schematic diagram of another stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2D is a schematic diagram of another stage of the method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2E is a schematic diagram of another stage of the method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2F is a schematic diagram of another stage of the method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 3A is a schematic diagram of the reaction between the first formula liquid and the second oxide layer according to some embodiments of the present disclosure. FIG. 3B is a schematic diagram of the reaction between the first formula liquid and the first oxide layer according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

M1: Methods

S110,S120,S130,S140,S150: Steps

Claims (10)

A method for manufacturing a semiconductor device comprises: forming a first oxide layer on a substrate; doping the first oxide layer; forming a stacked structure on the doped first oxide layer; performing a selective etching process, wherein the selective etching process comprises etching the stacked structure and a portion of the doped first oxide layer using a first formula liquid to form an opening, so that the opening has a first hole area away from the substrate, and the opening has a second hole area at the junction of the stacked structure and the first oxide layer, wherein the first hole area is larger than the second hole area, wherein the first formula liquid is alkaline; and filling the opening with a filling layer. The method for manufacturing a semiconductor device as described in claim 1, wherein the step of doping the first oxide layer further comprises: doping the first oxide layer with at least one of boron and phosphorus, wherein the doped first oxide layer further comprises silicon. The method for manufacturing a semiconductor device as described in claim 2, wherein the step of performing the selective etching process is to allow the first formula liquid to react with silicon adjacent to the dopant to form a first compound to etch the doped first oxide layer. The method for manufacturing a semiconductor device as described in claim 1, wherein the step of forming the stacked structure on the doped first oxide layer further comprises: forming a bottom layer on the doped first oxide layer; forming a second oxide layer on the bottom layer; and forming an overlying layer on the second oxide layer. The method for manufacturing a semiconductor device as described in claim 4 further comprises: performing a non-selective etching process before the step of performing the selective etching process, the non-selective etching process comprising etching the stacked structure using a second formula gas to form the opening, wherein the opening is enlarged after the step of performing the selective etching process. A method for manufacturing a semiconductor device as described in claim 5, wherein the selective etching process and the non-selective etching process are plasma etching processes. A method for manufacturing a semiconductor device as described in claim 5, wherein the second formula gas is an acidic gas. A method for manufacturing a semiconductor device as described in claim 1, wherein the step of performing the selective etching process is such that the opening has a third hole area adjacent to the substrate, and the second hole area is equal to the third hole area. A method for manufacturing a semiconductor device as described in claim 1, wherein the step of performing the selective etching process is such that the opening exposes a portion of the substrate. A method for manufacturing a semiconductor device as described in claim 9, wherein the step of filling the opening with the filling layer is such that the filling layer contacts a portion of the substrate and is flush with an upper surface of the stacked structure.

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