TWI879491B - Semiconductor device - Google Patents

Abstract

Embodiments provide a semiconductor device. The semiconductor device includes a substrate, a gate structure, a first interlayer dielectric layer, a drain structure, a second interlayer dielectric layer and a first field plate. The gate structure is disposed on the substrate. The first interlayer dielectric layer is disposed on the substrate and partially covers the substrate and the gate structure. The drain structure is disposed on the substrate and located on a first side of the gate structure. A drain electrode layer of the drain structure extends from the substrate not covered by the first interlayer dielectric layer to cover a portion of a first top surface of the first interlayer dielectric layer. The second interlayer dielectric layer is disposed on the first interlayer dielectric layer and covers the drain electrode layer. The first field plate is disposed on the second interlayer dielectric layer and partially overlaps the drain electrode layer on the first top surface of the first interlayer dielectric layer. The first field plate is electrically floating.

Description

Semiconductor Devices

The present invention relates to semiconductor devices, and more particularly to high electron mobility transistor devices.

High electron mobility transistor (HEMT), also known as heterostructure field effect transistor (HFET) or modulation-doped field effect transistor (MODFET), is a field effect transistor composed of semiconductor materials with different energy gaps. A two-dimensional electron gas layer is generated at the interface between adjacent different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, high electron mobility transistor devices can have advantages such as high breakdown voltage, high electron mobility, low on-resistance and low input capacitance, and are therefore suitable for use in high-power components.

However, although these high electron mobility transistor devices generally meet the requirements, they are still not satisfactory in every aspect. Therefore, there is a need to further improve high electron mobility transistor devices and their manufacturing methods to enhance performance and reliability.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a substrate, a gate structure, a first interlayer dielectric layer, a drain structure, a second interlayer dielectric layer, and a first field plate. The gate structure is disposed on the substrate. The first interlayer dielectric layer is disposed on the substrate and partially covers the substrate and the gate structure. The drain structure is disposed on the substrate and is located on a first side of the gate structure. The drain structure includes a drain electrode layer. The drain electrode layer is disposed on the substrate and extends from the substrate not covered by the first interlayer dielectric layer to cover a portion of the first top surface of the first interlayer dielectric layer. The second inter-layer dielectric layer is disposed on the first inter-layer dielectric layer and covers the drain electrode layer. The first field plate is disposed on the second inter-layer dielectric layer and partially overlaps with the drain electrode layer on the first top surface of the first inter-layer dielectric layer. The first field plate is electrically floating.

The present disclosure is more fully described below with reference to the drawings of embodiments of the present invention. However, the present disclosure may be implemented in a variety of different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the various drawings represent the same or similar elements. It is understood that additional steps may be provided before, during, or after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

Various different embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. When a first component is formed on a second component, the description may include embodiments in which the first and second components are directly in contact with each other, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact with each other. In addition, the embodiments of the present invention may use repeated component symbols in many examples. Such repetition is only for the purpose of simplification and clarity, and does not represent a specific relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below", "beneath", "below", "above", "upper" and other similar terms may be used in the following description to simplify the description of the relationship between one element or component and other elements or components as shown in the figures. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

FIG. 1 is a cross-sectional schematic diagram of a semiconductor device 500A of some embodiments of the present invention. In some embodiments, the semiconductor device 500A includes a high electron mobility transistor (HEMT), such as an enhanced high electron mobility transistor (E-mode GaN HEMT) based on gallium nitride (GaN). As shown in FIG. 1, the semiconductor device 500A includes a substrate 200, a gate structure 220, an interlayer dielectric layer 210, an interlayer dielectric layer 216, a source structure 230S, a drain structure 230D, and a field plate 218F1.

In some embodiments, the substrate 200 may include: an elemental semiconductor including silicon or germanium; a compound semiconductor including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and/or indium sulphide (InSb); an alloy semiconductor including silicon germanium alloy, phosphorus arsenic gallium alloy, arsenic aluminum indium alloy, arsenic aluminum gallium alloy, arsenic indium gallium alloy, phosphorus indium gallium alloy and/or phosphorus arsenic indium gallium alloy, or a combination of the above materials.

In some embodiments, the substrate 200 may be a semiconductor on insulator substrate, such as silicon on insulator (SOI) or silicon germanium on insulator (SGOI). In other embodiments, the substrate 200 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al ₂ O ₃ ) substrate (or sapphire substrate), a glass substrate, or other similar substrates. In some embodiments, the substrate 200 may include a ceramic substrate and a pair of barrier layers disposed on the upper and lower surfaces of the ceramic substrate, respectively, wherein the ceramic substrate may include a ceramic material, and the ceramic material includes a metal inorganic material. For example, the ceramic substrate may include: silicon carbide, aluminum nitride, sapphire substrate, or other suitable materials. The above-mentioned sapphire substrate may be aluminum oxide. In some embodiments, the barrier layer located on the upper and lower surfaces of the ceramic substrate may include a single or multiple insulating material layers and/or other suitable material layers, such as semiconductor layers. The insulating material layer may be an oxide, a nitride, a nitride oxide, or other suitable insulating materials. The semiconductor layer may be polycrystalline silicon. The barrier layer can prevent the diffusion of the ceramic substrate and can also prevent the ceramic substrate from interacting with other film layers or process equipment. In some embodiments, the barrier layer can also encapsulate the ceramic substrate. At this time, the barrier layer not only covers the upper and lower surfaces of the ceramic substrate, but also covers the two side surfaces of the ceramic substrate.

In some embodiments, the semiconductor device 500A further includes a buffer layer 202. As shown in FIG. 1 , the buffer layer 202 is located on the top surface 200T of the substrate 200. Since the lattice or thermal expansion coefficient of the substrate 200 may be different from that of the upper component (e.g., the channel layer 204), strain may be generated at or near the interface between the substrate 200 and the upper component, which may easily form defects such as cracks or warps. Therefore, the buffer layer 202 located on the substrate 200 can reduce the strain of the component (e.g., the channel layer 204) formed above the buffer layer 202, thereby preventing defects from being formed in the upper component. In some embodiments, the material of the buffer layer 202 may include a III-V compound semiconductor material, such as a III-nitride. For example, the material of the buffer layer 202 may include aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride ( _{AlxGa1 -} xN, where 0＜x＜1), aluminum indium nitride (AlInN), a combination thereof, or other similar materials. In some embodiments, the buffer layer 202 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination thereof. In some embodiments, the buffer layer 202 may be a multi-layer structure (not shown). For example, the buffer layer 202 may include a superlattice buffer layer and/or a gradient buffer layer, wherein the superlattice buffer layer is disposed on the substrate 200, and the gradient buffer layer is disposed on the superlattice buffer layer, which can effectively prevent the dislocation in the substrate 200 from entering the upper components, and further improve the crystallization quality of other films and/or layers above.

In some embodiments, the semiconductor device 500A may optionally include a seed layer (not shown) located between the substrate 200 and the buffer layer 202. The seed layer can alleviate the lattice difference between the substrate 200 and the film and/or layer grown thereon to improve the crystallization quality. In some embodiments, the material of the seed layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), other suitable materials, or a combination thereof. In some embodiments, the seed layer having a single-layer or multi-layer structure may be formed by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable processes, or a combination thereof.

In some embodiments, the semiconductor device 500A further includes a channel layer 204. As shown in FIG. 1 , the channel layer 204 is located on the buffer layer 202. In some embodiments, the material of the channel layer 204 includes a binary III-V compound semiconductor material, such as a III-nitride. For example, the material of the channel layer 204 may include gallium nitride (GaN). In some embodiments, the channel layer 204 may be doped with n-type doping or p-type doping. In some embodiments, the channel layer 204 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), other suitable processes, or combinations thereof.

In some embodiments, the semiconductor device 500A further includes a barrier layer 206. As shown in FIG. 1 , the barrier layer 206 is located on the channel layer 204. The material of the barrier layer 206 may include a ternary III-V compound semiconductor, such as a III-nitride. For example, the material of the barrier layer 206 may include aluminum gallium nitride ( _{AlyGa1 -yN} , where 0<y<1), aluminum indium nitride (AlInN), or a combination thereof. In other embodiments, the barrier layer 206 may also include: gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or combinations thereof. In some embodiments, the barrier layer 206 may be doped with n-type doping or p-type doping. In some embodiments, the barrier layer 206 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), other suitable processes, or combinations thereof.

According to some embodiments of the present invention, the channel layer 204 and the barrier layer 206 include different materials, and the interface between the two is a heterojunction structure. Due to the lattice mismatch between the channel layer 204 and the barrier layer 206, stress may be generated to cause a piezoelectric polarization effect, and the ionicity of the bond between group III metals (such as aluminum (Al), gallium (Ga), or indium (In)) and nitrogen is stronger, resulting in spontaneous polarization. Due to the energy gap difference between the heterogeneous materials of the channel layer 204 and the barrier layer 206 and the aforementioned piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas (2DEG) (not shown) is formed on the heterogeneous interface between the channel layer 204 and the barrier layer 206. In some embodiments, the two-dimensional electron gas is used as a conductive carrier of the semiconductor device 500A.

The gate structure 220 is disposed on the barrier layer 206 and covers a portion of the barrier layer 206. In some embodiments, the gate structure 220 includes a gate layer 208 and a gate electrode layer 218G.

The gate layer 208 is located on a portion of the barrier layer 206 and contacts the barrier layer 206. As shown in FIG. 1 , the gate layer 208 may have a rectangular cross section as shown in FIG. 1 . In addition, the cross section of the gate layer 208 may also be other shapes, such as a trapezoidal cross section. In some embodiments, the material of the gate layer 208 may include n-type or p-type doped III-V semiconductors, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), or other III-V semiconductors. In other embodiments, the gate layer 208 includes a p-type doped II-VI semiconductor, such as cadmium sulfide (CdS), cadmium telluride (CdTe), zinc sulfide (ZnS), or other II-VI semiconductors. In some embodiments, the gate layer 208 can be formed by metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination thereof, or other suitable methods and subsequent patterning processes. In this embodiment, the gate layer 208 may be doped. For example, the doping includes magnesium (Mg), zinc (Zn), calcium (Ca), benzene (Be), strontium (Sr), barium (Ba), radium (Ra), carbon (C), silver (Ag), gold (Au), lithium (Li) or sodium (Na), so that the conductivity type of the gate layer 208 is p-type.

The gate electrode layer 218G is located on the gate layer 208. The gate electrode layer 218G contacts and partially covers the top surface 208T of the gate layer 208. In some embodiments, the material of the gate electrode layer 218G may include metal, metal nitride, metal oxide, metal alloy, other suitable conductive materials, or a single layer or multi-layer structure formed by a combination of the above, or a combination of the above. For example, the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, alloys thereof, or a combination thereof. The metal alloy may include titanium tungsten (TiW). The metal nitride may include molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum nitride carbide (TaCN), titanium aluminum nitride (TiAlN), or other similar materials. In other embodiments, the conductive material of the gate electrode layer 218G may include nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), titanium aluminum (TiAl), or other similar materials. In this embodiment, the gate electrode layer 218G is titanium nitride (TiN).

In some embodiments, the gate electrode layer 218G may be formed by a deposition process and a subsequent patterning process. For example, the deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (eg, sputtering or evaporation).

As shown in FIG. 1 , the semiconductor device 500A further includes an interlayer dielectric layer 210 disposed on the barrier layer 206. Furthermore, the interlayer dielectric layer 210 partially covers the gate structure 220. As shown in FIG. 1 , the interlayer dielectric layer 210 contacts the opposite side surface (not shown) and a portion of the top surface 208T of the gate layer 208, a portion of the side surface of the gate electrode layer 218G, and the barrier layer 206 not covered by the gate structure 220.

In some embodiments, the interlayer dielectric layer 210 may be a single-layer structure or a multi-layer structure. In the present embodiment, the interlayer dielectric layer 210 may be a single-layer structure or a multi-layer structure formed of the same material.

In some embodiments, the interlayer dielectric layer 210 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), low-k dielectric materials, and/or other suitable dielectric materials, or combinations thereof. The aforementioned low-k dielectric material may include (but is not limited to): fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), polyimide, or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 210 may be formed by a deposition process. For example, the deposition process may include spin-on coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), other suitable processes, or a combination thereof.

As shown in FIG. 1 , the source structure 230S and the drain structure 230D are disposed on the substrate 200. The source structure 230S and the drain structure 230D are respectively located at the first side 220S1 and the second side 220S2 of the gate structure 220 along a direction 100 (also considered as a lateral direction) substantially parallel to the top surface 200T of the substrate 200. In addition, the source structure 230S and the drain structure 230D are respectively adjacent to the side surface 210S1 and the side surface 210S2 of the interlayer dielectric layer 210 that are opposite to each other along the direction 100. As shown in FIG. 1 , the source structure 230S and the drain structure 230D located on both sides of the gate layer 208 are separated from the gate layer 208 by the interlayer dielectric layer 210 along the direction 100. In addition, the interlayer dielectric layer 210 extends between the source structure 230S and the drain structure 230D along the direction 100. The source structure 230S and the drain structure 230D extend from above the interlayer dielectric layer 210 along the direction 110 (also considered as the vertical direction) substantially perpendicular to the top surface 200T of the substrate 200 into a portion of the channel layer 204 and contact the channel layer 204.

In some embodiments, the drain structure 230D may be a composite structure (multi-layer structure), which may include a drain electrode layer 214D, a drain contact member 224D, and a drain metal layer 228D in order from bottom to top. The drain electrode layer 214D is disposed on the substrate 200 and the barrier layer 206. The drain electrode layer 214D extends toward the gate structure 220 along the direction 100, and extends from the substrate 200 and the barrier layer 206 not covered by the interlayer dielectric layer 210 along the direction 100 to cover a portion of the top surface 210T of the interlayer dielectric layer 210. The drain contact feature 224D is located on the drain electrode layer 214D and extends along the direction 110. The drain metal layer 228D is located on the drain contact feature 224D and extends along the direction 100. In some embodiments, the drain metal layer 228D completely covers the drain electrode layer 214D.

In some embodiments, the drain electrode layer 214D is conformally formed on the interlayer dielectric layer 210 and the barrier layer 206. In the cross-sectional view shown in FIG. 1 , the drain electrode layer 214D is stepped. In this embodiment, the step number of the stepped drain electrode layer 214D is 2. Therefore, the drain electrode layer 214D has two upper surfaces 214D-1T and 214D-2T. As shown in FIG. 1 , the upper surface 214D-1T of the drain electrode layer 214D is located directly above the top surface 200T of the substrate 200 that is not covered by the interlayer dielectric layer 210. The upper surface 214D-2T of the drain electrode layer 214D is located directly above the top surface 210T of the interlayer dielectric layer 210. In some embodiments, the upper surfaces 214D-1T and 214D-2T are not coplanar. For example, in the direction 110, the upper surface 214D-1T is below the upper surface 214D-2T (i.e., the upper surface 214D-1T is closer to the top surface 200T of the substrate 200 than the upper surface 214D-2T).

In some embodiments, the source structure 230S may be a composite structure (multi-layer structure), which may include a source electrode layer 214S, a source contact component 224S, and a source metal layer 228S in order from bottom to top. The source electrode layer 214S is disposed on the substrate 200 and the barrier layer 206. The source electrode layer 214S extends toward the gate structure 220 along the direction 100, and extends from the substrate 200 and the barrier layer 206 not covered by the interlayer dielectric layer 210 along the direction 100 to cover another portion of the top surface 210T of the interlayer dielectric layer 210. Therefore, in the cross-sectional view shown in FIG. 1 , the source electrode layer 214S is stepped. The drain electrode layer 214D and the source electrode layer 214S cover different portions of the top surface 210T of the interlayer dielectric layer 210. The source contact component 224S is located on the source electrode layer 214S and extends along the direction 110. The source metal layer 228S is located on the source contact component 224S and extends along the direction 100. In some embodiments, the source metal layer 228S completely covers the source electrode layer 214S.

In some embodiments, the source electrode layer 214S is conformally formed on the interlayer dielectric layer 210 and the barrier layer 206. In the cross-sectional view shown in FIG1 , the source electrode layer 214S is stepped. For example, the stepped source electrode layer 214S has a step number of 2 and may have two upper surfaces.

In some embodiments, the drain electrode layer 214D and the source electrode layer 214S are formed simultaneously, the drain contact feature 224D and the source contact feature 224S are formed simultaneously, and the drain metal layer 228D and the source metal layer 228S are formed simultaneously.

The interlayer dielectric layer 216 is disposed on the interlayer dielectric layer 210 and extends from the source structure 230S to the drain structure 230D. As shown in FIG. 1 , the interlayer dielectric layer 216 covers the drain electrode layer 214D and the source electrode layer 214S, and is adjacent to the drain contact component 224D and the source contact component 224S. In other words, the drain contact component 224D and the source contact component 224S can pass through the interlayer dielectric layer 216 along the direction 110.

In some embodiments, the interlayer dielectric layers 210 and 216 may include the same or similar materials and processes. For example, the interlayer dielectric layers 210 and 216 are both silicon dioxide and have the same dielectric constant (k=3.9).

The semiconductor device 500A may include a plurality of field plates to make the surface electric field distribution of the semiconductor device 500A more uniform. The field plate may include a field plate 218F1 disposed on the drain side (close to the drain structure 230D) of the semiconductor device 500A and overlapping with the drain electrode layer 214D. As shown in FIG. 1 , the field plate 218F1 is disposed on the interlayer dielectric layer 216. The field plate 218F1 partially overlaps with the drain electrode layer 214D on the top surface 210T of the interlayer dielectric layer 210 and extends along the direction 100 toward the drain contact component 224D. Specifically, in the direction 110, the field plate 218F1 overlaps a portion of the drain electrode layer 214D on the top surface 210T of the interlayer dielectric layer 210. Furthermore, the field plate 218F1 does not overlap a portion of the drain electrode layer 214D located on the barrier layer 206 not covered by the interlayer dielectric layer 210. Therefore, the field plate 218F1 is closer to the gate structure 220 than the drain electrode layer 214D. As shown in FIG. 1 , the field plate 218F1 extends from the top surface 210T of the interlayer dielectric layer 210 not covered by the drain electrode layer 214D along the direction 100 to cover the first portion 214D-2TA of the upper surface 214D-2T of the drain electrode layer 214D, and exposes the second portion 214D-2TB of the upper surface 214D-2T from the field plate 218F1. The first portion 214D-2TA and the second portion 214D-2TB of the upper surface 214D-2T of the drain electrode layer 214D are adjacent to each other and are different portions of the upper surface 214D-2T of the drain electrode layer 214D.

In the direction 100, the upper surface 214D-2T of the drain electrode layer 214D has a length L1, and the first portion 214D-2TA of the upper surface 214D-2T has a length L2. In some embodiments, the ratio of the length L1 to the length L2 is greater than or equal to 2. If the ratio of the length L1 to the length L2 is less than 2, the overlapped portion of the field plate 218F1 and the drain electrode layer 214D may be too large to affect the uniformity of the surface electric field.

In some embodiments, the field plate 218F1 is conformally formed on the interlayer dielectric layer 210 and the drain electrode layer 214D. In the cross-sectional view shown in FIG. 1 , the drain electrode layer 214D is stepped. In this embodiment, the step number of the stepped drain electrode layer 214D is 2. Therefore, the field plate 218F1 may have two upper surfaces 218F1-1T and 218F1-2T and side surfaces 218F1-S1 and 218F1-S2 respectively connected to the upper surfaces 218F1-1T and 218F1-2T and opposite to each other. As shown in FIG. 1 , the upper surface 218F1-1T of the field plate 218F1 is located directly above the top surface 210T of the interlayer dielectric layer 210 that is not covered by the drain electrode layer 214D. The upper surface 218F1-2T of the field plate 218F1 is located directly above the first portion 214D-2TA of the upper surface 214D-2T of the drain electrode layer 214D. In some embodiments, the upper surface 218F1-1T of the field plate 218F1 is not coplanar with the upper surface 218F1-2T. For example, in the direction 110. The upper surface 218F1-1T is below the upper surface 218F1-2T (ie, the upper surface 218F1-1T is closer to the top surface 200T of the substrate 200 than the upper surface 218F1-2T).

As shown in FIG. 1 , the side surface 218F1-S1 of the field plate 218F1 close to the gate structure 220 is not located directly above the drain electrode layer 214D, and the side surface 218F1-S2 of the field plate 218F1 close to the drain structure 230D is located directly above the drain electrode layer 214D. Therefore, the side surface 218F1-S1 of the field plate 218F1 close to the gate structure 220 is closer to the gate structure 220 than the side surface 214D-S of the drain electrode layer 214D close to the gate structure 220.

In some embodiments, the field plate 218F1 may include polysilicon, metal (e.g., tungsten, titanium, aluminum, copper, iron, molybdenum, nickel, platinum, the like, or a combination thereof), metal alloy (e.g., nickel iron alloy (NiFe), benzene copper alloy (BeCu)), metal nitride (e.g., tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, the like, or a combination thereof), metal silicide (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, geron silicide, the like, or a combination thereof), metal oxide (ruthenium oxide, indium tin oxide, the like, or a combination thereof), other suitable conductive materials, or a combination thereof. In some embodiments, the field plate 218F1 may be formed by a deposition process and a subsequent patterning process. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam deposition, plasma enhanced chemical vapor deposition, other suitable processes, or a combination thereof.

As shown in FIG. 1 , the semiconductor device 500A further includes a dielectric pattern 212. The dielectric pattern 212 is disposed on a portion of the interlayer dielectric layer 210 between the gate structure 220 and the drain structure 230D. Furthermore, the dielectric pattern 212 covers a portion of the top surface 210T of the interlayer dielectric layer 210. The dielectric pattern 212 has a top surface 212T and side surfaces 212S1 and 212S2 connected to the top surface 212T and opposite to each other. The side surfaces 212S1 and 212S2 of the dielectric pattern 212 are both located on the top surface 210T of the interlayer dielectric layer 210. In a direction 110 substantially perpendicular to the top surface 200T of the substrate 200 (also referred to as a vertical direction), the dielectric pattern 212 partially overlaps the interlayer dielectric layer 210. As shown in FIG. 1 , in a direction 100 substantially parallel to the top surface 200T of the substrate 200 (also referred to as a lateral direction), a first distance D1 is between a side surface 212S1 of the dielectric pattern 212 and the gate layer 208 of the gate structure 220. In addition, a second distance D2 is between a side surface 212S2 of the dielectric pattern 212 and the drain contact part 224D of the drain structure 230D. In some embodiments, the first distance D1 is less than the second distance D2. In other words, in the direction 100, the gate structure 220 is closer to the dielectric pattern 212 than the drain contact feature 224D of the drain structure 230D.

In some embodiments, the dielectric pattern 212 may include a dielectric material, such as silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), and/or other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric pattern 212 may include a low-k dielectric material, a high-k dielectric material (a dielectric material having a k higher than that of silicon oxide (SiO ₂ ) (k=3.9)), and/or other suitable dielectric materials, or a combination thereof. The low-k dielectric material may include (but is not limited to): fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), polyimide, or a combination thereof. The high-k dielectric material may include (but is not limited to): silicon nitride, tantalum, tantalum silicon oxide, tantalum silicon oxynitride, tantalum uranium oxide, tantalum titanium oxide, tantalum zirconium oxide, zirconium oxide, aluminum oxide, tantalum oxide-aluminum oxide alloy, and/or combinations thereof or similar materials. In some embodiments, the dielectric pattern 212 may be a single-layer structure or a multi-layer structure formed by the above dielectric materials.

In some embodiments, the interlayer dielectric layers 210, 216 and the dielectric pattern 212 include different materials. In some embodiments, the dielectric constant of the interlayer dielectric layers 210, 216 is different from the dielectric constant of the dielectric pattern 212. The dielectric constant of the interlayer dielectric layers 210, 216 may be smaller than the dielectric constant of the dielectric pattern 212. For example, the interlayer dielectric layers 210, 216 are silicon dioxide (k=3.9), and the dielectric pattern 212 is silicon nitride (k=7.5).

In some embodiments, the dielectric pattern 212 may be formed by a deposition process and a subsequent patterning process. For example, the deposition process may include spin-on coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), other suitable processes, or a combination thereof.

The field plate of the semiconductor device 500A further includes a field plate 214F and a field plate 218F2 disposed between the gate structure 220 and the drain structure 230D of the semiconductor device 500A and overlapping the dielectric pattern 212 .

The field plate 214F is disposed on the substrate 200. Furthermore, the field plate 214F covers the interlayer dielectric layer 210 and the dielectric pattern 212 between the gate structure 220 and the dielectric pattern 212. As shown in FIG. 1 , the field plate 214F extends from the top surface 210T of the interlayer dielectric layer 210 along the direction 100 to cover and contact all the side surfaces 212S1 and the first portion 212T1 of the top surface 212T of the dielectric pattern 212, and exposes the second portion 212T2 of the top surface 212T from the field plate 214F. In other words, the field plate 214F does not extend to cover the side surface 212S2 of the dielectric pattern 212 close to the drain structure 230D, which can reduce the risk of short circuit between the field plate 214F and the drain structure 230D. In addition, the first portion 212T1 and the second portion 212T2 of the top surface 212T of the dielectric pattern 212 are adjacent to each other and are different portions of the top surface 212T of the dielectric pattern 212. For example, the first portion 212T1 of the top surface 212T of the dielectric pattern 212 is closer to the gate structure 220, while the second portion 212T2 is closer to the drain structure 230D.

In some embodiments, the field plate 214F is conformally formed on the interlayer dielectric layer 210 and the dielectric pattern 212. Therefore, the field plate 214F is stepped in the cross-sectional view shown in FIG. 1. In this embodiment, the step number of the stepped field plate 214F is 2. Therefore, the field plate 214F has two upper surfaces 214F-1T and 214F-2T in the direction 110 and side surfaces 214F-S1 and 214F-S2 connected to the upper surfaces 214F-1T and 214F-2T and opposite to each other. The upper surface 214F-1T of the field plate 214F is located directly above a portion of the interlayer dielectric layer 210 between the gate structure 220 and the dielectric pattern 212. The upper surface 214F-2T of the field plate 214F is located directly above the first portion 212T1 of the top surface 212T of the dielectric pattern 212. In some embodiments, the upper surfaces 214F-1T and 214F-2T are not coplanar. For example, in the direction 110, the upper surface 214F-1T is below the upper surface 214F-2T (i.e., the upper surface 214F-1T is closer to the top surface 200T of the substrate 200 than the upper surface 214F-2T).

As shown in FIG. 1 , a side surface 214F-S1 of the field plate 214F close to the gate structure 220 is located directly above a portion of the interlayer dielectric layer 210 between the gate structure 220 and the dielectric pattern 212, and a side surface 214F-S2 of the field plate 214F close to the drain structure 230D is located directly above the dielectric pattern 212. In some embodiments, the side surface 214F-S2 of the field plate 214F and the side surface 212S2 of the dielectric pattern 212 close to the drain structure 230D are not aligned with each other.

In some embodiments, the field plate 214F and the field plate 218F1 may include the same or similar materials and processes. In some embodiments, the field plate 214F may be formed simultaneously with the source electrode layer 214S of the source structure 230S and the drain electrode layer 214D of the drain structure 230D.

As shown in FIG. 1 , the interlayer dielectric layer 216 completely covers the dielectric pattern 212 and the field plate 214F, so that the dielectric pattern 212 and the field plate 214F are sandwiched between the interlayer dielectric layers 210 and 216 along the direction 110. In detail, the interlayer dielectric layer 216 covers and contacts the interlayer dielectric layer 210 exposed from the dielectric pattern 212 and the field plate 214F. The interlayer dielectric layer 216 covers and contacts the upper surface 214F-1T, 214F-2T and the side surface 214F-S1, 214F-S2 of the field plate 214F. Furthermore, the interlayer dielectric layer 216 covers and contacts the second portion 212T2 and the side surface 212S2 of the top surface 212T of the dielectric pattern 212. As shown in FIG. 1 , the field plate 214F and the interlayer dielectric layer 216 contact the opposite side surfaces 212S1 and 212S2 of the dielectric pattern 212, respectively. The drain structure 230D and the gate electrode layer 218G located on both sides of the field plate 214F are separated from each other by the interlayer dielectric layer 216 and the field plate 214F along the direction 100, respectively.

The field plate 218F2 is disposed above the field plate 214F and the dielectric pattern 212 and extends toward the drain structure 230D. The field plate 218F2 covers a portion of the interlayer dielectric layer 216 directly above the top surface 212T of the dielectric pattern 212 and is separated from the field plate 214F by the interlayer dielectric layer 216. In some embodiments, the field plate 214F partially overlaps with the field plate 218F2. In detail, in the direction 110, the field plate 218F2 overlaps with a portion of the field plate 214F on the first portion 212T1 of the top surface 212T of the dielectric pattern 212. Furthermore, the field plate 218F2 does not overlap with a portion of the field plate 214F on the interlayer dielectric layer 210 between the gate structure 220 and the dielectric pattern 212. Therefore, the field plate 218F2 is closer to the drain structure 230D than the field plate 214F. Furthermore, in the direction 110, the field plate 214F and the field plate 218F2 overlap with the source metal layer 228S of the source structure 230S, respectively. As shown in FIG. 1 , the source metal layer 228S can completely cover the field plate 214F and the field plate 218F2.

In some embodiments, the field plate 218F2 is conformally formed on the interlayer dielectric layer 210, the dielectric pattern 212, and the field plate 214F. Therefore, the field plate 218F2 is stepped in the cross-sectional view shown in FIG. 1. In this embodiment, the step number of the stepped field plate 218F2 is 2. Therefore, the field plate 218F2 has two upper surfaces 218F2-1T and 218F2-2T in the direction 110 and side surfaces 218F2-S1 and 218F2-S2 connected to the upper surfaces 218F2-1T and 218F2-2T and opposite to each other. The upper surface 218F2-1T of the field plate 218F2 is located directly above the first portion 212T1 of the top surface 212T of the dielectric pattern 212 (or the upper surface 214F-2T of the field plate 214F), and the upper surface 218F2-2T of the field plate 218F2 is located directly above the second portion 212T2 of the top surface 212T of the dielectric pattern 212. In some embodiments, the upper surfaces 218F2-1T and 218F2-2T are not coplanar. For example, in the direction 110, the upper surface 218F2-1T is above the upper surface 218F2-2T (i.e., the upper surface 218F2-2T is closer to the top surface 200T of the substrate 200 than the upper surface 218F2-1T).

As shown in FIG. 1 , the side surface 218F2-S1 of the field plate 218F2 close to the gate structure 220 is located directly above the first portion 212T1 of the top surface 212T of the dielectric pattern 212 (or the upper surface 214F-2T of the field plate 214F), and the side surface 218F2-S2 of the field plate 218F2 close to the drain structure 230D is located directly above the second portion 212T2 of the top surface 212T of the dielectric pattern 212. In some embodiments, the field plate 218F2 is located directly above the dielectric pattern 212 and covers a portion of the dielectric pattern 212. Therefore, the opposite sides 218F2-S1, 218F2-S2 of the field plate 218F2 may be misaligned with the corresponding sides 212S1, 212S2 of the dielectric pattern 212. Moreover, in the direction 100, the side 218F2-S2 of the field plate 218F2 close to the drain structure 230D is closer to the drain structure 230D than the side 214F-S2 of the field plate 214F close to the drain structure 230D, and the side 228S-S of the source metal layer 228S close to the drain structure 230D of the source structure 230S is closer to the drain structure 230D than the side 218F2-S2 of the field plate 218F2.

In some embodiments, the field plate 214F, the field plate 218F1, and the field plate 218F2 may include the same or similar materials and processes. In some embodiments, the field plate 218F1, the field plate 218F2, and the gate electrode layer 218G may be formed simultaneously.

As shown in FIG. 1 , the semiconductor device 500A further includes an interlayer dielectric layer 226. The interlayer dielectric layer 226 is disposed on the interlayer dielectric layer 216 and fully covers the source structure 230S, the drain structure 230D, and extends from the source structure 230S to the drain structure 230D. In addition, the drain structure 230D is separated from the field plate 218F1 and the field plate 218F2 by the interlayer dielectric layer 226 along the direction 100. In some embodiments, the interlayer dielectric layers 210, 216, and 226 may include the same or similar materials and processes. Therefore, in some embodiments, the interlayer dielectric layer 226 and the dielectric pattern 212 include different materials. The dielectric constant of the interlayer dielectric layer 226 is different from the dielectric constant of the dielectric pattern 212. The dielectric constant of the interlayer dielectric layer 226 may be smaller than the dielectric constant of the dielectric pattern 212. For example, the interlayer dielectric layer 226 is silicon dioxide (k=3.9) and the dielectric pattern 212 is silicon nitride (k=7.5). In some embodiments, the interlayer dielectric layer 226 may be a single-layer structure or a multi-layer structure.

In the present embodiment, the field plate 218F1 of the semiconductor device 500A extends toward the drain structure 230D along the direction 100 and partially overlaps with the drain electrode layer 214D in the direction 110. In some embodiments, the field plate 218F1 is electrically floating, which can prevent a large electric field peak from occurring at the edge of the drain electrode layer (e.g., the side surface 214D-S of the drain electrode layer 214D close to the gate structure 220), thereby reducing the drain-to-source on resistance (R _DS-ON ) from the source to the drain and increasing the breakdown voltage of the high electron mobility transistor. In this embodiment, the drain electrode layer 214D is a two-step drain electrode layer conformally formed on the barrier layer 206 and the interlayer dielectric layer 210. Furthermore, the field plate 218F1 is conformally formed on the interlayer dielectric layer 216 and the drain electrode layer 214D, and is a two-stepped shape field plate manufactured using a single-layer field plate process. This can achieve the electric field dispersion effect of a multi-layer field plate structure while saving one layer of field plate structure process cost (e.g., mask cost), thereby reducing the number of field plates set up and reducing the capacitance generated between the gate electrode and the drain region, so as to further improve the quality factor (Figure Of Merit, FOM) of the semiconductor device 500A (e.g., reducing the product of the on-resistance (drain-to-source on resistance, R _DS-ON ) and the output power capacitance (C _OSS ) of the semiconductor device 500A).

Furthermore, in some embodiments, when the dielectric pattern 212 is formed of a high-k dielectric material such as silicon nitride, and the interlayer dielectric layer 210 is formed of silicon dioxide, the dielectric pattern 212 can withstand a high electric field, thereby making the surface electric field distribution of the semiconductor device 500A more uniform, for example, reducing the electric field peak at the edge of a field plate formed subsequently (e.g., the side surface 214F-S2 of the field plate 214F close to the drain structure 230D). In addition, since the interlayer dielectric layer 210 and the dielectric pattern 212 are formed of different dielectric materials, when the patterning process (including lithography and etching process) for forming the dielectric pattern 212 is performed, the interlayer dielectric layer 210 can be used as an etching stop layer for the dielectric pattern 212, and the thickness of the interlayer dielectric layer 210 is not affected by the etching process, so as to further improve the quality factor (Figure Of Merit, FOM) of the semiconductor device 500A (for example, the pinch-off voltage of the semiconductor device 500A).

Furthermore, in some embodiments, the field plate 214F and the field plate 218F2 of the semiconductor device 500A extend toward the drain structure 230D along the direction 100 and are electrically connected to the source structure 230S. Therefore, the field plate 214F and the field plate 218F2 can also be used as the source field plate 214F, 218F2, which can effectively reduce the surface electric field (RESURF). Furthermore, the field plate 214F is a stepped source field plate conformally formed on the interlayer dielectric layer 210 and the dielectric pattern 212, and the field plate 218F2 is a stepped source field plate conformally formed on the interlayer dielectric layer 210, the dielectric pattern 212, and the field plate 214F, so that a multi-layer (e.g., double-layer) field plate structure can be manufactured using a single-layer field plate process. The field plate 214F and the field plate 218F2 of the embodiment of the present invention can achieve the electric field dispersion effect of a multi-layer field plate structure while saving the process cost of one layer of the field plate structure (such as the mask cost), thereby avoiding a large electric field peak at the edge of the field plate (such as the side 214F-S2 of the field plate 214F close to the drain structure 230D or the side 218F2-S2 of the field plate 218F2 close to the drain structure 230D), thereby reducing the drain-to-source on resistance (R _DS-ON ) from the source to the drain and increasing the breakdown voltage of the high electron mobility transistor. In addition, the field plate 214F and the field plate 218F2 are respectively disposed on different interlayer dielectric layers 210 and 216, so that the distance between each field plate and the barrier layer 206 can be adjusted to further increase the breakdown voltage. Since the field plate 214F and the field plate 218F2 can reduce the source-to-drain on resistance (R _DS-ON ), the quality factor (Figure Of Merit, FOM) of the semiconductor device 500A can be further improved (for example, the product of the on resistance (drain-to-source on resistance, R _DS-ON ) and the output power capacitance (C _OSS ) of the semiconductor device 500A can be reduced).

FIG. 2 is a cross-sectional schematic diagram of a semiconductor device 500B according to some embodiments of the present invention, wherein the same or similar element symbols as those in FIG. 1 represent the same or similar elements. As shown in FIG. 2, the semiconductor device 500B is different from the semiconductor device 500A in that the semiconductor device 500B further includes a dielectric pattern 312. In addition, the semiconductor device 500B replaces the drain electrode layer 214D with a drain electrode layer 314D, and replaces the field plate 218F1 with a field plate 318F1. Furthermore, the drain electrode layer 314D, the drain contact component 224D, and the drain metal layer 228D form a drain structure 330D. The dielectric pattern 312 is disposed on the drain side of the semiconductor device 500B (close to the drain structure 330D) and overlaps the drain electrode layer 314D and the field plate 218F1.

As shown in FIG. 2 , the dielectric pattern 312 is disposed on a portion of the interlayer dielectric layer 210 between the gate structure 220 and the drain structure 330D. The dielectric pattern 312 covers a portion of the top surface 210T of the interlayer dielectric layer 210. As shown in FIG. 2 , the interlayer dielectric layer 216 completely covers the dielectric pattern 312. Therefore, the dielectric pattern 312 is sandwiched between the interlayer dielectric layer 210 and the interlayer dielectric layer 216 along a direction 110 (also considered as a vertical direction) substantially perpendicular to the top surface 200T of the substrate 200. The dielectric pattern 312 has a top surface 312T and side surfaces 312S1 and 312S2 connected to the top surface 312T and opposite to each other. The side surfaces 312S1 and 312S2 of the dielectric pattern 312 are both located on the top surface 210T of the interlayer dielectric layer 210. In the direction 110 (also regarded as the vertical direction), the dielectric pattern 312 and the interlayer dielectric layer 210 partially overlap.

As shown in FIG. 2 , in a direction 100 (also referred to as a lateral direction) substantially parallel to the top surface 200T of the substrate 200 , a third distance D3 is between the side surface 312S1 of the dielectric pattern 312 and the gate layer 208 of the gate structure 220 , and a fourth distance D4 is between the side surface 312S2 of the dielectric pattern 312 and the drain contact feature 224D of the drain structure 330D. In some embodiments, the third distance D3 is greater than the fourth distance D4. In other words, in the direction 100 , the drain contact feature 224D of the drain structure 330D is closer to the dielectric pattern 312 than to the gate structure 220 .

The dielectric pattern 212 and the dielectric pattern 312 cover different portions of the top surface 210T of the interlayer dielectric layer 210. Furthermore, in the direction 100, the dielectric pattern 212 and the dielectric pattern 312 are spaced apart from each other. In some embodiments, the third distance D3 is greater than the first distance D1, and the fourth distance D4 is less than the second distance D2. In other words, in the direction 100, the dielectric pattern 212 is closer to the gate structure 220 than the dielectric pattern 312, and the dielectric pattern 312 is closer to the drain contact feature 224D of the drain structure 330D than the dielectric pattern 212.

As shown in FIG. 2 , in this embodiment, the drain electrode layer 314D is conformally formed on the barrier layer 206, the interlayer dielectric layer 210, and the dielectric pattern 312. In the cross-sectional view shown in FIG. 1 , the drain electrode layer 314D is stepped. In this embodiment, the number of steps of the stepped drain electrode layer 314D is 3. Therefore, the drain electrode layer 314D has three upper surfaces 314D-1T, 314D-2T, and 314D-3T. As shown in FIG. 2 , the upper surface 314D-1T of the drain electrode layer 314D is located directly above the top surface 200T (or barrier layer 206) of the substrate 200 that is not covered by the interlayer dielectric layer 210. The upper surface 314D-2T of the drain electrode layer 314D is located directly above the top surface 210T of the interlayer dielectric layer 210 that is not covered by the dielectric pattern 312 and is close to the drain contact feature 224D. The upper surface 314D-3T of the drain electrode layer 314D is located directly above the third portion 312T1 of the top surface 312T of the dielectric pattern 312, so that the fourth portion 312T2 of the top surface 312T of the dielectric pattern 312 is exposed from the drain electrode layer 314D. The third portion 312T1 and the fourth portion 312T2 of the top surface 312T of the dielectric pattern 312 are adjacent to each other and are different portions of the top surface 312T of the dielectric pattern 312. The drain electrode layer 314D contacts the top surface 200T of the substrate 200 not covered by the interlayer dielectric layer 210, the top surface 210T of the interlayer dielectric layer 210 not covered by the dielectric pattern 312 and close to the drain contact feature 224D, and the third portion 312T1 of the top surface 312T of the dielectric pattern 312. In some embodiments, the upper surfaces 314D-1T, 314D-2T, 314D-3T are not coplanar. For example, in the direction 110. The upper surface 314D-1T is below the upper surface 314D-2T (i.e., the upper surface 314D-1T is closer to the top surface 200T of the substrate 200 than the upper surface 314D-2T), and the upper surface 314D-2T is below the upper surface 314D-3T (i.e., the upper surface 314D-2T is closer to the top surface 200T of the substrate 200 than the upper surface 314D-3T).

In some embodiments, the dielectric pattern 212 and the dielectric pattern 312 may include the same or similar materials and processes. In addition, the dielectric pattern 212 and the dielectric pattern 312 may be formed at the same time. In some embodiments, the interlayer dielectric layers 210, 216 and the dielectric pattern 312 may include different materials. In some embodiments, the dielectric constant of the interlayer dielectric layers 210, 216 is different from the dielectric constant of the dielectric pattern 312. The dielectric constant of the interlayer dielectric layers 210, 216 may be less than the dielectric constant of the dielectric pattern 312. For example, the interlayer dielectric layers 210, 216 are silicon dioxide (k=3.9), and the dielectric pattern 312 is silicon nitride (k=7.5).

As shown in FIG. 2 , the field plate 318F1 is disposed on the interlayer dielectric layer 216 and the dielectric pattern 312. The field plate 318F1 partially overlaps with the drain electrode layer 314D on the top surface 312T of the dielectric pattern 312 and extends toward the drain contact member 224D along the direction 100. Specifically, in the direction 110, the field plate 318F1 overlaps with the drain electrode layer 314D on the third portion 312T1 of the top surface 312T of the dielectric pattern 312. The field plate 318F1 does not overlap with a portion of the drain electrode layer 314D on the top surface 210T of the interlayer dielectric layer 210 that is not covered by the dielectric pattern 312 and is close to the drain contact feature 224D. Also, the field plate 318F1 does not overlap with a portion of the drain electrode layer 314D located on the barrier layer 206 that is not covered by the interlayer dielectric layer 210. Therefore, the field plate 318F1 is closer to the gate structure 220 than the drain electrode layer 314D. As shown in FIG. 2 , the field plate 318F1 extends from the top surface 210T of the interlayer dielectric layer 210 that is not covered by the drain electrode layer 314D and the dielectric pattern 312 and is close to the gate structure 220, to a fourth portion 312T2 that covers the top surface 312T of the dielectric pattern 312 along the direction 100. The field plate 318F1 also extends from the first portion 314D-3TA of the upper surface 314D-3T of the drain electrode layer 314D, and exposes the second portion 314D-3TB of the upper surface 314D-3T from the field plate 318F1. The first portion 314D- 3TA and the second portion 314D- 3TB of the upper surface 314D- 3T of the drain electrode layer 314D are adjacent to each other and are different portions of the upper surface 314D- 3T of the drain electrode layer 314D.

In the direction 100, the upper surface 314D-3T of the drain electrode layer 314D has a length L3, and the first portion 314D-3TA of the upper surface 314D-3T has a length L4. In some embodiments, the ratio of the length L3 to the length L4 is greater than or equal to 2. If the ratio of the length L3 to the length L4 is less than 2, the overlapped portion of the field plate 318F1 and the drain electrode layer 314D may be too large to affect the uniformity of the surface electric field.

In some embodiments, the field plate 318F1 is conformally formed on the interlayer dielectric layer 210, the dielectric pattern 312, and the drain electrode layer 314D. In the cross-sectional view shown in FIG. 2, the drain electrode layer 314D is stepped. In this embodiment, the step number of the stepped drain electrode layer 314D is 3. Therefore, the field plate 318F1 may have three upper surfaces 318F1-1T, 318F1-2T, 318F1-3T and side surfaces 318F1-S1 and 318F1-S2 respectively connected to the upper surfaces 318F1-1T and 318F1-3T and opposite to each other. As shown in FIG. 1 , the upper surface 318F1-1T of the field plate 318F1 is located directly above the top surface 210T of the interlayer dielectric layer 210 that is not covered by the drain electrode layer 314D and the dielectric pattern 312. The upper surface 318F1-2T of the field plate 318F1 is located directly above the fourth portion 312T2 of the top surface 312T of the dielectric pattern 312 that is not covered by the drain electrode layer 314D. The upper surface 318F1-3T of the field plate 318F1 is located directly above the first portion 314D-3TA of the upper surface 314D-3T of the drain electrode layer 314D. In some embodiments, the upper surfaces 318F1-1T, 318F1-2T, and 318F1-3T of the field plate 318F1 are not coplanar. For example, in the direction 110, the upper surface 318F1-1T is below the upper surface 318F1-2T (i.e., the upper surface 318F1-1T is closer to the top surface 200T of the substrate 200 than the upper surface 318F1-2T), and the upper surface 318F1-2T is below the upper surface 318F1-3T (i.e., the upper surface 318F1-2T is closer to the top surface 200T of the substrate 200 than the upper surface 318F1-3T).

As shown in FIG. 2 , the side surface 318F1-S1 of the field plate 318F1 close to the gate structure 220 is not located directly above the drain electrode layer 214D and the dielectric pattern 312, and the side surface 318F1-S2 of the field plate 318F1 close to the drain structure 330D is located directly above the drain electrode layer 314D. Therefore, the side surface 318F1-S1 of the field plate 318F1 close to the gate structure 220 is closer to the gate structure 220 than the side surface 314D-S of the drain electrode layer 314D close to the gate structure 220.

The semiconductor device 500B has the advantages of the semiconductor device 500A. In addition, in this embodiment, the drain electrode layer 314D is a three-step drain electrode layer conformally formed on the barrier layer 206, the interlayer dielectric layer 210 and the dielectric pattern 312 . The field plate 318F1 is conformally formed on the interlayer dielectric layer 216, the dielectric pattern 312, and the drain electrode layer 214D, and is a three-step stepped field plate manufactured using a single-layer field plate process. In addition to having the advantages of the field plate 218F1 of the semiconductor device 500A, the electric field dispersion effect of the multi-layer field plate structure can be achieved while saving the process cost of the two-layer field plate structure (e.g., mask cost).

In addition, when the dielectric pattern 312 of the semiconductor device 500B is formed of a high-k dielectric material such as silicon nitride, and the interlayer dielectric layer 210 is formed of silicon dioxide, the dielectric pattern 312 can withstand a high electric field, thereby making the surface electric field distribution of the semiconductor device 500B more uniform, for example, reducing the electric field peak at the edge of the field plate formed subsequently (for example, the side surface 218F1-S2 of the field plate 218F1 close to the drain structure 330D). In addition, since the interlayer dielectric layer 210 and the dielectric pattern 312 are formed of different dielectric materials, when the patterning process (including lithography and etching processes) for forming the dielectric pattern 312 is performed, the interlayer dielectric layer 210 can be used as an etch stop layer for the dielectric pattern 312, and the thickness of the interlayer dielectric layer 210 can be precisely controlled to further improve the quality factor (Figure Of Merit, FOM) of the semiconductor device 500B (for example, the pinch-off voltage of the semiconductor device 500B).

The present invention provides a semiconductor device such as a high electron mobility transistor (HEMT) device. The semiconductor device may include a plurality of field plates, which may make the surface electric field distribution of the semiconductor device more uniform. The field plates may include a field plate (e.g., field plate 218F1) disposed on the drain side (close to the drain structure) of the semiconductor device and overlapping with the drain electrode layer, and a field plate (e.g., field plate 214F, field plate 218F2) disposed between the gate structure and the drain structure and overlapping with the dielectric pattern.

In some embodiments, the drain electrode layer is a two-step drain electrode layer. Furthermore, the field plate overlapping the drain electrode layer is conformally formed on the drain electrode layer, and a two-step stepped electrically floating field plate manufactured using a single-layer field plate process can achieve the electric field dispersion effect of a multi-layer field plate structure while saving one layer of field plate structure process cost (e.g., mask cost), thereby reducing the number of field plates set, and reducing the capacitance generated between the gate electrode and the drain region, thereby further reducing the product of the on-resistance (R _DS-ON ) and the output power capacitance (C _OSS ) of the semiconductor device, and improving the quality factor (FOM) of the semiconductor device.

In some other embodiments, a dielectric pattern (e.g., dielectric pattern 312) may be disposed between the first interlayer dielectric layer (e.g., interlayer dielectric layer 210) and the drain electrode layer. The dielectric pattern partially overlaps the drain electrode layer in the vertical direction. Therefore, the drain electrode layer is a three-step drain electrode layer. Furthermore, the field plate overlapping the drain electrode layer is conformally formed on the drain electrode layer and the above-mentioned dielectric pattern, and a three-step stepped electrically floating field plate manufactured using a single-layer field plate process can achieve the electric field dispersion effect of a multi-layer field plate structure while saving the process cost of a two-layer field plate structure (such as a mask cost), thereby further improving the quality factor (FOM) of the semiconductor device.

In some embodiments, the semiconductor device includes a dielectric pattern (e.g., dielectric pattern 212) disposed on a portion of a first interlayer dielectric layer (e.g., interlayer dielectric layer 210) between a gate structure and a drain structure, so that a field plate disposed between the gate structure and the drain structure and overlapping with the dielectric pattern is a two-step source field plate. Therefore, a multi-layer (e.g., double-layer) field plate structure can be manufactured using a single-layer field plate process, and the electric field dispersion effect of the multi-layer field plate structure can be achieved while saving the process cost of one layer of the field plate structure (e.g., mask cost), thereby avoiding the occurrence of a large electric field peak. Furthermore, the distance between each field plate and the barrier layer can be adjusted to reduce the source-to-drain on-resistance (R _DS-ON ), reduce the capacitance generated between the gate electrode and the drain region, and further increase the breakdown voltage of the high electron mobility transistor to improve the quality factor (FOM) of the semiconductor device.

In some embodiments, multiple dielectric patterns near the drain structure or near the gate structure are in contact with the first interlayer dielectric layer thereunder and are formed of dielectric materials with different dielectric constants. For example, the first interlayer dielectric layer can be formed of silicon dioxide, and the dielectric pattern can be formed of a high dielectric constant dielectric material such as silicon nitride. The above-mentioned dielectric pattern with a high dielectric constant can make the surface electric field distribution of the semiconductor device more uniform. In addition, during the etching process of forming the dielectric pattern, the first interlayer dielectric layer can be used as an etching stop layer of the etching process, so that the thickness of the first interlayer dielectric layer will not vary due to the above-mentioned etching process, so as to further improve the performance of the semiconductor device.

Although the present invention is disclosed as above by the aforementioned embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the attached patent application.

100,110: Direction 200: Substrate 200T,208T,210T,212T,312T: Top surface 202: Buffer layer 204: Channel layer 206: Barrier layer 208: Gate layer 208E: Edge 210,216,226: Interlayer dielectric layer 210S1,210S2,212S1,212S2,312S1,312S2,214D-S,314D-S,214F-S1,214F-S2,218F1-S1,218F1-S2,218F2-S1,218F2-S2,318F1-S1,318F1-S2,228S-S: Side surface 212,312: Dielectric pattern 212T1,214D-2TA,314D-3TA: First part 212T2,214D-2TB,314D-3TB: Second part 214D,314D: Drain electrode layer 214D-1T, 214D-2T, 314D-1T, 314D-2T, 314D-3T, 214F-1T, 214F-2T, 218F1-1T, 218F1-2T, 218F2-1T, 218F2-2T, 318F1-1T, 318F1-2T, 318F1-3T: top surface 214F, 218F1, 218F2, 318F1: field plate 214S: source electrode layer 218G: gate electrode layer 220: gate structure 220S1: first side 220S2: second side 224D: drain contact part 224S: Source contact part 228D: Drain metal layer 228S: Source metal layer 230S: Source structure 230D, 330D: Drain structure 312T1: Third part 312T2: Fourth part 500A, 500B: Semiconductor device D1: First distance D2: Second distance D3: Third distance D4: Fourth distance L1, L2, L3, L4: Length

When read in conjunction with the accompanying drawings, the following detailed description will provide a better understanding of the concepts of the present invention. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are provided for illustration purposes only. In fact, the size of the components may be arbitrarily enlarged or reduced to clearly illustrate the features of the present invention. FIG. 1 is a schematic cross-sectional view of a semiconductor device of some embodiments of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor device of some embodiments of the present invention.

100,110: Direction

200: Substrate

200T, 208T, 210T, 212T: Top surface

202: Buffer layer

204: Channel layer

206: Barrier layer

208: Gate layer

208E: Edge

210,216,226: Interlayer dielectric layer

210S1, 210S2, 212S1, 212S2, 214D-S, 214F-S1, 214F-S2, 218F1-S1, 218F1-S2, 218F2-S1, 218F2-S2, 228S-S: Side

212: Dielectric pattern

212T1,214D-2TA:Part 1

212T2,214D-2TB:Part 2

214D: Drain electrode layer

214D-1T, 214D-2T, 214F-1T, 214F-2T, 218F1-1T, 218F1-2T, 218F2-1T, 218F2-2T: Upper surface

214F,218F1,218F2: Field board

214S: Source electrode layer

218G: Gate electrode layer

220: Gate structure

220S1: First side

220S2: Second side

224D: Drain contact parts

224S: Source contact parts

228D: Drain metal layer

228S: Source metal layer

230S: Source structure

230D: Drain structure

500A:Semiconductor device

D1: First distance

D2: Second distance

L1, L2: length

Claims (20)

A semiconductor device comprises: a substrate; a gate structure disposed on the substrate; a first interlayer dielectric layer disposed on the substrate and partially covering the substrate and the gate structure; a drain structure disposed on the substrate and located on a first side of the gate structure, wherein the drain structure comprises: a drain electrode layer disposed on the substrate and extending from the substrate not covered by the first interlayer dielectric layer to cover a portion of a first top surface of the first interlayer dielectric layer; a second interlayer dielectric layer disposed on the first interlayer dielectric layer and covering the drain electrode layer; and A first field plate is disposed on the second inter-layer dielectric layer and partially overlaps with the drain electrode layer on the first top surface of the first inter-layer dielectric layer, wherein the first field plate is electrically floating. A semiconductor device as described in claim 1, wherein the drain electrode layer comprises: a first upper surface located directly above a second top surface of the substrate not covered by the first interlayer dielectric layer; and a second upper surface located directly above the first top surface of the first interlayer dielectric layer, wherein the first upper surface and the second upper surface are not coplanar. A semiconductor device as described in claim 2, wherein the first upper surface is below the second upper surface. A semiconductor device as described in claim 2, wherein the first field plate covers a first portion of the second upper surface. A semiconductor device as described in claim 4, wherein in a first direction, the second upper surface has a first length, the first portion of the second upper surface has a second length, and the ratio of the first length to the second length is greater than or equal to 2. A semiconductor device as described in claim 2, wherein in a cross-sectional view, the drain electrode layer and the first field plate are both step-shaped. A semiconductor device as described in claim 6, wherein the first field plate includes: a third upper surface located directly above the first interlayer dielectric layer not covered by the drain electrode layer; and a fourth upper surface located directly above the second upper surface of the drain electrode layer, wherein the third upper surface is below the fourth upper surface. The semiconductor device as described in claim 7 further includes: A first dielectric pattern disposed on the first interlayer dielectric layer between the gate structure and the drain structure, wherein the drain electrode layer contacts a third portion of a third top surface of the first dielectric pattern. A semiconductor device as described in claim 8, wherein in a first direction, the first dielectric pattern is separated from the gate structure by a first distance, the first dielectric pattern is separated from a drain contact part of the drain structure by a second distance, and the first distance is greater than the second distance. A semiconductor device as described in claim 8, wherein the first interlayer dielectric layer and the first dielectric pattern include different materials. A semiconductor device as described in claim 8, wherein the drain electrode layer further comprises: A fifth upper surface located directly above the third portion of the third top surface of the first dielectric pattern. A semiconductor device as described in claim 11, wherein the fifth upper surface is above the second upper surface. A semiconductor device as described in claim 11, wherein the first field plate further includes: a sixth top surface located directly above a fourth portion of the third top surface of the first dielectric pattern, wherein the third portion and the fourth portion are adjacent to each other and are different portions of the third top surface of the first dielectric pattern, wherein: the third top surface is located directly above the first interlayer dielectric layer not covered by the first dielectric pattern, the fourth top surface is located directly above the third portion of the third top surface of the first dielectric pattern, wherein the third top surface is below the sixth top surface, and the sixth top surface is below the fourth top surface. A semiconductor device as described in claim 1, wherein the drain structure further comprises: a drain contact component located on the drain electrode layer and passing through the second interlayer dielectric layer; and a drain metal layer located on the drain contact component, wherein the drain electrode layer and the drain metal layer extend along a first direction, and the drain contact component extends along a second direction. A semiconductor device as described in claim 14, wherein in the second direction, the first field plate partially overlaps with the drain metal layer. The semiconductor device as described in claim 14 further includes: A source structure disposed on the substrate and located on a second side of the gate structure, wherein the source structure includes; A source electrode layer disposed on the substrate, extending along the first direction and partially covering the first top surface of the first interlayer dielectric layer, wherein the opposite sides of the first interlayer dielectric layer are respectively covered by the drain electrode layer and the source electrode layer; A source contact component, located on the source electrode layer and extending along the second direction through the second interlayer dielectric layer; and A source metal layer is located on the source contact component, wherein the source electrode layer and the source metal layer extend along the first direction, and the source contact component extends along the second direction. The semiconductor device as described in claim 16 further includes: a second dielectric pattern disposed on the first interlayer dielectric layer between the gate structure and the drain structure, wherein the first interlayer dielectric layer and the second dielectric pattern include different materials; a second field plate disposed on the substrate and covering the first interlayer dielectric layer between the gate structure and the dielectric pattern and the second dielectric pattern; and a third field plate disposed on the second interlayer dielectric layer directly above the second dielectric pattern and partially overlapping with the second field plate, wherein in the first direction, the second field plate is closer to the gate structure than the third field plate, and the third field plate is closer to the gate structure than the first field plate. A semiconductor device as described in claim 17, wherein the second field plate and the third field plate are electrically connected to the source structure. A semiconductor device as described in claim 17, wherein the second field plate includes: a seventh upper surface located directly above the first interlayer dielectric layer between the gate structure and the second dielectric pattern; and an eighth upper surface located directly above a fifth portion of a fourth top surface of the second dielectric pattern, wherein the seventh upper surface is below the eighth upper surface. A semiconductor device as described in claim 19, wherein the third field plate includes: a ninth upper surface located directly above the fifth portion of the fourth top surface of the second dielectric pattern; and a tenth upper surface located directly above a sixth portion of the fourth top surface of the second dielectric pattern, wherein the ninth upper surface is above the tenth upper surface, wherein the fifth portion and the sixth portion are adjacent to each other and are different portions of the fourth top surface of the second dielectric pattern.

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