TWI879351B - Floating-point computing-in-memory device - Google Patents

Abstract

A floating-point computing-in-memory device is provided. The floating-point computing-in-memory device includes the exponent computing memory module and the mantissa computing memory module. The exponent computing memory module includes a plurality of weighting exponent memory circuits, a plurality of exponent computing circuits and a comparison circuit. The exponent computing circuits are used to obtain a plurality of exponent products. The mantissa computing memory module includes a bits shifting circuit, a plurality of weighting mantissa memory circuits, a plurality of mantissa computing circuits, a shift-and-addition circuit, a plurality of weighting sign memory circuits, a plurality of sign computing circuits and an addition circuit. The mantissa computing circuits and the shift-and-addition circuit are used to obtain a plurality of mantissa products. The sign computing circuits are used to obtain a plurality of sign products.

Description

Floating point in-memory device

The present disclosure relates to a floating point in-memory computing device.

Computing in memory (CIM) is considered as one of the effective technologies to solve the memory wall. It uses computing in memory to reduce the number of data transfers, which can significantly increase the computing speed to hundreds or even thousands of times that of traditional architectures. A large part of the energy of today's large AI networks (such as DNN) is consumed in data transfer. Computing in memory (CIM) can significantly reduce the energy consumed by this, and can be said to be a potential future AI technology that increases computing power and reduces power consumption.

The potential of CIM technology has led many manufacturers and research institutions to invest in and publish many innovative technologies, but they can only perform integer operations, and the analog sensing used may cause problems such as noise or process variation. The current CIM does not support floating-point operations. Therefore, researchers are working to develop a CIM architecture that supports floating-point numbers.

The present disclosure relates to a floating-point computing in memory device, which integrates floating-point computing circuits into the memory, avoiding data input and output, and thus has the advantages of fast computing, and can reduce power consumption and improve energy efficiency.

According to one aspect of the present disclosure, a floating-point computing in memory device is provided. The floating-point computing in memory device includes an exponent storage computing module and a mantissa storage computing module. The exponent storage computing module includes a plurality of weight exponent storage circuits, a plurality of exponent computing circuits and a comparison circuit. The weight exponent storage circuits are used to store the exponent parts of a plurality of weight data. The exponent computing circuits are used to perform an addition operation on the exponent parts of a plurality of input data and the exponent parts of the weight data to obtain a plurality of exponential product data. The comparison circuit is used to compare these exponential product data to obtain a maximum exponential product data. The mantissa storage operation module includes a digit shift circuit, a plurality of weight mantissa storage circuits, a plurality of mantissa operation circuits, a shift and addition circuit, a plurality of weight positive and negative sign storage circuits, a plurality of positive and negative sign operation circuits and a summing circuit. The digit shift circuit is used to shift the mantissa part of these input data according to the maximum exponential product data. These weight mantissa storage circuits are used to store the mantissa part of these weight data. These mantissa operation circuits are used to perform a multiplication operation on the mantissa part of these input data and the mantissa part of these weight data to obtain a plurality of mantissa product intermediate data. The shift and addition circuit is used to shift the intermediate data of the mantissa products and then sum them up to obtain a number of mantissa product data. The weight positive and negative sign storage circuits are used to store the positive and negative sign parts of the weight data. The positive and negative sign operation circuits are used to perform an exclusive-OR operation on the positive and negative sign parts of the input data and the positive and negative sign parts of the weight data to obtain a number of positive and negative sign product data. The summing circuit is used to integrate the positive and negative sign product data, the maximum exponent product data and the mantissa product data to obtain an input and weight product sum data.

According to another aspect of the present disclosure, an exponential storage operation module is proposed. The exponential storage operation module includes a plurality of weight index storage circuits, a plurality of exponential operation circuits and a comparison circuit. The weight index storage circuits are used to store the exponential parts of a plurality of weight data. The exponential operation circuits are used to perform an addition operation on the exponential parts of a plurality of input data and the exponential parts of the weight data to obtain a plurality of exponential product data. The comparison circuit is used to compare the exponential product data to obtain a maximum exponential product data.

According to another aspect of the present disclosure, a mantissa storage operation module is proposed. The mantissa storage operation module includes a plurality of weight mantissa storage circuits, a plurality of mantissa operation circuits and a shift and addition circuit. These weight mantissa storage circuits are used to store the mantissa parts of a plurality of weight data. These mantissa operation circuits are used to perform a multiplication operation on the mantissa parts of a plurality of input data and the mantissa parts of these weight data to obtain a plurality of mantissa product intermediate data. The shift and addition circuit is used to shift and then sum up these mantissa product intermediate data to obtain a plurality of mantissa product data.

In order to better understand the above and other aspects of the present disclosure, the following embodiments are specifically described in detail with reference to the accompanying drawings:

The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the interpretation of these terms shall be subject to the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement part or all of the technical features in any embodiment, or selectively combine part or all of the technical features in these embodiments.

Please refer to FIG. 1, which illustrates the multiplication operation of floating point data in an embodiment of the present disclosure. The floating point data is composed of a sign part S, an exponent part E, and a mantissa part M. Taking the 16-bit FP16 operation architecture as an example, the sign part S occupies 1 bit, the exponent part E occupies 8 bits, and the mantissa part M occupies 7 bits. The 7 bits of the mantissa part M are the values in order. , the value of this floating point data is .

When the sign part S is 0, it indicates a positive value; when the sign part S is 1, it indicates a negative value. The range that the exponent part E can represent is The range that the mantissa M can represent is 1.0 to 1.9921875.

As shown in Figure 1, both the input data IN and the weight data WT can use the FP16 computing architecture. After the input data IN and the weight data WT are multiplied, the product data ML can be obtained. The product data ML will also use the FP16 computing architecture. When the input data IN and the weight data WT are multiplied, the exponent part E is added, the mantissa part M is multiplied, and the sign part S is exclusive-ORed.

Please refer to the 2nd figure, it illustrates the storage mode of the floating point data according to this disclosure one embodiment. In one embodiment, the exponent part E, the positive and negative sign part S and the mantissa part M of the floating point data can be arranged in sequence and stored in the memory.

Please refer to FIG. 3, which shows a schematic diagram of a floating-point computing in memory device 100 according to an embodiment of the present disclosure. The floating-point computing in memory device 100 includes an exponent storage and operation module EP and a mantissa storage and operation module MT. The exponent storage and operation module EP is used to store and operate the exponent part E (shown in FIG. 1) of the floating-point data; the mantissa storage and operation module MT is used to store and operate the mantissa part M (shown in FIG. 1) of the floating-point data.

The exponent storage operation module EP includes a plurality of weight exponent storage circuits SRE, a plurality of exponent operation circuits LCCE and a comparison circuit COMP. The mantissa storage operation module MT includes a single-digit shift circuit SHT, a plurality of weight sign storage circuits SRS, a plurality of sign operation circuits LCCS, a plurality of weight mantissa storage circuits SRM, a plurality of mantissa operation circuits LCCM, a shift and addition circuit SHTA and a summing circuit MSA.

In the floating-point number in-memory operation device 100, storage units (such as weight exponent storage circuit SRE, weight sign storage circuit SRS, weight mantissa storage circuit SRM) and operation units (such as exponent operation circuit LCCE, comparison circuit COMP, bit shift circuit SHT, sign operation circuit LCCS, mantissa operation circuit LCCM, shift and addition circuit SHTA, summing circuit MSA) are integrated. Therefore, when performing floating-point operations, frequent input and output of data can be avoided, so it has the advantage of fast operation, and can reduce power consumption and improve energy efficiency.

Please refer to FIG. 3 and FIG. 4 simultaneously. FIG. 4 shows the data flow of the floating-point memory internal operation device 100 performing floating-point operation according to an embodiment of the present disclosure. The data flow of the floating-point memory internal operation device 100 performing floating-point operation includes the alignment AL of the exponent part E (shown in FIG. 1), the multiplication MLP of the mantissa part M (shown in FIG. 1), and the accumulation AC of the multiplication data ML (shown in FIG. 1). The alignment AL of the exponent part E is completed by the exponent operation circuit LCCE of the exponent storage operation module EP, the comparison circuit COMP, and the bit shift circuit SHT of the mantissa storage operation module MT. The multiplication MLP of the mantissa part M is completed by the mantissa operation circuit LCCM and the shift and addition circuit SHTA of the mantissa storage operation module MT. The accumulation AC of the multiplication result is completed by the summing circuit MSA of the mantissa storage operation module MT.

When performing a multiplication operation on floating point data, an addition operation is performed on the exponential part E. As shown in FIG. 4 , the exponential operation circuit LCCE is used to perform an addition operation on the exponential part IN_E of a plurality of input data IN and the exponential part WT_E of a plurality of weight data WT, respectively, to obtain a plurality of exponential product data ML_E. The exponential part WT_E of the weight data WT is stored in the weight exponent storage circuit SRE of FIG. 3 .

The comparison circuit COMP is connected to the exponential operation circuit LCCE. The comparison circuit COMP is used to compare the exponential product data ML_E to obtain a maximum exponential product data ML_E_max.

The bit shift circuit SHT is connected to the exponential operation circuit LCCE and the comparison circuit COMP. The bit shift circuit SHT shifts the mantissa IN_M of the input data IN according to the maximum exponential product data ML_E_max to obtain the mantissa IN_M' after shifting. The mantissa WT_M of the weight data WT is stored in the weight mantissa storage circuit SRM of FIG. 3 .

The mantissa operation circuit LCCM is connected to the bit shift circuit SHT. The mantissa operation circuit LCCM is used to perform a multiplication operation on the mantissa part IN_M' of the input data IN and the mantissa part WT_M of the weight data WT to obtain a plurality of mantissa product intermediate data ML_M_im. The mantissa product intermediate data ML_M_im is the data of the point-by-point product of each bit of the mantissa part WT_M and the mantissa part IN_M' in the multiplication operation.

The shift and add circuit SHTA is used to shift and then add up the mantissa product intermediate data ML_M_im to obtain the mantissa product data ML_M.

The sign operation circuit LCCS is used to perform an exclusive-OR operation on the sign part IN_S of the input data IN and the sign part WT_S of the weight data WT to obtain the sign product data ML_S. The sign part WT_S of the weight data WT is stored in the weight sign storage circuit SRS in FIG. 3 .

The summing circuit MSA is used to integrate the sign product data ML_S, the maximum exponent product data ML_E_max and the mantissa product data ML_M to obtain an input and weight product sum data MAC.

The following is a further detailed description of the detailed structure and operation of each component.

Please refer to Figure 5, which shows a schematic diagram of a weight index storage circuit SRE and an index operation circuit LCCE according to an embodiment of the present disclosure. The weight index storage circuit SRE includes a plurality of static random-access memories (SRAM) SR. Each static random-access memory SR includes six transistors (i.e., 6T-SRAM). The weight index storage circuit SRE, for example, has global bit lines GBL<0>~GBL<7>, GBLB<0>~GBLB<7> and local bit lines LBL<0>~LBL<7>, LBLB<0>~LBLB<7>. A certain row of static random access memories SR stores the index part WT_E of a set of weight data WT. When a static random access memory SR of a certain row is turned on, the exponential part WT_E of a set of weight data WT can be input into the exponential operation circuit LCCE via the local bit lines LBL<0>~LBL<7>.

The exponential operation circuit LCCE includes a plurality of switching and pre-charging circuits SAP and an adder AD. The switching and pre-charging circuit SAP is connected to the weight exponent storage circuit SRE. The switching and pre-charging circuit SAP is used to receive the exponential part WT_E of the weight data WT. The adder AD is connected to the switching and pre-charging circuit SAP to receive the exponential part WT_E of the weight data WT. The adder AD is used to perform addition operation on the exponential part IN_E of the input data IN and the exponential part WT_E of the weight data WT to obtain the exponential product data ML_E.

Please refer to FIG. 6 , which shows a schematic diagram of a comparison circuit COMP according to an embodiment of the present disclosure. The comparison circuit COMP includes a plurality of comparators CP. The comparators CP are used to compare two exponential product data ML_E of the exponential product data ML_E. After a hierarchical pairwise comparison, the maximum exponential product data ML_E_max can be obtained.

Please refer to FIG. 7 again, which shows a schematic diagram of a comparator CP according to an embodiment of the present disclosure. The comparator CP of the present embodiment includes a first judgment circuit CP1, a second judgment circuit CP2, and a third judgment circuit CP3. The first judgment circuit CP1 is used to compare the preceding bits A<0>~A<2>, B<0>~B<2> of the exponential product data ML_E. When the preceding bit A<2> is compared with the preceding bit B<2>, the mutually exclusive OR judge is activated by the enable signal EN, and the mutually exclusive OR result C<2> is output. The mutually exclusive OR results C<2>~C<0> can be output as a judgment result AWIN or a judgment result BWIN after being judged by the judge. The judgment result AWIN indicates that the previous bit A<0>~A<2> is greater than the previous bit B<0>~B<2>. If the size can be judged in the first judgment circuit CP1, there is no need to activate the subsequent second judgment circuit CP2 and the third judgment circuit CP3.

The second judging circuit CP2 is connected to the first judging circuit CP1. The second judging circuit CP2 is used to compare the middle bit of the exponential product data ML_E. If the size can be judged in the second judging circuit CP2, there is no need to activate the subsequent third judging circuit CP3.

The third judging circuit CP3 is connected to the second judging circuit CP2. The third judging circuit CP3 is used to compare the latter bits of the exponential product data ML_E.

Through the three-stage judgment circuit design of the comparator CP, the comparison of many exponential product data ML_E can omit the second judgment circuit CP2 and the third judgment circuit CP3, or omit the third judgment circuit CP3. Therefore, the power consumption can be greatly saved and the comparison speed can be accelerated.

Please refer to FIG. 8, which shows a schematic diagram of a bit shift circuit SHT according to an embodiment of the present disclosure. The bit shift circuit SHT includes a plurality of subtractors SB and a plurality of shifters SH. The subtractors SB are connected to the comparison circuit COMP. The subtractors SB are used to perform a subtraction operation on the maximum exponential product data ML_E_max and the exponential product data ML_E to obtain the shift amount data OF.

The shifter SH is connected to the subtracter SB. The shifter SH is used to shift the mantissa IN_M of the input data IN according to the shift amount data OF to obtain the mantissa IN_M' after the shift.

Please refer to Figure 9, which shows a schematic diagram of a mantissa calculation circuit LCCM according to an embodiment of the present disclosure. The weight mantissa storage circuit SRM includes a plurality of static random-access memories (SRAM) SR. Each static random-access memory SR includes six transistors (i.e., 6T-SRAM). The weight mantissa storage circuit SRM, for example, has global bit lines GBL<0>~GBL<7>, GBLB<0>~GBLB<7> and local bit lines LBL<0>~LBL<7>, LBLB<0>~LBLB<7>. A row of static random-access memories SR stores the mantissa part WT_M of a set of weight data WT. When a static random access memory SR of a certain row is turned on, the mantissa part WT_M of a set of weight data WT can be input into the mantissa operation circuit LCCM via the local bit lines LBL<0>~LBL<7>.

The mantissa calculation circuit LCCM includes a plurality of switching and pre-charging circuits SAP and a point-wise multiplier PWM. The switching and pre-charging circuit SAP is connected to the weight mantissa storage circuit SRM. The switching and pre-charging circuit SAP is used to receive the mantissa part WT_M of the weight data WT. The point-wise multiplier PWM is connected to the switching and pre-charging circuit SAP to receive the mantissa part WT_M of the weight data WT. The point-wise multiplier PWM is used to perform a multiplication operation on the mantissa part IN_M of the input data IN and the mantissa part WT_M of the weight data WT to obtain the mantissa product data ML_M.

Please refer to FIG. 10, which shows a schematic diagram of a point-by-point multiplier PWM according to an embodiment of the present disclosure. The point-by-point multiplier PWM is composed of a plurality of transistors TR and TRB. The static random access memory SR is used to store the bit value of the mantissa part WT_M of the weight data WT. The leftmost static random access memory SR corresponds to the most significant bit MSB[7], and the rightmost static random access memory SR corresponds to the least significant bit LSB[0].

The bit lines BL0 to BL7 of the static random access memory SR storing the mantissa WT_M of the weight data WT are connected to the serially connected transistors TR. The bit lines BLB0 to BLB7 of the static random access memory SR are connected to the serially connected transistors TRB. Both ends of the transistor TR are connected to the input terminals IN[0] to IN[7] and the output terminals OUT0[0] to OUT0[7], and both ends of the transistor TRB are connected to the ground terminal GD and the output terminals OUT0[0] to OUT0[7]. The mantissa IN_M of the input data IN is input from the input terminals IN[0] to IN[7].

According to the circuit structure of the point-by-point multiplier PWM, when the mantissa WT_M of the weight data WT is input as 1 from the bit line BL7 and the mantissa IN_M of the input data IN is input as 1 from the input terminal IN[7], the output terminal OUT7[7] outputs 1. When the mantissa WT_M of the weight data WT is input as 1 from the bit line BL7 and the mantissa IN_M of the input data IN is input as 0 from the input terminal IN[6], the output terminal OUT7[6] outputs 0. When the mantissa WT_M of the weight data WT is input as 0 from the bit line BL0 and the mantissa IN_M of the input data IN is input as 0 from the input terminal IN[7], the output terminal OUT0[7] outputs 0. When the mantissa part WT_M of the weight data WT is input as 0 from the bit line BL0 and the mantissa part IN_M of the input data IN is input as 1 from the input terminal IN[6], the output terminal OUT0[6] outputs 0.

Through the circuit structure of the point-by-point multiplier PWM, the point-by-point product results of the mantissa part WT_M of the weight data WT and the mantissa part IN_M of the input data IN can be obtained. These product results are the mantissa product intermediate data ML_M_im mentioned above.

Please refer to FIG. 11, which illustrates the operation of the shift and add circuit SHTA according to an embodiment of the present disclosure. The shift and add circuit SHTA is used to shift the mantissa product intermediate data ML_M_im and then add them up to obtain the mantissa product data ML_M.

Please refer to Figure 12, which shows a schematic diagram of a sign operation circuit LCCS according to an embodiment of the present disclosure. The weight sign storage circuit SRS includes a plurality of static random-access memories (SRAM) SR. Each static random-access memory SR includes six transistors (i.e., 6T-SRAM). The weight sign storage circuit SRS, for example, has global bit lines GBL＜7＞, GBLB＜7＞ and local bit lines LBL＜7＞, LBLB＜7＞. A static random-access memory SR stores the sign part WT_S of a set of weight data WT. When a static random access memory SR is turned on, the sign part WT_S of a set of weight data WT can be input into the sign operation circuit LCCS via the local bit line LBL＜7＞.

The positive and negative sign operation circuit LCCS includes a switching and pre-charging circuit SAP and an exclusive OR operator XOR.

The switching and pre-charging circuit SAP is connected to the weight sign storage circuit SRS. The switching and pre-charging circuit SAP is used to receive the sign part WT_S of the weight data WT. The exclusive OR operator XOR is connected to the switching and pre-charging circuit SAP to receive the sign part WT_S of the weight data WT. The exclusive OR operator XOR is used to perform an exclusive OR operation on the sign part IN_S of the input data IN and the sign part WT_S of the weight data WT to obtain the sign product data ML_S.

According to the above description, the floating-point memory in-body computing device 100 is able to support the FP16 computing architecture. In other embodiments, the floating-point memory in-body computing device 100 also supports the INT8 computing architecture. Please refer to Figure 13, which illustrates an example of the multiplication operation of integer data in an embodiment of the present disclosure. The sign part S and the mantissa part M of the floating-point data constitute the integer part INT of the integer data. The exponent part E is not used. The integer part INT occupies 8 bits. The input data IN can represent a range of 0 to 255. The weight data WT can represent a range of -128 to 127. After the input data IN and the weight data WT are multiplied, the product data ML can be obtained.

Please refer to Figure 14, which illustrates the data flow of integer operations performed by the floating-point memory in-body operation device 100 according to an embodiment of the present disclosure. The data flow of integer operations performed by the floating-point memory in-body operation device 100 includes multiplication MLP and accumulation AC. The multiplication MLP is completed by the mantissa operation circuit LCCM and the shift and addition circuit SHTA of the mantissa storage operation module MT. The accumulation AC of the multiplication data ML is completed by the summing circuit MSA of the mantissa storage operation module MT. In this way, the floating-point memory in-body operation device 100 can also support the INT8 operation architecture at the same time.

The above disclosure provides different features for implementing some embodiments or examples of the present disclosure. The above description of specific examples of components and configurations (e.g., the values or names mentioned) is to simplify/illustrate some embodiments of the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. In addition, some embodiments of the present disclosure may repeat reference symbols and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and/or configurations discussed.

According to the above embodiment, in the floating point number in-memory operation device 100, storage units (such as weight exponent storage circuit SRE, weight sign storage circuit SRS, weight mantissa storage circuit SRM) and operation units (such as exponent operation circuit LCCE, comparison circuit COMP, bit shift circuit SHT, sign operation circuit LCCS, mantissa operation circuit LCCM, shift and addition circuit SHTA, summing circuit MSA) are integrated. Therefore, when performing floating point operation, frequent input and output of data can be avoided, so it has the advantage of fast operation, and can reduce power consumption and improve energy efficiency.

The exponent storage operation module EP and/or the mantissa storage operation module MT proposed in this disclosure are all within the scope of protection of this disclosure. If the exponent storage operation module EP of this disclosure is implemented alone, the rest of the circuit design is combined with other methods, and it still does not deviate from the spirit and scope of this disclosure. If the mantissa storage operation module MT of this disclosure is implemented alone, the rest of the circuit design is combined with other methods, and it still does not deviate from the spirit and scope of this disclosure.

In summary, although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. A person with ordinary knowledge in the technical field to which the present disclosure belongs can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope defined by the attached patent application.

100: floating point memory internal operation device AC: accumulation AD: adder AL: alignment AWIN, BWIN: judgment result A＜0＞, A＜1＞, A＜2＞, B＜0＞, B＜1＞, B＜2＞: front bit BL0, BLB0, BL7, BLB7: bit line COMP: comparison circuit CP: comparator CP1: first judgment circuit CP2: second judgment circuit CP3: third judgment circuit C＜0＞, C＜1＞, C＜2＞: exclusive or result E: index part EN: enable signal EP: index storage operation module GBL＜0＞, GBL＜7＞, GBLB＜0＞, GBLB＜7＞: global bit line GD: ground terminal IN: input data INT: integer part IN[0], IN[6], IN[7]: Input terminal IN_E: Exponent of input data IN_M: Mantissa of input data IN_M': Mantissa after shift IN_S: Sign of input data LBL<0>, LBL<7>, LBLB<0>, LBL<7>: Local bit line LCCE: Exponent calculation circuit LCCM: Mantissa calculation circuit LCCS: Sign calculation circuit LSB[0]: Least significant bit M: Mantissa : Numerical MAC: Input and weight product sum data ML: Product data MLP: Product ML_E: Exponential product data ML_E_max: Maximum exponential product data ML_M: Mantissa product data ML_M_im: Mantissa product intermediate data ML_S: Significant product data MSA: Sum circuit MSB[7]: Most significant bit MT: Mantissa storage operation module OF: Displacement data OUT0[0], OUT0[6], OUT0[7], OUT7[0], OUT7[6], OUT7[7]: output PWM: point-by-point multiplier S: sign part SAP: switching and pre-charging circuit SB: subtractor SH: shifter SHT: bit shift circuit SHTA: shift and addition circuit SR: static random access memory SRE: weight exponent storage circuit SRM: weight mantissa storage circuit SRS: weight sign storage circuit TR, TRB: transistor WT: weight data WT_E: exponent part of weight data WT_M: mantissa part of weight data WT_S: sign part of weight data XOR: exclusive OR operator

FIG. 1 illustrates an example of a multiplication operation of floating-point data according to an embodiment of the present disclosure. FIG. 2 illustrates a storage method of floating-point data according to an embodiment of the present disclosure. FIG. 3 illustrates an architecture diagram of a floating-point computing in memory device according to an embodiment of the present disclosure. FIG. 4 illustrates a data flow of a floating-point computing in memory device according to an embodiment of the present disclosure for performing floating-point computing. FIG. 5 illustrates a schematic diagram of a weight index storage circuit and an index computing circuit according to an embodiment of the present disclosure. FIG. 6 illustrates a schematic diagram of a comparison circuit according to an embodiment of the present disclosure. FIG. 7 illustrates a schematic diagram of a comparator according to an embodiment of the present disclosure. FIG. 8 is a schematic diagram of a digit shift circuit according to an embodiment of the present disclosure. FIG. 9 is a schematic diagram of a mantissa operation circuit according to an embodiment of the present disclosure. FIG. 10 is a schematic diagram of a point-by-point multiplier according to an embodiment of the present disclosure. FIG. 11 illustrates an example of the operation of a shift and addition circuit according to an embodiment of the present disclosure. FIG. 12 is a schematic diagram of a positive and negative sign operation circuit according to an embodiment of the present disclosure. FIG. 13 illustrates an example of the multiplication operation of integer data according to an embodiment of the present disclosure. FIG. 14 illustrates a data flow of integer operation performed by an operation device in a floating-point memory according to an embodiment of the present disclosure.

100: Floating point memory operation device

COMP: Comparison circuit

EP: Exponential storage operation module

LCCE: Exponential calculation circuit

LCCM: Mantissa calculation circuit

LCCS: positive and negative operation circuit

MSA: summing circuit

MT: Mantissa storage operation module

SHT: Bit shift circuit

SHTA: Shift and Addition Circuit

SRE: Weight index storage circuit

SRM: weight mantissa storage circuit

SRS: weight positive and negative sign storage circuit

Claims (12)

A floating-point computing in memory device, comprising: an exponent storage operation module, comprising: a plurality of weight exponent storage circuits, for storing the exponent parts of a plurality of weight data; a plurality of exponent operation circuits, for performing an addition operation on the exponent parts of a plurality of input data and the exponent parts of the weight data to obtain a plurality of exponential product data; and a comparison circuit, for comparing the exponential product data to obtain a maximum exponential product data; and a mantissa storage operation module, comprising: A one-digit shift circuit, used to shift the mantissa of the input data according to the maximum exponential product data; A plurality of weight mantissa storage circuits, used to store the mantissa of the weight data; A plurality of mantissa operation circuits, used to perform a multiplication operation on the mantissa of the input data and the mantissa of the weight data to obtain a plurality of mantissa product intermediate data; A shift and addition circuit, used to shift the mantissa product intermediate data and then add them up to obtain a plurality of mantissa product data; A plurality of weight positive and negative sign storage circuits, used to store the positive and negative sign of the weight data; A plurality of positive and negative sign operation circuits for performing an exclusive-OR operation on the positive and negative sign parts of the input data and the positive and negative sign parts of the weight data to obtain a plurality of positive and negative sign product data; and a summing circuit for integrating the positive and negative sign product data, the maximum exponent product data and the mantissa product data to obtain an input and weight product sum data. A floating point in-memory arithmetic device as described in claim 1, wherein each weight index storage circuit includes a plurality of static random-access memories (SRAMs). A floating point memory in-memory arithmetic device as described in claim 2, wherein each of the static random access memories includes six transistors. The floating point memory in-body operation device as described in claim 1, wherein each of the exponential operation circuits comprises: a plurality of switching and precharging circuits connected to the weight exponent storage circuits and used to receive the exponential part of the weight data; and an adder connected to the switching and precharging circuits and used to receive the exponential part of the weight data to perform the addition operation on the exponential part of the input data and the exponential part of the weight data to obtain the exponential product data. The floating-point in-memory operation device as described in claim 1, wherein the comparison circuit is connected to the exponential operation circuits, and the comparison circuit includes: A plurality of comparators for comparing two exponential product data of the exponential product data. The floating point in-memory operation device as described in claim 5, wherein each comparator comprises: a first judgment circuit for comparing the preceding bits of the exponential product data; a second judgment circuit connected to the first judgment circuit and used to compare the middle bits of the exponential product data; and a third judgment circuit connected to the second judgment circuit and used to compare the following bits of the exponential product data. The floating-point memory intra-operation device as described in claim 1, wherein the bit shift circuit includes: a plurality of subtractors connected to the comparison circuit and used to perform subtraction operations on the maximum exponential product data and the exponential product data to obtain a plurality of displacement data; and a plurality of shifters connected to the subtractors and used to shift the mantissa of the input data according to the displacement data. A floating point in-memory arithmetic device as described in claim 1, wherein each weight mantissa storage circuit includes a plurality of static random-access memories (SRAMs). The floating-point memory in-body operation device as described in claim 1, wherein each of the mantissa operation circuits comprises: a plurality of switching and precharging circuits connected to the weight mantissa storage circuits and used to receive the mantissa part of the weight data; and a point-wise multiplier connected to the switching and precharging circuits and used to receive the mantissa part of the weight data to perform the multiplication operation on the mantissa part of the input data and the mantissa part of the weight data to obtain the mantissa product data. A floating point in-memory arithmetic device as described in claim 1, wherein each of the weight sign storage circuits includes a plurality of static random-access memories (SRAMs). A floating point in-memory arithmetic device as described in claim 10, wherein each of the static random access memories includes six transistors. The floating point number in-memory operation device as described in claim 1, wherein each of the positive and negative sign operation circuits comprises: a switching and precharging circuit connected to the weight positive and negative sign storage circuits and used to receive the positive and negative sign parts of the weight data; and a mutual exclusion or operator connected to the switching and precharging circuit and used to receive the positive and negative sign parts of the weight data to perform the mutual exclusion or operation on the positive and negative sign parts of the input data and the positive and negative sign parts of the weight data to obtain the positive and negative sign product data.

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