TWI878995B - Wiring substrate and installation structure using the same - Google Patents

Abstract

A wiring substrate of the present disclosure includes: a first insulating layer having a first surface; a second insulating layer located on the first surface and having a via hole; and a via conductor portion penetrating the second insulating layer. The via conductor portion has: a via land conductor located on the first surface; and a via hole conductor connected to the via land conductor and located in the via hole. The via land conductor at least has: a first layer including a connection portion connected to the via hole conductor; and a second layer connected to the first layer at the first insulating layer side. The via conductor portion has a continuous crystal which extending across the first layer and the via hole conductor via the connection portion. The first crystal grain size of the first layer is different from the second crystal grain size of the second layer.

Description

Wiring board and mounting structure using the wiring board

The present invention relates to a wiring substrate and a mounting structure using the wiring substrate.

In a wiring board, in order to electrically connect the conductor layers located on the upper and lower surfaces of the insulating layer, as shown in Patent Document 1, a conductor (via hole conductor) is filled in the connecting portion (via hole) formed in the insulating layer. The via hole conductor is usually connected to the via land at the bottom of the via portion. In the via hole conductor, stress is easily concentrated on the connecting portion between the bottom of the via portion and the via land. Therefore, when exposed to high temperature conditions, there will be a situation of breaking.

(Prior technical literature)

(Patent Literature)

Patent document 1: Japanese Patent Publication No. 2008-193025

The subject of the present invention is to provide a wiring substrate with good connection strength between the bottom of the connecting part and the connecting plate, and can reduce the breakage caused by the extension of cracks in the longitudinal and transverse directions in the connecting plate.

The wiring substrate disclosed in the present invention comprises: a first insulating layer having a first surface; a second insulating layer located on the first surface and having a through hole; and a connecting conductor portion penetrating the second insulating layer. The connecting conductor portion comprises: a connecting disk conductor located on the first surface; and a through hole conductor connected to the connecting disk conductor and located in the through hole. The connecting disk conductor comprises at least: a first layer including a connecting portion connected to the through hole conductor; and a second layer connected to the first insulating layer side of the first layer. The connecting conductor portion comprises a continuous crystal that crosses the first layer and the through hole conductor via the connecting portion. The first crystal grain size of the first layer is different from the second crystal grain size of the second layer.

Furthermore, the mounting structure disclosed herein includes: the above-mentioned wiring substrate; and electronic components located in the mounting area of the wiring substrate.

The wiring board disclosed in this disclosure has the structure described in the column of means for solving the problem, so that the connection strength between the bottom of the connecting part and the connecting plate is good, and the broken wire caused by the extension of cracks in the longitudinal and transverse directions in the connecting plate can be reduced.

1: Wiring board

2: Insulation layer

3: Conductor layer

3’: Metal foil

3a: Connecting the coil conductor

3a1: First level

3a1’: Connection part

3a2: Second layer

3a3: The third layer

3b: Through hole conductor

4: Solder resist

5: Solder

6: Resistants

21: First insulating layer

21a: Through hole conductor

21a’: Through hole

22: Second insulation layer

31: Connecting conductor part

211: First page

S: Components

X: Area

FIG1 is an illustrative diagram of a wiring substrate for illustrating one embodiment of the present disclosure.

Figure 2 is an electron microscope photograph showing an example of the area X shown in Figure 1.

FIG. 3 is an explanatory diagram for explaining an example of a method for forming a connecting conductor portion in a wiring substrate of an embodiment of the present disclosure.

FIG. 4 is an explanatory diagram for explaining an example of a method for forming a connecting conductor portion in a wiring substrate of an embodiment of the present disclosure.

FIG. 5 is an explanatory diagram for explaining an example of a method for forming a connecting conductor portion in a wiring substrate of an embodiment of the present disclosure.

According to Figures 1 and 2, a wiring substrate of one embodiment of the present disclosure is described. Figure 1 is an explanatory diagram for describing a wiring substrate 1 of one embodiment of the present disclosure. As shown in Figure 1, a wiring substrate 1 of one embodiment includes an insulating layer 2, a conductive layer 3, and a solder resist 4.

The insulating layer 2 includes a first insulating layer 21 and a second insulating layer 22. The first insulating layer 21 has upper and lower surfaces (first surface 211), and is not particularly limited as long as it is a material with insulating properties. As for the insulating material, for example, epoxy resin, dimaleimide-triazine resin, polyimide resin, polyphenylene ether resin and the like can be cited. These resins can also be mixed and used in combination of two or more. In the wiring substrate 1, the first insulating layer 21 is equivalent to the core insulating layer. The thickness of the first insulating layer 21 is not particularly limited. When the first insulating layer 21 is equivalent to the core insulating layer, it is, for example, not less than 100 μm and not more than 3000 μm.

The first insulating layer 21 may also include a reinforcing material. As for the reinforcing material, for example, insulating fabrics such as glass fiber, glass non-woven fabric, polyaramid non-woven fabric, polyaramid fiber, polyester fiber, etc. may be listed. Two or more reinforcing materials may also be used in combination. Furthermore, inorganic insulating fillers such as silicon dioxide, barium sulfate, talc, clay, glass, calcium carbonate, titanium oxide, etc. may also be dispersed in the first insulating layer 21.

In the first insulating layer 21, a through-hole conductor 21a is arranged to electrically connect the upper and lower surfaces of the first insulating layer 21. The through-hole conductor 21a is located in a through-hole that penetrates from the upper surface of the first insulating layer 21 to the lower surface. The through-hole conductor 21a is formed by metal plating such as copper plating. The through-hole conductor 21a is connected to the conductor layer 3 formed on both sides of the first insulating layer 21. The through-hole conductor 21a may be located only on the inner wall surface of the through-hole 21a', or may be filled in the through-hole 21a'.

In the first surface 211 of the first insulating layer 21, a build-up layer is arranged in which the conductive layer 3 and the insulating layer 2 are alternately stacked. In the build-up layer, at least two conductive layers 3 and one insulating layer 2 are stacked. The insulating layer 2 in the insulating layer 2 that contacts the first surface 211 of the first insulating layer 21 is equivalent to the second insulating layer 22.

The conductor layer 3 is not limited as long as it is a conductor such as metal. Specifically, the conductor layer 3 is formed by metal foil such as copper foil, metal plating such as copper plating, etc. The thickness of the conductor layer 3 is not particularly limited, for example, it is greater than 5μm and less than 20μm.

The insulating layer 2 constituting the build-up layer is the same as the first insulating layer 21, and there is no particular limitation as long as it is a material with insulating properties. As mentioned above, resins such as epoxy resins, dimaleimide-triazine resins, polyimide resins, and polyphenylene ether resins can be listed. These resins can also be mixed and used in combination of two or more. The insulating layer 2 constituting the build-up layer can be the same resin or different resins. The insulating layer 2 constituting the build-up layer and the first insulating layer 21 can be the same resin or different resins. The thickness of the insulating layer 2 constituting the build-up layer is not particularly limited, and may be, for example, greater than 10 μm and less than 50 μm. The insulating layer 2 constituting the build-up layer may have the same thickness or different thicknesses.

The insulating layer 2 constituting the build-up layer may also include a reinforcing material. As for the reinforcing material, for example, insulating fabrics such as glass fiber, glass non-woven fabric, polyaramid non-woven fabric, polyaramid fiber, polyester fiber, etc. may be listed. Two or more reinforcing materials may also be used in combination. Furthermore, in the insulating layer 2 constituting the build-up layer, inorganic insulating fillers such as silicon dioxide, barium sulfate, talc, clay, glass, calcium carbonate, titanium oxide, etc. may also be dispersed.

As shown in FIG1 , a solder resist 4 may also be arranged on the surface of the build-up layer. The solder resist 4 is formed of a resin, and examples of the resin include acrylic modified epoxy resins, etc. In the solder resist 4, an opening is provided to electrically connect the conductive layer 3 to the electrodes of the component via the solder 5. As for the components, examples include semiconductor integrated circuit components, optoelectronic components, etc.

A connecting conductor portion 31 is formed on the second insulating layer 22 to electrically connect the upper and lower surfaces of the second insulating layer 22. The connecting conductor portion 31 is located in a connecting hole formed in a manner penetrating the second insulating layer 22. That is, the connecting conductor portion 31 is configured in a manner penetrating the second insulating layer 22.

The connecting conductor part 31 is shown in FIG2, and includes a connecting plate conductor 3a and a connecting hole conductor 3b. FIG2 is an electron microscope photograph showing an example of the area X shown in FIG1. In the wiring substrate 1, the connecting plate conductor 3a is located on the first surface 211 of the first insulating layer 21. The connecting hole conductor 3b is filled in the connecting hole formed in the second insulating layer 22, and the bottom (the bottom surface close to the side of the first surface 211) is connected to the connecting plate conductor 3a. The connecting plate conductor 3a and the connecting hole conductor 3b are part of the conductive layer 3 and are formed of a metal such as copper.

In the wiring substrate 1, the connecting pad conductor 3a includes a first layer 3a1, a second layer 3a2, and a third layer 3a3. The first layer 3a1 includes a connecting portion 3a1' connected to the connecting hole conductor 3b. The first layer 3a1 and the connecting hole conductor 3b are connected by continuous crystals spanned by the connecting portion 3a1'. The second layer 3a2 is located closer to the first insulating layer 21 side than the first layer 3a1, and is connected to the first layer 3a1. The third layer 3a3 is located closer to the first insulating layer 21 side than the second layer 3a2, and is connected to the second layer 3a2. Continuous crystallization is achieved by observing the cross-section of the interconnecting disk conductor 3a and the interconnecting hole conductor 3b using a scanning electron microscope. It is sufficient to confirm that at least one crystal grain is arranged across the first layer 3a1 and the interconnecting hole conductor 3b.

In the wiring substrate 1, the crystal grain size of the crystals constituting the first layer 3a1 (hereinafter referred to as "the first crystal grain size") is different from the crystal grain size of the crystals constituting the second layer 3a2 (hereinafter referred to as "the second crystal grain size"). That is, except that the first layer 3a1 and the via conductor 3b are connected by continuous crystallization at the contact surface (connection portion 3a1') between the first layer 3a1 and the via conductor 3b, the first crystal grain size is different from the second crystal grain size. At the contact surface (connection portion 3a1') between the first layer 3a1 and the via conductor 3b, the first layer 3a1 and the via conductor 3b are connected by continuous crystallization. Therefore, in the connection portion 3a1' between the first layer 3a1 and the through-hole conductor 3b where thermal stress is easily concentrated, the crack extension along the direction (lateral direction) of the upper surface of the through-hole conductor 3a is reduced. Furthermore, since the first crystal grain size is different from the second crystal grain size, the interface of the crystal grains of the first layer 3a1 and the interface of the crystal grains of the second layer 3a2 become difficult to coincide. Therefore, the crack extension along the thickness direction (longitudinal direction) of the through-hole conductor 3a is reduced.

In the case where the second crystal grain size is larger than the first crystal grain size, for example, when cracks are generated in the thickness direction along the interface of the crystal grains of the first layer 3a1, the extension of the cracks can be reduced in the area outside the interface of the crystal grains of the second layer 3a2.

In the case where the interconnecting coil conductor 3a includes the first layer 3a1, the second layer 3a2, and the third layer 3a3, the first crystal grain size and the crystal grain size of the crystal constituting the third layer 3a3 (hereinafter referred to as the "third crystal grain size") may also be smaller than the second crystal grain size. That is, the second crystal grain size is larger than the first crystal grain size and the third crystal grain size. Compared with the interconnecting coil conductor 3a, by making the crystal grain size of the first layer 3a1 and the third layer 3a3 in contact with the insulating resin layer having a large thermal expansion coefficient smaller, the number of crystal grain boundaries having relatively softness increases. Therefore, the thermal stress generated in the first layer 3a1 and the third layer 3a3 becomes easier to be absorbed. Furthermore, even when cracks occur in the thickness direction of the first layer 3a1 and the third layer 3a3, since the second crystal grain size is larger than the first crystal grain size and the third crystal grain size, the extension of the cracks can be reduced in the area outside the interface of the crystal grains of the second layer 3a2.

The first crystal grain size can be, for example, 1 μm to 2.8 μm, or 1.5 μm to 2.1 μm. The second crystal grain size can be, for example, 2.9 μm to 9 μm, or 3.1 μm to 3.6 μm. The third crystal grain size can be, for example, 1 μm to 2.1 μm, or 1.4 μm to 1.8 μm. The crystal grain size is determined in accordance with JIS H 0501, for example. Specifically, the number of crystal grains captured by a test line with a known length is measured. The measurement is performed at any five locations. Then, the arithmetic mean is calculated for the number of crystal grains obtained at the five locations. Then, the average line segment length (i.e., crystal grain size) of each crystal grain of the test line is determined.

The thickness of the first layer 3a1, the second layer 3a2, and the third layer 3a3 is not limited. For example, the thickness of the first layer 3a1 may be greater than the thickness of the second layer 3a2 and the thickness of the third layer 3a3. The first layer 3a1 may have a thickness of, for example, 10 μm to 20 μm. The second layer 3a2 may have a thickness of, for example, 5 μm to 15 μm. The third layer 3a3 may have a thickness of, for example, 2 μm to 10 μm. The thickness of the first layer 3a1 may be defined, for example, as the distance between a virtual line including many flat areas at the root of the uneven surface of the first layer 3a1 on the second insulating layer 22 side and the interface between the first layer 3a1 and the second layer 3a2. The thickness of the second layer 3a2 can be defined as, for example, the distance between the interface between the first layer 3a1 and the second layer 3a2, and the interface between the second layer 3a2 and the third layer 3a3. The thickness of the third layer 3a3 can be defined as, for example, the distance between a virtual line including many flat areas at the root of the uneven surface of the third layer 3a3 on the first insulating layer 21 side, and the interface between the second layer 3a2 and the third layer 3a3.

For example, when thermal stress is generated in the connection portion 3a1' between the first layer 3a1 and the through-hole conductor 3b where thermal stress is easily concentrated, when the first crystal grain size of the first layer 3a1 is relatively small, even if thermal stress is generated and the crystal expands, the direction of expansion becomes easier to disperse. When the thickness of the first layer 3a1 becomes larger than the thickness of the second layer 3a2 and the thickness of the third layer 3a3, the direction of expansion becomes easier to disperse. As a result, the occurrence of cracks or peeling can be further reduced.

The arithmetic mean roughness of the upper and lower surfaces of the interconnecting coil conductor 3a, i.e., the surface on the second insulating layer 22 side of the first layer 3a1 and the surface on the first insulating layer 21 side of the third layer 3a3, is not limited. The surface on the second insulating layer 22 side of the first layer 3a1 refers to the surface in contact with the second insulating layer 22. By setting the arithmetic mean roughness of any surface relatively large, the close contact between the insulating layer 2 and the interconnecting coil conductor 3a can be improved. On the other hand, by setting the arithmetic mean roughness of any surface relatively small, it is less likely to cause a decrease in electrical characteristics.

For example, the arithmetic average roughness of the surface on the second insulating layer 22 side of the first layer 3a1 may be smaller than the arithmetic average roughness of the surface on the first insulating layer 21 side of the third layer 3a3. In this case, the adhesion between the first insulating layer 21 and the connecting plate conductor 3a can be improved, and the electrical characteristics as a conductor can also be maintained in a good state. The arithmetic average roughness of the surface on the second insulating layer 22 side of the first layer 3a1 may also be, for example, 50nm or more and 500nm or less. The arithmetic average roughness of the surface on the first insulating layer 21 side of the third layer 3a3 may also be, for example, 200nm or more and 1000nm or less.

Next, an embodiment of a method for forming a connecting conductor portion 31 is described based on FIGS. 3 to 5. FIGS. 3 to 5 are explanatory diagrams for describing an example of a method for forming a connecting conductor portion 31 in a wiring substrate 1 of an embodiment of the present disclosure.

First, as shown in FIG3A, a metal foil 3' such as copper foil is attached to the upper and lower surfaces (first surface 211) of the first insulating layer 21. For example, a double-sided copper laminate or other double-sided metal laminate can be prepared. The metal foil 3' is equivalent to the third layer 3a3 of the connecting plate conductor 3a in a wiring substrate 1 of one embodiment.

Next, as shown in FIG. 3B , through holes 21a’ are formed by penetrating the upper and lower surfaces of the first insulating layer 21 to which the metal foil 3’ is attached. The size and number of through holes 21a’ are appropriately set according to the size of the final wiring substrate 1. The through holes 21a’ are formed using, for example, a drill bit. In order to remove resin residues, degumming treatment is performed as needed.

Next, as shown in FIG3C , a seed layer is formed on the surface of the metal foil 3' and the inner wall surface of the formed through hole 21a'. By forming the seed layer, metal can be efficiently deposited by electrolytic plating in the next step. The seed layer is formed of a metal such as copper.

Next, as shown in FIG3D, a metal such as copper is deposited on the surface of the seed layer by electrolytic plating, and a through-hole conductor 21a is formed on the inner wall surface of the through-hole 21a'. A layer of a conductor identical to the through-hole conductor 21a is also formed on the surface of the metal foil 3' located on the upper and lower surfaces of the first insulating layer 21. The layer of a conductor identical to the through-hole conductor 21a is equivalent to the second layer 3a2 of the connecting pad conductor 3a in a wiring substrate 1 of one embodiment.

In a wiring substrate 1 of one embodiment, the crystal grain sizes of the layers constituting the interconnecting conductor 3a are different. Therefore, the crystal grain size of the metal foil 3' and the crystal grain size of the metal precipitated by electrolytic plating must be different. During electrolytic plating, the crystal grain size of the metal to be precipitated can be adjusted by adjusting, for example, the current density or the amount of additive. Specifically, the crystal grain size of the metal to be precipitated can be increased by increasing the current density or reducing the amount of the additive as a brightener. Conversely, the crystal grain size of the metal to be precipitated can be decreased by decreasing the current density or increasing the amount of the brightener. The brightener is adsorbed on the growth point of the crystal nucleus to inhibit the growth of the crystal. In this way, new crystal nuclei are generated on the coating surface, and the crystals are refined to form a dense coating film. That is, when the gloss agent is increased, the crystal grain size will become smaller, and when the gloss agent is reduced, the crystal grain size will become larger.

Next, as shown in FIG3E , resin is filled in the through hole 21a’. The resin filled in the through hole 21a’ is not limited, and examples thereof include epoxy resin, dimaleimide-triazine resin, polyimide resin, polyphenylene ether resin, and the like. After the resin is filled in the through hole 21a’, as shown in FIG4A , the resin is polished in such a way that the resin filled in the through hole 21a’ and the conductor layer of the same through hole conductor 21a formed on the surface of the metal foil 3’ are roughly aligned.

Next, as shown in FIG. 4B , copper or other metals are deposited on the roughly flat surface in FIG. 4A by electroless plating and electrolytic plating. The layer formed by the plating process is equivalent to the first layer 3a1 of the via conductor 3a in a wiring substrate 1 of an embodiment. Therefore, it is necessary to integrate the grain size with the via conductor 3b formed later. By integrating the grain size with the via conductor 3b, a continuous crystal can be formed that spans the first layer 3a1 and the via conductor 3b through the connecting portion 3a1'. The method for adjusting the grain size in electrolytic plating is as described above, and detailed description is omitted.

Next, as shown in FIG4C, a resist 6 is formed at the position where the interconnecting conductor 3a is to be formed. After the resist 6 is formed, an etching process is performed to remove the metal foil 3' and the plated metal in the portion where the resist 6 is not formed, as shown in FIG4D. Then, as shown in FIG5A, the resist 6 is removed to form the interconnecting conductor 3a including the first layer 3a1, the second layer 3a2 and the third layer 3a3.

Next, as shown in FIG. 5B , a second insulating layer 22 is formed on the first surface 211 of the first insulating layer 21 in a manner covering the connecting plate conductor 3a. The material for forming the second insulating layer 22 is as described above, and detailed description is omitted. After the second insulating layer 22 is formed, as shown in FIG. 5C , a connecting hole with the connecting plate conductor 3a as the bottom surface is formed in the second insulating layer 22. The connecting hole is formed by, for example, laser. The size and number of the connecting holes are appropriately set according to the size of the final wiring substrate 1, etc.

Next, as shown in FIG. 5D , copper or other metal is deposited in the formed through-hole by electroless plating and electrolytic plating, and the metal is filled in the through-hole to form the through-hole conductor 3b. As described above, the crystal grain size of the through-hole conductor 3b only needs to be integrated with the crystal grain size of the first layer 3a1 of the through-plate conductor 3a. The through-conductor portion 31 is formed in the above manner.

The mounting structure disclosed in the present invention includes: a wiring substrate 1 of an implementation form; and a component S located on the surface of the wiring substrate 1. The conductive layer 3 in the opening of the solder resist 4 and the electrode of the component S are connected via the solder 5. As for the component S, as mentioned above, semiconductor integrated circuit components, optoelectronic components, etc. can be listed. Components can also be arranged on both sides of the wiring substrate 1, and the component S can be arranged on one surface and a motherboard, etc. can be arranged on the other surface.

The wiring substrate disclosed in the present invention is not limited to the wiring substrate 1 of one of the above-mentioned embodiments. In the wiring substrate 1 of one embodiment, the connecting plate conductor 3a has a three-layer structure of a first layer 3a1, a second layer 3a2 and a third layer 3a3. However, in the wiring substrate disclosed in the present invention, the connecting plate conductor does not necessarily need to have a three-layer structure, and may also have a two-layer structure of a first layer and a second layer.

In the case where the interconnecting conductor has a two-layer structure, the arithmetic average roughness of the surface on the second insulating layer side of the first layer can also be smaller than the arithmetic average roughness of the surface on the first insulating layer side of the second layer. In this case, the adhesion between the first insulating layer and the interconnecting conductor can be improved, and the electrical properties as a conductor can also be maintained in a good state.

In a wiring substrate 1 of an embodiment, the core insulating layer is used as the first insulating layer 21, and the insulating layer 2 in contact with the first surface 211 of the core insulating layer among the insulating layers 2 constituting the build-up layer is used as the second insulating layer 22. Cracks or peeling are most likely to occur in the connecting conductor portion 31 located in the insulating layer 2, and the insulating layer 2 constitutes the build-up layer in contact with the core insulating layer. Therefore, in a wiring substrate 1 of an embodiment, in the insulating layer 2 constituting the build-up layer in contact with the core insulating layer, at least the above-mentioned connecting conductor portion 31 is configured. That is, in the other insulating layer 2 constituting the build-up layer, the known connecting pad and connecting hole conductors may be arranged, and the above-mentioned connecting conductor part 31 may also be arranged.

When the above-mentioned connecting conductor part 31 is arranged in the other insulating layer 2 constituting the build-up layer, or when there is no core insulating layer in the coreless substrate, among the insulating layers constituting the build-up layer, a certain insulating layer is the "first insulating layer", and the insulating layer located on the first surface of the first insulating layer can be the "second insulating layer".

The above is an explanation of the implementation form of the present disclosure. However, the invention of the present disclosure is not limited to the above-mentioned implementation form, and various changes and improvements can be made within the scope of the present disclosure shown in the following (1) and (6).

(1) The wiring substrate disclosed in the present invention comprises: a first insulating layer having a first surface; a second insulating layer located on the first surface and having a through hole; and a connecting conductor portion penetrating the second insulating layer. The connecting conductor portion comprises: a connecting disk conductor located on the first surface; and a through hole conductor connected to the connecting disk conductor and located in the through hole. The connecting disk conductor comprises at least: a first layer including a connecting portion connected to the through hole conductor; and a second layer connected to the first insulating layer side of the first layer. The connecting conductor portion comprises a continuous crystal that crosses the first layer and the through hole conductor via the connecting portion. The first crystal grain size of the first layer is different from the second crystal grain size of the second layer.

Regarding the implementation forms of this disclosure, the following implementation forms (2) to (5) are further disclosed.

(2) In the wiring substrate described in (1) above, the second crystal grain size is larger than the first crystal grain size.

(3) In the wiring substrate described in (1) or (2) above, the connecting winding conductor further includes a third layer connected to the first insulating layer side of the second layer, and the first crystal grain size and the third crystal grain size of the third layer are smaller than the second crystal grain size.

(4) In the wiring substrate described in (3) above, the arithmetic mean roughness of the surface of the first layer on the second insulating layer side is smaller than the arithmetic mean roughness of the surface of the third layer on the first insulating layer side.

(5) In the wiring substrate described in (3) or (4) above, the thickness of the first layer is greater than the thickness of the second layer and the thickness of the third layer.

(6) The mounting structure disclosed herein includes: a wiring substrate as described in any one of (1) to (5) above; and electronic components located in the mounting area of the wiring substrate.

3a: Connecting the coil conductor

3a1: First level

3a1’: Connection part

3a2: Second layer

3a3: The third layer

3b: Through hole conductor

21: First insulating layer

22: Second insulation layer

31: Connecting conductor part

Claims (6)

A wiring substrate comprises: a first insulating layer having a first surface; a second insulating layer located on the first surface and having a connecting hole; and a connecting conductor portion penetrating the second insulating layer; the connecting conductor portion comprising: a connecting plate conductor located on the first surface; and a connecting hole conductor connected to the connecting plate conductor and located in the connecting hole; the connecting plate conductor at least comprising: a first layer including a connecting portion connected to the connecting hole conductor; and a second layer connected to the first insulating layer side of the first layer; the first layer includes an electroless coating and an electrolytic coating located on the electroless coating; the second layer includes a seed layer and an electrolytic coating located on the seed layer; the connecting conductor portion has continuous crystals across the first layer and the connecting hole conductor via the connecting portion; the first crystal grain size of the electrolytic coating in the first layer is different from the second crystal grain size of the electrolytic coating in the second layer. The wiring substrate as described in claim 1, wherein the second crystal grain size is larger than the first crystal grain size. The wiring substrate as described in claim 1 or 2, wherein the connecting winding conductor further comprises a third layer connected to the first insulating layer side of the second layer; the first crystal grain size and the third crystal grain size of the third layer are smaller than the second crystal grain size. The wiring substrate as described in claim 3, wherein the arithmetic average roughness of the surface of the first layer on the side of the second insulating layer is smaller than the arithmetic average roughness of the surface of the third layer on the side of the first insulating layer. The wiring substrate as described in claim 3, wherein the thickness of the first layer is greater than the thickness of the second layer and the thickness of the third layer. A mounting structure includes: a wiring substrate as described in any one of claims 1 to 5; and electronic components located in the mounting area of the wiring substrate.