TWI877931B - Preparation method of solar cell - Google Patents

Abstract

A preparation method of a solar cell includes: providing a semiconductor substrate including a front surface and a back surface opposite the front surface; forming an oxide layer on the front surface of the semiconductor substrate; forming a doped silicon layer on the oxide layer; forming a passivation layer on the doped silicon layer; performing a laser annealing/patterning process to obtain a passivation pattern and a doped silicon pattern; and performing a post-cell process. The laser annealing/patterning process includes irradiating the front surface of the semiconductor substrate with a pulsed laser having a pulse width of greater than 0 ps and less than or equal to 10 ps. ​

Description

Method for preparing solar cell

The present invention relates to a method for preparing a semiconductor device, and in particular to a method for preparing a solar cell.

Sunlight is a permanent and environmentally friendly energy source. A solar cell is a photoelectric device that can directly convert sunlight into electrical energy.

Tunnel Oxide Passivated Contact (TOPCon) solar cells are a type of solar cell based on the selective carrier principle technology and are currently one of the most competitive commercial high-efficiency solar cells. Tunnel Oxide Passivated Contact solar cells can effectively reduce the recombination rate of carriers on the back of the battery, further improving the conversion efficiency of solar cells, and have the advantages of good stability in high temperature environments.

The present disclosure provides some embodiments, which are related to a method for preparing a solar cell, including: providing a semiconductor substrate including a front surface and a back surface opposite to the front surface; forming an oxide layer on the front surface of the semiconductor substrate; forming a doped silicon layer on the oxide layer; forming a passivation layer on the doped silicon layer; performing a laser annealing/patterning process to obtain a passivation pattern and a doped silicon pattern; and performing a battery post-process. The laser annealing/patterning process includes irradiating the front surface of the semiconductor substrate with a pulsed laser having a pulse width greater than 0 ps and less than or equal to 10 ps.

In order to make the features and advantages of the embodiments of the present disclosure more clearly understood, the present disclosure is described in detail below with reference to the accompanying drawings.

The following is a detailed description of some embodiments of the present disclosure. It should be understood that the following description provides many different embodiments or examples for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only for the purpose of simply and clearly describing some embodiments of the present disclosure. Of course, these are only used for exemplification and are not limitations of the present disclosure. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing some embodiments of the present disclosure, and do not represent any correlation between the different embodiments and/or structures discussed.

Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The quantities given here are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied.

Here, the term "less than or equal to" means including a given value and values below the given value, and the term "greater than or equal to" means including a given value and values above the given value. Conversely, the term "less than" means including values less than a given value but not including the given value, and the term "greater than" means including values exceeding a given value but not including the given value. For example, "greater than or equal to a" means including values a and above, and "greater than a" means including values exceeding a but not including a.

Here, the term "any combination of the above" means a combination including two or more of the listed features. For example, "including A, B, C or any combination of the above" means at least one combination of AB, AC, BC, and ABC.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this disclosure.

FIG. 1 is a flow chart of a method for preparing a solar cell according to an embodiment of the present disclosure. FIG. 2A to FIG. 2F are partial schematic diagrams of a semi-finished solar cell during the preparation of a solar cell according to an embodiment of the present disclosure. FIG. 2G is a schematic diagram of a solar cell according to an embodiment of the present disclosure. The following is a further description of a method for preparing a solar cell according to an embodiment of the present disclosure and a structure of a solar cell according to an embodiment of the present disclosure in combination with FIG. 1 and FIG. 2A to FIG. 2G.

As shown in FIG. 1 , a method for preparing a solar cell according to an embodiment of the present disclosure includes step S101 of providing a semiconductor substrate, step S103 of forming an oxide layer, step S105 of forming a doped silicon layer, step S107 of forming a passivation layer, step S109 of performing a laser annealing/patterning process, and step S111 of performing a battery post-process. The laser annealing/patterning process includes irradiating the front surface of the semiconductor substrate with a pulsed laser having a pulse width greater than 0 ps and less than or equal to 10 ps. The semiconductor substrate may include a front surface and a back surface opposite to the front surface, and an oxide layer, a doped silicon layer, and a passivation layer are formed on the front surface of the semiconductor substrate. The doped silicon layer is formed on the oxide layer, and the passivation layer is formed on the doped silicon layer. That is, the doped silicon layer is located between the oxide layer and the passivation layer.

The semiconductor substrate 10 provided in step S101 includes a front surface 10S1 and a back surface 10S2 opposite to the front surface 10S1. The semiconductor substrate 10 may include a silicon substrate. In some embodiments, the step S101 of providing the semiconductor substrate may include a substrate cleaning process and optionally a weaving structure forming process. The substrate cleaning process includes cleaning the semiconductor substrate 10 with a cleaning solution. The cleaning solution may include sulfuric acid, hydrochloric acid, ammonium hydroxide, hydrogen peroxide, hydrogen fluoride, deionized water, or any combination thereof. The weaving structure forming process includes potassium hydroxide, deionized water, a velveting additive, or any combination thereof. A weaving structure 101 including a plurality of protrusions and recesses is formed on the front surface 10S1 of the semiconductor substrate 10, but the present disclosure is not limited thereto. In some embodiments, the woven structure forming process may further include forming a woven structure 101 on the back surface 10S2 of the semiconductor substrate 10. In some embodiments, the woven structure forming process may be omitted.

In some embodiments, the method for preparing a solar cell according to an embodiment of the present disclosure may further include an emitter layer forming step between step S101 and step S103. The emitter layer forming step may form an emitter layer 20 on the woven structure 101 on the front surface 10S1 of the semiconductor substrate 10, as shown in FIG. 2A, but the present disclosure is not limited thereto. In some embodiments, the emitter layer forming step may include an ion diffusion process. Specifically, in some embodiments, the formation of the emitter layer 20 includes performing an ion diffusion process to diffuse ions on the front surface 10S1 of the semiconductor substrate 10 to form the emitter layer 20. In some embodiments, the ions used in the emitter layer formation step may be P-type ions, but the present disclosure is not limited thereto. Examples of P-type ions may include, but are not limited to, boron ions, aluminum ions, gallium ions, indium ions, or any combination thereof. In some embodiments, the ion diffusion process may include a thermal diffusion process, a laser diffusion process, any suitable diffusion process, or any combination thereof.

Step S103 may be performed after the emitter layer formation step, in which an oxide layer 30 may be formed on the front surface 10S1 of the semiconductor substrate 10. In some embodiments, the oxide layer 30 may be formed on the structure shown in FIG. 2A. That is, the oxide layer 30 may be formed on the emitter layer 20, and the emitter layer 20 may be disposed between the oxide layer 30 and the front surface 10S1 of the semiconductor substrate 10, as shown in FIG. 2B, but the present disclosure is not limited thereto. In some embodiments, the oxide layer 30 may be a tunneling oxide layer. In some embodiments, the oxide layer 30 may include silicon oxide, but the present disclosure is not limited thereto. The oxide layer 30 may be formed by a physical deposition process, a chemical deposition process, or a combination thereof. Examples of physical deposition processes may include vacuum evaporation, sputtering plating, ion plating, etc., but the present disclosure is not limited thereto. Examples of chemical deposition processes may include electroplating, chemical vapor deposition, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), etc., but the present disclosure is not limited thereto.

Step S105 may be performed after step S103. In step S105, a doped silicon layer 40 may be formed on the oxide layer 30. For example, in some embodiments, the doped silicon layer 40 may be formed on the structure shown in FIG. 2B. That is, the oxide layer 30 may be disposed between the emitter layer 20 and the doped silicon layer 40, as shown in FIG. 2C, but the present disclosure is not limited thereto. The oxide layer 30 may be disposed between the front surface 10S1 of the semiconductor substrate 10 and the doped silicon layer 40. In some embodiments, the doped silicon layer 40 may include amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, silicon carbide, or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the ions doped in the doped silicon layer 40 may be P-type ions and/or N-type ions. Examples of P-type ions are as described above. Examples of N-type ions may include but are not limited to phosphorus ions, arsenic ions, terbium ions, bismuth ions, or any combination thereof. In some embodiments, the doped silicon layer 40 may be boron ion doped microcrystalline silicon or boron ion doped amorphous silicon, but the present disclosure is not limited thereto. The ions doped in the doped silicon layer 40 may be the same as or different from the ions used in the emitter layer forming step. In some embodiments, the ions doped in the doped silicon layer 40 and the ions used in the emitter layer forming step are both boron ions, but the present disclosure is not limited thereto. The doped silicon layer 40 may be formed by a physical deposition process, a chemical deposition process, or a combination thereof. Examples of the physical deposition process and the chemical deposition process are described above.

Step S107 is performed after step S105. In step S107, a passivation layer 50 may be formed on the doped silicon layer 40. For example, in some embodiments, the passivation layer 50 may be formed on the structure shown in FIG. 2C. That is, the doped silicon layer 40 may be disposed between the oxide layer 30 and the passivation layer 50, as shown in FIG. 2D. In some embodiments, the passivation layer 50 may include silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or any combination thereof, but the present disclosure is not limited thereto. The passivation layer 50 may be formed by a physical deposition process, a chemical deposition process, or a combination thereof. Examples of physical deposition processes and chemical deposition processes are described above.

Step S109 is performed after step S107. The laser annealing/patterning process in step S109 may include a laser modification process and a pattern formation process. The laser modification process includes irradiating a specific area of the front surface 10S1 of the semiconductor substrate 10 with a pulsed laser L having a pulse width greater than 0 ps and less than or equal to 10 ps. The laser wavelength of the pulsed laser L may be greater than or equal to 235 nm and less than 533 nm. In some embodiments, the laser wavelength of the pulsed laser L may be 355 nm, but the present disclosure is not limited thereto.

In the laser modification process, the doped silicon layer 40 in the specific region is annealed by the pulsed laser L to form an annealed doped silicon layer 40', and the passivation layer 50 is modified by the pulsed laser L to form a modified passivation layer 50', as shown in FIG. 2E. In the annealed doped silicon layer 40', the doping ions originally in the doped silicon layer 40 can be activated by the pulsed laser L and/or doped to a deeper level. In the embodiment where the doped silicon layer 40 includes microcrystalline silicon or amorphous silicon, the doped silicon layer 40 is annealed by pulsed laser L to form an annealed doped silicon layer 40' including polycrystalline silicon. The modified passivation layer 50' formed after the passivation layer 50 is modified by pulsed laser L can improve the acid and alkali resistance of the passivation layer. The modified passivation layer 50' also has the advantages of reducing the carrier recombination rate and increasing the life of minority carriers in the subsequently formed solar cell. That is, through the laser modification process, the passivation layer 50 can be transformed into a modified passivation layer 50' with better acid and alkali resistance, the doped silicon layer 40 can be transformed into an annealed doped silicon layer 40' in which doping ions are activated, and the doped silicon layer 40 including microcrystalline silicon or amorphous silicon can be transformed into an annealed doped silicon layer 40' including polycrystalline silicon, and the subsequently formed solar cell can have better photoelectric conversion efficiency.

The pattern forming process may include removing the doped silicon layer 40 and the passivation layer 50 with an etchant and forming a passivation pattern 51 and a doped silicon pattern 41, as shown in FIG. 2F. In some embodiments, the etchant used in the pattern forming process may include hydrofluoric acid, but the present disclosure is not limited thereto. In some embodiments, the width W of the passivation pattern 51 is greater than or equal to 150 μm and less than or equal to 300 μm. In some embodiments, the width W of the passivation pattern 51 is greater than or equal to 200 μm and less than or equal to 250 μm. In some embodiments, the width W of the passivation pattern 51 is approximately equal to 210 μm.

Step S111 is performed after step S109. The battery post-process of step S111 includes an optional back surface treatment process and an electrode formation process. That is, in some embodiments, the battery post-process may only include an electrode formation process. In an embodiment in which the battery post-process only includes an electrode formation process, the back surface treatment process may be performed before step S103, but the present disclosure is not limited thereto. In an embodiment in which the battery post-process includes a back surface treatment process and an electrode formation process, the electrode formation process may be performed after the back surface treatment process. In some embodiments, the execution temperature of the back surface treatment process may be less than or equal to the execution temperature of the laser modification process in step S109 to avoid damaging the layers formed on the front surface 10S1 of the semiconductor substrate 10 or reduce the risk of damaging the layers formed on the front surface 10S1 of the semiconductor substrate 10.

The back surface treatment process may include forming a back tunneling oxide passivation structure 80 including a back oxide layer 81 and a back passivation layer 83 on the back surface 10S2 of the semiconductor substrate 10. The electrode formation process may include a positive electrode formation process for forming a positive electrode 60 on the passivation pattern 51 and the doped silicon pattern 41 and a back electrode formation process for forming a back electrode 70 on the back surface 10S2 of the semiconductor substrate 10.

In some embodiments, the positive electrode forming process and the back electrode forming process may include a screen printing process, a physical vapor deposition process, an inkjet printing process, etc. In some embodiments, the positive electrode 60 and the back electrode 70 may include copper, silver, aluminum, gold, or any combination thereof. In some embodiments, the back electrode 70 may be formed on the back tunneling oxide passivation structure 80. The back passivation layer 83 may be located between the back oxide layer 81 and the back electrode 70. In some embodiments, the back surface treatment process may further include forming a protective layer 85 on the back tunneling oxide passivation structure 80. In some embodiments, the protective layer 85 may have an opening that exposes a portion of the back passivation layer 83. The back electrode 70 may be formed in the opening and contact the back passivation layer 83, as shown in FIG. 2G, but the present disclosure is not limited thereto. The back tunneling oxide passivation structure 80 and the protective layer 85 may be formed by any method and material known in the art, and thus will not be described in detail herein. The solar cell of the present disclosure may be completed after step S111, and the completed solar cell has a structure as shown in FIG. 2G, but the present disclosure is not limited thereto. In some embodiments, the back tunneling oxide passivation structure 80 may also include a texturing structure formed on the back surface 10S2 of the semiconductor substrate 10.

By using the above steps, especially the laser annealing/patterning process in step 109, the method for preparing solar cells disclosed herein can obtain a modified passivation layer 50' with better acid and alkali resistance, and at the same time obtain an annealed doped silicon layer 40' in which doping ions are activated and doped to a deeper level, or an annealed doped silicon layer 40' in which microcrystalline silicon or amorphous silicon is converted into polycrystalline silicon. Therefore, the method for preparing solar cells disclosed herein can prepare solar cells with fewer process steps, thereby achieving the purpose of reducing production costs. In addition, the pulsed laser L with a pulse width greater than 0 ps and less than or equal to 10 ps will not damage the oxide layer 30 below the doped silicon layer 40, so the preparation method of the solar cell disclosed in the present invention can maintain the integrity of the oxide layer 30, thereby improving the electrical properties of the solar cell. Furthermore, the pulsed laser L with a laser wavelength greater than or equal to 235 nm and less than 533 nm can be absorbed on the surface of the solar cell without affecting the underlying film layer, thereby avoiding the overall high temperature from affecting other film layers.

One or more advantages of the present disclosure will now be further described with reference to the following examples. However, this example is only used to illustrate the present disclosure embodiment and is not intended to limit the scope of the present disclosure embodiment.

Preparation of solar cells

Example 1

A silicon substrate (manufacturer: AUO) is provided, and after cleaning the silicon substrate with a mixture of hydrochloric acid, hydrogen peroxide and deionized water, and a hydrofluoric acid aqueous solution, a mixed aqueous solution of potassium hydroxide, deionized water, and a velvet additive (TS55, purchased from Changzhou Shichuang Energy Co., Ltd.) heated to 80°C is applied to the front of the silicon substrate to form a woven structure. Then, boron diffusion is performed by LPCVD to diffuse boron ions on the front of the silicon substrate with the woven structure to form a boron emitter layer.

By chemical vapor deposition, oxygen is introduced to react with the silicon substrate to form a tunnel oxide layer with a thickness of 1nm~2nm. Then, a boron-doped microcrystalline silicon layer is deposited on the tunnel oxide layer by low-pressure chemical vapor deposition process. Finally, a silicon nitride layer is deposited on the boron-doped microcrystalline silicon layer by plasma enhanced chemical vapor deposition process.

A laser with a wavelength of 355 nm and a pulse width of 7 ps is irradiated on a specific area on the front surface of a silicon substrate where a boron emitter layer, a tunneling oxide layer, a boron-doped microcrystalline silicon layer, and a silicon nitride layer are formed. The boron-doped microcrystalline silicon layer on the specific area is transformed into a boron-doped polycrystalline silicon layer after laser irradiation, and the silicon nitride layer on the specific area is transformed into a modified silicon nitride layer after laser irradiation.

The unmodified silicon nitride layer and the boron-doped microcrystalline silicon layer outside the specific area are removed by using a 7% hydrofluoric acid and 25% sodium hydroxide aqueous solution to form a passivation pattern and a doped silicon pattern. A back-side tunneling oxide passivation structure is formed on the back side of the silicon substrate by using a known method and material to complete the preparation of the semi-finished solar cell.

Finally, a positive electrode and a back electrode are formed on the passivation pattern and the doped silicon pattern and the back tunneling oxide passivation structure, thereby completing the preparation of the solar cell.

Comparison Example 1

A solar cell semi-finished product and a solar cell are prepared in the same manner as in Example 1, except that a laser with a wavelength of 533 nm and a pulse width of 20 ns is irradiated on a specific area on the front surface of the silicon substrate having a boron emitter layer, a tunneling oxide layer, a boron-doped microcrystalline silicon layer, and a silicon nitride layer.

Comparison Example 2 (L-biPC Traditional Process)

A silicon substrate (manufacturer: AUO) is provided, and after the silicon substrate is cleaned with a mixture of hydrochloric acid, hydrogen peroxide and deionized water, and a hydrofluoric acid aqueous solution, a mixed aqueous solution of potassium hydroxide, deionized water and a velvet additive heated to 80°C is used to form a woven structure on the front side of the silicon substrate. Then, boron diffusion is performed by LPCVD to diffuse boron ions on the front side of the silicon substrate with the woven structure to form a boron emitter layer.

By chemical vapor deposition, oxygen is introduced to react with the silicon substrate to form a tunnel oxide layer with a thickness of 1nm~2nm. Then, a boron-doped microcrystalline silicon layer is deposited on the tunnel oxide layer by LPCVD. After the boron-doped microcrystalline silicon layer is deposited, a high-temperature annealing treatment at 880℃ to 910℃ is performed to transform the boron-doped microcrystalline silicon layer into a boron-doped polycrystalline silicon layer. Finally, a silicon nitride layer is deposited on the boron-doped polycrystalline silicon layer by PECVD.

Use resist and screen printing technology to screen print specific areas of the boron emitter layer, tunnel oxide layer, boron-doped polysilicon layer, and silicon nitride layer on the front side of the silicon substrate. Ensure that the specific area maintains the required layer structure in the subsequent process.

The unmodified silicon nitride layer and the boron-doped polysilicon layer outside the specific area are removed by a mixed aqueous solution of 7% hydrofluoric acid and 25% sodium hydroxide to form a passivation pattern and a doped silicon pattern.

The resist on the silicon substrate is removed using a 70% nitric acid solution. This step ensures that the resist is completely removed, restoring the surface of the silicon substrate to a clean state. A back-side tunneling oxide passivation structure is formed on the back side of the silicon substrate using known methods and materials to complete the preparation of the semi-finished solar cell product.

Finally, a positive electrode and a back electrode are formed on the passivation pattern and the doped silicon pattern and the back tunneling oxide passivation structure, thereby completing the preparation of the solar cell.

Comparison Example 3 (TOPCon Battery)

A silicon substrate (manufacturer: AUO) is provided, and after the silicon substrate is cleaned with a mixture of hydrochloric acid, hydrogen peroxide and deionized water, and a hydrofluoric acid aqueous solution, a mixed aqueous solution of potassium hydroxide, deionized water and a velvet additive heated to 80°C is applied to the front side of the silicon substrate to form a woven structure. Then, boron diffusion is performed by LPCVD to diffuse boron ions on the front side of the silicon substrate with the woven structure to form a boron emitter layer.

Oxygen is introduced by chemical vapor deposition to react with the back of the silicon substrate to form a tunnel oxide layer with a thickness of 1nm~2nm. Then, a boron-doped microcrystalline silicon layer is deposited on the tunnel oxide layer by LPCVD. After the boron-doped microcrystalline silicon layer is deposited, a high-temperature annealing treatment of 880℃ to 910℃ is performed to transform the boron-doped microcrystalline silicon layer into a boron-doped polycrystalline silicon layer. Finally, a silicon nitride layer is deposited on the boron-doped polycrystalline silicon layer by PECVD.

Finally, a positive electrode and a back electrode are formed on the front silicon nitride passivation layer and the doped silicon pattern and on the back tunnel oxide passivation structure, thereby completing the preparation of the solar cell.

Solar cell semi-finished product performance evaluation

The imply open circuit voltage (iVoc) of four semi-finished solar cells of Example 1, four semi-finished solar cells of Comparative Example 1, four semi-finished solar cells of Comparative Example 2, and four semi-finished solar cells of Comparative Example 3 was measured using a quasi-steady-state photoconductance (QSSPC) method. The results are shown in Table 1 and FIG. 3 below.

The composite current (J0) and minority carrier life (Lifetime) of four semi-finished solar cells of Example 1, four semi-finished solar cells of Comparative Example 1, four semi-finished solar cells of Comparative Example 2, and four semi-finished solar cells of Comparative Example 3 were measured by QSSPC method. The results are shown in Table 1 below. Table 1 No. Minority carrier life (μs) iVoc (mV) J ₀ (fA/cm ² ) Example 1 E1.1 679 732 5.3 E1.2 686 732 5.7 E1.3 695 732 4.4 E1.4 708 733 4.1 average 692 732.25 4.875 Comparison Example 1 C1.1 191 699 27.2 C1.2 234 701 49.8 C1.3 302 697 36.7 C1.4 134 693 35.7 average 215.25 697.5 37.35 Comparison Example 2 C2.1 444 729 6.2 C2.2 415 729 4.8 C2.3 371 724 7.1 C2.4 357 719 9.1 average 396.75 725.25 6.8 Comparison Example 3 C3.1 527 725 5.6 C3.2 512 724 6.5 C3.3 499 724 6.6 C3.4 516 725 6.5 average 513.5 724.5 6.3

FIG. 3 is a schematic diagram illustrating the iVoc of the semi-finished solar cell according to the examples and comparative examples disclosed herein. The higher the iVoc, the better the surface passivation effect of the semi-finished solar cell, and the better the photoelectric conversion effect of the subsequently formed solar cell. In addition, the higher the minority carrier lifetime, the better the photoelectric conversion effect of the subsequently formed solar cell. In addition, the J0 parameter refers to the dark saturation current density, which is a key indicator for measuring the carrier recombination loss in semiconductor materials. A low J0 value usually means a small carrier recombination loss, and a higher open circuit voltage can be obtained, thereby improving the efficiency of the solar cell. It can be clearly seen from FIG. 3 and Table 1 that the average iVoc of the solar cell semi-finished product of Example 1 is at least 7 mV higher than the average iVoc of the solar cell semi-finished products of Comparative Examples 1 to 3. The average minority carrier lifetime of the solar cell semi-finished product of Example 1 is at least 178.5 μs longer than the average minority carrier lifetime of the solar cell semi-finished products of Comparative Examples 1 to 3. The average J0 of the solar cell semi-finished product of Example 1 is at least 1.425 fA/cm ² less than the average J0 of the solar cell semi-finished products of Comparative Examples 1 to 3. Therefore, the solar cell manufactured according to the solar cell manufacturing method disclosed in the present invention has at least a better photoelectric conversion effect, and can reduce more than two manufacturing processes, thereby reducing costs.

Solar Cell Performance Evaluation

FIG4 shows the relationship between the current density and the voltage of the solar cell of Example 1 and the solar cell of Comparative Example 2 measured using a solar simulator IV meter.

The short circuit current density (Jsc), open circuit voltage (Voc), fill factor (FF) and battery efficiency (Eff) of the solar cell of Example 1 and the solar cell of Comparative Example 2 were measured by a solar simulator IV measurement instrument. The above measurement results are shown in the following Table 2. Table 2 Jsc(mA/cm ² ) Voc(mV) FF(%) Eff(%) Example 1 35.87 657 77.26 18.11 Comparison Example 2 35.84 664 75.10 17.88

FIG. 4 is a graph showing the relationship between current density and voltage of the solar cell according to the example and the comparative example disclosed herein. As can be seen from FIG. 4 and Table 2, the solar cell of Example 1 has a 2.16% higher F.F. and a 0.23% higher Eff than the solar cell of Comparative Example 2. It is obvious that the solar cell prepared according to the method for preparing the solar cell disclosed herein has at least a better photoelectric conversion efficiency.

In summary, the method for preparing a solar cell disclosed herein can not only prepare a solar cell with fewer process steps, thereby achieving the purpose of reducing production costs, but also the prepared solar cell has at least a better photoelectric conversion efficiency.

Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure content of some embodiments of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described here, they can be used according to some embodiments of the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each patent application and embodiment.

S101, S103, S105, S107, S109, S111: Steps 10: Semiconductor substrate 101: Texturing structure 10S1: Front surface 10S2: Back surface 20: Emitter layer 30: Oxide layer 40: Doped silicon layer 40’: Annealed doped silicon layer 41: Doped silicon pattern 50: Passivation layer 50’: Modified passivation layer 51: Passivation pattern 60: Positive electrode 70: Back electrode 80: Back tunneling oxide passivation structure 81: Back oxide layer 83: Back passivation layer 85: Protective layer L: Laser W: Width

The following is a detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein: FIG. 1 is a flow chart of a method for preparing a solar cell according to an embodiment of the present disclosure; FIG. 2A to FIG. 2F are partial schematic diagrams of a semi-finished solar cell during the preparation of a solar cell according to an embodiment of the present disclosure; FIG. 2G is a schematic diagram of a solar cell according to an embodiment of the present disclosure; FIG. 3 is a schematic diagram illustrating the average hidden open circuit voltage of a semi-finished solar cell according to an example and a comparative example of the present disclosure; and FIG. 4 is a diagram illustrating the relationship between current density and voltage of a solar cell according to an example and a comparative example of the present disclosure.

S101, S103, S105, S107, S109, S111: Steps

Claims (11)

A method for preparing a solar cell comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises a front surface and a back surface opposite to the front surface; forming an oxide layer on the front surface of the semiconductor substrate; forming a doped silicon layer on the oxide layer; forming a passivation layer on the doped silicon layer; performing a laser annealing/patterning process to obtain a passivation pattern and a doped silicon pattern; and performing a post-battery process, wherein the laser annealing/patterning process comprises irradiating the front surface of the semiconductor substrate with a pulsed laser having a pulse width greater than 0 ps and less than 10 ps. A method for preparing a solar cell as described in claim 1, wherein the laser wavelength of the pulsed laser is greater than or equal to 235 nm and less than 533 nm. A method for preparing a solar cell as described in claim 2, wherein the laser wavelength of the pulsed laser is 355 nm. The method for preparing a solar cell as described in claim 1, wherein the step of providing the semiconductor substrate includes forming a texturing structure on the front surface of the semiconductor substrate. The method for preparing a solar cell as described in claim 1 further includes forming an emitter layer on the front surface of the semiconductor substrate before forming the oxide layer. The method for preparing a solar cell as described in claim 5, wherein the formation of the emitter layer includes performing an ion diffusion process to form the emitter layer. The method for preparing a solar cell as described in claim 1, wherein the width of the passivation pattern is greater than or equal to 150 μm and less than or equal to 300 μm. A method for preparing a solar cell as described in claim 1, wherein the doped silicon layer includes amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, silicon carbide, or any combination thereof. The method for preparing a solar cell as described in claim 1, wherein the passivation layer comprises silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, or any combination thereof. A method for preparing a solar cell as described in claim 1, wherein the oxide layer comprises silicon oxide. A method for preparing a solar cell as described in claim 1, wherein the cell post-process includes a back surface treatment process, a positive electrode formation process and/or a back electrode formation process.

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