TWI877923B - Test pattern vectors in homogenous multi-die packages - Google Patents

Abstract

Connecting test equipment to an input pin of the MCM, transmitting pipeline delay configuration data for a first die-under-test (DUT) to configure a first die input pipeline register with a first delay value at a first die of the MCM, transmitting ATP data into a first die scan chain register in a predetermined number of clock cycles via the first delay value of the first die input pipeline register, configuring the first die to perform a scan chain test with the ATP datal, transmitting pipeline delay configuration data for a second DUT to configure the first die input pipeline register with a second delay value, transmitting the ATP data into a second die scan chain register in the predetermined number of clock cycles via the reconfigured first die input pipeline register and a die-to-die interconnect, and configuring the second die to perform a scan chain test with the ATP data.

Description

Test pattern vectors in homogeneous multi-die packaging

One or more disclosed embodiments relate to testing integrated circuits (ICs), and more particularly, to inter-wafer scan testing, where data is delivered to homogeneous dies using one or more pipelines configured to enable vector depth and test time optimization.

Semiconductor integrated circuits (ICs) are manufactured using a multi-stage process. Packaging usually refers to the process of mounting or placing the die (referred to herein as a "tile") within a plastic, ceramic, or other package that facilitates the use of multiple dies in a device. Typically, each die is tested individually because packaged devices have heterogeneous dies.

Typically, ICs are characterized by performance. Performance can be measured as to whether the IC is able to perform established design requirements related to operating frequency, signal fidelity, signal response, or the like. Performance analysis identifies ICs that do not meet minimum design requirements. ICs include a sequence of combinatorial logic made of thousands of logic gates, latches, and the like. Scan chain testing is used to load the combinatorial logic gates with a known automated test pattern (ATP) and analyze their outputs against known results to determine if one or more faults are present in the combinatorial logic. Faults in an IC can include one or more of stuck-at faults, transistor faults, bridge faults, open circuit faults, delay faults, and the like.

The test cost is affected by the size of the pattern stored in the tester memory (i.e., vector depth), and the speed at which bits are shifted in and out through the scan chain (i.e., flip-flops), i.e., the shift clock frequency. ATE (Automatic Test Equipment) runs a fixed loop with cycle accuracy (e.g., 10 ns), where all inputs are driven relative to the clock cycle. At the same time, the response of the device to the output is monitored (i.e., strobed); the output is always monitored with a delay interval of the cycle that depends on the scan chain length. Electronic design automation (EDA) tools therefore generate patterns with automatic test pattern generation (ATPG) that enables test scans.

Embodiments are described herein for accessing and testing internal die (or dies) within a packaged multi-chip-module (MCM) device with limited input/output (I/O) for use by test equipment, wherein all die are interconnected on a package substrate to reduce costs by utilizing compatible specifications. In addition to the duration of test equipment use, costs associated with production testing involve storage capacity used to store test vectors. The embodiments described herein address ATPG scan pattern vector depth by reusing the same set of patterns to test all die (or the same die), which reduces the amount of memory required to store test patterns. Furthermore, by using scan chain latches between dies of a multi-die MCM, a higher ATPG scan shift pattern frequency can be used, which reduces the total test time for testing all dies during production of packaged devices with multiple dies. Dynamically configuring scan chain pipeline registers in serially connected homogeneous dies allows the same pattern set to be reused regardless of which die is under test, thereby saving vector memory depth, which in turn reduces packaged device test costs at production. Similarly, configurable scan chain pipeline registers allow for increased ATPG shift pattern frequency (i.e., higher frequency, shorter time period) to reduce the actual time spent, thereby reducing the associated device test costs for testing each device in production.

Briefly, an MCM system architecture and a method for selective test vector scanning between chips of homogeneous dies packaged in an MCM device are using restricted accessible pins and in combination with reconfigurable input scan chain pipeline registers. Inter-die interconnects with through-routing are used to select inter-die channels between each of the dies. Automatic test pattern (ATP) test vectors are loaded into the scan chain of each circuit die with the same ATP data and timing constraints throughout the MCM by adjusting delay values through the reconfigurable input pipeline registers and configuring the inter-die interconnects for a predetermined number of clock cycles. A described test method configures a first die input pipeline register with a first delay value at a first die of the MCM. ATP data is loaded into a first die scan chain register in a predetermined number of clock cycles via a first delay value in a first die pipeline register, and a scan chain test of the first die is performed using the ATP data. The first die input pipeline register is reconfigured with a second delay value, and ATP data is loaded into a second die scan chain register in a predetermined number of clock cycles via a second delay value in the first die pipeline register and an inter-die interconnect, and a scan chain test of the second die is performed. The described method can further be extended to three, four, or more homogeneous dies.

FIG. 1 is a block diagram illustrating an embodiment of a selective test vector scan of a packaged die for a multi-chip module (MCM) device, here a multi-chip integrated circuit (IC) MCM structure 10. In some embodiments, the MCM may have limited accessible input/output (I/O) pins and may thereby use reconfigurable input pipeline registers for a die/plurality of dies (including a first die 12 and a second die 14). The MCM may include at least one associated reconfigurable input pipeline register 22. The embodiments described herein relate particularly to a plurality of homogeneous circuit dies, however, such a constraint should not be considered limiting. The MCM of FIG. 1 further includes inter-die interconnects between each of the dies that may be reused from, for example, a serial peripheral interface (SPI) application to convey automatic test pattern (ATP) test vectors. Each circuit die includes scan chain registers, and the ATP test vectors are loaded into the scan chain registers of a selected homogeneous die with the same ATP data and timing provided to the MCM by configuring the reconfigurable input pipeline registers of the corresponding die with a specific number of clock cycles by adjusting the delay values to account for the delay introduced by the inter-die interconnects. Homogeneous dies use the same ATP data loaded into die scan chains in a defined timing pattern, wherein each die scan chain can be properly loaded within the same predetermined number of clock cycles regardless of the specific die position within the group of serially connected homogeneous dies. A plurality of circuit dies can be configured in a serially connected hierarchical structure. That is, when the scan chain register is loaded in a selected die, the ATP data is transmitted from the input pipeline register of the first circuit die to the input pipeline register of the second circuit die through the inter-die interconnect, and possibly to a third circuit die through another inter-die interconnect. At least one output pin from the MCM IC package connects the die scan output coupling of the plurality of dies to the reconfigurable output pipeline register. The MCM structure 10 limited accessible pins may be re-purposed pins for testing.

FIG. 1 is a block diagram of n homogeneous circuit dies of a hierarchical MCM structure 10 according to an embodiment of the present invention. An IC package 20 includes a plurality of n dies within the IC package 20, each of the dies 12, 14 having at least one associated reconfigurable input pipeline register 22 configured to provide a die scan_in coupling 28 to at least one die scan chain 26. Each of the dies 12, 14 further includes at least one reconfigurable output pipeline register 24 from a die scan_out coupling 30. At least one input pin IC package connection 16 is provided for loading ATP scan data into the IC package 20 via the reconfigurable input pipeline register 22. The input pin IC package connection 16 can load the ATP scan data into the input pipeline register 22 of the first circuit die (such as chip die 12) by default. The input pipeline register 22 of the first circuit die 12 can be selectively configured to couple the ATP scan data to the scan chain 26 on the first die, or reroute the ATP scan data to the follower circuit die 14 to be loaded into the scan chain 36 through the inter-die interconnect.

At least one output pin IC package connection 18 is provided from the IC package 20 for outputting the results of the scan chain test, that is, the captured state of the combined logic after the scan data is loaded. As shown, the output pin IC package connection 18 is connected to the die scan_out coupling 30, 34 of one of the plurality of n dies via a reconfigurable output pipeline register 34 for communicating the die scan_out coupling 30 with the selected one of the plurality of n dies. The inter-die interconnect 46 with a through-route 48 establishes a plurality of inter-die channels 50 between each of the plurality of dies 12, 14 within the IC package 20.

In some embodiments, input pipeline register 22 includes multiplexing logic for selectively routing incoming ATP scan data received via input pins 16 to scan chain 26 within first circuit die 12, or to the input pipeline register of a second circuit die of the n homogeneous circuit die. Similarly, multiplexing logic in output pipeline register 24 may be used to selectively output scan chain results from scan chain 26 within one of the n homogeneous circuit die, i.e., first circuit die 12, or scan chain results 30 received via inter-die interconnect 46. An integrated circuit (IC) structure may include an interposer including a plurality of inter-die routings and a first die coupled to the interposer. The first die may include a first output and a first input, the first output including a first flip-flop coupled to a first inter-die routing of the plurality of inter-die routings, and the first input including a second flip-flop coupled to a second inter-die routing of the plurality of inter-die routings. The IC may include existing inter-die substrate connections for, for example, inter-die serial peripheral interface (SPI) communications. Such inter-die data interfaces may be reused for the purpose of scan input/output data access. Based on the above appropriate hardware structure, the IC may be configured (i.e., dynamically through a device initialization sequence) to apply an ATPG pattern to an active die under test. In some embodiments, configuration of the die includes enabling the number of pipeline stages in each die based on the spread between the die before applying the ATPG pattern to the die under test. Latching within each input pipeline register 22 for the follower die is configured to latch the ATPG pattern received through the inter-die interconnect to protect the data from clock skew.

FIG. 2 is a block diagram of a circuit die 12 according to some embodiments. As shown, the input and output pipeline register package connections are shown as interconnecting dies from a single first die 12 of homogeneous dies 12, 14 of a flip-flop (FF) scan chain 26. The scan chain is loaded via a reconfigurable input pipeline register 22 associated with one or more input pins 16, 16'. FIG. 3 is a schematic diagram for a reconfigurable input pipeline register 22 according to some embodiments. As shown, if multiple input pins are available, multiple input pipeline registers 22 associated with the input pins 16, 16' of FIG. 2 and FIG. 3 can be configured in parallel for each homogeneous die, but such constraints should not be considered limiting. As shown, each input pipeline register 22 includes a sequence of flip-flops, each flip-flop having a corresponding output connector. The flip-flops are configured to apply a configurable delay to the ATP scan data. The input pipeline register 22 further includes a multiplexer having a plurality of inputs, each input connected to a corresponding output connector of the sequence of flip-flops. The multiplexer is configured to receive a selection signal and select one of the plurality of output connectors of the sequence of flip-flops to apply a configurable delay value to the ATP scan data. The delay value selected by the multiplexer can be associated with which homogeneous die of a plurality of homogeneous dies is under test. When a circuit die further down in the hierarchy is under test, an ATP test signal may be transmitted through a chain of input pipeline registers. As described above, each input pipeline register includes a plurality of flip-flop circuits that incrementally advance the ATP test signal. By utilizing the sequence of flip-flop circuits from the input pins to the scan chain inputs of the circuit die under test, a long signal path that originally had a long propagation delay (and therefore a slow shift clock rate) is decomposed into a larger number of smaller paths with small individual propagation delays. Because the shift clock rate depends on the longest propagation delay, minimizing the maximum propagation delay therefore reduces the shift clock rate, which speeds up the scan chain test itself when the scan chain and load of the input pipeline register are performed using the same clock signal. The die-level JTAG IEEE 1149.1 (Joint Test Action Group) standard defines the test logic included in the MCM 10 circuit to provide a standardized serial bus test clock signal. According to the JTAG test standard, the clock scan shift frequency can be accelerated to reduce the test time. In some alternative embodiments, the clock signal can be directly supplied as if it is directly routed between dies.

FIG. 4 shows a FF scan chain for testing the digital logic of each die of the MCM structure 10 according to some embodiments. As shown, each scan chain includes a sequence of flip-flops. In the shift register method as described above, the flip-flops are serially loaded with ATP scan data in a predetermined number of clock cycles. The ATP scan data is loaded in parallel with the combinational logic (not shown) of the MCM and processed by the combinational logic using a single clock cycle. The output of the combinational logic is latched into the scan chain flip-flops and shifted out at the scan_out port 40 for analysis. The multiplexed scan pattern is an industry standard method for testing manufacturing defects in digital circuits during production. Manufacturing defects can be stuck-at faults where any standard cell (e.g. flip-flops, logic gates) can be stuck at GND or power during the manufacturing process. Defects can also be due to RC variations in metals, which affect the transition of signals between states. Pipeline registers are set up in each die, and then once a bit is latched in FF1 of die #1, the signal is changed to the next bit. By having these pipeline registers in each die, the test pattern bit sequence can be accepted at a faster rate. The increased frequency of loading serially connected dies is a beneficial byproduct of using pipeline registers.

FIG. 5 is a schematic diagram of a reconfigurable output pipeline register 24 for scan data of MCM 10 according to some embodiments. Each homogeneous circuit die includes an output pipeline register 24 as shown. The processed scan chain data is propagated through each circuit die in the circuit die hierarchy according to a delay value similar to the delay value used by input pipeline register 22 to load scan data into the scan chain. For example, if the first circuit die 12 is currently being tested, the output pipeline register 24 of the first chip block is the only output stage in use, and the delay value can be the highest setting. As the circuit die 14 further down in the chain is selected as the current die under test, the processed scan chain data is still advanced through the output pipeline registers 24 of the circuit die higher in the circuit die hierarchy. The amount of delay imposed by each output pipeline register 24 can be reduced in proportion to the number of circuit dies in the entire hierarchy relative to the current die under test. In the example herein, the ATPG calibrated die test is used to implement the design for test (DFT) test of the MCM structure 10 multi-die IC for multiple homogeneous dies in the IC package. DFT testing allows selection from a plurality of different available outputs from the input and output pipeline registers, adjusting the pipeline registers with configurable delay values in a manner that programs the delays of the first die pipeline registers to route ATP sequence data to a second die in the hierarchy. When testing the second circuit die in the hierarchy, the pipeline configuration information is transmitted to the MCM via the input pins to configure the first die input pipeline registers 22 with reduced delay values that take into account the delays caused by propagating the inter-die interconnects. In such an embodiment, ATP sequence data is loaded into the scan chain of the second die in the same predetermined number of clock cycles in which the ATP scan data is loaded into the scan chain of the first circuit die in the hierarchy. Similarly, transmitting pipeline configuration information to the MCM via input pins configures the first die output pipeline register 24 of the first circuit die with reduced latency values that compensate for the scan chain results of the second circuit die across the inter-die interconnect.

The determined actual time measurements can be compared to expected time measurements to determine if any defects may exist within the DUT and, for example, within the die-to-die routing or the connections between the die-to-die routing and within the die. When the ATP data is loaded into the first die scan chain register, the inter-die interconnect between the first die and the second die of the MCM 10 loads the ATP data into the second die scan chain register in the same predetermined number of clock cycles. This can result in more accurate full-speed path delay testing. Full-speed testing can be particularly important for high-speed devices, where quantities such as signal propagation delays and resistance can vary significantly with increasing frequency. Therefore, the test signals propagate throughout the IC structure at full speed rather than at a much lower speed. Multi-die testing in a packaged device is accomplished by enabling and interconnecting pipeline stages in multiple dies, looking at and characterizing each die under test across the entire package, where the interconnecting pipeline stages have individually configurable delay values that depend on the die under test being configured.

FIG. 6A and FIG. 6B show homogeneous circuit dies 12, 14 of an MCM according to some embodiments, respectively. The circuit dies 12 and 14 each have corresponding reconfigurable input pipeline registers 22 and output pipeline registers 24, wherein an inter-die interface interconnects the input pipeline stages and the output pipeline stages. In some embodiments, a test instrument is connected to the input pins of the MCM. The test instrument transmits pipeline delay configuration data for a first die under test (DUT) to configure the first die input pipeline register 22 with a first delay value. The test instrument transmits ATP data to a calibrated die scan chain register on the first die in a predetermined number of clock cycles via a first delay value of a first die pipeline register. The first die is configured to perform a scan chain test using the ATP data. The test instrument transmits pipeline delay configuration data for a second DUT to configure the first die input pipeline register 22 with a second delay value, and transmits the ATP data to a second die scan chain register in a predetermined number of clock cycles via the reconfigured first die input pipeline register and inter-die interconnect. In some embodiments, the pipeline delay configuration data further includes data to configure a second die input pipeline register with a third delay value, and the ATP data is transmitted through the second die input pipeline register to the second die scan chain register. In such an embodiment, the ATP scan data may be propagated through the first die input pipeline register in the same number of clock cycles as transmitted through the first die input pipeline register and the second die input pipeline register having the second delay value and the third delay value, respectively. ATPG vector testing of the MCM 10 using ATP testing may be used with lossless compression (e.g., 1:10 compression) when loading and configuring test data.

FIG7 illustrates a data path for loading ATP data into a first die scan chain register of an MCM having multiple homogeneous circuit dies 12, 14 according to some embodiments. The ATP data flow is indicated by arrows. The test instrument is connected to the input pins of the MCM, and the pipeline delay configuration data for the first DUT is transmitted to the MCM to configure the first die input pipeline register with a first delay value, shown as two flip-flop stages in FIG7. The pipeline delay configuration data for the first DUT may include a selection signal of a multiplexer connected to a plurality of output terminals of the flip-flop sequence. The ATP data is transmitted to the first die scan chain register, and a scan chain test is performed on the first die.

After the scan chain test, the result of the scan chain is shifted to the first die output pipeline register 24. Similar to the first die input pipeline register 22, the first die output pipeline register 24 can be configured to have a variable delay, which is shown in Figure 7 as a flip-flop sequence. The flip-flop sequence has a plurality of output connectors connected to a multiplexer. The pipeline delay configuration data transmitted to the MCM can be similarly configured for the selection signal of the multiplexer in the first die pipeline output register 24. In Figure 7, the multiplexer selection in the first die pipeline output register 24 corresponds to the output of two flip-flop delay values. As described in more detail below, configurable pipeline output registers in each circuit die further ensure that scan chain test results are seen at the output pins of the MCM after the same number of clock cycles, regardless of which circuit die is actively under test.

FIG8 illustrates a data path for loading ATP data into a second die scan chain register according to some embodiments. Pipeline delay configuration data is transmitted to the MCM via input pins to configure the first input pipeline register 22 and the second input pipeline register 22', respectively. Specifically, the first die input pipeline register 22 is configured with a second delay value corresponding to a pipeline flip-flop delay, while the second die input pipeline register 22' is configured with a third delay value corresponding to a pipeline flip-flop delay. It should be noted that because each die is homogeneous, each die therefore includes an input pipeline register that can be used for configurable delays. The embodiments herein may be extended to an MCM having inter-die interconnects between non-homogeneous circuit dies, wherein an input pipeline register may have a configurable delay value having delay value settings for a plurality of DUT settings. Similar to FIG. 7 , the data path of the ATP data through each pipeline flip-flop is indicated by an arrow. As shown, the ATP data is transmitted to the MCM via an input pin. The ATP data propagates through a first die input pipeline stage and a second die input pipeline stage, each having a delay flip-flop. As described above, the shift pattern frequency of the clock used by the flip-flops may be related to the propagation delay between the output of the first die input pipeline register and the input of the second die input pipeline register 22'. Thus changing the ATP data acquisition route so that the timing is the same regardless of which die is being tested, the same exact pattern with the same exact stored sequence and pattern can then be read from the same memory location in the tester, which means cost savings.

Similar to FIG. 7 , the first circuit die and the second circuit die may include pipeline output registers 24 and 24 ′, respectively. As described above, the first die pipeline output register 24 has two flip-flop delays while the first circuit die is actively under test. The pipeline delay configuration data for the second DUT may include data for reconfiguring the first die pipeline output register 24 to have less (i.e., one flip-flop delay value) because additional output delays are introduced through inter-die interconnections when the second circuit die is actively under test. The pipeline delay configuration data configures the second die pipeline output register 24 ′ with one flip-flop delay value. The scan chain result is output from the second die scan chain register to the second die pipeline output register 24', which outputs the result to the first die pipeline output register 24 via the inter-die interconnect. As described above, the shift frequency is selected to ensure sufficient propagation time on the inter-die interconnect. The number of flip-flops in the above example is purely illustrative and should not be considered limiting.

Addressing the ATPG scan pattern vector depth by reusing the same pattern set to test all dies (or the same die) results in a higher ATPG scan shift mode frequency and reduces the overall test time to test all dies during production of packaged devices with multiple dies. Reusing the same pattern set regardless of which die is under test saves vector memory, thus reducing packaged device test costs at production. Additionally, pipeline stages in each homogeneous circuit die reduce the propagation delay between each consecutive flip-flop and increase the ATPG shift mode frequency (i.e., higher frequency, shorter time period), which in turn reduces the actual time to test each device. As described, the test pattern data routing facilitates identical timing regardless of which die is under test.

By configuring the input delays for each pipeline stage based on which die is actively under test in a multi-die package, the same set of ATP patterns can be used in each circuit die because from the test instrument point of view, the number of shift vector cycles is the same regardless of which circuit die is currently under test. For example, if vector depth (VD) = 60M cycles and shift-frequency (F) = 10ns; then the test equipment time (TT) = 60M*10ns = 600ms and is as follows:

Additional implementation example Case 1: If the scan chain test is for 4 chips, and the pipeline register with configurable delay is used to load ATP into each chip, then VD=60*4=240M, F=10ns, TT=2.4 seconds;

Additional Embodiment Case 2: If the scan chain test is performed for 4 chips and the ATP is loaded into the chip individually without pipeline registers, the shift frequency is reduced and the period between clock cycles is increased to 40ns. In this embodiment, VD=60*4=240M, F=40ns, TT=2.4*4 seconds=9.6 seconds. The goal is to increase the shift frequency (F) for all 4 chips in complex cases and reuse the same pattern set.

In this case, VD=60M total, F=10ns, TT=4*60*10=2.4 seconds; In the above case, VD=60M, which is independent of the chip block. In case 1, compared to case 2 above, the shift frequency is F=10ns, where F=40ns due to the pipeline register stage.

In a further exemplary embodiment, 4 dies may be utilized in a packaged device, so by calibrating the test block having 500 as the scan chain length within the design (die). Adding 4 pipeline flip-flops for the scan data input and 4 pipelines (PL) in the scan data output before moving the scan data to/from the test block in the die helps speed up the scan shift mode frequency, where the test block in the die takes 500+4+4=508 as the length; 500 flip-flops from the scan chain of the die under test, 4 flip-flops from the scan data input path, and 4 flip-flops from the scan data output path. The goal is to increase the shift mode frequency, which is limited by the I/O delay and routing delay in the scan data input/output path. By enabling pipeline stages, this can be overcome and the shift mode frequency can be increased. By assuming a pipeline minimum at each die in the scan data input/output path to help increase the frequency of the shift mode ATPG pattern, we can see the solution as follows. - 4(PL/Block0) + 500(Blocks from Block0 under test) + 4(PL/Block0) => Blocks from Block0 under test = length(508, i.e. 508 vector cycles per pattern) - 1(PL/Block0) + 3(PL/Block1) + 500(Blocks from Block1 under test - same blocks as above but different die) + 3(PL/Block1) + 1(PL/Block0) => Same blocks from Block1 under test = length(508) - 1(PL/Block0) + 1(PL/Block1) + 2(PL/Block2) + 500(Blocks from Block2 under test -same block as above but different die) + 2(PL/Block 2) + 1(PL/Block 1) + 1(PL/Block 0) => same block in test Block 2 = length(508) - 1(PL/Block 0) + 1(PL/Block 1) + 1(PL/Block 2) + 1(PL/Block 3) + 500(Block 2 under test -same block as above but different die) + 1(PL/Block 3) + 1(PL/Block 2) + 1(PL/Block 1) + 1(PL/Block 0) => same block in test Block 2 = length(508). By configuring the multiplexers and pipeline stages in each die based on the die under test before applying the ATPG pattern (which is a high-capacity vector cycle), the same set of ATPG patterns can be used and the shift-in/shift-out time (high-frequency shift clock) can be reduced because the shift-in/shift-out data can be safely transferred, which in turn affects the total test time. In the above example, to test one block in the die, it takes 508 * 10000 (i.e., pattern) * 10ns (=shift pattern frequency) = 508ms, where the total test time depends on the shift pattern frequency. The embodiments described herein further reduce test costs by reusing the same ATPG pattern across various homogeneous die.

One or more embodiments disclosed in this specification may be embodied in other forms without departing from its spirit or essential attributes. Therefore, when indicating the scope of one or more embodiments, reference should be made to the following patent application scope rather than the aforementioned specification. One or more embodiments may be implemented in hardware or a combination of hardware and software. One or more embodiments may be implemented in a centralized manner in a system, or in a distributed manner in which different elements are spread across several interconnected systems. Any type of data processing system or other equipment adapted to implement at least a portion of the method described herein is applicable. However, it should be understood that one or more embodiments are merely exemplary. Therefore, the specific structural and functional details disclosed in this specification should not be interpreted as limiting but only as the basis for the scope of the patent application, and as a representative basis for teaching those with ordinary knowledge in the art to adopt one or more embodiments in almost any appropriate detailed structure. Further, the terms and phrases used herein are not intended to be limiting, but to provide an understandable description of one or more embodiments disclosed herein.

10: MCM structure 12: First die 14: Second die 16,16’: Input pin IC package connection 18,18’: Output pin IC package connection 20: IC package 22,22’: Input pipeline register 24,24’: Output pipeline register 26: Scan chain 28: Die scan_in coupling 30: Die scan_out coupling 34: Output pipeline register 36: Scan chain 40: Scan_out port 46: Inter-die interconnection 48: Through-through routing 50: Inter-die channel

Various embodiments according to the present disclosure will be described with reference to the drawings. The same numbers are used throughout the present disclosure and drawings to refer to similar components and features. [FIG. 1] is a block diagram of homogeneous dies in a multi-chip module (MCM) package according to an embodiment of the present invention, for a plurality of n dies/n dies having at least one associated reconfigurable pipeline at a level of a multi-die integrated circuit (IC) structure. [FIG. 2] A diagram showing the pipeline input/output package connections of interconnected dies for displaying a flip-flop (FF) scan chain in a network of a single die, i.e., a central block scan chain of a single die of a multi-die IC structure according to the first die (die) of the block diagram of FIG. 1 with homogeneous dies in its package. [FIG. 3] A reconfigurable input stage for pipeline scan data of a multi-die IC structure is provided for the FF scan chain network of FIG. 2 for each of the dies packaged according to FIG. 1 in accordance with the disclosed embodiments. [FIG. 4] shows an FF scan chain for ATPG testing digital logic of each IC device of FIG. 1 having a homogeneous die according to each of the packaged die. [FIG. 5] provides a reconfigurable pipeline output stage for scan data of a multi-die IC structure according to the disclosed embodiment. [FIG. 6A] and [FIG. 6B] are multiple dies in which at least one reconfigurable pipeline is associated with two (2) identical dies in a simplified manner in a stage, showing channel routing on a substrate, wherein the pipeline FF is located in the scan input/output path, and two interconnected dies are used for a scan chain network IC of a two-die MCM structure. [FIG. 7] shows a first die test of two (2) identical dies, showing the data path highlighted by arrows on the substrate calibrating the channel routing of the scan chain in the first die of the two-die MCM structure according to the present embodiment. [FIG. 8] shows a second die test of two (2) identical dies, showing the data path highlighted by arrows on the substrate calibrating the channel routing of the scan chain in the second die of the two-die MCM structure.

10: MCM structure

12: First grain

14: Second grain

16,16’: Input pin IC package connection

18,18’: Output pin IC package connection

20: IC packaging

22,22’: Input pipeline register

24,24’: Output pipeline register

26: Scan link

28: Grain scan_in coupling

30: grain scan_out coupling

34: Output pipeline register

36: Scan link

40: scan_out port

46: Interconnection between grains

48: Straight-through bypass

50: Inter-grain channel

Claims (21)

A method for testing a multi-chip-module (MCM) using an automated test pattern (ATP), the method comprising: connecting a test instrument to an input pin of the MCM; transmitting pipeline delay configuration data for a first die-under-test (DUT) to configure a first die input pipeline register with a first delay value at a first die of the MCM; and configuring the first die input pipeline register to output the first delay value of the first die input pipeline register within a predetermined number of clock cycles. ATP data is transmitted to a first die scan chain register; the first die is configured with the ATP data to perform a scan chain test; pipeline delay configuration data for a second DUT is transmitted to configure the first die input pipeline register with a second delay value; the ATP data is transmitted to a second die scan chain register of the second DUT in the predetermined number of clock cycles via the reconfigured first die input pipeline register and an inter-die interconnect; and the second DUT is configured with the ATP data to perform a scan chain test. The method of claim 1, wherein the transmitted pipeline delay configuration data for the first DUT configures a multiplexer logic in the first die input pipeline register, the multiplexer logic applying the first delay value to the ATP data by selecting one of a plurality of output connectors. The method of claim 1, wherein the transmitted pipeline configuration data for the second DUT further configures a second die input pipeline register with a third delay value, the second die input pipeline register being located between the inter-die interconnect and the second die scan chain register. The method of claim 1 further comprises transmitting a scan chain clock to the MCM via a clock input pin, the scan chain clock being used to clock the first die input pipeline register and the first die scan chain register. The method of claim 4, wherein the scan chain clock has a frequency associated with a propagation delay of the inter-die interconnect. The method of claim 1, wherein the pipeline delay configuration data for the first DUT further configures a first die output pipeline register on the first die based on the first delay value, and the pipeline delay configuration data for the second DUT further configures the first die output pipeline register on the first die based on the second delay value. The method of claim 6 further comprises capturing a first scan chain result from the scan chain test on the first die from the first die output pipeline register, and capturing a second scan chain result from the scan chain test on the second DUT from the first die output pipeline register, the first scan chain result and the second scan chain result are each captured during a second predetermined number of clock cycles. The method of claim 6, wherein the transmitted pipeline delay data for the first DUT and the transmitted pipeline delay data for the second DUT each include respective data for configuring multiplexing logic in the first die pipeline output register based on the first delay value and the second delay value, respectively. The method of claim 8, wherein the multiplexing logic selects an output connector of the plurality of output connectors of the first die pipeline output register based on the first delay value and the second delay value, respectively. The method of claim 1, further comprising: transmitting pipeline configuration data for a third DUT to the MCM to reconfigure the first die input pipeline register with a third delay value and reconfigure a second die input pipeline register with a fourth delay value; loading the ATP data into a third die scan chain register in the predetermined number of clock cycles via the reconfigured first die input pipeline register, the second die input pipeline register, and an inter-die interconnect between the second DUT and the third DUT; and configuring the third DUT with the ATP data to perform a scan chain test. A method for testing a multi-chip module (MCM) using an automatic test pattern (ATP), the method comprising: configuring a first timing delay from an MCM input pin to a first data path of a first die under test (DUT) by adjusting a delay of at least one first pipeline register with a first delay value at a first die of the MCM; loading an ATP data sequence into the first pipeline register through the first pipeline register; a scan chain register of the first DUT; performing a scan chain test of the first DUT; configuring a second timing delay from the input pin of the MCM through the at least first pipeline register to a second data path of a second DUT by re-adjusting the delay of the first pipeline register; and loading the ATP data sequence into a scan chain register of the second DUT; and performing a scan chain test of the second DUT. The method of claim 11, wherein the first die and the second die are homogeneous, wherein the ATP data applied to the scan chain register of the first die has the same ATP data applied to the scan chain register of the second die according to a defined timing pattern. The method of claim 12, wherein the second timing delay configuration step includes setting a programmable delay by adjusting the delay of the first pipeline register to apply the same ATP data to the second die scan chain register according to the same defined timing pattern. The method of claim 12, wherein the second timing delay configuration step includes reducing the delay of the first pipeline register to apply the same ATP data to the second die scan chain register according to the same defined timing pattern. The method of claim 11, wherein the ATP data includes a defined Automatic Test Pattern Generation (ATPG) data pattern. The method of claim 11, further comprising providing a scan pattern router of the first die connected to the first die input pipeline register, wherein the loading step comprises using the scan pattern router to load the first die scan chain register according to the ATP data having a defined timing pattern to adjust the delay of the first die pipeline register and route the ATP sequence data to a second die. As in the method of claim 16, receiving a retransmission of the ATP sequence data at the first die, and forwarding the retransmitted ATP sequence data to a second die through the first die pipeline register and through the scan pattern router according to the defined timing pattern. A multi-chip module (MCM) test instrument method, the method comprising: configuring a first die input pipeline register at a first die in the MCM with a first delay value having a command from the test instrument; issuing an automatic test pattern (ATP) from the test instrument to load ATP data into a first die scan chain register in a predetermined number of clock cycles via the first delay value of the first die pipeline register; using a read path to the test instrument Performing a scan chain test on the first die using the ATP data; configuring the first die input pipeline register with a second delay value; providing an inter-die interconnect from the first die to a second die of the MCM; loading the ATP data into the second die scan chain register in the predetermined number of clock cycles via the second delay value of the first die pipeline register and the inter-die interconnect; and performing a scan chain test on the second die using the read path to the test instrument. The method of claim 18, further comprising routing an ATP data scan pattern of the first die connecting the first die input pipeline register to the second die input pipeline register, wherein a command from the test instrument reconfigures the inter-die interconnect from the first die to the second die of the MCM to provide a step of loading the same ATP data loaded into the first die scan chain register into the second die scan chain register with the same predetermined number of clock cycles. As in the method of claim 19, a retransmission of the ATP sequence data is received at the first die and forwarded to a second die through the first die pipeline register along with an ATP data scan pattern routing to the sequence data according to a defined timing pattern. A multi-chip module (MCM) comprising a plurality of homogeneous circuit dies interconnected via an inter-die interface, the MCM comprising: an input pin configured to serially receive pipeline delay configurations for a plurality of device under test (DUT) operation modes; a scan chain register on each circuit die of the plurality of homogeneous circuit dies, each scan chain register configured to load an automatic test pattern (ATP) after a predetermined number of clock cycles data, and performing a scan chain test on the ATP data; an input pipeline register configured to receive the pipeline delay configurations for each DUT operation mode, and responsively adjust a configurable delay value of the input pipeline register depending on a current DUT operation mode; and an output pipeline register configured to output a result for each scan chain test based on a configurable delay value, the configurable delay value being set based on the current DUT operation mode.