TWI876621B - Chip packaging structure and method for manufacturing air chamber for protecting chip functional area - Google Patents

Abstract

The chip packaging structure of the present invention includes a substrate, a chip fixed to the substrate, a packaging body and a plurality of electrical connectors. The chip has at least one chip functional area and a plurality of electrical contacts located around the chip functional area; the packaging body is fixed to the substrate and surrounds and covers the chip, and the packaging body has at least one air chamber for accommodating each chip functional area, and a plurality of through holes corresponding to each electrical contact; the electrical connectors are respectively arranged in each through hole of the packaging body, and each electrical connector has an inner end electrically connected to each electrical contact, and an outer end exposed outside the packaging body. Thereby, the processing cost of the chip packaging structure of the present invention is relatively low. In addition, the present invention further provides a method for manufacturing an air chamber for protecting the chip functional area, which can reduce additional processing procedures and is conducive to mass production.

Description

Chip packaging structure and method for manufacturing air chamber for protecting chip functional area

The present invention relates to packaging of surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, RF filters of SAW resonators, and micro-electromechanical sensors, and in particular to a chip packaging structure and a method for manufacturing an air chamber for protecting a chip functional area.

Taiwan Patent Publication No. I720239 discloses an embedded RF filter package structure and a manufacturing method thereof. Referring to FIG. 4 of the aforementioned patent (the following reference numbers are quoted from the aforementioned patent), the filter package structure 10 includes a first dielectric layer 18, a SAW filter 14 disposed on the first dielectric layer 18, an adhesive 24 bonded between the SAW filter 14 and the first dielectric layer 18, a dielectric packaging material 20 covering the SAW filter 14, a plurality of through holes 26 respectively penetrating the first dielectric layer 18 and the adhesive 24, and a plurality of metal interconnects 28 respectively disposed in each through hole 26. The SAW filter 14 has an active region 34, and the SAW filter 14 is adhered to the adhesive 24 with the active region 34 facing downward, so that the active region 34 is accommodated in an air cavity 32 of the adhesive 24, so that the active region 34 of the SAW filter 14 and the piezoelectric substrate (please refer to Figure 1 in the aforementioned patent) generate appropriate vibrations and associated acoustic waves.

However, when manufacturing the filter package structure 10, the adhesive 24 needs to be applied to the dielectric layer 18 by laser ablation or selectively (e.g., inkjet) to form the air cavity 32, and the first dielectric layer 18 and the adhesive layer 24 need to be processed by laser ablation, laser drilling, plasma etching, photolithography or mechanical drilling to form the through holes 26, which makes the manufacturing method more complicated and increases the processing cost. Therefore, the filter package structure 10 and the manufacturing method thereof in the aforementioned patent case still have room for improvement.

In view of the above shortcomings, the main purpose of the present invention is to provide a chip packaging structure with low processing cost.

To achieve the above main purpose, the chip package structure of the present invention includes a substrate, a chip, a package body, and a plurality of electrical connectors. The substrate has a top surface; the chip is fixed to the top surface of the substrate, the chip has a top surface, at least one chip functional area located on the top surface, and a plurality of electrical contacts located on the top surface, and the electrical contacts are located around at least one chip functional area; the package body is fixed to the top surface of the substrate and surrounds and covers the chip, the package body has at least one air chamber and a plurality of through holes, at least one of the air chambers accommodates at least one chip functional area of the chip, and the through holes correspond to each of the electrical contacts respectively; a plurality of electrical connectors are respectively arranged in each of the through holes of the package body, and each of the electrical connectors has an inner end electrically connected to each of the electrical contacts, and an outer end exposed outside the package body.

By virtue of the above technical features, since the package body provided by the chip package structure of the present invention does not need to be processed through additional processing procedures (such as laser ablation, laser drilling, plasma etching, photolithography or mechanical drilling) to form at least one of the air chambers and the through holes one by one, the processing cost of the chip package structure of the present invention is relatively low.

Preferably, the package has a first mold layer and a second mold layer, the first mold layer covers the top surface of the substrate and surrounds the periphery of the chip, and the first mold layer has a plurality of through holes, the second mold layer covers a top surface of the first mold layer and each of the electrical connectors, and forms at least one air chamber between the second mold layer and the first mold layer. In this way, the package is formed by the first and second mold layers, so that the package does not need to be formed by additional processing to form the air chambers and the through holes.

Preferably, the first molded layer has a first sublayer and a second sublayer covering the first sublayer, the first sublayer covers the top surface of the substrate and surrounds the periphery of the chip, the second sublayer has a step, a bottom surface of the step is fixed to the top surface of the chip, and the step is penetrated by the through hole; the second molded layer covers a top surface of the second sublayer and forms at least one air chamber between the second sublayer. In this way, the first molded layer is closely attached to the substrate and the chip through the first and second sublayers.

Preferably, the step of the second sub-layer has an inner wall surface adjacent to the bottom surface, and the inner wall surface and a bottom surface of the second molded layer surround and form at least one air chamber.

Preferably, the outer end of each of the electrical connectors is provided with a solder pad, and the solder pads are used to electrically connect to an external device (such as a printed circuit board).

Another object of the present invention is to provide a method for manufacturing an air chamber for protecting a functional area of a chip, which can reduce additional processing steps and is conducive to mass production.

The manufacturing method of the air chamber for protecting the chip functional area of the present invention comprises the following steps: a) fixing a plurality of chips at intervals on a substrate, each of the chips having at least one chip functional area on its top surface, and a plurality of electrical contacts located on the top surface and around the periphery of each chip functional area; b) forming a first molding layer, the first molding layer covering a top surface of the substrate and surrounding the periphery of each chip, the first molding layer having a plurality of cavities and a plurality of through holes formed by a lithography process, the cavities corresponding to each chip functional area respectively, and the through holes corresponding to each electrical contact respectively; c) fixing a plurality of electrical contacts on the top surface of the substrate, and the plurality of electrical contacts on the top surface of the substrate; The electrical connectors are inserted into each of the through holes; d) forming a second mold layer, the second mold layer covers a top surface of the first mold layer and each of the electrical connectors, the first and second mold layers together form a package body, the package body has a plurality of air chambers corresponding to the functional areas of each chip; e) flattening a top surface of the package body so that each of the electrical connectors has an outer end exposed outside the package body; f) forming a plurality of solder pads on the top surface of the package body, the solder pads are electrically connected to the outer ends of each of the electrical connectors; and g) cutting the substrate and the package body to form a plurality of chip packaging structures.

Through the above-mentioned technical features, the manufacturing method of the present invention forms the package body through the first and second molding layers together, so that the package body does not need to be formed through additional processing to form the air chambers and the through holes. In addition, the manufacturing method of the present invention can also mass-produce the chip packaging structure of the present invention, thereby reducing the manufacturing cost of the chip packaging structure of the present invention.

Preferably, between step f) and step g), there is further included a step of planarizing a bottom surface of the substrate to reduce the thickness of the substrate.

Preferably, in step b), the first molded layer has a first sublayer and a second sublayer covering the first sublayer; the first sublayer covers the top surface of the substrate and surrounds the periphery of each chip, the second sublayer has a plurality of steps, a bottom surface of each step is fixed to the top surface of each chip, and each step is penetrated by the through hole; the second molded layer covers a top surface of the second sublayer. In this way, the first molded layer is closely attached to the substrate and the chip through the first and second sublayers.

Preferably, in step b), each step of the second sublayer has an inner wall surface adjacent to the bottom surface, and each inner wall surface surrounds and forms each cavity. Thus, the size of the cavities can be changed by adjusting the thickness of the second sublayer.

Preferably, in step d), the second molded layer covers a top surface of the second sub-layer and forms each of the air chambers together with each of the inner wall surfaces of the second sub-layer.

The detailed structure, steps and features of the chip packaging structure and the manufacturing method of the gas chamber for protecting the chip functional area provided by the present invention will be described in detail in the subsequent implementation methods. However, those with ordinary knowledge in the field should understand that the detailed description and the specific embodiments listed for implementing the present invention are only used to illustrate the present invention and are not used to limit the scope of the patent application of the present invention.

First of all, it should be noted that the technical features provided by the present invention are not limited to the specific structures, uses and applications described in the embodiments. The terms used in the description are all exemplary descriptive terms that can be understood by ordinary knowledgeable people in the relevant technical fields. The directional descriptive terms such as "front, top, bottom, back, left, right, top, bottom, inside, and outside" mentioned in this manual are only exemplary descriptive terms based on the normal use direction and are not intended to limit the scope of the claims.

Please refer to FIG. 1 . The chip package structure 1 of the present invention includes a substrate 10 , a chip 20 , a package body 30 , a plurality of electrical connectors 40 , and a plurality of bonding pads 50 .

The substrate 10 is an integrally formed plate-like structure having a top surface 11 and a bottom surface 12 opposite to the top surface 11. In the present embodiment, the material of the substrate 10 may be one of the following materials, such as a polyimide film (e.g., Kapton®, Upilex®), polyetherimide (e.g., Ultem®), polytetrafluoroethylene (PTFE for short), a polysulfone material (e.g., Udel®, Radel®), or another polymer film, such as a liquid crystal polymer (LCP for short).

The chip 20 may be (but not limited to) a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, or an RF filter of a SAW resonator, as well as a micro-electromechanical sensor, etc. In this embodiment, the chip 20 is an example of a SAW filter. The chip 20 has a top surface 21, a chip functional area 22 on the top surface 21 (the chip functional area 22 in FIG. 1 is one, but is not limited to one in practice), and a plurality of electrical contacts 23 on the top surface 21. The electrical contacts 23 are located around the chip functional area 22, and the electrical contacts 23 are all solder pads. The chip functional area 22 is an interdigital transducer (IDT), which is used to convert input electrical signals into sound waves. Since IDT is a commonly used SAW filter component, it will not be described in detail here.

The material of the package body 30 may be (but not limited to) a polymer material or an epoxy resin. The package body 30 has a first mold layer 37, and the first mold layer 37 has a first sublayer 371 and a second sublayer 372 covering the first sublayer 371. The first sublayer 371 covers the top surface 11 of the substrate 10 and surrounds the periphery of the chip 20 to protect the structure of the chip 20 from damage. The second sublayer 372 has a There is a step 34, the step 34 has a bottom surface 35 and an inner wall surface 36 adjacent to the bottom surface 35, the second sublayer 372 is fixed to the top surface 21 of the chip 20 with the bottom surface 35 of the step 34, and the second sublayer 372 also has a plurality of through holes H penetrating the step 34, and the through holes H correspond to each electrical contact 23 of the chip 20 respectively. The package body 30 also has a second molded layer 38, which covers the top surface 373 of the second sub-layer 372 and forms an air chamber C between the second molded layer 38 and the inner wall surface 36 of the second sub-layer 372. Since the air chamber C accommodates the chip functional area of the chip, the number of air chambers C depends on the number of chip functional areas 22 (there is one air chamber C in Figure 1, but it is not limited to one in practice).

In this embodiment, the electrical connectors 40 are all metal parts (such as copper pillars), and the electrical connectors 40 are respectively disposed in each through hole H of the package body 30. Each electrical connector 40 has an inner end 41 electrically connected to each electrical contact 23 of the chip 20, and an outer end 42 exposed outside the package body 30.

Each solder pad 50 is disposed on the outer end 42 of each electrical connector 40 for electrically connecting to an external device (eg, a printed circuit board).

The above are the structural features of the chip package structure 1 of the present invention. The manufacturing method of the air chamber for protecting the chip functional area will be further described below. As shown in FIG. 2 , the manufacturing method of the present invention includes the following steps:

As shown in step S1 of FIG. 2 and FIG. 3 , a plurality of chips 20 are fixed to the substrate 10 at intervals, and each chip 20 has at least one chip functional region 22 located on its top surface 21, and a plurality of electrical contacts 23 located on the top surface 21 and at the periphery of each chip functional region 22. In this step, a layer of adhesive (not shown) is applied to the top surface 11 of the substrate 10, and then a plurality of chips 20 (four in this embodiment, which can be changed according to the actual manufacturing quantity) are adhered to the top surface 11 of the substrate 10 at intervals for fixing.

As shown in step S2 of FIG. 2 and FIG. 4 , a first molding layer 37 is formed. The first molding layer 37 covers the top surface 11 of the substrate 10 and surrounds the periphery of each chip 20. The first molding layer 37 has a plurality of cavities O and a plurality of through holes H formed by a lithography process. The cavities O correspond to each chip functional area 22, respectively, and the through holes H correspond to each electrical contact 23, respectively.

In this step, a mold (not shown) is used to heat the packaging material (such as polymer material or epoxy resin) to a molten state, and then the molten material is molded to form a first molded layer 37 in a gel state. The first molding layer 37 has a first sublayer 371 and a second sublayer 372 covering the first sublayer 371. The first sublayer 371 covers the top surface 11 of the substrate 10 and surrounds the periphery of the chip 20. The second sublayer 372 has a step 34. The step 34 has a bottom surface 35 and an inner wall surface 36 adjacent to the bottom surface 35. The bottom surface 35 of the step 34 is fixed to the top surface 21 of the chip 20. The inner wall surface 36 of the step 34 surrounds to form an open cavity O. Each cavity O corresponds to the chip functional area 22 of each chip 20. The size of each cavity O can be adjusted by adjusting the thickness of the second sublayer 372. In addition, the second sub-layer 372 also has a plurality of through holes H penetrating the step 34, and the through holes H respectively correspond to the electrical contacts 23 of the chip 20. It should be noted that the second sub-layer 372 can form the cavities O and the through holes H at one time through a lithography process, so the processing time can be greatly reduced. The lithography process is a common procedure in semiconductor manufacturing, so it will not be described here.

As shown in step S3 of FIG. 2 and FIG. 5 , a plurality of electrical connectors 40 are respectively inserted into each through hole H, so that the inner end 41 of each electrical connector 40 is respectively electrically connected to each electrical contact 23 .

As shown in step S4 of FIG. 2 and FIG. 6 , a second mold layer 38 is formed, and the second mold layer 38 covers a top surface 373 of the first mold layer 37 and each electrical connector 40. The first and second mold layers 37 and 38 together form a package body 30, and the package body 30 has a plurality of air chambers C corresponding to each chip functional area 22.

In this step, another mold (not shown) is used to heat a packaging material (such as a polymer material or epoxy resin) that is the same as the first mold layer 37 to a molten state, and then the molten material is molded to form a second mold layer 38 in a gel state. The second mold layer 38 has a top surface 381 and a bottom surface opposite to the top surface 381. The second molded layer 38 covers the top surface 373 of the second sub-layer 372 (i.e., the top surface 373 of the first molded layer 37) and each electrical connector 40 with the bottom surface 382, so that a closed air chamber C is formed between the bottom surface 382 of the second molded layer 38 and each inner wall surface 36 of the second sub-layer 372 (as shown in FIG. 6).

As shown in step S5 of FIG. 2 and FIG. 7 , the top surface 381 of the package body 30 is flattened so that each electrical connector 40 has an outer end 42 exposed outside the package body 30. In this step, a grinder (not shown) is used to grind and remove excess material from the top surface 381 of the package body 30 (i.e., the top surface 381 of the second molding layer 38), so that the top surface 381 of the package body 30 remains flat until the outer end 42 of each electrical connector 40 is exposed outside the package body 30.

As shown in step S6 of FIG. 2 and FIG. 8 , a plurality of solder pads 50 are formed on the top surface 381 of the package body 30, and the solder pads 50 are respectively electrically connected to the outer ends 42 of the electrical connectors 40. In this step, the solder pads 50 may be (but not limited to) solder bumps.

As shown in step S7 of FIG. 2 and FIG. 9 , the bottom surface 12 of the substrate 10 is planarized to reduce the thickness of the substrate 10. In this step, a grinder is also used to grind and remove excess material from the bottom surface 12 of the substrate 10, so that the bottom surface 12 of the substrate 10 remains flat.

As shown in step S8 of FIG. 2 and FIG. 10 , the substrate 10 and the package body 30 are cut to form a plurality of chip package structures 1 , thus completing the entire processing steps.

In summary, the manufacturing method of the present invention forms the package body 30 by the first and second mold layers 37 and 38 together, so that the package body 30 does not need to go through additional processing procedures (such as laser ablation, laser drilling, plasma etching, photolithography or mechanical drilling, etc.) to form the air chambers C and the through holes H, so that the overall processing steps are simpler and easier to achieve, and the chip package structure 1 of the present invention has a lower processing cost. In addition, since the manufacturing method of the present invention can mass-produce the chip package structure 1 of the present invention, the manufacturing cost of the chip package structure 1 of the present invention is reduced.

1: Chip packaging structure

10: Substrate

11: Top

12: Bottom

20: Chip

21: Top

22: Chip functional area

23: Electrical contacts

30: Package

34: Class

35: Bottom

36: Inner wall

37: First molding layer

371: First sublayer

372: Second sublayer

373: Top

38: Second molding layer

381: Top

382: Bottom

40: Electrical connector

41: Inner

42: Outer end

50:Welding pad

C: Air chamber

H:Through hole

S1-S8: Steps

O: Cavity

The following is a further description of the chip packaging structure and the manufacturing method of the air chamber for protecting the chip functional area provided by the present invention with the help of an embodiment and drawings, wherein: FIG. 1 is a cross-sectional view of the chip packaging structure of the present invention; FIG. 2 is a flow chart of the manufacturing method of the air chamber for protecting the chip functional area of the present invention; FIG. 3 is a cross-sectional view showing that a plurality of chips are fixed to a substrate at intervals; FIG. 4 is a continuation of FIG. 3, showing the formation of a first molded layer covering the substrate; FIG. 5 is a continuation of FIG. 4, showing that a plurality of electrical connectors are respectively inserted into each through hole; FIG. 6 is a continuation of FIG. 5, showing the formation of a second molded layer covering the first molded layer and each electrical connector; FIG. 7 is a continuation of FIG. 6, showing a top surface of a package body being flattened so that each electrical connector has an outer end exposed outside the package body; FIG. 8 is a continuation of FIG. 7, showing a plurality of solder pads formed on the top surface of the package body; FIG. 9 is a continuation of FIG. 8, showing a bottom surface of a substrate being flattened to reduce the thickness of the substrate; and FIG. 10 is a continuation of FIG. 9, showing a substrate and a package body being cut to form a plurality of chip package structures.

1: Chip packaging structure

10: Substrate

11: Top

12: Bottom

20: Chip

21: Top

22: Chip functional area

23: Electrical contacts

30:Package

34: Class

35: Bottom

36: Inner wall

37: First molding layer

371: First sublayer

372: Second sublayer

373: Top

38: Second molding layer

40: Electrical connectors

41: Inner end

42: Outer end

50: Solder pad

C: Air chamber

H:Through hole

Claims (9)

A chip packaging structure includes: a substrate having a top surface; a chip fixed to the top surface of the substrate, the chip having a top surface, at least one chip functional area located on the top surface, and a plurality of electrical contacts located on the top surface, and the electrical contacts are located around at least one chip functional area; a packaging body fixed to the top surface of the substrate and surrounding and covering the chip, the packaging body having at least one air chamber and a plurality of through holes, at least one of the air chambers accommodating at least one chip functional area of the chip, and the through holes respectively corresponding to each of the electrical contacts ; and a plurality of electrical connectors, respectively disposed in each of the through holes of the package body, and each of the electrical connectors has an inner end electrically connected to each of the electrical contacts, and an outer end exposed outside the package body; wherein the package body has a first molded layer and a second molded layer, the first molded layer covers the top surface of the substrate and surrounds the periphery of the chip, and the first molded layer has a plurality of the through holes, the second molded layer covers a top surface of the first molded layer and each of the electrical connectors, and forms at least one of the air chambers between the second molded layer and the first molded layer. The chip packaging structure as described in claim 1, wherein the first molded layer has a first sublayer and a second sublayer covering the first sublayer, the first sublayer covers the top surface of the substrate and surrounds the periphery of the chip, the second sublayer has a step and a plurality of through holes, a bottom surface of the step is fixed to the top surface of the chip and is penetrated by a plurality of through holes; the second molded layer covers a top surface of the second sublayer and forms at least one air chamber between the second sublayer and the second sublayer. The chip packaging structure as described in claim 2, wherein the step of the second sub-layer has an inner wall surface adjacent to the bottom surface, and the inner wall surface and a bottom surface of the second molded layer surround and form at least one of the air chambers. A chip package structure as described in claim 1, wherein each of the outer ends of the electrical connector is provided with a solder pad. A method for manufacturing an air chamber for protecting a chip functional area comprises the following steps: a) fixing a plurality of chips at intervals on a substrate, each of the chips having at least one chip functional area on its top surface, and a plurality of electrical contacts located on the top surface and around each chip functional area; b) forming a first mold layer, the first mold layer covering a top surface of the substrate and surrounding each chip, the first mold layer having a plurality of cavities and a plurality of through holes formed by a lithography process, the cavities corresponding to each chip functional area, and the through holes corresponding to each electrical contact; c) connecting a plurality of electrical connectors to the substrate; d) forming a second molded layer, the second molded layer covers a top surface of the first molded layer and each of the electrical connectors, the first and second molded layers together form a package body, the package body has a plurality of air chambers corresponding to each of the chip functional areas; e) flattening the top surface of the package body so that each of the electrical connectors has an outer end exposed outside the package body; f) forming a plurality of solder pads on the top surface of the package body, the solder pads are electrically connected to the outer ends of each of the electrical connectors; and g) cutting the substrate and the package body to form a plurality of chip package structures. The manufacturing method as described in claim 5, wherein between step f) and step g), there is further included a step of flattening a bottom surface of the substrate to reduce the thickness of the substrate. The manufacturing method as described in claim 5, wherein in step b), the first molded layer has a first sublayer and a second sublayer covering the first sublayer; the first sublayer covers the top surface of the substrate and surrounds the periphery of each of the chips, the second sublayer has a plurality of steps and a plurality of through holes, a bottom surface of each of the steps is fixed to the top surface of each of the chips and penetrated by a plurality of through holes; the second molded layer covers a top surface of the second sublayer. The manufacturing method as described in claim 7, wherein in the step b), each step of the second sublayer has an inner wall surface adjacent to the bottom surface, and each inner wall surface surrounds and forms each cavity. A manufacturing method as described in claim 8, wherein in the step b), each inner wall surface of the second sub-layer and a bottom surface of the second molded layer surround and form each air chamber.

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