TWI874852B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a gate electrode disposed on a substrate. A source region and a drain region are disposed in the substrate, respectively located on two sides of the gate electrode, where the drain region includes a plurality of drain segments that are laterally spaced apart from each other, the drain segments have a first conductive type and the substrate has a second conductive type. A plurality of drain contacts is electrically connected to the plurality of drain segments, where each drain segment corresponds to at least one of the drain contacts. A drain electrode is electrically connected to the plurality of drain contacts, and a source electrode is electrically connected to the source region.

Description

Semiconductor devices

The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices having electrostatic protection capabilities.

In order to prevent the integrated circuit from being damaged by electrostatic discharge (ESD) during the manufacturing process and/or use, an ESD protection component is usually installed in the integrated circuit, which provides an ESD current path to prevent the current from flowing into the internal circuit of the integrated circuit and causing damage during electrostatic discharge. Generally speaking, under normal operation of the integrated circuit, the ESD protection component is turned off, and when an ESD event occurs, the ESD protection component will be turned on.

Since no component can be turned on faster than the initial-on component, conventional ESD protection components cannot effectively protect the initial-on component. In addition, for ESD protection of ultra-high voltage (UHV) components, adding ESD protection components will increase the layout area, which is not conducive to the demand for miniaturization of component size.

In view of this, the present disclosure proposes a semiconductor device that divides the drain region into a plurality of drain blocks, which are laterally separated from each other and electrically connected to the drain electrode in parallel through a plurality of drain contacts, wherein each drain contact corresponds to each drain block. In this way, the current can be dispersed to the entire drain region during electrostatic discharge, thereby improving the ESD protection capability of the initial-on type semiconductor device itself without increasing the layout area of the semiconductor device.

According to an embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a gate electrode, a source region, a drain region, a plurality of drain contacts, a drain electrode and a source electrode. The gate electrode is disposed on the substrate, the source region and the drain region are disposed in the substrate, and are respectively located on both sides of the gate electrode, wherein the drain region includes a plurality of drain blocks laterally separated from each other, the drain blocks have a first conductivity type, and the substrate has a second conductivity type. A plurality of drain contacts are disposed on the drain region and electrically connected to the drain blocks, wherein each drain block corresponds to at least one drain contact, the drain electrode is electrically connected to the drain contacts, and the source electrode is electrically connected to the source region.

In order to make the features of the present disclosure clear and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and layouts. The purpose of providing these embodiments is only for illustration and not for any limitation. For example, the description below of "a first feature is formed on or above a second feature" may mean "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, and are not used to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in the present disclosure, such as "under", "low", "down", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they themselves do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupled", "coupled", and "electrically connected" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

Although the invention disclosed herein is described below by means of specific embodiments, the inventive principles of the invention disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and the omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure is related to the improvement of the electrostatic discharge (ESD) protection capability of an initially conductive semiconductor device. In an embodiment of the present disclosure, a drain region is divided into a plurality of drain blocks laterally separated from each other, and a plurality of drain contacts are electrically connected to the drain region, wherein each drain block corresponds to at least one drain contact, and these drain contacts are electrically connected to the drain electrode in parallel, so that the ESD current can be dispersed to the entire drain region, thereby improving the ESD protection capability of the semiconductor device itself, and will not increase the layout area of the semiconductor device.

FIG. 1 is a schematic top view of a semiconductor device 100 according to an embodiment of the present disclosure. In one embodiment, in a top view layout, the semiconductor device 100 includes a drain electrode 110 having a circular area disposed on a substrate 101, a gate electrode 120 is also disposed on the substrate 101 and is an annular area surrounding the drain electrode 110, and a source electrode 130 is also disposed on the substrate 101 and is another annular area surrounding the gate electrode 120. The semiconductor device 100 further includes a source region 132 and a drain region 112 disposed in the substrate 101 and respectively located on both sides of the gate electrode 120, wherein the distance between the drain region 112 and the gate electrode 120 is greater than the distance between the source region 132 and the gate electrode 120. According to some embodiments of the present disclosure, the drain region 112 includes a plurality of drain blocks 112P laterally separated from each other. In one embodiment, as shown in FIG. 1 , in a top view layout, the drain blocks 112P are, for example, a plurality of circular blocks separated from each other. In addition, a plurality of drain contacts 113P are disposed on the drain region 112 and electrically connected to the drain blocks 112P, wherein each drain block 112P corresponds to at least one of the drain contacts 113P, that is, each drain block 112P may correspond to one or more drain contacts 113P, and the drain contacts 113P are electrically connected in parallel to the drain electrode 110. In the top view, the drain blocks 112P and the drain contacts 113P are located within the circular block of the drain electrode 110.

As shown in FIG. 1 , in the top view layout, the gate electrode 120 can be electrically connected to a gate contact region 122 located in the substrate 101 via at least one annular gate contact 123 (i.e., one or more annular gate contacts 123 ), and the gate electrode 120 can also be electrically connected to a field plate (not shown) via a plurality of contacts 124 , and the aforementioned one or more annular gate contacts 123 and these contacts 124 are located within the range of the annular block of the gate electrode 120 . In addition, the source electrode 130 may be electrically connected to the source region 132 located in the substrate 101 via at least one annular source contact 133 (ie, one or more annular source contacts 133 ), and the one or more annular source contacts 133 are located within the range of the annular region of the source electrode 130 . In addition, a first isolation region 151 is disposed between the gate contact region 122 and the drain region 112, and a second isolation region 152 is disposed between the gate contact region 122 and the source region 132. In some embodiments, the first isolation region 151 and the second isolation region 152 may be an annular field oxide (FOX) or an annular shallow trench isolation (STI).

FIG. 2 is a schematic cross-sectional view of a semiconductor device 100A along the cross-sectional cut line AA of FIG. 1 according to an embodiment of the present disclosure. In one embodiment, the semiconductor device 100A is a junction field effect transistor (JFET), which is an initial-on type semiconductor device. As shown in FIG. 2, the semiconductor device 100A includes a first well region 103 disposed in a substrate 101, the first well region 103 has a first conductivity type, such as a high voltage n-type well region (HVNW), and the substrate 101 has a second conductivity type opposite to the first conductivity type, such as a p-type silicon substrate (PSUB). The source region 132 and the drain region 112 are disposed in the first well region 103, and both the source region 132 and the drain region 112 have a first conductivity type, for example, an N-type heavily doped region (n ⁺ ), wherein the source region 132 is electrically connected to the source electrode 130 via a source contact 133, and the drain region 112 is electrically connected to the drain electrode 110 via a plurality of drain contacts 113P. In order to make the diagram clear and easy to understand, FIG. 2 only shows a simplified form of the drain region 112 and the drain contact 113P, and the detailed structure of the frame area C can be found in the descriptions of the subsequent FIG. 3 and FIG. 4.

In addition, the semiconductor device 100A further includes a second well region 105 disposed in the first well region 103, the second well region 105 having a second conductivity type, such as a p-type well region (PW), a gate contact region 122 disposed in the second well region 105, and the gate contact region 122 having a second conductivity type, such as a p-type heavily doped region (P ⁺ ), and the gate contact region 122 being electrically connected to the gate electrode 120 via the gate contact 123. In addition, a first isolation region 151 is disposed between the drain region 112 and the gate contact region 122, and the first isolation region 151 surrounds the drain region 112. The second isolation region 152 is disposed between the source region 132 and the gate contact region 122, and the second isolation region 152 surrounds the gate contact region 122. In one embodiment, the first isolation region 151 and the second isolation region 152 may both be field oxide layers (FOX) and are located on the first well region 103.

In addition, the semiconductor device 100A further includes a field plate 126 disposed on the first isolation region 151 , and the field plate 126 is electrically connected to the gate electrode 120 via the contact 124 . In one embodiment, the field plate 126 may be formed of polysilicon. In addition, the semiconductor device 100A further includes a third well region 107 disposed in the substrate 101 and adjacent to the first well region 103, the third well region 107 having a second conductivity type, such as a P-type well region (PW), a bulk contact region 142 disposed in the third well region 107 and having a second conductivity type, such as a P-type heavily doped region (P ⁺ ), the bulk contact region 142 being electrically connected to a bulk electrode 140 via a bulk contact 143, wherein the source electrode 130 is located between the bulk electrode 140 and the gate electrode 120. In addition, the third isolation region 153 is disposed between the substrate contact region 142 and the source region 132, and the third isolation region 153 surrounds the source region 132. The fourth isolation region 154 is disposed outside the substrate contact region 142 and surrounds the substrate contact region 142. In one embodiment, the third isolation region 153 and the fourth isolation region 154 may both be field oxide layers (FOX), wherein the third isolation region 153 is located at the junction of the first well region 103 and the third well region 107, and the fourth isolation region 154 is located on the third well region 107. In some embodiments, the bottom surface of the first well region 103 is lower than the bottom surface of the second well region 105 and the bottom surface of the third well region 107, the second well region 105 and the third well region 107 are spaced apart laterally, for example, spaced apart from each other along the X-axis direction, and a portion of the first well region 103 is located between the second well region 105 and the third well region 107. In this embodiment, the semiconductor device 100A is an n-channel junction field effect transistor, and when no voltage is applied to the gate electrode 120, the channel region CH between the source region 132 and the drain region 112 is conductive, that is, the junction field effect transistor is an initially conductive semiconductor device.

FIG. 3 is a partial cross-sectional schematic diagram of the semiconductor device 100A in the frame area C of FIG. 2 according to an embodiment of the present disclosure. As shown in FIG. 3, in one embodiment, the drain region 112 of the semiconductor device 100A includes a plurality of drain blocks 112P that are laterally separated from each other. These drain blocks 112P have a first conductivity type, such as an N-type heavily doped region (N ⁺ ). A plurality of isolation blocks 150P are disposed in the drain region 112 and are respectively located between adjacent drain blocks 112P. These drain blocks 112P can be separated from each other by these isolation blocks 150P. In some embodiments, the isolation blocks 150P may be a field oxide layer (FOX) or a shallow trench isolation region (STI). The isolation blocks 150P and the drain blocks 112P are both disposed in the first well region 103, and the bottom surface of the drain block 112P may be lower than the bottom surface of the isolation block 150P. In one embodiment, in a top view layout, the isolation blocks 150P may form a grid structure, and the drain blocks 112P are located in the grid of the grid structure. In one embodiment, the isolation blocks 150P may be formed in the first well region 103, and in the ion implantation process for forming the drain blocks 112P, the grid structure formed by the isolation blocks 150P may be used as a mask for the ion implantation. In addition, the semiconductor device 100A further includes a plurality of drain contacts 113P, which are electrically connected to the drain blocks 112P, wherein each drain block 112P corresponds to at least one drain contact 113P, and the drain contacts 113P are electrically connected to the drain electrode 110 in parallel.

FIG. 4 is a partial cross-sectional schematic diagram of the semiconductor device 100A in the frame area C of FIG. 2 according to another embodiment of the present disclosure. The difference between FIG. 4 and FIG. 3 is that in the embodiment of FIG. 4, no isolation block is set between the multiple drain blocks 112P that are laterally separated from each other. In the ion implantation process for forming these drain blocks 112P, a patterned mask can be used to separate these drain blocks 112P from each other in the first well area 103. In addition, a plurality of drain contacts 113P are electrically connected to the drain blocks 112P, respectively, wherein each drain block 112P corresponds to at least one drain contact 113P, and the drain contacts 113P are electrically connected to the drain electrode 110 in parallel.

According to some embodiments of the present disclosure, the drain region 112 of the semiconductor device 100 is divided into a plurality of drain blocks 112P laterally separated from each other, each of the drain blocks 112P may correspond to and be electrically connected to at least one drain contact 113P, these drain blocks 112P are electrically connected to the drain electrode 110 in parallel via these drain contacts 113P, and each drain block 112P may be regarded as a small resistor. When electrostatic discharge (ESD) occurs, the small resistor formed by each drain block 112P can play a role in independently withstanding ESD energy, and the ESD current can be evenly conducted to each drain block 112P through each drain contact 113P, so that the ESD current is dispersed to each drain block 112P, making the potential of the entire drain area 112 smaller. Therefore, the ability of the semiconductor device disclosed in the present invention to withstand ESD is improved, thereby obtaining better ESD protection capability.

In addition, according to some embodiments of the present disclosure, the ESD protection mechanism of the semiconductor device 100 is kept in the open state under normal operation, so for the initial conduction type semiconductor device, there will be no problem of the ESD protection element turning on slowly. In addition, according to some embodiments of the present disclosure, the ESD protection element of the semiconductor device 100 is provided by a plurality of drain blocks 112P, so the ESD protection element does not occupy the layout area of the semiconductor device, which is conducive to the miniaturization of the element size, and the semiconductor device of the present disclosure has its own ESD protection capability, which is conducive to the application of ultra-high voltage (UHV) elements.

FIG. 5 is a cross-sectional schematic diagram of a semiconductor device 100B according to another embodiment of the present disclosure. In one embodiment, the semiconductor device 100B is a depletion mode metal oxide semiconductor field effect transistor (D-mode MOSFET), which is an initially conductive semiconductor device. As shown in FIG. 5 , the semiconductor device 100B includes a first well region 103 disposed in a substrate 101. The first well region 103 has a first conductivity type, such as a high voltage N-type well region (HVNW), and the substrate 101 has a second conductivity type opposite to the first conductivity type, such as a P-type silicon substrate (PSUB). The drain region 112 is disposed in the first well region 103, and the drain region 112 has a first conductivity type, for example, an N-type heavily doped region (N ⁺ ). The drain region 112 is electrically connected to the drain electrode 110 via a plurality of drain contacts 113P. In order to make the diagram clear and easy to understand, FIG5 only shows a simplified version of the drain region 112 and the drain contacts 113P. The detailed structure of the framed area C can be found in the descriptions of the aforementioned FIGS. 3 and 4. Referring to FIGS. 3 and 5 , in one embodiment, the drain region 112 of the semiconductor device 100B includes a plurality of drain blocks 112P laterally separated from each other. The drain blocks 112P have a first conductivity type, such as an N-type heavily doped region (N ⁺ ). A plurality of isolation blocks 150P are disposed in the drain region 112 and are respectively located between adjacent drain blocks 112P. The isolation blocks 150P can separate the drain blocks 112P from each other. Referring to FIG. 4 and FIG. 5 , in another embodiment, no isolation block is provided between the plurality of drain blocks 112P that are laterally separated from each other in the drain region 112 of the semiconductor device 100B, and these drain blocks 112P are separated from each other in the first well region 103. In addition, the semiconductor device 100B further includes a plurality of drain contacts 113P that are electrically connected to these drain blocks 112P, wherein each drain block 112P corresponds to at least one drain contact 113P, and these drain contacts 113P are electrically connected to the drain electrode 110 in parallel.

Still referring to FIG. 5 , the semiconductor device 100B further includes a second well region 105 disposed in the substrate 101, the second well region 105 having a second conductivity type, such as a P-type well region (PW), and the second well region 105 is adjacent to the first well region 103, wherein the bottom surface of the first well region 103 is lower than the bottom surface of the second well region 105. In addition, a source region 132 is disposed in the second well region 105, the source region 132 having a first conductivity type, such as an N-type heavily doped region (N ⁺ ), and the source region 132 is electrically connected to the source electrode 130 via a source contact 133. In addition, the first isolation region 151 is disposed on the first well region 103 and surrounds the drain region 112. The gate electrode 120 spans the first well region 103 and the second well region 105. A portion of the gate electrode 120 extends from a side surface of the first isolation region 151 to a top surface of the first isolation region 151, and another portion of the gate electrode 120 is adjacent to the source region 132. In one embodiment, the gate electrode 120 may be formed of polysilicon. The drain region 112 and the gate electrode 120 are laterally spaced apart by a distance, and the first isolation region 151 is located between the drain region 112 and the gate electrode 120 , wherein the distance between the drain region 112 and the gate electrode 120 is greater than the distance between the source region 132 and the gate electrode 120 . In addition, the semiconductor device 100B further includes a body contact region 142 disposed in the second well region 105, the body contact region 142 has a second conductivity type, for example, a P-type heavily doped region (P ⁺ ), the body contact region 142 is electrically connected to the body electrode 140 via a body contact 143, wherein the source region 132 is located between the body contact region 142 and the gate electrode 120. In addition, a third isolation region 153 is disposed between the source region 132 and the body contact region 142, a fourth isolation region 154 is disposed outside the body contact region 142, and the third isolation region 153 and the fourth isolation region 154 are located on the second well region 105. In some embodiments, the first isolation region 151, the third isolation region 153, and the fourth isolation region 154 are, for example, field oxide layers (FOX) or shallow trench isolation regions (STI). In this embodiment, the semiconductor device 100B is an n-channel depletion-type MOSFET. When no voltage is applied to the gate electrode 120, the source region 132 and the drain region 112 can be conductive via the N-type channel region CH, that is, the depletion-type MOSFET is an initially conductive semiconductor device.

FIG. 6 is a schematic top view of a semiconductor device 200 according to another embodiment of the present disclosure. The difference between the semiconductor device 200 in FIG. 6 and the semiconductor device 100 in FIG. 1 is that the drain region 114 of the semiconductor device 200 in FIG. 6 is a circular block, the drain region 114 is not divided into a plurality of blocks, a plurality of drain contacts 115 correspond to and are electrically connected to the same block of the drain region 114, and the drain region 114 is electrically connected to the drain electrode 110 via these drain contacts 115. For other features of the semiconductor device 200 of FIG. 6 , such as the gate electrode 120 , the gate contact region 122 , the gate contact 123 , the contact 124 , the source electrode 130 , the source region 132 , the source contact 133 , the first isolation region 151 and the second isolation region 152 , reference can be made to the description of FIG. 1 mentioned above.

FIG. 7 is a partial cross-sectional schematic diagram of a semiconductor device 200 along the cross-sectional cutting line B-B of FIG. 6 according to another embodiment of the present disclosure. As shown in FIG. 7 , the drain region 114 of the semiconductor device 200 is a block surrounded by the first isolation region 151, and a plurality of drain contacts 115 correspond to and are electrically connected to the same block of the drain region 114, and these drain contacts 115 are electrically connected to the drain electrode 110. In the semiconductor device 200, when electrostatic discharge (ESD) occurs, a few drain contacts 115 located at the edge of the drain region 114 are more susceptible to being attacked by the ESD current and burned than the drain contacts 115 at other locations (e.g., the center region of the drain region 114). Through the electrostatic discharge test of the human body mode (HBM) 4000 volts (4kV), it can be seen that the few drain contacts 115 located at the edge of the drain region 114 of the semiconductor device 200 of FIG. 6 will be burned by the current and appear in a charred state. All drain contacts 113P of the drain region 112 of the semiconductor device 100 in FIG. 1 are evenly distributed and appear to be charred, which means that each drain contact 113P of the semiconductor device 100 in FIG. 1 will disperse the ESD current, while only a few drain contacts 115 located at the edge of the drain region 114 of the semiconductor device 200 in FIG. 6 will disperse the ESD current. Therefore, according to some embodiments of the present disclosure, the semiconductor device 100 including a plurality of drain blocks 112P laterally separated from each other can have better and more uniform ESD current dispersion capability, thereby obtaining better ESD protection capability, which is suitable for ultra-high voltage (UHV) components, such as UHV components greater than 200V to 1000V.

FIG. 8 is a waveform diagram of the drain voltage V _D versus time of the semiconductor device 200 in FIG. 6 of an embodiment of the present disclosure under a 200V electrostatic discharge test of the human body discharge mode (HBM), wherein the vertical axis is the drain voltage V _D (unit is volt (V)), and the horizontal axis is the time (unit is millisecond (ms)). As shown in FIG. 8, the peak voltage of the HBM waveform of the semiconductor device 200 in FIG. 6 is 120V, and the pulse width of the HBM waveform is 2 ms.

FIG. 9 is a waveform diagram of the drain voltage V _D versus time of the semiconductor device 100 of FIG. 1 in an embodiment of the present disclosure under a 200V electrostatic discharge test of the human body discharge mode (HBM), wherein the vertical axis is the drain voltage V _D (unit is volt (V)), and the horizontal axis is the time (unit is nanosecond (ns)). As shown in FIG. 9, the peak voltage of the HBM waveform of the semiconductor device 100 of FIG. 1 is 11V, and the pulse width of the HBM waveform is 400ns.

As can be seen from the comparison between FIG. 8 and FIG. 9, compared to the semiconductor device 200 of FIG. 6, according to some embodiments of the present disclosure, when the semiconductor device 100 including a plurality of drain blocks 112P separated laterally from each other is subjected to ESD, the peak voltage of the HBM waveform is lower (from 120V to 11V), and the pulse width is narrower (from 2 ms to 400 ms). ns), which proves that the semiconductor device 100 of some embodiments of the present disclosure can effectively reduce the energy occurring in the drain and make the potential of the drain smaller. Therefore, the semiconductor device 100 of some embodiments of the present disclosure can disperse the energy of ESD in the drain by a plurality of drain blocks 112P separated laterally from each other to obtain a higher ESD protection capability.

The semiconductor device of the embodiment disclosed herein includes a plurality of drain blocks separated laterally from each other, which can be used as the ESD protection element of the semiconductor device itself, and will not occupy the layout area, which is conducive to the miniaturization of the element size, and will not have the problem of the known ESD protection element turning on slower than the initial conduction type semiconductor device. In addition, these drain blocks can be used as small resistors, which are electrically connected to the drain electrode in parallel through their respective drain contacts, thereby dispersing the ESD current, so that the semiconductor device disclosed herein has an improved ability to withstand ESD and obtains better ESD protection capability, which is conducive to the application of ultra-high voltage (UHV) components. The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

100, 100A, 100B, 200: semiconductor device 101: substrate 103: first well region 105: second well region 107: third well region 110: drain electrode 112, 114: drain region 112P: drain block 113P, 115: drain contact 120: gate electrode 122: gate contact region 123: gate contact 124: contact 126: field plate 130: source electrode 132: source region 133: source contact 140: substrate electrode 142: substrate contact area 143: substrate contact 150P: isolation block 151: first isolation area 152: second isolation area 153: third isolation area 154: fourth isolation area C: frame area CH: channel area

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to at the same time when reading this disclosure. Through the specific embodiments in this article and referring to the corresponding drawings, the specific embodiments of the disclosure are explained in detail, and the working principle of the specific embodiments of the disclosure is explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced. Figure 1 is a schematic top view of a semiconductor device drawn according to an embodiment of the disclosure. Figure 2 is a schematic cross-sectional view of a semiconductor device drawn along the cross-sectional tangent line A-A of Figure 1 according to an embodiment of the disclosure. FIG. 3 is a partial cross-sectional schematic diagram of a semiconductor device in the frame area C of FIG. 2 according to an embodiment of the present disclosure. FIG. 4 is a partial cross-sectional schematic diagram of a semiconductor device in the frame area C of FIG. 2 according to another embodiment of the present disclosure. FIG. 5 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present disclosure. FIG. 6 is a top view schematic diagram of a semiconductor device according to another embodiment of the present disclosure. FIG. 7 is a partial cross-sectional schematic diagram of a semiconductor device along the cross-sectional tangent line B-B of FIG. 6 according to another embodiment of the present disclosure. FIG. 8 is a waveform diagram of the drain voltage corresponding to time of the semiconductor device of FIG. 6 of an embodiment of the present disclosure under the human body discharge mode test. Figure 9 is a waveform diagram showing the drain voltage versus time of the semiconductor device in Figure 1 of an embodiment of the present disclosure under the human body discharge mode test.

100: semiconductor device 101: substrate 110: drain electrode 112: drain region 112P: drain block 113P: drain contact 120: gate electrode 122: gate contact region 123: gate contact 124: contact 126: field plate 130: source electrode 132: source region 133: source contact 151: first isolation region 152: second isolation region

Claims (18)

A semiconductor device comprises: A gate electrode disposed on a substrate; A source region and a drain region disposed in the substrate and respectively located on both sides of the gate electrode, wherein the drain region comprises a plurality of drain blocks laterally separated from each other, the drain blocks have a first conductivity type, and the substrate has a second conductivity type; A plurality of isolation blocks are disposed in the drain region and respectively located between the adjacent drain blocks; A plurality of drain contacts are disposed on the drain region, wherein each of the drain blocks corresponds to at least one of the drain contacts; A drain electrode electrically connected to the drain contacts, wherein the drain contacts are electrically connected to the drain electrode in parallel; and A source electrode electrically connected to the source region, wherein in a top view layout, the gate electrode includes an annular block surrounding the drain electrode, and the source electrode includes another annular block surrounding the gate electrode. A semiconductor device as described in claim 1, wherein the isolation blocks include field oxide layers or shallow trench isolation regions. A semiconductor device as described in claim 1, wherein the distance between the drain region and the gate electrode is greater than the distance between the source region and the gate electrode. The semiconductor device as described in claim 1 is an initially conductive element and includes a junction field effect transistor or a depletion metal oxide semiconductor field effect transistor. The semiconductor device as described in claim 1 is a junction field effect transistor and further comprises: a first well region disposed in the substrate and having the first conductivity type, wherein the source region and the drain region are disposed in the first well region; a second well region disposed in the first well region and having the second conductivity type; and a gate contact region disposed in the second well region, having the second conductivity type and electrically connected to the gate electrode. The semiconductor device as described in claim 5 further includes: a first isolation region disposed between the drain region and the gate contact region; a field plate disposed on the first isolation region, wherein the field plate is electrically connected to the gate electrode; and a second isolation region disposed between the source region and the gate contact region. The semiconductor device as described in claim 5 further includes: a third well region disposed in the substrate, having the second conductivity type and adjacent to the first well region; a substrate contact region disposed in the third well region, having the second conductivity type; and a substrate electrode electrically connected to the substrate contact region, wherein the source electrode is located between the substrate electrode and the gate electrode. A semiconductor device as described in claim 7, wherein the substrate has the second conductivity type, and the bottom surface of the first well region is lower than the bottom surface of the second well region and the bottom surface of the third well region. A semiconductor device as described in claim 7, wherein the second well region and the third well region are laterally separated, and a portion of the first well region is located between the second well region and the third well region. The semiconductor device as described in claim 1 is a depletion metal oxide semiconductor field effect transistor, and further comprises: a first well region disposed in the substrate and having the first conductivity type, wherein the drain region is disposed in the first well region; and a second well region disposed in the substrate and having the second conductivity type and adjacent to the first well region, wherein the source region is disposed in the second well region and has the first conductivity type. The semiconductor device as described in claim 10 further includes an isolation region disposed on the first well region, between the drain region and the gate electrode, and a portion of the gate electrode extends from a side surface of the isolation region to a top surface of the isolation region. A semiconductor device as described in claim 11, wherein the drain region and the gate electrode are laterally separated by a distance, and another portion of the gate electrode is adjacent to the source region. A semiconductor device as described in claim 10, wherein the gate electrode spans the first well region and the second well region. The semiconductor device as described in claim 10 further includes: a substrate contact region disposed in the second well region and having the second conductivity type; and a substrate electrode electrically connected to the substrate contact region, wherein the source electrode is located between the substrate electrode and the gate electrode. A semiconductor device as described in claim 1, wherein in a top-view layout, the drain electrode includes a circular block. A semiconductor device as described in claim 15, wherein in the top view layout, the drain blocks and the drain contacts are within the circular block of the drain electrode. A semiconductor device as described in claim 15, wherein in the top-view layout, the gate electrode is electrically connected to a gate contact region via at least one annular gate contact, and is electrically connected to a field plate via a plurality of contacts, and the at least one annular gate contact and the contacts are within the annular region of the gate electrode. A semiconductor device as described in claim 15, wherein in the top-view layout, the source electrode is electrically connected to the source region via at least one annular source contact, and the at least one annular source contact is within the other annular region of the source electrode.

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