TWI874760B - Electronic device - Google Patents

Abstract

An electronic device including a substrate, a signal line, and a spacer is provided. The signal line is disposed on the substrate and includes at least one curve segment. The spacer is disposed on the substrate and is disposed corresponding to the at least one curve segment.

Description

Electronic devices

The present disclosure relates to an electronic device.

Most devices (such as display devices or light switches) have multiple spacers randomly arranged in multiple pixels to support the cell gap. These spacers are usually shielded by a light-shielding pattern to reduce light leakage. When the device needs to increase the aperture ratio (or transmittance), the space for multiple spacers becomes limited.

The present disclosure provides an electronic device which can improve the opening rate or the transmittance.

In an embodiment of the present disclosure, an electronic device includes a substrate, a signal line, and a spacer. The signal line is disposed on the substrate and includes at least one curved line segment. The spacer is disposed on the substrate and corresponds to the at least one curved line segment.

In order to make the above features and advantages of the present disclosure more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and description to represent the same or like parts.

Certain terms are used throughout this disclosure and in the attached patent claims to refer to specific components. A person of ordinary skill in the art will understand that electronic device manufacturers may refer to the same component by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and patent claims, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to..."

Directional terms such as "up", "down", "front", "back", "left", "right", etc., mentioned herein are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present disclosure. In the accompanying drawings, each diagram depicts the general characteristics of the methods, structures and/or materials used in a particular embodiment. However, these diagrams should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for the sake of clarity, the relative size, thickness and position of each film layer, region and/or structure may be reduced or exaggerated.

A structure (or layer, element, substrate) described in the present disclosure is located on/above another structure (or layer, element, substrate), which may mean that the two structures are adjacent and directly connected, or may mean that the two structures are adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate spacing) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is disposed "on" another structure, it may mean that the certain structure is "directly" on the other structure, or it may mean that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

The terms "approximately," "equal to," "equal," or "same," "substantially," or "substantially" are generally interpreted as being within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

The ordinal numbers used in the specification and patent application, such as "first", "second", etc., are used to modify the components. They do not imply or represent any previous ordinal number of the component (or components), nor do they represent the order of one component to another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The patent application and the specification may not use the same terms. Accordingly, the first component in the specification may be the second component in the patent application.

The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but not limited to these.

In the present disclosure, the thickness, length and width can be measured by using an optical microscope (OM), and the thickness or width can be measured by using a cross-sectional image in an electron microscope, but it is not limited thereto. In addition, any two values or directions used for comparison may have a certain error. In addition, the terms "equal to", "equal", "same", "substantially" or "approximately" mentioned in the present disclosure generally represent within 10% of a given value or range. In addition, the terms "a given range is from a first value to a second value", "a given range falls within the range from a first value to a second value" indicate that the given range includes the first value, the second value and other values therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

It should be noted that the following embodiments may replace, reorganize, or mix features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features between embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

In the present disclosure, the electronic device may include a display device, a backlight device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The electronic device may, for example, include liquid crystal, a light-emitting diode, fluorescence, phosphor, quantum dot (QD), other suitable display media or a combination thereof. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat or ultrasound, but is not limited thereto. In the present disclosure, the electronic device may include electronic components, and the electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the foregoing, but is not limited thereto. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have a driving system, a control system, a light source system, etc. peripheral systems to support a display device, an antenna device, a wearable device (such as an augmented reality or a virtual reality), a vehicle-mounted device (such as a car windshield), or a splicing device.

It should be noted that the technical solutions provided in the following different embodiments can be replaced, combined or mixed with each other to constitute another embodiment without violating the spirit of the present disclosure.

FIG. 1, FIG. 5, and FIG. 9A to FIG. 9C are partial top views of electronic devices according to some embodiments of the present disclosure. FIG. 2 is an enlarged schematic view of region R in FIG. 1. FIG. 3 and FIG. 4 are cross-sectional schematic views of section line A-A' in FIG. 1 and section line B-B' in FIG. 2, respectively. FIG. 6A to FIG. 6D, FIG. 8A, and FIG. 8B are top views of various relative arrangement relationships of signal lines and spacers. FIG. 7 is a schematic view of the relative arrangement relationship of liquid crystal molecules and spacers.

Please refer to Figures 1 to 4, the electronic device 1 may include a substrate 10, a signal line 12 and a spacer 14. The signal line 12 is arranged on the substrate 10 and includes at least one curved line segment (such as the curved line segment 120 in Figure 5). The spacer 14 is arranged on the substrate 10 and corresponds to the at least one curved line segment 120, that is, the spacer 14 at least partially overlaps with the at least one curved line segment 120 in the top view direction of the electronic device 1 (such as direction D3). The electronic device 1 disclosed in the present invention can be applied to augmented reality and can be used for dimming (light switch) to increase the contrast of the display, but is not limited to this. The "curve" in the present disclosure is, for example, a non-straight line segment or a line segment with at least one radius of curvature. The curve can be, for example, an S-shape or a line segment with at least one inflection point.

Specifically, the substrate 10 may be a hard substrate or a flexible substrate. The material of the substrate 10 may include, for example, glass, quartz, ceramic, sapphire, or plastic, but is not limited thereto. In some embodiments, the substrate 10 may be a flexible substrate, and the material of the substrate 10 may include polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), other suitable flexible materials, or a combination of the foregoing materials, but is not limited thereto.

The signal line 12 may be, for example, a scan line, a data line, or other types of signal lines. The material of the signal line 12 may include metal, metal alloy, metal oxide, transparent conductive material, any conductor, or a combination thereof, but is not limited thereto. In some embodiments, the signal line 12 may be formed of a material with high conductivity, such as a metal or metal alloy, to reduce impedance or facilitate signal transmission. In other embodiments, the signal line 12 may be formed of a transparent conductive material, which may reduce optical interference (such as diffraction) to improve the display quality of the electronic device.

FIG. 1 schematically illustrates that the signal line 12 includes a plurality of curve segments, and the plurality of curve segments are arranged in a direction D1 and connected to form a wave shape. However, it should be understood that the type of the signal line 12, the number of curve segments, the arrangement of the plurality of curve segments, or the shape formed by connecting the plurality of curve segments can be changed according to actual needs, and is not limited to what is shown in FIG. 1. In other embodiments, the electronic device further includes a signal line 13 extending substantially along another direction (e.g., direction D2), and the plurality of curve segments of the signal line 13 can be arranged in direction D2 and connected to each other, but is not limited thereto. In the present disclosure, direction D1 is, for example, the extension direction of the signal line 12, and direction D2 is, for example, the extension direction of the signal line 13, and direction D2 and direction D3 can be substantially perpendicular, and direction D3 is, for example, a normal direction parallel to the surface of the substrate 10, and direction D3 can be perpendicular to direction D1 and direction D2.

The spacer 14 may include a main spacer, a sub-spacer, or a combination thereof. The opposite ends of the main spacer may contact the active device array substrate SUB-A and the opposite substrate SUB-B, respectively, as shown in the spacer 15 of FIG. 4 . One end of the sub-spacer may contact one of the active device array substrate SUB-A and the opposite substrate SUB-B, and the other end of the sub-spacer does not contact the other of the active device array substrate SUB-A and the opposite substrate SUB-B when the electronic device 1 is not pressed, as shown in the spacer 14 of FIG. 3 . The active device array substrate SUB-A may include, for example, a substrate 10 and film layers (e.g., insulating layers, conductive layers, and semiconductor layers) on the substrate 10, and the counter substrate SUB-B may include, for example, a substrate 11 and film layers (e.g., insulating layers, conductive layers) on the substrate 11. In some embodiments, the maximum thickness of the secondary spacer (e.g., the maximum thickness T14 of the spacer 14 in the direction D3 in FIG. 3 ) is less than the maximum thickness of the primary spacer (e.g., the maximum thickness T15 of the spacer 15 in the direction D3 in FIG. 4 ). In other embodiments, the main spacer and/or the secondary spacer may be disposed in correspondence with another supporting element (not shown). For example, when the main spacer is disposed on the active element array substrate, a supporting element may be disposed on the opposite substrate and at least partially overlap with the main spacer in the direction D3, that is, one end of the main spacer contacts the supporting element at the other end of the substrate; another supporting element may also be disposed in correspondence with the secondary spacer, but the present disclosure is not limited thereto.

The electronic device 1 may include a plurality of spacers 14. In the present embodiment, the plurality of spacers 14 are, for example, a plurality of sub-spacers, but the present invention is not limited thereto. In other embodiments, although not shown, the plurality of spacers 14 may be a plurality of main spacers; or, the plurality of spacers 14 may be a combination of a plurality of main spacers and a plurality of sub-spacers, that is, some spacers 14 are main spacers, and other spacers 14 are sub-spacers.

The plurality of spacers 14 may be arranged corresponding to the plurality of curve segments of the signal line 12. Taking FIG. 1 as an example, the plurality of spacers 14 may be arranged corresponding to the crests C, troughs T, or a combination thereof of the signal line 12, that is, the plurality of spacers 14 may be arranged overlappingly with the plurality of crests C of the signal line 12; or, the plurality of spacers 14 may be arranged overlappingly with the plurality of troughs T of the signal line 12; or, the plurality of spacers 14 may be arranged overlappingly with the plurality of crests C and the plurality of troughs T of the wave shape. However, it should be understood that the relative arrangement relationship between the plurality of spacers 14 and the plurality of curve segments may be changed according to actual needs, and is not limited to that shown in FIG. 1 .

By designing that the spacers 14 are arranged correspondingly to the signal lines 12, the signal lines 12 or a light shielding pattern (not shown) shielding the signal lines 12 can be used to shield the spacers 14, thereby increasing the space and density of the spacers. Therefore, the electronic device 1 can maintain the required resilience or uniformity of the spacers while maintaining the required resolution and/or aperture ratio.

In some embodiments, the electronic device 1 may further include a dielectric layer ML and a substrate 11, wherein the substrate 10 is disposed corresponding to the substrate 11. The dielectric layer ML is disposed between the substrate 10 and the substrate 11 and has an alignment direction DA. The at least one curved line segment 120 of the signal line 12 extends along a direction DE, and the direction DE and the alignment direction DA have an angle θ, and the angle θ is, for example, greater than or equal to 0 degrees and less than or equal to 20 degrees.

For example, the dielectric layer ML may include a liquid crystal material, but is not limited thereto. Referring to FIG. 3 and FIG. 4 , the electronic device 1 may further include an alignment layer AL1 and an alignment layer AL2, and the alignment layer AL1 and the alignment layer AL2 are respectively disposed on opposite sides of the dielectric layer ML to control the alignment direction DA of the dielectric layer ML. The alignment direction DA of the dielectric layer ML may be measured using a polarimeter (such as AxoScan) or a phase difference measurement system (such as RETS), but is not limited thereto. In other embodiments, an optical microscope may be used to observe the dragging traces around the spacer to measure the alignment direction. 6A , the extension direction (direction DE) of the curve segment 120 may be the tangent direction TD of the vertex A of the curve segment 120 ; or, the major axis direction L of the minimum rectangle RT surrounding the curve segment 120 may be used as the extension direction (direction DE) of the curve segment 120 .

As shown in FIG. 7 , the liquid crystal molecules M adjacent to the spacer 14 in the dielectric layer ML are easily affected by the topography of the spacer 14, resulting in alignment anomalies/defects (mura), causing light leakage LL1. In addition, the liquid crystal molecules M adjacent to the spacer 14 on the side opposite to the alignment direction DA are easily caused by insufficient friction, resulting in alignment anomalies/defects, causing light leakage LL2. The spacer 14 can be shielded by the signal line 12 or a light shielding pattern (not shown) overlapped with the signal line 12 to reduce the visibility of the light leakage LL1. On the other hand, the design of 0 degrees ≦ angle θ ≦ 20 degrees can be used to reduce the impact area of the light leakage LL2 or to shield the light leakage LL2 with the light shielding pattern without significantly affecting the aperture ratio.

2 and 4 , in some embodiments, the electronic device 1 may further include an active element AD and another spacer 15. The active element AD is disposed on the substrate 10 and is electrically connected to the signal line 12. The active element AD may include a transistor, but is not limited thereto. For example, the active element AD may include a gate GE, a semiconductor pattern CH, a source SE, and a drain DE, but is not limited thereto. The region RAD where the active element AD is located is defined, for example, by a minimum rectangular frame surrounding the gate GE, the semiconductor pattern CH, the source SE, and the drain DE.

The spacer 15 overlaps at least a portion of the active element AD, that is, the spacer 15 overlaps at least a portion of the region RAD where the active element AD is located in the direction D3. By designing that the spacer 15 overlaps at least a portion of the active element AD, a light shielding pattern (not shown) for shielding the active element AD can be used to shield the spacer 15, thereby increasing the space for setting the spacer. Therefore, the electronic device 1 can maintain the required resilience or uniformity of the spacer while maintaining the required resolution and/or aperture ratio.

The spacers 15 may include primary spacers, secondary spacers, or a combination thereof. The electronic device 1 may include a plurality of spacers 15. In the present embodiment, the plurality of spacers 15 are, for example, a plurality of primary spacers, but are not limited thereto. In other embodiments, although not shown, the plurality of spacers 15 may be a plurality of secondary spacers; or, the plurality of spacers 15 may be a combination of a plurality of primary spacers and a plurality of secondary spacers, that is, some spacers 15 are primary spacers, and other spacers 15 are secondary spacers.

According to different requirements, the electronic device 1 may further include other components or film layers. For example, as shown in FIG. 3 and FIG. 4 , the electronic device 1 may further include a light shielding layer LS, an insulating layer BF, a semiconductor layer SL, an insulating layer GI, a first conductive layer C1, an insulating layer ILD, a second conductive layer C2, an insulating layer PLN, a third conductive layer C3, and a fourth conductive layer C4, but the present invention is not limited thereto. The electronic device 1 may increase or decrease one or more components/film layers according to different requirements.

The active device array substrate SUB-A includes, for example, a substrate 10, a light shielding layer LS, an insulating layer BF, a semiconductor layer SL, an insulating layer GI, a first conductive layer C1, an insulating layer ILD, a second conductive layer C2, an insulating layer PLN, a third conductive layer C3, and an alignment layer AL1. The counter substrate SUB-B includes, for example, a substrate 11, a fourth conductive layer C4, and an alignment layer AL2.

The light shielding layer LS is disposed on the substrate 10. The light shielding layer LS may be formed of a reflective material (such as metal or metal alloy) or a light absorbing material (such as a black matrix). The light shielding layer LS may include a light shielding pattern LSP. The light shielding pattern LSP may be disposed corresponding to the channel region RCH of the semiconductor layer SL, that is, the light shielding pattern LSP overlaps with the channel region RCH in the direction D3.

The insulating layer BF is disposed on the substrate 10 and covers the light shielding layer LS. The material of the insulating layer BF may include an inorganic insulating material, such as silicon oxide or silicon nitride, but is not limited thereto.

The semiconductor layer SL is disposed on the insulating layer BF. The material of the semiconductor layer SL may include an oxide semiconductor material, such as, but not limited to, Indium Gallium Zinc Oxide (IGZO). In other embodiments, the material of the semiconductor layer SL may include amorphous silicon, polysilicon, metal oxide, or a combination thereof (for example, when there are multiple active elements). The semiconductor layer SL may include a semiconductor pattern CH. The semiconductor pattern CH may include, but not limited to, a channel region RCH, a source region RSE, and a drain region RDE.

The insulating layer GI is disposed on the semiconductor layer SL. For example, the material of the insulating layer GI may include an inorganic material, such as silicon oxide or silicon nitride, but is not limited thereto.

The first conductive layer C1 is disposed on the insulating layer GI. For example, the material of the first conductive layer C1 includes metal or a metal stack, such as aluminum, molybdenum or titanium/aluminum/titanium. The first conductive layer C1 may include a gate GE, a signal line (such as the signal line 13 shown in FIG. 2 ), etc., but is not limited thereto. The gate GE is disposed corresponding to the channel region RCH, that is, the gate GE and the channel region RCH overlap in the direction D3. The signal line 13 may be a scan line, a data line, or other types of signal lines. FIG. 1 schematically illustrates that the signal line 13 includes a plurality of curve segments, and the plurality of curve segments are arranged in the direction D2 and connected in a wavy shape. However, it should be understood that the type of signal line 13, the number of curve segments, the arrangement of multiple curve segments, or the shape formed by connecting multiple curve segments can be changed according to actual needs and is not limited to what is shown in FIG. 1 .

The insulating layer ILD is disposed on the first conductive layer C1. For example, the material of the insulating layer ILD may include an inorganic material, such as silicon oxide or silicon nitride, but is not limited thereto. In some embodiments, although not shown, the insulating layer ILD may be a stacked layer of multiple insulating materials.

The second conductive layer C2 is disposed on the insulating layer ILD. For example, the material of the second conductive layer C2 includes metal, metal oxide or metal stack, such as aluminum, molybdenum or titanium/aluminum/titanium, indium tin oxide. The second conductive layer C2 may include a source SE, a drain DE, a signal line (such as the signal line 12), etc., but is not limited thereto. The source SE penetrates the insulating layer ILD and the insulating layer GI and is connected to the source region RSE. The drain DE penetrates the insulating layer ILD and the insulating layer GI and is connected to the drain region RDE.

The insulating layer PLN is disposed on the insulating layer ILD and covers the second conductive layer C2. For example, the material of the insulating layer PLN includes an organic material or a polymer material, such as polymethyl methacrylate (PMMA), epoxy, acylic-based resin, silicone, polyimide polymer, or a combination thereof, but not limited thereto. In some embodiments, although not shown, the insulating layer PLN may be a stacked layer of multiple layers of organic material or polymer material.

The third conductive layer C3 is disposed on the insulating layer PLN. The material of the third conductive layer C3 includes a transparent conductive material, such as metal oxide, but not limited thereto. The third conductive layer C3 may include a pixel electrode PE, but not limited thereto. The pixel electrode PE penetrates the insulating layer PLN and is connected to the drain DE.

The alignment layer AL1 is disposed on the third conductive layer C3. The alignment layer AL1 may be a photo-alignment layer, but is not limited thereto.

The fourth conductive layer C4 and the alignment layer AL2 are sequentially arranged on the surface of the substrate 11 facing the active device array substrate SUB-A. The substrate 11 can be a hard substrate or a flexible substrate. The material of the substrate 11 can be the same as or similar to the material of the substrate 10, which will not be repeated here. The material of the fourth conductive layer C4 includes a transparent conductive material, such as metal oxide, but is not limited to this. The fourth conductive layer C4 can be a conductive layer of the entire surface, but is not limited to this. The alignment layer AL2 can be a photo-alignment layer, but is not limited to this.

Referring to FIG5 , the main difference between the electronic device 1A and the electronic device 1 of FIG1 is that a plurality of spacers 14 are respectively overlapped with the signal line 12 and the signal line 13. In addition, the orientation direction DA of the dielectric layer (not shown) in FIG5 is different from the orientation direction DA of the dielectric layer (not shown) in FIG1 , and the relative arrangement relationship between the spacers 14 and the signal line 12 (or the signal line 13) is changed according to the orientation direction DA of the dielectric layer to meet the design that the angle between the extension direction (direction DE) of the curve segment 120 of the signal line 12 (or the curve segment 130 of the signal line 13) and the orientation direction DA is greater than or equal to 0 degrees and less than or equal to 20 degrees.

In some embodiments, the spacer 14 overlapping the signal line 12 (or the signal line 13) may be a single spacer (as shown in FIG. 6A ) to have a greater support strength; or, the spacer 14 may be a spacer group (as shown in FIGS. 6B to 6D ) to reduce the risk of peeling of the spacer.

In some embodiments, the shape of the spacer 14 may be a straight line (as shown in FIG. 5 ), a curve (as shown in FIG. 6A and FIG. 6B ), a dot (a circle or a polygon as shown in FIG. 6C and FIG. 6D ), or a combination thereof to provide different prepressing heights.

In some embodiments, in order to shield the light leakage LL2 caused by the region with abnormal alignment/defect due to insufficient friction on the side of the spacer 14 opposite to the alignment direction DA in FIG. 7 , as shown in FIG. 8A and FIG. 8B , the relative setting relationship between the spacer 14 and the signal line 12 (or signal line 13) can be changed according to the alignment direction DA of the dielectric layer (not shown), so that the alignment trace area RT (i.e., the region with abnormal alignment/defect due to insufficient friction on the side of the spacer 14 opposite to the alignment direction DA) falls in the region RAD where the active element is located, so as to utilize the shading pattern (not shown) of the shielding region RAD to shield the light leakage LL2 in FIG. 7 .

In some embodiments, as shown in FIGS. 9A to 9C , the signal line 12 and/or the signal line 13 may be a straight line or a folded line, and the area enclosed by two adjacent signal lines 12 and two adjacent signal lines 13 may be a quadrilateral, a hexagon or other polygon. In FIGS. 9A to 9C , the light leakage caused by the provision of the spacer 14 may be reduced by referring to the design in which the angle between the extension direction (direction DE) of the signal line 12 and the alignment direction DA is greater than or equal to 0 degrees and less than or equal to 20 degrees as in FIGS. 1 or 5 and/or the design in which the alignment trace area RT falls in the area RAD as in FIGS. 8A or 8B .

In the embodiment of the present disclosure, by designing that the spacers are arranged correspondingly to the signal lines, the signal lines or the light shielding patterns that shield the signal lines can be used to shield the spacers, which helps to increase the space for arranging the spacers, and it is not necessary to reduce the number or arrangement density of the spacers based on the consideration of resolution and/or aperture ratio. Therefore, the electronic device can maintain the required resilience or uniformity of the spacers while maintaining the required resolution and/or aperture ratio.

The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure is described in detail with reference to the above embodiments, a person skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalent ones. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure, and the features between the embodiments can be arbitrarily mixed and replaced with each other to form other new embodiments. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the content of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described here, they can be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each and every embodiment. The scope of protection of the present disclosure shall be determined by the scope of the attached patent application.

1, 1A: electronic device 10, 11: substrate 12, 13: signal line 14, 15: spacer 120: curve segment A: vertex AD: active element AL1, AL2: alignment layer BF, GI, ILD, PLN: insulating layer C: wave crest C1: first conductive layer C2: second conductive layer C3: third conductive layer C4: fourth conductive layer CH: semiconductor pattern D1, D2, D3, DE: direction DA: alignment direction DE: drain GE: gate L: long axis direction LL1, LL2: light leakage LS: light shielding layer LSP: light shielding pattern M: liquid crystal molecules ML: dielectric layer PE: Pixel electrode R, RAD: Region RCH: Channel region RDE: Drain region RSE: Source region RT: Alignment trace region SE: Source SL: Semiconductor layer SUB-A: Active element array substrate SUB-B: Opposite substrate T: Valley T14, T15: Maximum thickness TD: Tangent direction A-A’, B-B’: Section line θ: Angle

FIG. 1, FIG. 5, and FIG. 9A to FIG. 9C are partial top view schematic diagrams of electronic devices according to some embodiments of the present disclosure. FIG. 2 is an enlarged schematic diagram of region R in FIG. 1. FIG. 3 and FIG. 4 are cross-sectional schematic diagrams of section line A-A' in FIG. 1 and section line B-B' in FIG. 2, respectively. FIG. 6A to FIG. 6D, FIG. 8A, and FIG. 8B are top view schematic diagrams of various relative arrangement relationships of signal lines and spacers. FIG. 7 is a schematic diagram of the relative arrangement relationship between liquid crystal molecules and spacers.

1: Electronic devices

10: Substrate

12, 13: Signal line

14, 15: Interstitial

C: Peak

D1, D2, D3, DE: Direction

DA: Alignment direction

R, RAD: Region

T:Trough

A-A’: section line

θ: angle of intersection

Claims (8)

An electronic device comprises: a substrate; a signal line disposed on the substrate and comprising at least one curved line segment; a spacer disposed on the substrate and corresponding to the at least one curved line segment, wherein the spacer is curved, overlaps with the at least one curved line segment in the projection direction of the substrate, and the projection of the spacer on the substrate is completely located within the projection of the at least one curved line segment on the substrate; and a dielectric layer disposed on the substrate and having an orientation direction, wherein the at least one curved line segment of the signal line extends along a direction, the direction and the orientation direction have an angle, and the angle is greater than or equal to 0 degrees and less than or equal to 20 degrees. An electronic device as described in claim 1, wherein the spacer includes a primary spacer, a secondary spacer, or a combination thereof. An electronic device as described in claim 1, wherein the dielectric layer includes a liquid crystal material. The electronic device as described in claim 1 further comprises: an active element disposed on the substrate and electrically connected to the signal line; and another spacer, wherein the other spacer overlaps at least a portion of the active element. An electronic device as described in claim 1, wherein the signal line is a scan line or a data line. The electronic device as described in claim 1 further comprises: An alignment layer disposed on the substrate, wherein the alignment layer is a photo-alignment layer. An electronic device as described in claim 1, wherein the electronic device includes a plurality of spacers, and the plurality of spacers correspond to the peaks, troughs, or a combination thereof of the signal line. The electronic device as described in claim 1 further includes: an active element, which is arranged on the substrate and electrically connected to the signal line; and another spacer, which is arranged on the substrate, wherein the active element includes a gate, a semiconductor pattern, a source and a drain, and the area where the active element is located is defined by a minimum rectangular frame surrounding the gate, the semiconductor pattern, the source and the drain, wherein, when viewed from a top view of the electronic device, the other spacer completely falls within the area.

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