TWI874275B - Memory module with improved timing adaptivity of sensing amplification - Google Patents

Abstract

A memory module with improved timing adaptivity of sensing amplification, comprises at least one sensing amplifier, a tracking word line, a tracking bit line and a pulse-width controller. The tracking word line comprises a front node and an end node. Each said sensing amplifier is enabled/disabled when an enabling signal is activated/deactivated. The pulse-width controller is coupled to the tracking bit line, the front node and the end node. When a voltage of the tracking bit line changes to a predetermined voltage, the pulse-width controller activates the enabling signal, and causes a voltage of the front node to change. When the voltage of the front node changes, the tracking word line causes a voltage of the end node to change after a first delay time. When the voltage of the end node changes, the pulse-width controller deactivates the enabling signal after a second delay time.

Description

Memory module capable of improving the adaptability of sensing and amplification timing

The present invention relates to a memory module capable of improving the timing adaptability of a sense amplifier, and in particular to a memory module capable of adapting the duration of enabling a sense amplifier to the input/output number and/or the supply voltage of the sense amplifier.

Memory modules, such as embedded static random access memory modules, are important basic building blocks of integrated circuits (semiconductor chips).

The memory module is provided with a plurality of memory cells and a plurality of sense amplifiers; these sense amplifiers are controlled by an enable signal. When the enable signal is activated, each sense amplifier is activated and operates; when the enable signal is stopped, each sense amplifier is disabled and does not operate.

When the memory module wants to read the data stored in a memory cell in a read cycle, the bit line corresponding to the memory cell will be connected to a corresponding sense amplifier, and then the enable signal will be activated, enabling the sense amplifier to sense the voltage of the corresponding bit line and judge the data stored in the memory cell accordingly; after that, the enable signal will be stopped, disabling the sense amplifier and stopping sensing, and the read cycle will end. In each read cycle, the length of time the sense amplifier is enabled depends on the length of time the enable signal is activated, that is, the pulse width of the enable signal. If the pulse width of the enable signal is insufficient, the sense amplifier will not have enough time to operate, and the accuracy of data reading will also be affected.

In the known technology, a fixed number of inverters connected in series are set in the known memory module, and the pulse width of the enable signal depends on the sum of the gate delays of these inverters connected in series. Therefore, in the known technology, the pulse width of the enable signal lacks flexibility and is difficult to adapt to the different requirements of various memory modules. In addition, these inverters connected in series will also occupy a lot of layout area.

One of the purposes of the present invention is to provide a memory module (e.g., 100, FIG. 1 ) capable of improving the adaptability of sense amplification timing, comprising at least one bit line (e.g., BL[q]), at least one word line (e.g., WL[p]), a tracking bit line (e.g., TBL), a tracking word line (e.g., TWL), at least one memory cell (e.g., c[p,q]), at least one tracking cell (e.g., tc[p]), at least one sense amplifier (e.g., SA[k]), and a pulse width controller (e.g., 300, FIG. 4 ). The tracking word line comprises a front node (e.g., w1) and a rear node (e.g., w3), and the length between the front node and the rear node is positively correlated to the length of each of the word lines. Each of the memory cells is coupled to one of the at least one bit line and one of the at least one word line. Each of the tracking units is coupled to the tracking bit line. Each of the sense amplifiers is coupled to one of the at least one bit line and receives an enable signal (e.g., GS); each of the sense amplifiers is controlled to be enabled when the enable signal is activated, and is disabled when the enable signal stops being activated. A pulse width controller is coupled to the tracking bit line, the front node, and the rear node, and provides the enable signal. When the voltage of the tracking bit line (e.g., vTBL, FIG. 5) changes to a preset voltage (e.g., vt0, at time t3, FIG. 5), the pulse width controller activates the enable signal (e.g., at time t6, FIG. 5), and changes the voltage of the front node (e.g., vw1, FIG. 5) (e.g., switching from voltage v4 to voltage v3 at time t7, FIG. 5). When the voltage of the front node changes, the tracking word line changes the voltage of the rear node (e.g., vw3, FIG. 5) after a first delay time (e.g., d1, FIG. 5) (e.g., switching from voltage v4 to voltage v3 at time t8, FIG. 5). When the voltage of the rear node changes, the pulse width controller stops activating the enable signal (for example, at time t12, FIG. 5 ) after a second delay time (for example, d2, FIG. 5 ).

In one embodiment (e.g., FIG. 6 ), a portion of the pulse width controller (e.g., logic gate G1, FIG. 6 ) is powered by a first supply voltage (e.g., Vdd1, FIG. 6 ), and at least a portion of each of the sense amplifiers (e.g., SA[k], FIG. 6 ) (e.g., s2[k], FIG. 6 ) is powered by a second supply voltage (e.g., Vdd2, FIG. 6 ). In one embodiment, the first supply voltage is different from the second supply voltage, and the length of the second delay time is negatively correlated to the magnitude of the second supply voltage.

In one embodiment (e.g., FIG. 6 ), the pulse width controller has two parts (e.g., logic gate G1 and delay circuit 500, FIG. 6 ) which are respectively powered by two phase-differential supply voltages (e.g., Vdd1 and Vdd2, FIG. 6 ), and the length of the second delay time is negatively related to one of the two phase-differential supply voltages (e.g., Vdd2, FIG. 6 ).

In one embodiment (e.g., FIG. 4 ), the pulse width controller includes a first logic gate (e.g., G1, FIG. 4 ). The first logic gate includes a first input terminal (e.g., i1), a second input terminal (e.g., i2), and a first output terminal (e.g., o1), which are respectively coupled to the tracking bit line, the rear node, and a first node (e.g., n1). The pulse width controller forms the enable signal at a third node (e.g., n3), and the third node is coupled to the at least one sense amplifier. When the memory module performs data reading, the voltage of the third node is controlled by the voltage of the first node. When the pulse width controller activates the enable signal, the enable signal is switched from a first level (e.g., v1, FIG. 5) to a second level (e.g., v2, FIG. 5); when the pulse width controller stops activating the enable signal, the enable signal is switched from the second level back to the first level. In one embodiment (e.g., FIG. 4), the pulse width controller further includes a first inverter (e.g., iv1, FIG. 4), coupled between the tracking bit line and the first input terminal. In one embodiment (e.g., FIG. 4), the first logic gate is a NAND gate.

In one embodiment (e.g., FIG. 4 ), the pulse width controller further includes a third logic gate (e.g., G3, FIG. 4 ) and a delay circuit (e.g., 500, FIG. 4 ). The third logic gate includes a fifth input terminal (e.g., i5), a sixth input terminal (e.g., i6), and a third output terminal (e.g., o3). The fifth input terminal is coupled to a second node (e.g., n2), the delay circuit is coupled between the second node and the sixth input terminal, and the third output terminal is coupled to the third node. When the memory module performs data reading, the voltage of the second node is controlled by the voltage of the first node. In one embodiment (eg, FIG. 4 ), the pulse width controller further includes a third inverter (eg, iv3 , FIG. 4 ) coupled between the third output terminal and the third node.

In one embodiment (e.g., FIG. 6 ), the first logic gate and the delay circuit are powered by a first supply voltage (e.g., Vdd1, FIG. 6 ) and a second supply voltage (e.g., Vdd2, FIG. 6 ), respectively, and the first supply voltage is different from the second supply voltage. In one embodiment (e.g., FIG. 6 ), at least a portion of each sense amplifier (e.g., s2[k], FIG. 6 ) is powered by the second supply voltage.

In one embodiment (e.g., FIG. 4 ), the pulse width controller further includes a second logic gate (e.g., G2, FIG. 4 ). The second logic gate includes a third input terminal (e.g., i3), a fourth input terminal (e.g., i4), and a second output terminal (e.g., o2), which are respectively coupled to the first node, a fourth node (e.g., n4), and the second node.

In one embodiment (e.g., FIG. 4 ), the pulse width controller further includes a fourth logic gate (e.g., G4, FIG. 4 ). The fourth logic gate includes a seventh input terminal (e.g., i7), an eighth input terminal (e.g., i8), and a fourth output terminal (e.g., o4), which are respectively coupled to a first indication signal (e.g., SCANEN), a second indication signal (e.g., WEI), and the fourth node. In one embodiment (e.g., FIG. 4 ), the second logic gate, the third logic gate, and the fourth logic gate are all negative OR gates.

In one embodiment (e.g., FIG. 4 ), the memory module further includes a finite state machine circuit (e.g., 400, FIG. 4 ) coupled between the pulse width controller and the previous node. When the pulse width controller changes the voltage of the previous node, the finite state machine circuit changes the voltage of the previous node.

In one embodiment (eg, FIG. 4 ), the finite state machine circuit includes a fifth node (eg, n5, FIG. 4 ) and a sixth node (eg, n6, FIG. 4 ); wherein the fifth node is coupled to the first node, and the sixth node is coupled to the previous node.

In one embodiment (e.g., FIG. 4 ), the finite state machine circuit further includes a seventh node (e.g., n7) coupled to a clock (e.g., CLK). In one embodiment (e.g., FIG. 4 ), the memory module further includes a second inverter (e.g., iv2, FIG. 4 ) coupled between the sixth node and the previous node.

One of the purposes of the present invention is to provide a memory module (e.g., 100, FIG. 1 ) capable of improving the adaptability of sense amplification timing, which may include at least one bit line (e.g., BL[q]), at least one word line (e.g., WL[p]), a tracking bit line (e.g., TBL), a tracking word line (e.g., TWL), at least one memory cell (e.g., c[p,q]), at least one tracking cell (e.g., tc[p]), at least one sense amplifier (e.g., SA[k]), and a first logic gate (e.g., G1, FIG. 4 ). The tracking word line extends from a front node (e.g., w1) to a rear node (e.g., w3), and the length from the front node to the rear node is positively correlated to the length of each word line. Each memory cell is coupled to one of the at least one bit line and one of the at least one word line. Each of the tracking units is coupled to the tracking bit line. Each of the sensing amplifiers is coupled to one of the at least one bit line and is further coupled to a third node (e.g., n3). Each of the sensing amplifiers is disabled when the voltage of the third node is a first level (e.g., v1, FIG. 5), and is controlled to be enabled when the voltage of the third node is a second level (e.g., v2, FIG. 5). The first logic gate includes a first input terminal (e.g., i1, FIG. 4), a second input terminal (e.g., i2, FIG. 4), and a first output terminal (e.g., o1, FIG. 4), which are respectively coupled to the tracking bit line, the rear node, and the front node. When the memory module performs data reading, the voltage of the third node is controlled by the voltage of the first output terminal.

In one embodiment (FIG. 4), the memory module further includes a third logic gate (e.g., G3, FIG. 4) and a delay circuit (e.g., 500, FIG. 4). The third logic gate includes a fifth input terminal (e.g., i5), a sixth input terminal (e.g., i6) and a third output terminal (e.g., o3); the fifth input terminal is coupled to a second node (e.g., n2), the delay circuit is coupled between the second node and the sixth input terminal, the third output terminal is coupled to the third node, and the second node is coupled to the first output terminal. In one embodiment (e.g., FIG. 6), the first logic gate and the delay circuit are powered by two phase-differential supply voltages (e.g., Vdd1 and Vdd2, FIG. 6), respectively.

In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings:

FIG1 shows a memory module 100 according to an embodiment of the present invention, which may include P*Q memory cells c[1,1] to c[P,Q], P word lines WL[1] to WL[P], Q groups of bit lines BL[1], BLb[1] to BL[Q], BLb[Q], P tracking cells tc[1] to tc[P], an auxiliary word line w0, a group of tracking bit lines TBL and TBLb, a tracking word line TWL, K buffers bf[1] to bf[K], K sense amplifiers SA[1] to SA[K], K write circuits WB[1] to WB[K], two peripheral circuits 130 and 140, and a control circuit 200. The numbers P, Q, and K may be preset integers. The number Q may be an integer multiple of the number K; for example, the number Q may be one, two, or four times the number K. The number K (the number of sense amplifiers and write circuits) represents the number of inputs and outputs of the memory module 100 .

In the memory module 100, each memory cell c[p, q] (p=1 to P, q=1 to Q) is coupled to a corresponding word line WL[p] and a set of corresponding bit lines BL[q] and BLb[q], and can store one bit of data. Continuing with FIG1, FIG2 illustrates an embodiment of each memory cell c[p, q]; each memory cell c[p, q] may include a set of inverters iA[p, q] and iB[p, q], and a set of pass gate transistors A[p, q] and B[p, q] (such as n-channel metal oxide semiconductor transistors). Inverters iA[p, q] and iB[p, q] form a latch L[p, q]. Transistor A[p,q] has a controlled terminal (such as a gate terminal) and two channel terminals (such as a drain terminal and a source terminal), which are respectively coupled to the word line WL[p], the bit line BL[q] and one end of the latch L[p,q]. Transistor B[p,q] has a controlled terminal and two channel terminals, which are respectively coupled to the word line WL[p], the bit line BLb[q] and the other end of the latch L[p,q].

In the memory module 100 of FIG1 , each tracking cell tc[p] is coupled to the auxiliary word line w0 and the tracking bit lines TBL and TBLb. The circuit of each tracking cell tc[p] can be the same as the circuit of each memory cell c[p,q], so that each tracking cell tc[p] can reflect (track) the properties (such as response time, etc.) of each memory cell c[p,q].

As shown in FIG1 , in the memory module 100 , the tracking word line TWL may extend from a node w1 to another node w2, and then extend from node w2 to another node w3. The length of the tracking word line TWL from node w1 (via node w2) to node w3 may be positively correlated to the length of each word line WL[p]. In one embodiment, the line structure (such as line length and line width) of the tracking word line TWL may be close to or substantially equal to the line structure of each word line WL[p] to reflect (track) the properties of each word line WL[p], such as equivalent impedance, equivalent load and response. As shown in FIG1 , the tracking word line TWL can extend horizontally from node w1 to node w2 by a distance D1, and then extend in the opposite direction from node w2 by the same distance D1 (or a similar distance) to node w3. In other words, the length of the tracking word line TWL between nodes w1 to w3 can be twice the distance D1. As shown in FIG1 , the distance D1 can horizontally span the space between bit lines BL[J+1], BLb[J+1] to BL[Q], BLb[Q], and the number J can be a preset integer; for example, the number Q can be an even number, and the number J can be equal to half of the number Q. Thus, twice the distance D1 will be equal to (or approach) the length of each word line WL[p], because each word line WL[p] horizontally spans the bit lines BL[1], BLb[1] to BL[J], BLb[J] and the bit lines BL[J+1], BLb[J+1] to BL[Q], BLb[Q]. The tracking word line TWL may not be coupled to any memory cell c[p,q]; that is, the tracking word line TWL may be isolated from any of the memory cells c[1,1] to c[P,Q].

The peripheral circuit 130 is coupled to the word lines WL[1] to WL[P] and is controlled by the control circuit 200. The peripheral circuit 140 is coupled to each group of bit lines BL[1], BLb[1] to BL[Q], BLb[Q], sense amplifiers SA[1] to SA[K] and write circuits WB[1] to WB[K] and is also controlled by the control circuit 200.

The control circuit 200 receives a clock CLK to control the operation of the memory module 100. The control circuit 200 is coupled to the peripheral circuits 130 and 140, coupled to the nodes w1 and w3 following the word line TWL, coupled to the following bit line TBL at a node n0, and coupled to the buffers bf[1] to bf[K] at another node n3.

The control circuit 200 outputs a signal GS from the node n3, which is the enable signal of the sense amplifiers SA[1] to SA[K]. Each sense amplifier SA[k] is coupled to the peripheral circuit 140 and is also coupled to the node n3 via the corresponding buffer bf[k] to receive the signal GS.

When data is to be written into a memory cell c[p,q] in a data write round, the control circuit 200 controls the peripheral circuits 130 and 140, and the peripheral circuit 140 conducts the corresponding bit lines BL[q] and BLb[q] to one of the write circuits WB[1] to WB[K], WB[k], and the peripheral circuit 130 drives the corresponding word line WL[p] so that the latch L[p,q] (FIG. 2) in the memory cell c[p,q] can be conducted to the bit lines BL[q] and BLb[q]. In this way, the write circuit WB[k] can write data into the memory cell c[p,q] via the bit lines BL[q] and BLb[q].

Continuing with FIG. 1 and FIG. 2, FIG. 3 illustrates the waveform timing of the relevant signals when the memory module 100 is performing data reading. As shown in FIG. 3, in one cycle T1 of the clock CLK, the voltage of the clock CLK alternates between the voltage vck1 and the voltage vck2 once. When the memory cell c[p,q] (FIG. 1) is to be read, as the clock CLK starts to switch from the voltage vck1 to the voltage vck2 at a time point ta1, the control circuit 200 controls the peripheral circuits 130 and 140, so that the peripheral circuit 140 turns on the corresponding bit line BL[q], BLb[q] to one of the sense amplifiers SA[1] to SA[K] SA[k], and at a later time At point ta2, the peripheral circuit 130 drives the voltage vWL[p] of the corresponding word line WL[p] from a voltage vWL1 (e.g., a voltage that cannot turn on the gate transistor) to another voltage vWL2 (e.g., a voltage sufficient to turn on the gate transistor), so that the latch L[p,q] (FIG. 2) in the memory cell c[p,q] can be turned on to the bit lines BL[q] and BLb[q]. At another time point ta3, the control circuit 200 starts to activate the signal GS, that is, the signal GS starts to switch from a level v1 representing non-activation to another level v2 representing activation. The activated signal GS enables the sense amplifiers SA[1] to SA[K], and the activated sensor SA[k] senses the voltage difference between the bit lines BL[q] and BLb[q], and then determines the data stored in the memory cell c[p,q]. At a later time point ta4, the control circuit 200 causes the peripheral circuit 130 (Figure 1) to stop driving the word line WL[p], so that the voltage vWL[p] starts to switch from the voltage vWL2 back to the voltage vWL1. At a later time point ta5, the control circuit 200 starts to stop activating the signal GS, that is, the signal GS starts to switch from the level v2 back to the level v1. As the signal GS stops being activated, the sense amplifiers SA[1] to SA[K] are also disabled and no longer operate. At the next time point ta6, the period T1 of the clock CLK ends. As shown in FIG3 , the pulse width pw1 of the signal GS is maintained at the level v2, which is the period during which the sense amplifiers SA[1] to SA[K] can be controlled to be enabled.

Continuing with FIG. 1 to FIG. 3 , FIG. 4 illustrates an embodiment of the control circuit 200 of the present invention. As shown in FIG. 4 , in an embodiment of the present invention, the control circuit 200 may include a pulse width controller 300, a finite state machine circuit 400, two buffers bf1 and bf2, and an inverter iv2. The pulse width controller 300 may include four logic gates G1 to G4, inverters iv1 and iv3, and a delay circuit 500. The delay circuit 500 may include a buffer bf3. The finite state machine circuit 400 may be coupled between a supply voltage Vdd1 and a ground voltage Vss1, and may include nodes n5, n6, and n7; the clock CLK may be coupled to the node n7. The control circuit 200 may also include other circuit elements, but they have been omitted without affecting the technical disclosure of the present invention.

As shown in FIG4 , in the control circuit 200, the buffer bf1 is coupled between a node n1 of the pulse width controller 300 and a node n5 of the finite state machine circuit 400, and the inverter iv2 and the buffer bf2 are connected in series between a node n6 of the finite state machine circuit 400 and a node w1 following the word line TWL. The finite state machine circuit 400 can control the operation state of the memory module 100 under the triggering of the clock CLK, and the pulse width controller 300 can control the timing of the signal GS, including its pulse width pw1 ( FIG3 ).

In the pulse width controller 300, the logic gate G1 may be an NAND gate, and the logic gates G2 to G4 may be NOR gates. The logic gate G1 may include two input terminals i1 and i2 and an output terminal o1, the logic gate G2 may include two input terminals i3 and i4 and an output terminal o2, the logic gate G3 may include two input terminals i5 and i6 and an output terminal o3, and the logic gate G4 may include two input terminals i7 and i8 and an output terminal o4. The inverter iv1 is coupled between the node n0 and the input terminal i1, the delay circuit 500 is coupled between a node n2 and the input terminal i6, the inverter iv3 is coupled between the output terminal o3 and the node n3, and the voltage of the node n3 can form the signal GS.

As shown in FIG4 , regarding the logic gate G1, the following bit line TBL can be coupled to the input terminal i1 via the node n0 and the inverter iv1, the node w3 following the word line TWL can be coupled to the input terminal i2, and the output terminal o1 can be coupled to the node n1, and the voltage of the node n1 can form a signal TBL_LB. As shown in FIG4 , two circuit paths can be branched from the node n1. One circuit path allows the output end o1 of the logic gate G1 to be coupled to the node w1 that follows the word line TWL via the buffer bf1, the node n5 and the node n6 of the finite state machine circuit 400, the inverter iv2 and the buffer bf2. The other circuit path allows the output end o1 of the logic gate G1 to be coupled to the node n3 that forms the signal GS via the logic gate G2, the node n2 and the delay circuit 500, the logic gate G3 and the inverter iv3.

In the pulse width controller 300, the input terminal i3 and the output terminal o2 of the logic gate G2 can be coupled to the nodes n1 and n2 respectively, and the input terminal i4 can be coupled to another node n4. The input terminal i5 of the logic gate G3 can be coupled to the node n2. The input terminals i7, i8 and the output terminal o4 of the logic gate G4 can be coupled to an indication signal SCANEN, an indication signal WEI and the node n4 respectively. The signal SCANEN indicates whether the memory module 100 (FIG. 1) performs a scanning operation. When the signal SCANEN is logic 1, the memory module 100 performs a scan operation; when it is logic 0, the memory module 100 does not perform a scan operation, so data can be read or written. The signal WEI indicates whether the memory module 100 performs data reading. When the signal WEI is logic 0, the memory module 100 performs data writing; when it is logic 1, the memory module 100 performs data reading.

7a and 7b illustrate a state list and a state diagram of the finite state machine circuit 400 in one embodiment. As shown in FIG7a and 7b, in one embodiment of the present invention, the finite state machine circuit 400 can switch between states S0, P0, Launch, Idle0, Idle1 and P1; the logic values of nodes n5 and n7 (FIG4) can be regarded as inputs of the finite state machine circuit 400, and the logic value of node n6 can be regarded as outputs of the finite state machine circuit 400. The logic values of nodes n5, n7 and n6 are represented in the form of xy/z in FIG7a and 7b.

Continuing with FIG. 1 to FIG. 4 , FIG. 5 illustrates the waveform timing of each relevant signal in the control circuit 200 ( FIG. 4 ) when the memory module 100 ( FIG. 1 ) is reading data, wherein voltages vw1, vw3, vTBL, vi5, and vi6 are voltages of node w1, node w3, tracking bit line TBL (node n0), and input terminals i5 and i6, respectively. At a time point t0, the clock CLK starts to switch from voltage vck1 (e.g., a voltage representing logic 0) to voltage vck2 (e.g., a voltage representing logic 1). When the clock CLK switches from voltage vck1 to voltage vck2, the finite state machine circuit 400 (FIG. 4) can change the voltage of node n6 from supply voltage Vdd1 (which can represent logic 1) to ground voltage Vss1 (which can represent logic 0). As the voltage of node n6 changes, the operation of inverter iv2 and buffer bf2 causes the voltage vw1 of node w1 (FIG. 5) to start switching from voltage v3 (e.g., a voltage representing logic 0) to voltage v4 (e.g., a voltage representing logic 1) at a later time t1. Due to the length of the tracking word line TWL, the voltage vw3 of the node w3 switches from voltage v3 to voltage v4 after a delay time d1.

As the voltage of the tracking word line TWL switches to the voltage v4, the voltage vTBL of the tracking bit line TBL at the node n0 will start to change (e.g., decrease) from an initial voltage vpr0 after a time point t2, and change to a preset voltage vt0 at another time point t3. For example, the voltage vt0 can be the flip voltage of the inverter iv1; before the voltage of the node n0 has not changed to this voltage vt0 (i.e., before the time point t3), the inverter iv1 will determine the voltage of the node n0 as a logical 1; after the voltage of the node n0 changes to this voltage vt0 (i.e., after the time point t3), the inverter iv1 will switch to determine the voltage of the node n0 as a logical 0. Therefore, the inverter iv1 switches the logic 0 output to the input terminal i1 to the logic 1 after the time point t3. In response to the input change of the input terminal i1, the logic gate G1 causes the signal TBL_LB of the node n1 to start switching from the voltage v6 (e.g., a voltage representing the logic 1) to the voltage v5 (e.g., a voltage representing the logic 0) at the next time point t4.

During data reading, the signals SCANEN (FIG. 4) and WEI will cause the logic gate G4 to continuously output logic 0 from the output terminal o4 to the input terminal i4 of the logic gate G2. Therefore, when the signal TBL_LB starts to switch from voltage v6 to voltage v5 at time t4, the logic gate G2 will start to switch the voltage vi5 (FIG. 5) of the input terminal i5 from voltage v7 (e.g., a voltage representing logic 0) to voltage v8 (e.g., a voltage representing logic 1) at the next time t5. When the voltage vi5 of the input terminal i5 (FIG. 5) starts to switch from the voltage v7 to the voltage v8 at the time point t5, the voltage vi6 of the input terminal i6 will still be maintained at the voltage v7 due to the delay circuit 500 (FIG. 4) between the node n2 and the input terminal i6. Therefore, as the voltage vi5 starts to switch from the voltage v7 to the voltage v8 at the time point t5, the operation of the logic gate G3 and the inverter iv3 will cause the signal GS of the node n3 to switch from the level v1 (e.g., a level representing logic 0) to the level v2 (e.g., a level representing logic 1) at a later time point t6, that is, the signal GS starts to be activated. That is, as the tracking bit line TBL changes to the preset voltage vt0 at time t3, the inverter iv1, the logic gates G1, G2, G3 and the inverter iv3 are driven to operate in series, and then the signal GS starts to be activated at time t6.

When the signal TBL_LB of the node n1 starts to switch from the voltage v6 to the voltage v5 at the time t4, the buffer bf1 will cause the voltage of the node n5 to switch accordingly; in response to the voltage switching of the node n5, the finite state machine circuit 400 will change the voltage of the node n6 to the supply voltage Vdd1; the operation of the inverter iv2 and the buffer bf2 will cause the voltage vw1 of the node w1 to start switching from the voltage v4 back to the voltage v3 at a time t7. That is, as the tracking bit line TBL changes to the preset voltage vt0 at time t3, the inverter iv1, the logic gate G1 and the buffer bf1, the finite state machine circuit 400, the inverter iv2 and the buffer bf2 are also driven to operate in series, thereby causing the voltage vw1 of the node w1 to start changing at time t7 (switching from voltage v4 back to voltage v3).

When the voltage vw1 of node w1 starts to change at time t7, the tracking word line TWL will cause the voltage vw3 of node w3 to also start to change at another time t8 (= t7 + d1) after a delay time d1, switching from voltage v4 back to voltage v3. As the voltage of the tracking word line TWL returns to voltage v3, the voltage vTBL of the tracking bit line TBL can be restored to voltage vpr0.

As the voltage vw3 starts to switch from the voltage v4 back to the voltage v3 at the time t8, the logic gate G1 will make the signal TBL_LB start to switch from the voltage v5 back to the voltage v6 at a later time t9. In conjunction, the logic gate G2 will make the voltage vi5 of the input terminal i5 start to switch from the voltage v8 back to the voltage v7 at the later time t10, and the delay circuit 500 will make the voltage vi6 of the input terminal i6 start to switch from the voltage v8 back to the voltage v7 at another time t11 (=t10+d2) after the delay time d2. As the voltages vi5 and vi6 of the input terminals i5 and i6 are switched back to the voltage v7, the operation of the logic gate G3 and the inverter iv3 causes the signal GS to start switching from the level v2 back to the level v1 at a time point t12, and the signal GS is stopped from being excited. That is, as the voltage vw3 of the node w3 starts to change at the time point t8, the logic gates G1, G2, the delay circuit 500, the logic gate G3 and the inverter iv3 are driven to operate in series, and the signal GS is stopped from being excited at the time point t12.

From the above description, the pulse width control of the signal GS of the present invention can be briefly described as follows. When the voltage vTBL of the tracking bit line TBL changes to the preset voltage vt0 (time point t3), the pulse width controller 300 will activate the enable signal GS at time point t6 (through the operation of the inverter iv1, the logic gates G1, G2, G3 and the inverter iv3 from time points t3 to t6), and change the voltage vw1 of the node w1 at time point t7 (through the operation of the inverter iv1, the logic gate G1, the buffer bf1, the finite state machine circuit 400, the inverter iv2 and the buffer bf2 from time points t3 to t7). When the voltage vw1 of the node w1 changes at time t7, the voltage vw3 of the node w3 changes at time t8 after the delay time d1 following the word line TWL. When the voltage vw3 of the node w3 changes at time t8, the pulse width controller 300 stops activating the enable signal GS at time t12 after the delay time d2 (through the operation of the logic gates G1, G2, the delay circuit 500, the logic gate G3 and the inverter iv3 from time t8 to t12).

As shown in FIG5 , through the operation of the pulse width controller 300, the time interval from the "start of the excitation signal GS" (time point t6) to the "start of the stop excitation signal GS" (time point t12) (hereinafter referred to as the excitation time interval AT1) covers the sum of the delay times d1 and d2. Since a transient time (such as a rise time) is required after the "start of the excitation signal GS" to allow the signal GS to truly reach the excited level (such as the level of logic 1) from the unexcited level (such as the level of logic 0), the pulse width of the signal GS that is truly maintained at the excited level depends on the result of the excitation time interval minus the transient time. Since the signal GS needs to be transmitted to all sense amplifiers SA[1] to SA[K] (via buffers bf[1] to bf[K]), the more inputs and outputs the memory module has (the number of sense amplifiers K), the greater the impedance faced by the excitation signal GS, and consequently, the longer the transient time.

In conventional technology, the excitation time interval between "start excitation signal GS" and "start stop excitation signal GS" is fixed; therefore, if the number of inputs and outputs of the memory module is large and the transient time is long, the pulse width of the signal GS (the difference between the fixed excitation time interval and the longer transient time) will become relatively shorter, resulting in the problem of insufficient pulse width of the signal GS.

Compared to the fixed excitation time interval of the prior art, in the present invention, the excitation time interval AT1 between "start excitation signal GS" and "start stop excitation signal GS" is adaptive. If the number of inputs and outputs K of the memory module is large, the length of each word line WL[p] and the tracking word line TWL (Figure 1) will be longer, so the delay time d1 (Figure 5) will also be longer, and the excitation time interval AT1 covering the delay time d1 will also become longer. In this way, even if the transient time is longer, the pulse width of the signal GS (the difference between the longer excitation time interval and the longer transient time) will not be insufficient.

In the memory module 100, the control circuit 200 originally uses the tracking word line TWL to track the characteristics and performance of each word line WL[p], and dynamically adjusts the control of the memory module 100 accordingly. The pulse width controller 300 of the present invention further expands the use of the tracking word line TWL, and uses the existing tracking word line TWL for feedback (from the output end o1 to the input end i2) so that the length of the excitation time interval AT1 can be positively correlated with the number of inputs and outputs K, thereby ensuring that the signal GS has sufficient pulse width. In this way, the pulse width controller 300 of the present invention can be applied to various memory modules with different numbers of inputs and outputs. Furthermore, the delay circuit 500 in the pulse width controller 300 does not need too many series inverters to extend the activation time interval AT1, thereby reducing the layout area of the pulse width controller 300. In one embodiment, the buffer bf3 in the delay circuit 500 can be simply formed by two series inverters (not shown).

Continuing with Figures 1 to 5, Figure 6 illustrates a supply voltage configuration according to an embodiment of the present invention. In response to special requirements on power consumption, performance and/or operation, some memory modules will span different power domains, and different parts will use different supply voltages. For example, as shown in FIG. 6 , each sense amplifier SA[k] (k=1 to K) may include two parts s1[k] and s2[k], which belong to two power domains respectively; the part s1[k] may be biased between a supply voltage Vdd1 and a ground voltage Vss1, and powered by the supply voltage Vdd1 (e.g., a memory supply voltage), and the part s2[k] may be biased between another supply voltage Vdd2 and another ground voltage Vss2, and powered by the supply voltage Vdd2 (e.g., an interface supply voltage).

In an embodiment using a dual-rail sense amplifier mechanism, supply voltages Vdd1 and Vdd2 are different, supply voltage Vdd1 can be greater than or less than supply voltage Vdd2, and ground voltages Vss1 and Vss2 can be coupled together. Since portion s2[k] of each sense amplifier SA[k] is powered by supply voltage Vdd2, the operating speed of the sense amplifier SA[k] is related to the level of supply voltage Vdd2; and, as a result, the pulse width requirement of signal GS is also related to the level of supply voltage Vdd2. If the supply voltage Vdd2 is lower, the sense amplifier SA[k] operates slower and the pulse width of the signal GS should be longer so that the slower sense amplifier SA[k] has more time to sense. If the supply voltage Vdd2 is higher, the sense amplifier SA[k] operates faster and the pulse width of the signal GS can be shortened accordingly.

To adapt to the supply voltage Vdd2 of the sense amplifier SA[k], the delay circuit 500 (buffer bf3) in the pulse width controller 300 can be biased between the supply voltage Vdd2 and the ground voltage Vss2 like the portion s2[k] of the sense amplifier SA[k] and powered by the supply voltage Vdd2. On the other hand, the logic gates G1 to G4 and inverters iv1 and iv3 in the pulse width controller 300, as well as the finite state machine circuit 400, inverter iv2 and buffers bf1 and bf2 in the control pulse circuit 200 can be biased between the supply voltage Vdd1 and the ground voltage Vss1 like part s1[k] of the sense amplifier SA[k], and powered by the supply voltage Vdd1. Thus, the delay time d2 of the delay circuit 500 will be negatively related to the level of the supply voltage Vdd2; if the supply voltage Vdd2 is lower, the operation speed of the delay circuit 500 will be slower, and the delay time d2 will be longer; if the supply voltage Vdd2 is higher, the operation speed of the delay circuit 500 will be faster, and the delay time d2 will be shorter. Since the activation time interval AT1 of the signal GS covers the delay time d2 of the delay circuit 500 (FIG. 5), the length of the activation time interval AT1 will be negatively related to the level of the supply voltage Vdd2, just like the delay time d2; if the supply voltage Vdd2 is lower, the activation time interval AT1 and the pulse width of the signal GS will be adaptively extended; if the supply voltage Vdd2 is higher, the activation time interval AT1 and the pulse width of the signal GS will be adaptively shortened.

In another embodiment of the dual-rail sense amplifier mechanism, the buffer bf1 and/or bf2 may also be biased between the supply voltage Vdd2 and the ground voltage Vss2, and together with the auxiliary delay circuit 500, the activation time interval AT1 (FIG. 5) is negatively related to the supply voltage Vdd2. In another embodiment, the buffer bf1 and/or bf2 are biased between the supply voltage Vdd2 and the ground voltage Vss2, the delay circuit 500 may be omitted, and the logic gate G3 may be an inverter coupled between the node n2 and the inverter iv3.

Compared to the dual-rail sense amplifier mechanism, in another type of single-rail sense amplifier mechanism embodiment, the supply voltage Vdd2 can be equal to the supply voltage Vdd1, that is, the control circuit 200 and each sense amplifier SA[k] belong to the same power domain and are uniformly powered by the supply voltage Vdd1.

In summary, in the prior art, the enable signal of the sense amplifier is limited by a fixed excitation time interval and cannot adapt to the different needs of various memory modules. In contrast, the technology of the present invention can expand the use of existing tracking word lines. In the pulse width controller of the present invention, the feedback of the tracking word line is used to make the excitation time interval positively related to the number of inputs and outputs, so as to adapt to various memory modules with different numbers of inputs and outputs. Furthermore, in response to the dual-track sense amplifier mechanism, different parts of the pulse width controller of the present invention can also belong to different power supply domains, so that the excitation time interval of the enable signal can be negatively related to the supply voltage of the sense amplifier, thereby adapting to various memory modules with different supply voltage configurations.

In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person having ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the attached patent application.

100: memory module 130, 140: peripheral circuit 200: control circuit 300: pulse width controller 400: finite state machine circuit 500: delay circuit WL[1]-WL[P]: word line BL[1]-BL[Q], BLb[1]-BLb[Q]: bit line c[1,1]-c[P,Q]: memory cell TWL: tracking word line CLK: clock D1: distance TBL, TBLb: tracking bit line w0: auxiliary word line tc[1]-tc[P]: tracking cell bf[1]-bf[K], bf1-bf3: buffer SA[1]-SA[K]: sense amplifier WB[1]-WB[K]: write circuit A[p,q], B[p,q]: transistor n0-n7, w1-w3: node T1: cycle pw1: pulse width G1-G4: logic gate i1-i8: input o1-o4: output iv1-iv3, iA[p,q], iB[p,q]: inverter L[p,q]: latch GS, TBL_LB, SCANEN, WEI: signal v1-v2: level vck1-vck2, vWL1-vWL2, v3-v8, vpr0, vt0: voltage vWL[p], vw1, vw3, vTBL, vi5, vi6: voltage AT1: triggering time ta1-ta6, t0-t12: timing Vdd1, Vdd2: supply voltage Vss1, Vss2: ground voltage s1[1]-s1[K], s2[1]-s2[K]: part S0, P0, Launch, Idle0, P1, Idle1: status x, y, z: logical value

FIG. 1 illustrates a memory module according to an embodiment of the present invention, which may include a plurality of memory cells and a control circuit. FIG. 2 illustrates an embodiment of the memory cell of FIG. 1. FIG. 3 illustrates an embodiment of the waveform timing of the memory module of FIG. 1 when reading data. FIG. 4 illustrates an embodiment of the control circuit of FIG. 1. FIG. 5 illustrates an embodiment of the waveform timing of the control circuit of FIG. 4. FIG. 6 illustrates an embodiment of the supply voltage configuration in FIG. 4. FIG. 7a and FIG. 7b illustrate a state list and a state diagram of the finite state machine circuit in FIG. 4 in an embodiment.

200: Control circuit 300: Pulse width controller 400: Finite state machine circuit 500: Delay circuit TBL: Follow bit line TWL: Follow word line n0-n7, w1-w3: Node G1-G4: Logic gate i1-i8: Input o1-o4: Output iv1-iv3: Inverter bf[1]-bf[K], bf1-bf3: Buffer SA[1]-SA[K]: Sense amplifier CLK: Clock GS, TBL_LB, SCANEN, WEI: Signal Vdd1: Supply voltage Vss1: Ground voltage

Claims (20)

A memory module capable of improving the timing adaptability of sensing and amplification comprises: At least one bit line, at least one word line, a tracking bit line and a tracking word line; the tracking word line comprises a front node and a rear node, and the length between the front node and the rear node is positively correlated with the length of each word line; At least one memory cell, each memory cell is coupled to one of the at least one bit line and one of the at least one word line; At least one tracking cell is coupled to the tracking bit line; At least one sensing amplifier, each sensing amplifier is coupled to one of the at least one bit line; A pulse width controller is coupled to the tracking bit line, a first node, the front node, the rear node and each of the sensing amplifiers, and controls the voltage of the first node according to the voltage of the tracking bit line and the voltage of the rear node, and controls whether each of the sensing amplifiers is enabled according to the voltage of the first node; and a finite state machine circuit is coupled to a clock, the first node and the front node, and controls the voltage of the front node according to the voltage of the clock and the voltage of the first node. A memory module as described in claim 1, wherein: In response to the voltage of the clock changing from a first clock voltage to a second clock voltage, the finite state machine circuit changes the voltage of the front node from a third voltage to a fourth voltage; In response to the voltage of the front node changing from the third voltage to the fourth voltage, the tracking word line changes the voltage of the rear node from the third voltage to the fourth voltage after a first delay time; In response to the voltage of the rear node changing from the third voltage to the fourth voltage, the voltage of the tracking bit line begins to change; and In response to the voltage of the tracking bit line changing to a preset voltage, the pulse width controller changes the voltage of the first node from a sixth voltage to a fifth voltage and enables each of the sense amplifiers. A memory module as described in claim 2, wherein: In response to the voltage of the first node changing from the sixth voltage to the fifth voltage, the finite state machine circuit changes the voltage of the front node from the fourth voltage to the third voltage; In response to the voltage of the front node changing from the fourth voltage to the third voltage, the tracking word line changes the voltage of the rear node from the fourth voltage to the third voltage after the first delay time; and In response to the voltage of the rear node changing from the fourth voltage to the third voltage, the pulse width controller stops enabling each of the sense amplifiers after a second delay time. A memory module as described in claim 3, wherein: the pulse width controller is partially powered by a first supply voltage; each of the sense amplifiers is at least partially powered by a second supply voltage; the first supply voltage is different from the second supply voltage; and the length of the second delay time is negatively related to the magnitude of the second supply voltage. A memory module as claimed in claim 1, wherein the pulse width controller has two parts which are respectively powered by two phase-different supply voltages. A memory module as claimed in claim 1, wherein each of the sense amplifiers has two parts which are respectively powered by two out-of-phase supply voltages. A memory module as described in claim 1, wherein: the pulse width controller includes a third logic gate and a delay circuit; the third logic gate includes a fifth input terminal and a sixth input terminal; and the delay circuit is coupled between the fifth input terminal and the sixth input terminal. A memory module as described in claim 7, wherein the third logic gate is an NOR gate. A memory module as described in claim 7, wherein: the third logic gate further comprises a third output terminal; the pulse width controller is coupled to each of the sense amplifiers at a third node; and the pulse width controller further comprises a third inverter coupled between the third output terminal and the third node. A memory module as described in claim 7, wherein the third logic gate and the delay circuit are powered by a first supply voltage and a second supply voltage respectively, and the first supply voltage is different from the second supply voltage. A memory module as described in claim 10, wherein each of the sense amplifiers comprises two parts, which are powered by the first supply voltage and the second supply voltage respectively. A memory module as described in claim 7, wherein: The pulse width controller further includes a first logic gate; and The first logic gate includes a first input terminal, a second input terminal and a first output terminal, which are respectively coupled to the tracking bit line, the rear node and the first node. The memory module of claim 12, wherein the first logic gate is a NAND gate. A memory module as described in claim 12, wherein the pulse width controller further includes a first inverter coupled between the tracking bit line and the first input terminal. A memory module as described in claim 7, wherein: The pulse width controller further includes a second logic gate; and The second logic gate includes a third input terminal, a fourth input terminal and a second output terminal, which are respectively coupled to the first node, a fourth node and the fifth input terminal. A memory module as described in claim 15, wherein the second logic gate is a NOR gate. A memory module as described in claim 15, wherein: The pulse width controller further includes a fourth logic gate; and The fourth logic gate includes a seventh input terminal, an eighth input terminal and a fourth output terminal, which are respectively coupled to a first indication signal, a second indication signal and the fourth node. A memory module as described in claim 17, wherein the fourth logic gate is a NOR gate. A memory module as described in claim 7, wherein: In response to the voltage of the first node changing from a sixth voltage to a fifth voltage, the finite state machine circuit changes the voltage of the front node from a fourth voltage to a third voltage; In response to the voltage of the front node changing from the fourth voltage to the third voltage, the tracking word line changes the voltage of the rear node from the fourth voltage to the third voltage after a first delay time. A memory module as described in claim 19, wherein: In response to the voltage of the rear node changing from the fourth voltage to the third voltage, the voltage of the fifth input terminal changes from an eighth voltage to a seventh voltage; In response to the voltage of the fifth input terminal changing from the eighth voltage to the seventh voltage, the delay circuit changes the voltage of the sixth input terminal from the eighth voltage to the seventh voltage after a second delay time; In response to the voltage of the sixth input terminal changing from the eighth voltage to the seventh voltage, the pulse width controller stops enabling each of the sense amplifiers.

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