TWI874110B - Planarization method for imd in gan metal-insulator-semiconductor high-electron-mobility transistor (mis-hemt) and mis-hemt using the same - Google Patents

Abstract

The embodiment of the present invention relates to a planarization method for IMD in GaN MIS-HEMT and a MIS-HEMT using the same. The method includes: performing a GaN MIS-HEMT process in a semiconductor substrate; performing a PECVD on the GaN MIS-HEMT to obtain a first upper oxide layer; performing a spin coating process by a polymer material on the first upper oxide layer to obtain a spin layer; performing an etching-back process; and performing a PECVD to obtain a second upper oxide layer.

Description

Metal dielectric layer planarization method of metal-insulated semiconductor enhanced high electron mobility transistor based on gallium nitride and metal-insulated semiconductor enhanced high electron mobility transistor using the same

The present invention relates to a semiconductor manufacturing process technology, and in particular to a method for planarizing a metal inter-dielectric layer of a metal insulating layer semiconductor enhanced high electron mobility transistor based on gallium nitride and a metal insulating layer semiconductor enhanced high electron mobility transistor using the same.

Gallium nitride metal insulator semiconductor enhanced high electron mobility transistor (GaN MIS-HEMT) has attracted widespread attention in the field of semiconductor manufacturing. Its unique performance and advantages make it an ideal choice for the next generation of high-power and high-frequency applications. Gallium nitride material itself has excellent electronic properties. Gallium nitride is a wide bandgap semiconductor with excellent electron saturation drift velocity, high electric field response, and excellent thermal properties. These characteristics enable gallium nitride devices to perform well in high-temperature and high-frequency applications, while having excellent power conversion efficiency.

Secondly, the metal insulator semiconductor structure provides a better ability to control and regulate current for the metal insulator semiconductor enhanced high electron mobility transistor of gallium nitride. The metal insulator can prevent the current leakage of electrons between the channel and the gate, thereby improving the switching speed and efficiency of the device. In addition, the metal insulator also helps to reduce leakage current and improve the reliability of the device. One of the most significant advantages is high electron mobility. Due to the special structure of gallium nitride material, gallium nitride metal-insulated semiconductor-enhanced high electron mobility transistors can achieve high electron mobility, which means that when carriers move in the crystal, they encounter relatively little resistance.

In order to more effectively utilize the device area, GaN-based metal-insulated semiconductor-enhanced high-electron-mobility transistors widely use the Circuit Under Pad (CUP) technology. This technology places the circuit layout under the chip packaging area, allowing the chip surface to be more fully used for other functions or components.

FIG1 is a cross-sectional view of a GaN-based metal insulating layer semiconductor enhanced high electron mobility transistor of the prior art. Referring to FIG1 , in this embodiment, in order to electrically connect the GaN-based metal insulating layer semiconductor enhanced high electron mobility transistor circuit below, and because the high voltage device requires a sufficiently thick metal layer MT2, MT3, MT4 and a sufficiently thick inter-metal dielectric (IMD) layer to resist bonding stress and increase withstand voltage. However, the successful implementation of the circuit under pad technology requires high flatness of the inter-metal dielectric (IMD) layer. If the intermetallic dielectric layer is not flat and the height difference is too large, it will exceed the exposure focus distance (Depth Of Focus, DOF) of the subsequent yellow light process. This will cause the subsequent metal layer MT2, MT3, and MT4 images to be unable to be resolved, and electrical abnormalities may occur, reducing the performance and reliability of the device.

The present invention provides a method for planarizing a metal inter-dielectric layer of a gallium nitride-based metal insulating layer semiconductor enhanced high electron mobility transistor and a gallium nitride-based metal insulating layer semiconductor enhanced high electron mobility transistor using the method, which is used to planarize the gallium nitride metal insulating layer semiconductor enhanced high electron mobility transistor, thereby allowing the circuit under pad to be implemented, increasing the yield and reducing the cost.

The embodiment of the present invention provides a method for planarizing the intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulating layer of gallium nitride. The method for planarizing the metal inter-dielectric layer of the metal insulating layer semiconductor enhanced high electron mobility transistor based on gallium nitride includes: performing a metal insulating layer semiconductor enhanced high electron mobility transistor process of gallium nitride on a substrate; performing chemical vapor deposition of an oxide layer on the above-mentioned metal insulating layer semiconductor enhanced high electron mobility transistor of gallium nitride to obtain a first upper oxide layer; performing a spin coating process on a polymer material on the above-mentioned first upper oxide layer to obtain a spin coating layer; performing a back etching; performing chemical vapor deposition of an oxide layer to obtain a second upper oxide layer.

An embodiment of the present invention provides a gallium nitride metal-insulated semiconductor enhanced high electron mobility transistor. The gallium nitride metal-insulated semiconductor enhanced high electron mobility transistor includes a semiconductor substrate, a gallium nitride metal-insulated semiconductor enhanced high electron mobility transistor circuit and a flat surface. The gallium nitride metal-insulated semiconductor enhanced high electron mobility transistor circuit is configured on the above-mentioned semiconductor substrate. The flat plane is arranged on a metal insulating layer semiconductor enhanced high electron mobility transistor circuit of gallium nitride, and the flat plane includes a first upper oxide layer, a first spin coating layer and a second upper oxide layer. The first upper oxide layer is vapor-deposited on the metal insulating layer semiconductor enhanced high electron mobility transistor circuit of gallium nitride. The first spin coating layer is spin-coated on the first upper oxide layer. The second upper oxide layer is arranged on the first upper oxide layer and the spin coating layer.

According to the preferred embodiment of the present invention, the metal inter-dielectric layer planarization method of the metal insulating layer semiconductor enhanced high electron mobility transistor based on gallium nitride and the metal insulating layer semiconductor enhanced high electron mobility transistor using the same, wherein the polymer material is subjected to the spin coating process on the above-mentioned first upper oxide layer to obtain the first spin coating layer, including: performing a spin coating glass (SOG) process to obtain the first spin coating layer. In another preferred embodiment, the polymer material is subjected to the spin coating process on the first upper oxide layer to obtain the first spin coating layer, including: a polyimide is subjected to the spin coating process to obtain the first spin coating layer.

According to the method for planarizing the metal inter-dielectric layer of the metal-insulated semiconductor enhanced high electron mobility transistor based on gallium nitride and the metal-insulated semiconductor enhanced high electron mobility transistor using the same described in the preferred embodiment of the present invention, the planarized plane further includes a second spin coating layer and a third upper oxide layer. The second spin coating layer is disposed on the second upper oxide layer. The third upper oxide layer is arranged on the second spin coating layer, wherein the method for manufacturing the flat plane further comprises: performing the spin coating process on the second upper oxide layer to obtain the second spin coating layer; performing the etching back; and performing chemical vapor deposition on the oxide layer to obtain the third upper oxide layer.

In summary, the embodiment of the present invention uses a spin coating process to spin-coat the deposited oxide layer after the oxide layer is deposited on the metal insulating layer semiconductor enhanced high electron mobility transistor circuit of gallium nitride, and then the excess polymer material and the uneven oxide layer are etched away by etching back. After that, the oxide layer is deposited again to make the metal insulating layer semiconductor enhanced high electron mobility transistor of gallium nitride more flat, so that the image resolution of the metal layer can be improved in the subsequent yellow light process, so that the circuit under pad (CUP) can be implemented. This can reduce the chip size and increase the total number of gross dies that can be cut from the wafer.

In order to further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and accompanying drawings, so that the purpose, features and concepts of the present invention can be thoroughly and specifically understood. However, the following detailed description and accompanying drawings are only used for reference and explanation of the implementation of the present invention, and are not used to limit the present invention.

Reference will now be made in detail to exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and the specification to refer to the same or similar components. In addition, the exemplary embodiments are only one of the implementation methods of the design concept of the present invention, and the following examples are not intended to limit the present invention.

As mentioned above, in order to make the circuit under pad (CUP) above the metal insulating layer of gallium nitride semiconductor enhanced high electron mobility transistor circuit, the subsequent metal layer needs to be deposited. If there is a depression, the metal layer will fill the height difference. Since the metal layer will be etched later to define the pattern (PATTERN), the height difference will cause the thickness to be different, resulting in electrical abnormalities. In addition, for yellow light analysis, there is an optimal depth of focus (Depth Of Focus, DOF). If the height difference is too large, it will exceed the exposure focus distance of the subsequent yellow light process, resulting in the metal layer image cannot be resolved, resulting in residual problems. When stacking many layers of metal, the higher the metal layer is, the greater the height difference will be, and the clarity of the image will be worse.

In order to solve the above problems, FIG2 is a flow chart of a method for planarizing the intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulating layer of gallium nitride according to a preferred embodiment of the present invention. Referring to FIG2, the method for planarizing the intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulating layer of gallium nitride includes the following steps:

Step S201: Start.

Step S202: Performing a gallium nitride metal insulating layer semiconductor enhanced high electron mobility transistor process on a substrate. FIG3A is a schematic diagram of step S202 of a method for planarizing a metal dielectric layer of a gallium nitride metal insulating layer semiconductor enhanced high electron mobility transistor according to a preferred embodiment of the present invention. Referring to FIG3A , in this step, a gallium nitride metal insulating layer semiconductor enhanced high electron mobility transistor circuit 301 is fabricated on a substrate.

Step S203: Perform chemical vapor deposition of an oxide layer on the above-mentioned metal insulating layer semiconductor enhanced high electron mobility transistor circuit of gallium nitride. FIG3B is a schematic diagram of step S203 of a method for planarizing a metal dielectric layer of a metal insulating layer semiconductor enhanced high electron mobility transistor based on gallium nitride according to a preferred embodiment of the present invention. Referring to FIG3B , a first upper oxide layer 302 is obtained by chemical vapor deposition of the above-mentioned oxide layer.

Step S204: On the first upper oxide layer, a polymer material is subjected to a spin coating process to obtain a spin coating layer. FIG3C is a schematic diagram of step S204 of a method for planarizing a metal inter-dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention. Please refer to FIG3C , the spin coating layer 303 of this step can be, for example, a spin on glass (SOG) process. However, it should be known that polyimide or other polymer materials can also be subjected to a spin coating process to form the above-mentioned spin coating layer 303. The present invention is not limited thereto. In addition, if the spin coating uses spin-on glass SOG, it will also go through a baking process, but the description is omitted here.

Step S205: perform an etch back. FIG3D is a schematic diagram of step S205 of a method for planarizing a metal dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulating layer of gallium nitride according to a preferred embodiment of the present invention. Referring to FIG3D , after the above spin-on glass process is completed, the excess spin-on glass is removed by, for example, plasma etching, and a portion of the above-mentioned first upper oxide layer is removed.

Step S206: Perform chemical vapor deposition of an oxide layer to obtain a second upper oxide layer. FIG3E is a schematic diagram of step S206 of a method for planarizing a metal dielectric layer of a semiconductor enhanced high electron mobility transistor based on a gallium nitride metal insulating layer according to a preferred embodiment of the present invention. Please refer to FIG3E. Since step S204 uses a polymer material, which is generally in a viscous liquid state, the second upper oxide layer 304 is required to cover the material to avoid subsequent through hole (VIA) drilling and metal layer deposition, which may cause poor electrical properties due to the fluidity of the liquid.

Step S207: On the second upper oxide layer, the polymer material is subjected to the above-mentioned spin coating process to obtain a second spin coating layer. FIG3F is a schematic diagram of step S207 of a method for leveling a metal inter-dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulating layer of gallium nitride according to a preferred embodiment of the present invention. Referring to FIG3F , in this embodiment, assuming that after the above-mentioned oxide layer chemical vapor deposition is completed and the second upper oxide layer 304 obtained is still not flat enough, the spin coating process will be performed again to obtain a spin coating layer 305.

Step S208: Perform the above-mentioned etching back. FIG. 3G is a schematic diagram of step S208 of a method for planarizing a metal dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulating layer of gallium nitride according to a preferred embodiment of the present invention. Referring to FIG. 3G , this step is also to remove the excess portion of the above-mentioned spin coating layer 305 by, for example, plasma etching, and to remove part of the second upper oxide layer 304.

Step S209: Perform chemical vapor deposition of the above-mentioned oxide layer to obtain the third upper oxide layer. FIG3H is a schematic diagram of step S209 of a method for leveling the metal inter-dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulating layer of gallium nitride according to a preferred embodiment of the present invention. Please refer to FIG3H. For the same reason, since step S208 uses a polymer material, which is generally in a viscous liquid state, the third upper oxide layer 306 is required to cover it to avoid subsequent through hole (VIA) drilling and metal layer deposition, which may cause poor electrical properties due to the fluidity of the liquid.

FIG. 3H of the above embodiment is the lower half of the GaN metal insulating layer semiconductor enhanced high electron mobility transistor of a preferred embodiment of the present invention, and the upper half will be subjected to metal sputtering, through hole setting and circuit under pad (CUP) related processes. No further details will be given here.

In the above embodiment, if the flatness requirement is met when step S206 is completed, steps S207 to S209 do not need to be performed. The present invention is not limited to this embodiment. In addition, for the sake of flatness, a thicker oxide layer can actually be deposited in step S203. However, depositing a thick oxide layer will greatly extend the process time, which is much longer than the time for executing steps S204 to S209, and the production efficiency will be greatly reduced. Therefore, the above embodiment can also increase the production efficiency.

In addition, some people may think of increasing the thickness of the metal layer to, for example, three times the thickness and directly sputtering it, which can ideally also achieve a circuit under pad (CUP). However, those with ordinary knowledge in the relevant technical field should know that the metal sputtering process can only achieve 4um at a time. Continuously performing metal sputtering four times will result in a hardening layer (interface oxidation resistance) between the metal sputtering and the metal sputtering layer interface, resulting in a very high interface resistance. Ultimately, it will cause poor electrical properties. Therefore, the preferred embodiment of the present invention can not only increase the production speed, but also relatively reduce the above-mentioned poor electrical properties, which can increase the production yield.

In summary, the embodiment of the present invention uses a spin coating process to spin-coat the deposited oxide layer after the oxide layer is deposited on the metal insulating layer semiconductor enhanced high electron mobility transistor circuit of gallium nitride, and then the excess polymer material and the uneven oxide layer are etched away by etching back. After that, the oxide layer is deposited again to make the metal insulating layer semiconductor enhanced high electron mobility transistor of gallium nitride more flat, so that the image resolution of the metal layer can be improved in the subsequent yellow light process, so that the circuit under pad (CUP) can be implemented. This can reduce the chip size and increase the total number of gross dies that can be cut from the wafer.

It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes thereto will be suggested to those skilled in the art and are to be included within the spirit and scope of the present application and the scope of the appended claims.

S201-S209: Process steps of a method for leveling a metal inter-dielectric layer of a metal insulating layer semiconductor enhanced high electron mobility transistor based on gallium nitride according to a preferred embodiment of the present invention 301: Metal insulating layer semiconductor enhanced high electron mobility transistor circuit of gallium nitride 302: First upper oxide layer 303: Spin coating layer 304: Second upper oxide layer 305: Spin coating layer 306: Third upper oxide layer

The accompanying drawings are provided to enable a person with ordinary knowledge in the art to which the present invention belongs to further understand the present invention, and are incorporated into and constitute a part of the specification of the present invention. The accompanying drawings show exemplary embodiments of the present invention, and are used together with the specification of the present invention to explain the principles of the present invention.

FIG. 1 is a cross-sectional view of a prior art GaN-based metal insulating layer semiconductor enhanced high electron mobility transistor.

FIG. 2 is a flow chart showing a method for planarizing an intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention.

FIG. 3A is a schematic diagram of step S202 of a method for planarizing an intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention.

FIG. 3B is a schematic diagram of step S203 of a method for planarizing an intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention.

FIG. 3C is a schematic diagram of step S204 of a method for planarizing an intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention.

FIG. 3D is a schematic diagram of step S205 of a method for planarizing an intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention.

FIG. 3E is a schematic diagram of step S206 of a method for planarizing an intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention.

FIG. 3F is a schematic diagram of step S207 of a method for planarizing an intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention.

FIG. 3G is a schematic diagram of step S208 of a method for planarizing an intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention.

FIG. 3H is a schematic diagram of step S209 of a method for planarizing an intermetallic dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulation layer of gallium nitride according to a preferred embodiment of the present invention.

S201~S209: Process steps of a method for leveling the metal inter-dielectric layer of a semiconductor enhanced high electron mobility transistor based on a metal insulating layer of gallium nitride according to a preferred embodiment of the present invention

Claims (10)

A method for planarizing a metal inter-dielectric layer of a metal insulating layer semiconductor enhanced high electron mobility transistor based on gallium nitride, comprising: Performing a process for a metal insulating layer semiconductor enhanced high electron mobility transistor based on gallium nitride on a substrate; Performing chemical vapor deposition of an oxide layer on the above-mentioned metal insulating layer semiconductor enhanced high electron mobility transistor to obtain a first upper oxide layer; Performing a spin coating process, which is to spin-coat a polymer material on the above-mentioned first upper oxide layer to obtain a first spin coating layer; Performing a back etching (plasma etching); and The above-mentioned oxide layer is chemically vapor deposited to obtain a second upper oxide layer. According to the method for planarizing the metal inter-dielectric layer of the metal insulating layer semiconductor enhanced high electron mobility transistor based on gallium nitride as described in claim 1, the polymer material is subjected to the spin coating process on the first upper oxide layer to obtain the first spin coating layer, including: Subjecting a monoimide polymer (polyimide) to the spin coating process to obtain the first spin coating layer. According to the method for planarizing the metal inter-dielectric layer of the semiconductor enhanced high electron mobility transistor based on the metal insulating layer of gallium nitride described in claim 1, the polymer material is subjected to the spin coating process on the first upper oxide layer to obtain the first spin coating layer, including: Performing a spin coating glass (SOG) process to obtain the first spin coating layer. According to claim 1, the method for planarizing the metal inter-dielectric layer of the semiconductor enhanced high electron mobility transistor based on the metal insulating layer of gallium nitride further includes: On the second upper oxide layer, the polymer material is subjected to the spin coating process to obtain a second spin coating layer; Performing the above-mentioned etching back; and Performing chemical vapor deposition of the above-mentioned oxide layer to obtain a third upper oxide layer. According to the method for planarizing the intermetallic dielectric layer of the semiconductor enhanced high electron mobility transistor based on the metal insulating layer of gallium nitride described in claim 1, the etching back comprises: Performing a plasma etching to remove the excess first spin coating layer. A gallium nitride metal insulating layer semiconductor enhanced high electron mobility transistor, comprising: A semiconductor substrate; A gallium nitride metal insulating layer semiconductor enhanced high electron mobility transistor circuit, arranged on the semiconductor substrate; A flat plane, arranged on the gallium nitride metal insulating layer semiconductor enhanced high electron mobility transistor circuit, comprising: A first upper oxide layer, vapor-deposited on the gallium nitride metal insulating layer semiconductor enhanced high electron mobility transistor circuit; A first spin coating layer, spin-coated on the first upper oxide layer; A second upper oxide layer is disposed on the first upper oxide layer and the spin coating layer. According to the metal insulating layer semiconductor enhanced high electron mobility transistor of gallium nitride described in claim 6, the method for making the flat surface includes: Performing chemical vapor deposition of an oxide layer on the metal insulating layer semiconductor enhanced high electron mobility transistor circuit of gallium nitride to obtain the first upper oxide layer; Performing a spin coating process on a polymer material on the first upper oxide layer to obtain the first spin coating layer; Performing a back etching; and Performing chemical vapor deposition of the oxide layer to obtain the second upper oxide layer. According to the metal insulating layer semiconductor enhanced high electron mobility transistor of gallium nitride described in claim 6, the flat plane includes: a second spin coating layer, arranged on the second upper oxide layer; and a third upper oxide layer, arranged on the second spin coating layer, wherein the method for making the flat plane also includes: on the second upper oxide layer, a polymer material, is subjected to the spin coating process to obtain the second spin coating layer; etching back; and chemical vapor deposition of the oxide layer to obtain the third upper oxide layer. According to the metal-insulated semiconductor enhanced high electron mobility transistor of gallium nitride described in claim 6, the first spin coating layer includes: A polyimide polymer. According to the metal-insulated semiconductor enhanced high electron mobility transistor of gallium nitride described in claim 6, the first spin-coated layer includes: A spin-coated glass (SOG).

Images