TWI873892B - Electronic package and manufacturing method thereof - Google Patents
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- TWI873892B TWI873892B TW112137927A TW112137927A TWI873892B TW I873892 B TWI873892 B TW I873892B TW 112137927 A TW112137927 A TW 112137927A TW 112137927 A TW112137927 A TW 112137927A TW I873892 B TWI873892 B TW I873892B
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- H10W44/20—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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Abstract
Description
本發明係有關一種半導體封裝製程,尤指一種具有天線之電子封裝件。 The present invention relates to a semiconductor packaging process, in particular to an electronic package with an antenna.
目前的多媒體內容因畫質的提升而造成其檔案資料量變得更大,故無線傳輸的頻寬也需變大,因而產生第五代的無線傳輸(5G)技術。另5G因傳輸頻率較高,其相關無線通訊模組的尺寸的要求也較高。 As the image quality of current multimedia content increases, the file size becomes larger, so the bandwidth of wireless transmission also needs to increase, resulting in the fifth generation of wireless transmission (5G) technology. In addition, due to the higher transmission frequency of 5G, the size requirements of its related wireless communication modules are also higher.
此外,當天線結構為平面型時,該天線結構與電子元件之間的電磁輻射特性將受到限制,從而難以提升天線效能。 In addition, when the antenna structure is planar, the electromagnetic radiation characteristics between the antenna structure and the electronic components will be limited, making it difficult to improve the antenna performance.
因此,如何克服上述習知技術之問題,實已成為目前業界亟待克服之課題。 Therefore, how to overcome the above-mentioned knowledge and technology problems has become an urgent issue that the industry needs to overcome.
鑒於上述習知技術之缺失,本發明提供一種電子封裝件,係包括:封裝模組,係包含一電子元件及複數電性連接該電子元件之電性接點;以及天線模組,係堆疊於該封裝模組上,且該天線模組係包含一具有相對之 第一表面與第二表面的板體、一結合該第一表面之線路部、及一結合該第二表面之天線部,其中,該線路部接置於該複數電性接點上,且該天線部與該線路部相互電磁耦合,以於該天線模組內形成駐波。 In view of the above-mentioned deficiencies in the prior art, the present invention provides an electronic package, comprising: a package module, comprising an electronic component and a plurality of electrical contacts electrically connected to the electronic component; and an antenna module, stacked on the package module, and the antenna module comprises a plate having a first surface and a second surface opposite to each other, a circuit portion coupled to the first surface, and an antenna portion coupled to the second surface, wherein the circuit portion is connected to the plurality of electrical contacts, and the antenna portion and the circuit portion are electromagnetically coupled to each other to form a stationary wave in the antenna module.
本發明復提供一種電子封裝件之製法,係包括:於一承載件上形成封裝模組,且該封裝模組係包含一電子元件及複數電性連接該電子元件之電性接點;將天線模組堆疊於該封裝模組上,且該天線模組係包含一具有相對之第一表面與第二表面的板體、一結合該第一表面之線路部、及一結合該第二表面之天線部,其中,該線路部接置於該複數電性接點上,且該天線部與該線路部相互電磁耦合,以於該天線模組內形成駐波;以及移除該承載件。 The present invention further provides a method for manufacturing an electronic package, comprising: forming a package module on a carrier, wherein the package module includes an electronic component and a plurality of electrical contacts electrically connected to the electronic component; stacking an antenna module on the package module, wherein the antenna module includes a plate having a first surface and a second surface opposite to each other, a circuit portion coupled to the first surface, and an antenna portion coupled to the second surface, wherein the circuit portion is connected to the plurality of electrical contacts, and the antenna portion and the circuit portion are electromagnetically coupled to each other to form a stationary wave in the antenna module; and removing the carrier.
前述之電子封裝件及其製法中,該封裝模組之製程係包括:於該承載件上形成一承載結構;於該承載結構上形成複數導電柱,且於該承載結構上設置該電子元件,以令該承載結構電性連接該電子元件與該複數導電柱;以及於該承載結構上形成包覆層,使該包覆層包覆該複數導電柱與該電子元件,並使該複數導電柱之端面外露於該包覆層,以作為該電性接點。 In the aforementioned electronic package and its manufacturing method, the manufacturing process of the packaging module includes: forming a supporting structure on the supporting member; forming a plurality of conductive posts on the supporting structure, and arranging the electronic component on the supporting structure so that the supporting structure electrically connects the electronic component and the plurality of conductive posts; and forming a coating layer on the supporting structure, so that the coating layer covers the plurality of conductive posts and the electronic component, and the end faces of the plurality of conductive posts are exposed on the coating layer to serve as the electrical contacts.
前述之電子封裝件及其製法中,該複數電性接點係提供接地。 In the aforementioned electronic package and its manufacturing method, the plurality of electrical contacts provide grounding.
前述之電子封裝件及其製法中,該板體係為半導體板材,其具有複數貫穿之導電矽穿孔。 In the aforementioned electronic package and its manufacturing method, the board is a semiconductor board having a plurality of conductive silicon through-holes.
前述之電子封裝件及其製法中,該天線部係為天線層形式。 In the aforementioned electronic package and its manufacturing method, the antenna portion is in the form of an antenna layer.
由上可知,本發明之電子封裝件及其製法,主要藉由將天線模組堆疊於該封裝模組上,且該天線模組產生駐波,從而得到較佳的天線效能。 As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly obtain better antenna performance by stacking the antenna module on the package module, and the antenna module generates stationary waves.
1:電子封裝件 1: Electronic packaging
2a:封裝模組 2a: Packaging module
2b:天線模組 2b: Antenna module
20:承載結構 20: Load-bearing structure
20a:第一側 20a: First side
20b:第二側 20b: Second side
200:第一絕緣層 200: First insulation layer
201:第一線路層 201: First circuit layer
21:電子元件 21: Electronic components
21a:作用面 21a: Action surface
21b:非作用面 21b: Non-active surface
210:電極墊 210:Electrode pad
211:導電凸塊 211: Conductive bump
22:天線部 22: Antenna Department
23:導電柱 23: Conductive column
23a:端面 23a: End face
230:電性接點 230: Electrical contact
24:板體 24: Board
24a:第一表面 24a: First surface
24b:第二表面 24b: Second surface
240:導電矽穿孔 240: Conductive silicon vias
25:包覆層 25: Coating layer
26:線路部 26: Circuit Department
260:第二絕緣層 260: Second insulation layer
261:第二線路層 261: Second circuit layer
27:導電元件 27: Conductive element
28:導電凸塊 28: Conductive bump
9:承載件 9: Carrier
90:暫時性結合層 90: Temporary bonding layer
F:駐波 F: Resident in Bo
L:傳送路徑 L: Transmission path
S:切割路徑 S: cutting path
圖1係為本發明之電子封裝件之剖面示意圖。 Figure 1 is a schematic cross-sectional view of the electronic package of the present invention.
圖2A至圖2E係為本發明之電子封裝件之製法之剖視示意圖。 Figures 2A to 2E are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the restrictive conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second" and "one" used in this specification are only used to facilitate the clarity of the description, and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships, without substantially changing the technical content, should also be regarded as the scope of implementation of the present invention.
圖1係為本發明之電子封裝件1之剖面示意圖。如圖1所示,該電子封裝件1係包括一封裝模組2a以及一堆疊於該封裝模組2a上之天線模組2b。
FIG1 is a schematic cross-sectional view of the electronic package 1 of the present invention. As shown in FIG1 , the electronic package 1 includes a
所述之封裝模組2a係包含至少一電子元件21及複數電性連接該電子元件21之電性接點230。
The
所述之天線模組2b係包含一具有相對之第一表面24a與第二表面24b的板體24、一結合該第一表面24a之線路部26、及一結合該第二表面24b之天線部22,其中,該線路部26接置於該複數電性接點230上,且
該天線部22與該線路部26相互電磁耦合,以於該天線模組2b內形成駐波F。
The
於一實施例中,該封裝模組2a復包括:一承載結構20,係承載該電子元件21並電性連接該電子元件21;複數導電柱23,係設於該承載結構20上並電性連接該承載結構20;以及一包覆層25,係包覆該複數導電柱23與該電子元件21,以令該複數導電柱23之端面外露於該包覆層25,俾作為該電性接點230,以供天線模組2b透過複數導電凸塊28接置於該複數電性接點230上。
In one embodiment, the
於一實施例中,該複數電性接點230係提供接地。
In one embodiment, the plurality of
於一實施例中,該板體24係為半導體板材,其具有複數貫穿之導電矽穿孔240。
In one embodiment, the
於一實施例中,該天線部22係為天線層形式。
In one embodiment, the
因此,本發明之電子封裝件1主要藉由將天線模組2b堆疊於該封裝模組2a上而呈立體式天線,且該天線模組2b產生駐波F,再經由該複數導電柱23傳送至該電子元件21(如圖1所示之傳送路徑L),因而能得到較佳的天線效能。
Therefore, the electronic package 1 of the present invention mainly forms a three-dimensional antenna by stacking the
圖2A至圖2E係為本發明之電子封裝件1之製法之剖面示意圖。 Figures 2A to 2E are cross-sectional schematic diagrams of the manufacturing method of the electronic package 1 of the present invention.
如圖2A所示,於一承載件9上形成一承載結構20,其具有相對之第一側20a與第二側20b,再於該承載結構20之第一側20a上形成複數導電柱23,並設置至少一電子元件21於該承載結構20之第一側20a上。
As shown in FIG. 2A , a supporting
於本實施例中,該承載件9可依需求選擇膠帶、晶圓型板體(Wafer form substrate)或一般面板型板體(Panel form substrate),其可包括例如晶圓、矽板等之半導體材載體或玻璃材的圓形暫時性載體等之構造。
例如,該承載件9上可形成一如離形膜之暫時性結合層90,以結合該承載結構20之第二側20b。
In this embodiment, the
再者,該承載結構20係例如為無核心層(coreless)形式之線路結構,其包含至少一第一絕緣層200及至少一結合該第一絕緣層之第一線路層201,如至少一扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL),且形成該第一絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)之介電材。
Furthermore, the
又,藉由電鍍金屬製程,以形成導電柱23,且形成該導電柱23之材質係為如銅之金屬材或銲錫材。
Furthermore, the
另外,該電子元件21係為主動元件、被動元件或其組合者。該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於本實施例中,該電子元件21係為半導體晶片,其具有相對之作用面21a與非作用面21b,該作用面21a具有複數電極墊210,以藉由複數如銲錫材料、金屬柱(pillar)或其它等之導電凸塊211利用覆晶方式設於該承載結構20之第一側20a之第一線路層201上並電性連接該第一線路層201;或者,該電子元件21可藉由複數銲線(圖未示)以打線方式電性連接該承載結構20之第一側20a之第一線路層201;亦或,該電子元件21可直接接觸該承載結構20之第一側20a之第一線路層201。因此,可於該承載結構20上接置所需類型及數量之電子元件,以提升其電性功能,且有關電子元件21電性連接承載結構20之方式繁多,並不限於上述。
In addition, the
如圖2B所示,形成一包覆層25於該承載結構20之第一側20a上,以令該包覆層25包覆該電子元件21與該些導電柱23,以形成封裝模組2a,並使該導電柱23之端面23a外露於該包覆層25,以作為電性接點230。
As shown in FIG. 2B , a
於本實施例中,形成該包覆層25之材質係為聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)等絕緣材,但並不限於上述。例如,可採用壓合(lamination)或模壓(molding)等方式將該包覆層25形成於該承載結構20之第一側20a上。
In this embodiment, the material forming the
再者,可依需求進行整平製程,以令該包覆層25之上表面齊平該導電柱23之端面23a,使該導電柱23之端面23a外露出該包覆層25,甚至可使該包覆層25之上表面齊平該非作用面21b,以令該非作用面21b外露出該包覆層25。例如,可藉由研磨方式進行該整平製程,以移除該導電柱23之部分材質與該包覆層25之部分材質。
Furthermore, a flattening process can be performed as required to make the upper surface of the
又,該包覆層25包覆該些導電凸塊211;或者,可先以如底膠或非導電薄膜(Non-Conductive Film,簡稱NCF)等絕緣材包覆該些導電凸塊211,再以該包覆層25包覆該絕緣材。
Furthermore, the
如圖2C所示,將一天線模組2b堆疊於該封裝模組2a上,且該天線模組2b係包含一具有相對之第一表面24a與第二表面24b的板體24、一結合該第一表面24a之線路部26、及一結合該第二表面24b之天線部22。
As shown in FIG. 2C , an
於本實施例中,該板體24係為半導體板材,如矽基板、玻璃板或其它適當板材,其具有複數貫穿之導電矽穿孔(Through-silicon via,簡稱TSV)240,以形成一矽中介板(Through Silicon interposer,簡稱TSI)。
In this embodiment, the
再者,該線路部26係藉由複數導電凸塊28接置於該導電柱23之電性接點230上,且該線路部26包括有第二絕緣層260及設於該絕緣層260上並電性連接該複數導電矽穿孔240之第二線路層261,如重佈線路層(redistribution layer,簡稱RDL)。例如,該導電凸塊28可包含銲錫材料或金屬柱,且形成該第二線路層261之材質係為銅,而形成該第二絕緣層260之
材質係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)之介電材。
Furthermore, the
又,該天線部22係為天線層形式,如貼片(patch)材,其與該第二線路層261係以耦合方式傳輸訊號。例如,該天線部22與該第二線路層261係可相互電磁耦合,使天線訊號能於該天線部22與該第二線路層261之間傳遞。
Furthermore, the
另外,該電性接點230係提供接地,且該第二線路層261亦具有接地墊,以令該電性接點230與該接地墊之間藉由該導電凸塊28相連接,使該天線部22與該第二線路層261之訊號耦合於複數個電性接點230之間以形成駐波F。
In addition, the
如圖2D及圖2E所示,移除該承載件9及該暫時性結合層90,再形成複數如銲球之導電元件27於該承載結構20之第二側20b之第一線路層201上。
As shown in FIG. 2D and FIG. 2E, the
接著,沿圖2D所示之切割路徑S進行切單製程,以獲取該電子封裝件1。 Next, a singulation process is performed along the cutting path S shown in FIG. 2D to obtain the electronic package 1.
於本實施例中,該電子封裝件1可藉由該複數導電元件27接合至一電路板(圖略)上。
In this embodiment, the electronic package 1 can be bonded to a circuit board (not shown) via the plurality of
因此,本發明之電子封裝件之製法係主要藉由將天線模組2b堆疊於該封裝模組2a上而呈立體式天線,因而無需於該承載結構20上增加佈設區域,故本發明能於預定的承載結構20尺寸下增加天線功能,能使該電子封裝件1符合微小化之需求。
Therefore, the manufacturing method of the electronic package of the present invention is mainly to stack the
綜上所述,本發明之電子封裝件及其製法,係藉由將天線模組堆疊於該封裝模組上,且該天線模組產生駐波,從而得到較佳的天線效能。 In summary, the electronic package and its manufacturing method of the present invention achieves better antenna performance by stacking the antenna module on the package module and the antenna module generates a stationary wave.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.
1:電子封裝件 1: Electronic packaging components
2a:封裝模組 2a: Packaging module
2b:天線模組 2b: Antenna module
20:承載結構 20: Load-bearing structure
21:電子元件 21: Electronic components
22:天線部 22: Antenna Department
23:導電柱 23: Conductive column
230:電性接點 230: Electrical contact
24:板體 24: Board
24a:第一表面 24a: First surface
24b:第二表面 24b: Second surface
25:包覆層 25: Coating layer
26:線路部 26: Circuit Department
28:導電凸塊 28: Conductive bump
L:傳送路徑 L: Transmission path
F:駐波 F: Resident in Bo
Claims (10)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2023111888472 | 2023-09-14 | ||
| CN202311188847.2A CN119627026A (en) | 2023-09-14 | 2023-09-14 | Electronic packaging and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI873892B true TWI873892B (en) | 2025-02-21 |
| TW202512453A TW202512453A (en) | 2025-03-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW112137927A TWI873892B (en) | 2023-09-14 | 2023-10-03 | Electronic package and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN119627026A (en) |
| TW (1) | TWI873892B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170324135A1 (en) * | 2014-12-12 | 2017-11-09 | Sony Corporation | Microwave antenna apparatus, packing and manufacturing method |
| TW202320408A (en) * | 2021-11-04 | 2023-05-16 | 大陸商青島新核芯科技有限公司 | Electronic device and manufacturing method thereof |
| TW202326872A (en) * | 2021-12-29 | 2023-07-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
| CN116666940A (en) * | 2022-02-18 | 2023-08-29 | 日月光半导体制造股份有限公司 | Semiconductor device and manufacturing method thereof |
-
2023
- 2023-09-14 CN CN202311188847.2A patent/CN119627026A/en active Pending
- 2023-10-03 TW TW112137927A patent/TWI873892B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170324135A1 (en) * | 2014-12-12 | 2017-11-09 | Sony Corporation | Microwave antenna apparatus, packing and manufacturing method |
| TW202320408A (en) * | 2021-11-04 | 2023-05-16 | 大陸商青島新核芯科技有限公司 | Electronic device and manufacturing method thereof |
| TW202326872A (en) * | 2021-12-29 | 2023-07-01 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
| CN116666940A (en) * | 2022-02-18 | 2023-08-29 | 日月光半导体制造股份有限公司 | Semiconductor device and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN119627026A (en) | 2025-03-14 |
| TW202512453A (en) | 2025-03-16 |
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