TWI873508B - Electronic package, package substrate and fabricating method thereof - Google Patents

Abstract

An method of an electronic package is provided, in which two coreless circuit structures are laminated on two opposite surfaces of a carrier, respectively, so that electronic components are arranged on each of the circuit structures, and then a build-up structure is formed on each of the circuit structures to encapsulate the electronic components, and finally, the carrier is removed to obtain a plurality of electronic packages. Therefore, by simultaneously laminating the circuit structures on the opposite sides of the carrier, two warpage generated from a stress in the circuit structures are eliminated to improve yield.

Description

Electronic packaging components and packaging substrates and manufacturing methods

The present invention relates to a semiconductor packaging process, in particular to an electronic packaging component and its packaging substrate and manufacturing method that can prevent warping during the process.

With the booming development of the electronics industry, electronic products tend to be thinner, lighter, and smaller in size, and their functions are developing towards high performance, high functionality, and high speed. Therefore, in order to meet the high integration and miniaturization requirements of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

As shown in FIG. 1 , a coreless package substrate 1 is known to include a plurality of stacked dielectric layers 11 and a circuit layer 12 disposed on each of the dielectric layers 11.

As the functional requirements increase, the number of circuit layers 12 also increases, so the overall planar packaging area of the packaging substrate 10 also becomes larger and larger.

However, in the manufacturing method of the known package substrate 1, the dielectric layer 11 is prone to warpage due to the excessively large package area. As shown in the warp direction F in the figure, the package substrate 1 is shaped like a smiley face, causing the circuit layer 12 to stretch or shrink, making the circuit layer 12 prone to fracture, thus causing poor electrical reliability and low process yield.

Therefore, how to overcome the above-mentioned problems of knowledge and technology has become an issue that needs to be solved urgently.

In view of the various deficiencies of the above-mentioned prior art, the present invention provides a packaging substrate, which includes: a circuit structure without a core layer, which includes at least one first insulating layer and a first circuit layer disposed on the first insulating layer; and a build-up structure, which is disposed on the circuit structure, wherein the build-up structure includes at least one second insulating layer formed on the first insulating layer and a second circuit layer disposed on the second insulating layer and electrically connected to the first circuit layer, and the material forming the second insulating layer is an Ajinomoto build-up film, which is different from the material forming the first insulating layer.

In the aforementioned package substrate, the circuit structure has a first side and a second side opposite to each other, so that the build-up layer structure is disposed on the first side and/or the second side.

The present invention also provides a method for manufacturing a package substrate, comprising: providing a carrier and a plurality of coreless layered circuit structures, wherein the carrier has a first surface and a second surface opposite to each other, wherein each of the circuit structures comprises at least a first insulating layer and a first circuit layer formed on the first insulating layer; pressing the circuit structures on the first surface and the second surface of the carrier, respectively, wherein the circuit structures are formed by peeling The peeling layer is pressed onto the carrier, and the first circuit layer is embedded in the peeling layer; a build-up structure is formed on each of the circuit structures, and the build-up structure includes at least one second insulating layer formed on the first insulating layer, and a second circuit layer formed on the second insulating layer, so that the second circuit layer is electrically connected to the first circuit layer, wherein the material forming the second insulating layer is Ajinomoto build-up film, which is different from the material forming the first insulating layer; and the carrier is removed to obtain a plurality of packaging substrates.

In the aforementioned manufacturing method, the circuit structure has a first side and a second side opposite to each other, so that the circuit structure is bonded to the carrier with its second side, and a metal layer is bonded to the first side of the circuit structure. For example, it further includes removing the metal layer first and then manufacturing the build-up structure.

In the aforementioned manufacturing method, the circuit structure has a first side and a second side opposite to each other, so that the build-up structure is disposed on the first side; and further includes forming another build-up structure on the second side after removing the carrier.

The present invention also provides an electronic package, comprising: the aforementioned package substrate; and an electronic component, which is disposed on the circuit structure and embedded in the second insulating layer of the build-up structure, so that the electronic component is electrically connected to the first circuit layer or the second circuit layer.

In the aforementioned electronic package, the electronic component is electrically connected to the first circuit layer via a plurality of conductive bumps.

The present invention further provides a method for manufacturing an electronic package, comprising: providing a carrier and a plurality of coreless layer circuit structures, wherein the carrier has a first surface and a second surface opposite to each other, wherein each of the circuit structures comprises at least a first insulating layer and a first circuit layer formed on the first insulating layer; and pressing the circuit structures on the first surface and the second surface of the carrier, respectively, wherein the circuit structures are pressed on the carrier via a release layer. The first circuit layer is embedded in the peeling layer; an electronic component is disposed on each of the circuit structures; a build-up structure is formed on each of the circuit structures, and the build-up structure includes at least one second insulating layer formed on the first insulating layer to cover the electronic component, and a second circuit layer formed on the second insulating layer to electrically connect the second circuit layer to the first circuit layer, wherein the material forming the second insulating layer is Ajinomoto build-up film. Build-up film) that is different from the material forming the first insulating layer; and removing the carrier to obtain a plurality of electronic packages, wherein the electronic components are embedded in the second insulating layer of the build-up structure and electrically connected to the first circuit layer or the second circuit layer.

In the aforementioned manufacturing method, the electronic component is electrically connected to the first circuit layer via a plurality of conductive bumps.

As can be seen from the above, the electronic package and its packaging substrate and manufacturing method of the present invention mainly use the two opposite sides of the carrier to simultaneously press the circuit structure to offset the warp caused by the stress in the first insulation layer, so that the first insulation layer on the outermost side of the circuit structure remains flat. Therefore, in the subsequent manufacturing process, it can ensure that the second circuit layer or electronic component is effectively aligned and connected to the first circuit layer, so as to improve the yield of the packaging substrate or electronic package.

Furthermore, the carrier is pressed into the peeling layer, which can effectively prevent the carrier from infiltrating chemicals, copper foil floating, copper foil wrinkling or other problems during the manufacturing process.

In addition, since the warping of the first insulating layer of the circuit structure on the two opposite sides of the carrier can offset each other, compared with the conventional technology, the first circuit layer of the circuit structure will not be broken, which is conducive to meeting the requirements of electrical reliability and process yield.

1,2:Packaging substrate

11: Dielectric layer

12: Circuit layer

20: Metal layer

21: Circuit structure

21a: First side

21b: Second side

210: First insulation layer

211: First circuit layer

22,23: Adding layers to the structure

220,230: Second insulation layer

221,231: Second circuit layer

3,4: Electronic packaging

30: Electronic components

30a: Action surface

30b: Non-active surface

300:Electrode pad

31: Conductive bump

40: Adhesive layer

9: Carrier

9a: First surface

9b: Second surface

92: Peeling layer

F: Curvature direction

S: cutting path

Figure 1 is a cross-sectional view of a conventional packaging substrate.

Figures 2A to 2D are cross-sectional schematic diagrams of the manufacturing method of the packaging substrate of the present invention.

FIG2E is a cross-sectional schematic diagram of the subsequent process of FIG2D.

Figures 3A to 3D are cross-sectional schematic diagrams of the manufacturing method of the electronic package of the present invention.

FIG3E is a cross-sectional schematic diagram of the subsequent process of FIG3D.

FIG4 is a cross-sectional schematic diagram of another embodiment of FIG3D.

The following is a specific and concrete example to illustrate the implementation of the present invention. People familiar with this technology can easily understand other advantages and effects of the present invention from the content disclosed in this manual.

It should be noted that the structures, proportions, sizes, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the restrictive conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second", "one" etc. used in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments in their relative relationships shall also be regarded as the scope of implementation of the present invention without substantially changing the technical content.

Figures 2A to 2D are cross-sectional schematic diagrams of the manufacturing method of the package substrate 2 of the present invention.

As shown in FIG. 2A , a carrier 9 and a plurality of circuit structures 21 are provided, wherein the carrier 9 has a first surface 9a and a second surface 9b opposite to each other.

In this embodiment, the carrier 9 is a temporary carrier plate, and the plate body can be a metal plate such as copper foil or other plate materials.

Furthermore, each of the circuit structures 21 is coreless, having a first side 21a and a second side 21b opposite to each other, and including at least one first insulating layer 210 and a first circuit layer 211 formed on the first insulating layer 210. For example, the first insulating layer 210 is a dielectric layer, such as polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

Furthermore, the circuit structure 21 is fabricated on a metal layer 20 of a carrier plate (such as a copper foil substrate) having the metal layer 20, so that the metal layer 20 is bonded to the first side 21a of the circuit structure 21, and then the carrier plate is removed to obtain the circuit structure 21 having the metal layer 20. For example, the first circuit layer 211 is fabricated by electroplating metal (such as copper) using a build-up process or other methods.

It should be understood that by using the layer-adding method, the circuit structures 21 can add multiple layers of the first insulating layer 210 as needed to produce multiple layers of the first circuit layer 211.

In addition, if the circuit structure 21 is made on the carrier plate, after the carrier plate is removed, the circuit structure 21 will be warped due to uneven stress distribution, as shown in the warping direction F of the left and right sides, which makes the circuit structure 21 look like a smiling face or a crying face.

As shown in FIG. 2B , the circuit structures 21 are symmetrically formed on the first surface 9a and the second surface 9b of the carrier 9 by pressing, and the circuit structure 21 is pressed on the carrier 9 by the second side 21b thereof through the release layer 92.

In this embodiment, the peeling layer 92 is a dielectric layer, and the peeling layer 92 covers the first circuit layer 211 of the second side 21b, so that the first circuit layer 211 of the second side 21b is embedded in the peeling layer 92, and the metal layer 20 of the first side 21a of the circuit structure 21 faces outward.

As shown in FIG. 2C , a build-up structure 22 is formed on the first side 21a of each circuit structure 21.

In this embodiment, the build-up structure 22 includes at least one second insulating layer 220 formed on the first insulating layer 210, and a second circuit layer 221 formed on the second insulating layer 220, so that the second circuit layer 221 is electrically connected to the first circuit layer 211. For example, the build-up method is used to manufacture the build-up structure 22.

Furthermore, the material forming the second insulating layer 220 is different from the material forming the first insulating layer 210. For example, the material forming the second insulating layer 220 is Ajinomoto build-up film (ABF), and the material forming the first insulating layer 210 is prepreg (PP).

Furthermore, the metal layer 20 can be removed first, and then the build-up structure 22 can be made. Alternatively, the metal layer 20 can be used to make the second circuit layer 221.

As shown in FIG. 2D , the singulation process is performed along the cutting path S shown in FIG. 2C , and the carrier 9 is removed to obtain a plurality of package substrates 2 , which expose the second side 21b of the circuit structure 21 .

In this embodiment, another build-up structure 23 may be formed on the second side 21b of the circuit structure 21 by a build-up method, as shown in FIG2E. For example, the build-up structure 23 includes at least one second insulating layer 230 formed on the first insulating layer 210, and a second circuit layer 231 formed on the second insulating layer 230, so that the second circuit layer 231 is electrically connected to the first circuit layer 211.

Furthermore, the material forming the second insulating layer 230 is different from the material forming the first insulating layer 210. For example, the material forming the second insulating layer 230 is Ajinomoto build-up film (ABF), while the material forming the first insulating layer 210 is prepreg (PP). It should be understood that the structures of the build-up structures 22 and 23 are roughly the same.

Therefore, the manufacturing method of the present invention simultaneously compresses the circuit structures 21 on the opposite sides of the carrier 9 to offset the warping caused by the stress in the first insulating layer 210, so that the first insulating layer 210 on the outermost side of the circuit structure 21 remains flat. Therefore, in the subsequent manufacturing process of the layer-building structure 22, it can ensure that the second circuit layer 221 is effectively aligned and connected to the first circuit layer 211, so as to improve the yield of the package substrate 2.

Furthermore, the carrier 9 is pressed into the peeling layer 92 (i.e. the interlayer material covers the copper foil) to effectively prevent the carrier 9 from infiltrating chemicals, copper foil floating, copper foil wrinkling or other problems during the manufacturing process.

In addition, since the warping of the first insulating layer 210 of the circuit structure 21 on the two opposite sides of the carrier 9 can offset each other, the first circuit layer 211 of the circuit structure 21 will not be broken, which is conducive to meeting the requirements of electrical reliability and process yield.

Figures 3A to 3D are cross-sectional schematic diagrams of the manufacturing method of the electronic package 3 of the present invention. In this embodiment, the manufacturing method of the package substrate 2 is used, so the same points will not be repeated below.

As shown in FIG. 3A, the process shown in FIG. 2B is continued.

As shown in FIG. 3B , the metal layer 20 is removed, and at least one electronic component 30 is disposed on the first side 21a of the circuit structures 21 so that the electronic component 30 is electrically connected to the first circuit layer 211.

In this embodiment, the electronic component 30 is an active component, a passive component or a combination of the two, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor or an inductor. For example, if the electronic component 30 is a semiconductor chip, it has an active surface 30a and an inactive surface 30b opposite to each other, and the active surface 30a has a plurality of electrode pads 300, which are electrically connected to the first circuit layer 211 through a plurality of conductive bumps 31 with the active surface 30a facing downward (such as a flip chip method); or, the electronic component 30 can also be electrically connected to the first circuit layer 211 by a plurality of bonding wires (not shown) in a wire bonding manner; or, the electronic component 30 can directly contact the first circuit layer 211. However, the method of electrically connecting the electronic element 30 to the first circuit layer 211 is not limited to the above.

As shown in FIG. 3C , a build-up structure 22 is formed on the first side 21a of each circuit structure 21 so that the electronic component 30 is embedded in the build-up structure 22.

In this embodiment, the added layer structure 22 is a second insulating layer 220 that covers the electronic element 30.

As shown in FIG3D , the singulation process is performed along the cutting path S shown in FIG3C , and the carrier 9 is removed to obtain a plurality of electronic packages 3 including a package substrate 2 and an electronic component 30 .

In this embodiment, another build-up structure 23 can be formed on the second side 21b of the circuit structure 21 by using a build-up method, as shown in FIG. 3E .

In another embodiment, the embedding method of the electronic component 30 can also adopt the method of facing the active surface 30a upward, such as the electronic package 4 shown in FIG. 4, so that the electronic component 30 is bonded to the first side 21a of the circuit structure 21 with its inactive surface 30b through the adhesive layer 40, so that the second circuit layer 221 of the build-up structure 22 is electrically connected to the electrode pad 300 of the electronic component 30.

Therefore, the manufacturing method of the present invention simultaneously compresses the circuit structures 21 on the opposite sides of the carrier 9 to offset the warping caused by the stress in the first insulating layer 210, so that the first insulating layer 210 on the outermost side of the circuit structure 21 remains flat. Therefore, when the electronic component 30 is subsequently arranged, it can ensure that the conductive bump 31 is effectively aligned and connected to the first circuit layer 211, so as to improve the yield of the electronic package 3.

Furthermore, even if the embedding method of the electronic component 30 adopts the method of facing the active surface 30a upward, as shown in FIG4 , the electronic component 30 can still be evenly arranged on the first side 21a of the circuit structure 21, so that the second circuit layer 221 of the build-up structure 22 can effectively align and connect the electrode pad 300 of the electronic component 30, thereby improving the yield of the electronic package 4.

In addition, the carrier 9 is pressed into the peeling layer 92 (i.e., the interlayer material covers the copper foil) to effectively prevent the carrier 9 from infiltrating chemicals, copper foil floating, copper foil wrinkling or other problems during the manufacturing process.

In addition, since the warping of the first insulating layer 210 of the circuit structure 21 on the two opposite sides of the carrier 9 can offset each other, the first circuit layer 211 of the circuit structure 21 will not be broken, which is conducive to meeting the requirements of electrical reliability and process yield.

The present invention also provides a packaging substrate 2, comprising: a coreless circuit structure 21 having a first side 21a and a second side 21b opposite to each other, and build-up structures 22, 23 disposed on the circuit structure 21.

The circuit structure 21 includes at least one first insulating layer 210 and a first circuit layer 211 disposed on the first insulating layer 210.

The build-up structures 22, 23 are disposed on the circuit structure 21, wherein the build-up structures 22, 23 include at least one second insulating layer 220, 230 formed on the first insulating layer 210 and a second circuit layer 221, 231 disposed on the second insulating layer 220, 230 and electrically connected to the first circuit layer 211, and the material forming the second insulating layer 220, 230 is Ajinomoto build-up film, which is different from the material forming the first insulating layer 210.

In one embodiment, the added layer structures 22, 23 are disposed on the first side 21a and/or the second side 21b.

The present invention also provides an electronic package 3, 4, which includes: a package substrate 2 and at least one electronic component 30.

The electronic element 30 is disposed on the circuit structure 21 and embedded in the second insulating layer 220 of the build-up structure 22, so that the electronic element 30 is electrically connected to the first circuit layer 211 or the second circuit layer 221.

In one embodiment, the electronic component 30 is electrically connected to the first circuit layer 211 via a plurality of conductive bumps 31.

In summary, the electronic package and its packaging substrate and manufacturing method of the present invention simultaneously compress the circuit structure on the two opposite sides of the carrier to offset the warp caused by the stress in the first insulating layer, so that the first insulating layer on the outermost side of the circuit structure remains flat. Therefore, in the subsequent manufacturing process, it can ensure that the second circuit layer or electronic component is effectively aligned and connected to the first circuit layer, so as to improve the yield of the packaging substrate or electronic package.

Furthermore, the carrier is pressed into the peeling layer, which can effectively prevent the carrier from infiltrating chemicals, copper foil floating, copper foil wrinkling or other problems during the manufacturing process.

In addition, since the warping of the first insulating layer of the circuit structure on the two opposite sides of the carrier can offset each other, the first circuit layer of the circuit structure will not be broken, which is conducive to meeting the requirements of electrical reliability and process yield.

The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

2:Packaging substrate

21: Circuit structure

210: First insulation layer

22: Adding layers to the structure

220: Second insulation layer

221: Second circuit layer

3: Electronic packaging

30: Electronic components

31: Conductive bump

Claims (7)

A package substrate includes: a circuit structure without a core layer, including at least one first insulating layer and a first circuit layer disposed on the first insulating layer, wherein the circuit structure has a first side and a second side opposite to each other, and the first circuit layer and the first side of the circuit structure are coplanar; a build-up layer structure is disposed on the first side of the circuit structure, and includes at least one second insulating layer formed on the first insulating layer and a second circuit layer disposed on the second insulating layer and electrically connected to the first circuit layer, wherein the material forming the second insulating layer is Ajinomoto build-up film. film), which is different from the material forming the first insulating layer; and another build-up layer structure is formed on the second side of the circuit structure. A method for manufacturing a package substrate includes: providing a carrier and a plurality of coreless layer circuit structures, wherein the carrier has a first surface and a second surface opposite to each other, and each of the circuit structures includes at least one first insulating layer and a first circuit layer formed on the first insulating layer, wherein the circuit structure has a first side and a second side opposite to each other, so that the circuit structure is bonded to the carrier with its second side, and the first circuit layer is coplanar with the first side of the circuit structure; The circuit structure is pressed onto the two surfaces respectively, wherein the circuit structure is pressed onto the carrier by a peeling layer, and the first circuit layer is embedded in the peeling layer; a build-up layer structure is formed on the first side of each of the circuit structures, wherein the build-up layer structure includes at least one second insulating layer formed on the first insulating layer, and a second circuit layer formed on the second insulating layer, so that the second circuit layer is electrically connected to the first circuit layer, wherein the material forming the second insulating layer is Ajinomoto build-up film (Ajinomoto a build-up film) that is different from the material forming the first insulating layer; removing the carrier; and after removing the carrier, forming another build-up structure on the second side to produce a plurality of the package substrates. The method for manufacturing a package substrate as described in claim 2, wherein a metal layer is bonded to the first side of the circuit structure, and the method for manufacturing the package substrate further includes first removing the metal layer and then manufacturing the build-up structure. An electronic package includes: a package substrate as described in claim 1; and an electronic component, which is disposed on the circuit structure and embedded in the second insulating layer of the build-up structure, and the electronic component is electrically connected to the first circuit layer or the second circuit layer. An electronic package as described in claim 4, wherein the electronic component is electrically connected to the first circuit layer via a plurality of conductive bumps. A method for manufacturing an electronic package includes: providing a carrier and a plurality of coreless layer circuit structures, wherein the carrier has a first surface and a second surface opposite to each other, and each of the circuit structures includes at least a first insulating layer and a first circuit layer formed on the first insulating layer, wherein the circuit structure has a first side and a second side opposite to each other, so that the circuit structure is bonded to the carrier with its second side, and the first circuit layer is coplanar with the first side of the circuit structure; and pressing the circuit structure on the first surface and the second surface of the carrier, respectively. , wherein the circuit structure is pressed onto the carrier by a peeling layer, and the first circuit layer is embedded in the peeling layer; an electronic component is disposed on the first side of each circuit structure; and a build-up layer structure is formed on the first side of each circuit structure, wherein the build-up layer structure includes at least one second insulating layer formed on the first insulating layer to cover the electronic component, and a second circuit layer formed on the second insulating layer, and the second circuit layer is electrically connected to the first circuit layer, wherein the material forming the second insulating layer is Ajinomoto build-up film (Ajinomoto Build-up film) which is different from the material forming the first insulating layer; remove the carrier; and after removing the carrier, form another build-up structure on the second side to obtain a plurality of electronic packages, wherein the electronic components are embedded in the second insulating layer of the build-up structure and electrically connected to the first circuit layer or the second circuit layer. A method for manufacturing an electronic package as described in claim 6, wherein the electronic component is electrically connected to the first circuit layer via a plurality of conductive bumps.

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