TWI873481B - Clock synchronization method and device, electronic equipment and storage medium - Google Patents

Abstract

A clock synchronization method and device, an electronic device and a storage medium. The clock synchronization method comprises: sending a trigger signal to a second processing module, and recording the current count value of a first timer when the trigger signal is sent as a first count value, wherein the second processing module and the first processing module belong to different clock domains; reading a second count value from the second processing module, wherein the second count value is the current count value of a second timer of the second processing module when the second processing module receives the trigger signal, and the count value of the second timer is used as a timing reference of the second processing module and increases sequentially; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

Description

Clock synchronization method and device, electronic equipment and storage medium

The embodiments of the present invention relate to a clock synchronization method, a system clock synchronization method, a clock synchronization device, an electronic device and a non-transitory computer-readable storage medium.

Due to the system limitations of large integrated circuits, it is often necessary to exchange data between multiple different clock frequency systems, receive and send data or process asynchronous signals between different clock frequency systems through input and output interfaces, etc., that is, there may be multiple clock domains in the integrated circuit, and each clock domain is an area in the integrated circuit controlled by the same clock signal.

The clock signals corresponding to different clock domains are called asynchronous clocks. For two modules connected in an integrated circuit, for example, each module can be composed of some circuit logic to complete specific functions. If the two modules are driven by different clocks (that is, asynchronous clocks), the clock signals of the two modules are called asynchronous clock signals (Asynchronous Interface), and the two modules belong to different clock domains; if the two modules are driven by the same clock, the clock signals of the two modules are called synchronous clock signals (Synchronous Interface), and the two modules belong to the same clock domain.

This content section is provided to introduce the concepts in a concise form, which will be described in detail in the specific implementation section below. This content section is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to be used to limit the scope of the technical solution claimed for protection.

At least one embodiment of the present invention provides a clock synchronization method for a first processing module, wherein the first processing module includes a first timer, and the count value of the first timer is used as a timing reference of the first processing module and increases in sequence. The clock synchronization method includes: sending a trigger signal to a second processing module, and recording the current count value of the first timer when the trigger signal is sent as a first count value, wherein the second processing module and the first processing module belong to different clock domains. ; Read a second count value from the second processing module, wherein the second count value is the current count value of the second timer of the second processing module when the second processing module receives the trigger signal, and the count value of the second timer is used as the timing reference of the second processing module and increases sequentially; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

At least one embodiment of the present invention provides a clock synchronization method for a second processing module, wherein the second processing module includes a second timer, and the count value of the second timer is used as a timing reference of the second processing module and increases in sequence. The clock synchronization method includes: in response to receiving a trigger signal sent by the first processing module, recording the current count value of the second timer as a second count value, wherein the second processing module and the first processing module belong to different Clock domain; wherein the second count value is used to combine with the first count value for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, the first count value is the current count value of the first timer of the first processing module when the first processing module sends a trigger signal to the second processing module, and the count value of the first timer is used as the timing reference of the first processing module and increases sequentially.

At least one embodiment of the present invention provides a system clock synchronization method, wherein the system includes a first processing module and a second processing module, the first processing module includes a first timer, the count value of the first timer is used as a timing reference of the first processing module and increases sequentially, the second processing module includes a second timer, the count value of the second timer is used as a timing reference of the second processing module and increases sequentially, the first processing module and the second processing module belong to different clock domains, and the system clock synchronization The method includes: the first processing module sends a trigger signal to the second processing module, the first processing module records the current count value of the first timer when sending the trigger signal as the first count value, and the second processing module records the current count value of the second timer when receiving the trigger signal as the second count value; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

At least one embodiment of the present invention provides a clock synchronization device for a first processing module, wherein the first processing module includes a first timer, the count value of the first timer is used as a timing reference of the first processing module and increases in sequence, and the clock synchronization device includes: a first recording unit, configured to send a trigger signal to a second processing module, and simultaneously record the current count value of the first timer when the trigger signal is sent as a first count value, wherein the second processing module and the first processing module belong to different clocks. domain; a reading unit configured to read a second count value from the second processing module, wherein the second count value is the current count value of the second timer of the second processing module when the second processing module receives the trigger signal, and the count value of the second timer is used as the timing reference of the second processing module and increases sequentially; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

At least one embodiment of the present invention provides a clock synchronization device for a second processing module, wherein the second processing module includes a second timer, and the count value of the second timer is used as a timing reference of the second processing module and increases in sequence. The clock synchronization device includes: a second recording unit, configured to respond to receiving a trigger signal sent by the first processing module, and record the current count value of the second timer as a second count value, wherein the second processing module and the first processing module are synchronized. Belong to different clock domains; wherein the second count value is used to combine with the first count value for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, the first count value is the current count value of the first timer of the first processing module when the first processing module sends a trigger signal to the second processing module, and the count value of the first timer is used as the timing reference of the first processing module and increases sequentially.

At least one embodiment of the present invention provides an electronic device, comprising a first processing module and a second processing module, wherein the first processing module comprises a first timer, the count value of the first timer is used as a timing reference of the first processing module and increases sequentially, the second processing module comprises a second timer, the count value of the second timer is used as a timing reference of the second processing module and increases sequentially, the first processing module and the second processing module belong to different clock domains, wherein the first The processing module is configured to send a trigger signal to the second processing module, and record the current count value of the first timer when sending the trigger signal as the first count value, and the second processing module is configured to record the current count value of the second timer when receiving the trigger signal as the second count value; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

At least one embodiment of the present invention provides an electronic device, comprising: a memory, which non-temporarily stores computer executable instructions; a processor, which is configured to execute the computer executable instructions, wherein the computer executable instructions, when executed by the processor, implement the clock synchronization method or system clock synchronization method according to any embodiment of the present invention.

At least one embodiment of the present invention provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the clock synchronization method or system clock synchronization method described in any embodiment of the present invention is implemented.

100: Clock synchronization device

101: First recording unit

102: Reading unit

103: First-time compensation unit

200: Clock synchronization device

201: Second recording unit

202: Second time compensation unit

300: Electronic equipment

310: First processing module

320: Second processing module

400: Electronic equipment

410:Processor

420:Memory

500: Storage medium

510: Computer readable instructions

S10, S20, S301, S302, S401, S402, S50, S601, S602, S603: Steps

T0~Tn+1, T0’~Tn+1’: time

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only involve some embodiments of the present invention, rather than limiting the present invention.

FIG1 is a schematic diagram of a hierarchical structure of a central processing unit; FIG2 is a schematic diagram of a clock synchronization process; FIG3 is a schematic flow chart of a clock synchronization method provided by at least one embodiment of the present invention; FIG4 is a flow chart of a clock synchronization method provided by at least one embodiment of the present invention; FIG5 is a schematic diagram of an interactive process of a clock synchronization method provided by at least one embodiment of the present invention; FIG6 is a flow chart of a clock synchronization method provided by at least one embodiment of the present invention; FIG7 is a schematic flow chart of another clock synchronization method provided by at least one embodiment of the present invention; FIG8A is a flow chart of a system clock synchronization method provided by at least one embodiment of the present invention; Schematic diagram of the interaction process; FIG. 8B is a schematic block diagram of the transmission delay between the compensation processing modules provided by at least one embodiment of the present invention; FIG. 9A is a schematic block diagram of a clock synchronization device provided by at least one embodiment of the present invention; FIG. 9B is a schematic block diagram of another clock synchronization device provided by at least one embodiment of the present invention; FIG. 9C is a schematic block diagram of an electronic device provided by at least one embodiment of the present invention; FIG. 10 is a schematic block diagram of an electronic device provided by at least one embodiment of the present invention; FIG. 11 is a schematic diagram of a non-transient computer-readable storage medium provided by at least one embodiment of the present invention.

In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be described clearly and completely in conjunction with the attached drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by a person of ordinary knowledge in the field without creative labor are within the scope of protection of the present invention.

Unless otherwise defined, the technical or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, but do not exclude other elements or objects. The words "connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In order to keep the following description of the embodiments of the present invention clear and concise, the present invention omits the detailed description of some known functions and known components.

For the asynchronous clock domain, in some scenarios, each asynchronous clock domain needs to be able to synchronize scheduling and assist operations, that is, it is necessary to maintain the synchronization of each asynchronous clock domain.

For example, for the central processing unit (CPU), its physical layer structure diagram is shown in Figure 1.

As shown in Figure 1, the CPU includes two physical slots (sockets), each of which can be inserted with a CPU package (CPU Package or CPU socket), such as Socket0 and Socket1 in Figure 1.

Each CPU package can include one or more CPU Dies. CPU Dies refer to small blocks cut from the silicon wafer during the production process of the processor. Before cutting, each small block (Die) needs to go through various processes to engrave the circuit logic onto the Die. Each CPU Die can be regarded as a processing unit with circuit logic. As shown in Figure 1, each CPU package includes two Dies, for example, Socket0 includes Die0 and Die1.

Each CPU Die may include one or more processing cores (CPU Core). For example, as shown in Figure 1, DIE0 includes processing core Core0 and processing core Core1.

Of course, Figure 1 only shows a schematic diagram of a central processing unit. The number of CPU packages, the number of CPU Dies in each CPU package, and the number of processing cores in each CPU Die may be different for different CPUs, which will not be elaborated here.

For example, since each CPU Die or CPU Socket is physically independent of each other, each CPU Die or CPU Socket usually has its own phase-locked loop (PLL) to generate a working clock signal or a reference clock signal.

For example, the phase-locked loop can receive a clock signal (e.g., 100MHz) provided by a clock source, multiply the clock signal to generate a working clock signal (e.g., 2.4GHz), and the CPU Die or CPU Socket performs operations in conjunction with the working clock signal. For example, the phase-locked loop also provides a reference clock signal (e.g., 100MHz) to devices including the system timer based on the clock signal, so that these devices can work normally.

For example, each processing module on the CPU (such as CPU Die or CPU Socket) includes its own system timer, which is used to provide a timing reference. For example, the system timer usually selects the timer with the highest accuracy on the chip as the timing basis of the system time to avoid large time offsets after the system has been running for a long time. For example, the count value of the system timer is used as the timing basis of the processing module and increases sequentially. For example, after the system is restarted, the time can be re-obtained from the RTC (real_time clock), and periodic counting can continue based on this time to set the system clock, provide an alarm or a periodic timer.

For example, for symmetric multi-processing (SMP), multiple processing modules (such as CPU Die or CPU Socket) share memory and bus structure. In order to make multiple processing modules have better synchronization scheduling and assist operation efficiency, it is necessary to keep the system timers of multiple processing modules with the same count value to meet the needs of timer (system tick) trigger scheduling, IPC (Inter-Process Communication) waiting timeout synchronization, and the need to add time stamps during the debugging phase.

Figure 2 is a schematic diagram of a clock synchronization process. It is applied between the main processing module (such as Master CPU Die) and the slave processing module (such as Slave CPU Die).

As shown in Figure 2, at time T0, the slave processing module initiates a synchronization request to the master processing module to apply for synchronization. At time T1, the master processing module receives the request and responds to the slave processing module to accept the request. At time T2, the master processing module starts to initiate synchronization and sends a synchronization request to the slave processing module. At time T3, the slave processing module receives the request and responds to the master processing module to accept the master processing module's request. At time T4, the master processing module receives the slave processing module's response, completing a handshake.

At time T5, the master processing module sends a synchronous count value to the slave processing module, and the slave processing module receives the count value at time T6. The count value is related to time T5, communication delay, etc.

At time T7, the main processing module sends a synchronization request again. At time T8, the slave processing module receives the request and responds to the main processing module, while updating its own count value.

For example, if the synchronization count value is received from the processing module, but the synchronization fails (for example, the waiting timeout has not received a response from the other party), then a new round of synchronization process will be restarted at time T9.

In the synchronization process shown in Figure 2, multiple stages are required to complete the synchronization, and the risk of synchronization failure is high. In addition, since the communication between processing modules needs to be realized through the bus on the chip or the interconnect bus, the communication in multiple stages will increase the impact of clock jitter and delay on the bus, and the synchronization accuracy is low.

In addition, when the clock sources that provide clock signals to the master processing module and the slave processing module are non-coherent clocks, there is a lack of efficient processing solutions for non-coherent clocks. For example, for non-coherent clocks, when measuring the time taken for a certain operation, the execution thread of the operation may change from processing module A to processing module B, and the start time of the measured operation is based on the clock signal of processing module A, and the end time of the measured operation is based on the clock signal of processing module B. This will cause clock measurement problems because the clock signal of processing module A and the clock signal of processing module B are asynchronous clock signals. For example, non-cognate clocks require frequent calibration, and when time calibration is performed during operation, applications related to time measurement/delay will experience errors.

At least one embodiment of the present invention provides a clock synchronization method, a clock synchronization device, a system clock synchronization method, an electronic device, and a non-transitory computer-readable storage medium.

The system clock synchronization method includes: sending a trigger signal to the second processing module, and recording the current count value of the first timer when the trigger signal is sent as the first count value, wherein the second processing module and the first processing module belong to different clock domains; reading the second count value from the second processing module, wherein the second count value is the current count value of the second timer of the second processing module when the second processing module receives the trigger signal, and the count value of the second timer is used as the timing reference of the second processing module and increases sequentially; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

In at least one embodiment, the first processing module and the second processing module freeze the current count value of the system timer based on the same trigger signal, and record the current count value respectively, so that the relationship and deviation between each timer can be understood through the count value of each system timer, and the clock compensation can be completed using the count value. This clock synchronization method greatly reduces the stages required for clock synchronization. The count values of each timer are recorded through the same trigger signal to obtain the relationship and deviation between the timers. Even if communication failure occurs later, it will not cause synchronization failure. In addition, the synchronization accuracy is greatly improved, eliminating software intervention and reducing the impact of clock jitter and delay on the bus. The interface used for clock synchronization is reduced from two to one, reducing interface occupancy and improving resource utilization.

The following is a detailed description of the embodiments of the present invention in conjunction with the attached drawings, but the present invention is not limited to these specific embodiments.

Figure 3 is a schematic flow chart of a clock synchronization method provided by at least one embodiment of the present invention.

For example, the clock synchronization method is used for a first processing module, the first processing module includes a first timer, and the count value of the first timer is used as a timing reference of the first processing module and increases sequentially. For example, the first timer is a system timer of the first processing module.

As shown in FIG3 , the clock synchronization method provided by at least one embodiment of the present invention includes steps S10 to S20.

For example, in step S10, a trigger signal is sent to the second processing module, and the current count value of the first timer when the trigger signal is sent is recorded as the first count value.

For example, the first count value is recorded in the register of the first processing module.

For example, in step S20, the second count value is read from the second processing module.

For example, the second count value is the current count value of the second timer of the second processing module when the second processing module receives the trigger signal. The count value of the second timer serves as the timing reference of the second processing module and increases sequentially.

For example, the second timer is a system timer of the second processing module.

For example, the second count value is recorded in a register of the second processing module.

For example, the first count value and the second count value are used for clock compensation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, the first processing module and the second processing module can be CPU Die or CPU Socket. For example, the first processing module can be Die0 in Figure 1, and the second processing module can be Die1 in Figure 1. For example, the first processing module can be Socket0 in Figure 1, and the second processing module can be Socket1 in Figure 1. Of course, the first processing module and the second processing module can be other hardware modules that need to be synchronized with the clock. The present invention does not impose specific restrictions on the structure and function of the first processing module and the second processing module.

For example, the second processing module and the first processing module belong to different clock domains.

For example, the integrated circuit includes a first clock domain determined based on a first clock source and a second clock domain determined based on a second clock source. For example, the first clock domain is a region controlled by the first clock source, and the first processing module is located in the first clock domain. For example, the second clock domain is a region controlled by the second clock source, and the second processing module is located in the second clock domain. For example, Die0 and Die1 in FIG1 belong to two different clock domains, for example, Die0 is located in the first clock domain and works according to the first reference clock signal provided by the first clock source, and Die1 is located in the second clock domain and works according to the second reference clock signal provided by the second clock source.

For example, the second processing module and the first processing module belong to different clock domains, which means they belong to asynchronous clock domains. There may be two reasons for this:

1. The first processing module includes a first phase-locked loop, which is configured to receive a first reference clock signal provided by a first clock source, and to generate a first working clock signal according to the first reference clock signal and provide it to the first processing module; the second processing module includes a second phase-locked loop, which is configured to receive a first reference clock signal provided by a first clock source, and to generate a second working clock signal according to the first reference clock signal and provide it to the second processing module. That is, the first processing module and the second processing module have their own phase-locked loops, but the phase-locked loops receive the same source clock signal. Since the time phase relationship of the lock at power-on is random, the phase relationship between the launch edge and the capture edge between different phase-locked loops is also random, so even if the first processing module and the second processing module essentially receive the same source clock signal, they still need to be processed as asynchronous clock domains.

2. The first processing module is provided with a reference clock signal by the first clock source, and the second processing module is provided with a reference clock signal by the second clock source. The first clock source and the second clock source are non-coherent clock sources. At this time, the first processing module includes a first phase-locked loop, which is configured to receive a first reference clock signal provided by the first clock source, and generate a first working clock signal according to the first reference clock signal and provide it to the first processing module; the second processing module includes a second phase-locked loop, which is configured to receive a second reference clock signal provided by the second clock source, and generate a second working clock signal according to the second reference clock signal and provide it to the second processing module. The first clock signal and the second clock signal are asynchronous clock signals. For example, for non-cognate clock sources, although the phase-locked loop can perform phase tracking, since it is impossible for two crystal oscillators to have exactly the same frequency, non-cognate clock sources not only have different phases, but also different clock frequencies.

It should be noted that the integrated circuit may also include a third clock domain, a fourth clock domain, etc., that is, the integrated circuit may include multiple clock domains. When performing clock synchronization, two processing modules controlled by asynchronous clocks are selected from multiple processing modules as the first processing module and the second processing module, and the asynchronous clocks corresponding to the two processing modules are synchronized based on the clock synchronization method provided by the present invention.

In the clock synchronization method provided in at least one embodiment of the present invention, a snapshot function of the first timer and the second timer is implemented. For example, when the first timer and the second timer receive the rising edge of the same trigger signal (such as a timer trigger signal or a signal of a universal input/output interface), the current count value of the first timer is frozen in a register in the first processing module, and the current count value of the second timer is frozen in a register in the second processing module. Since multiple timers are synchronously triggered by only one signal, the relationship and deviation of each timer can be obtained by reading the register used to store the recorded count value of each timer, thereby determining the compensation value for clock compensation. For example, clock compensation is performed based on the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For asynchronous clock domains caused by different reasons, the processing methods are also different when the clock is synchronized. The following is a detailed description of the processing process for two asynchronous clock domains caused by different reasons, combined with the attached diagrams.

For example, taking the CPU as an example, multiple processing modules usually include a master processing module (Master) and multiple slave processing modules. The master processing module usually performs scheduling and assistance, entrusting the execution of services to different slave processing modules.

For example, in the following embodiments, the first processing module is described as a slave processing module and the second processing module is described as a master processing module. Of course, the present invention is not limited to this, and technicians in this field can also select the first processing module as the master processing module and the second processing module as the slave processing module according to actual needs, or there can be no master-slave relationship between the first processing module and the second processing module.

In the case where the first processing module and the second processing module use the same clock source to provide a reference clock signal, but have different phase-locked loops, after being processed by the phase-locked loop, the reference clock signals received by the first processing module and the second processing module have the same frequency, but a fixed phase difference. Therefore, the first processing module only needs to obtain the first count value and the second count value, and compensate the first timer according to the difference between the first count value and the second count value. After compensation, the first timer and the second timer will always be consistent, and no maintenance is required unless the power is turned off and restarted. For example, clock compensation can be triggered by software once when needed, such as setting a flag bit, and compensation is performed when the flag bit is valid. Since the deviation of the count value has been recorded in the register through the same trigger signal, the synchronization failure problem is eliminated.

For example, the clock synchronization is performed when the first processing module is in the power-on stage, that is, when the first processing module is just powered on and before any specific operation is performed. At this time, since the first processing module has not yet performed any specific operation, the clock compensation does not need to consider the problem of maintaining monotonic increase in time.

Of course, if the clock synchronization is performed when the first processing module is working, that is, the first processing module has already performed a specific operation, then the problem of monotonic increase in time needs to be considered. The specific process can be referred to in the relevant description of the non-homologous clock source in the following text, and will not be elaborated here.

Figure 4 is a flow chart of a clock synchronization method provided by at least one embodiment of the present invention.

As shown in FIG4 , after step S20, the clock synchronization method further includes step S301 and step S302.

Step S301, determine the deviation between the first count value and the second count value.

Step S302, based on the deviation, the first timer is compensated so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, in step S301, the deviation is the difference between the first count value and the second count value.

For example, step S302 may include: obtaining the current count value of the first timer as the third count value; adding the deviation to the third count value to obtain an updated count value; updating the count value of the first timer to the updated count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, the first count value is N1, the second count value is N2, and N1 and N2 are positive integers. The deviation between the first count value and the second count value is, for example, N1-N2.

For example, after the deviation is calculated, clock compensation can be performed when necessary. For example, when the flag bit indicating clock compensation is valid, the current count value N3 of the first timer is obtained as the third count value, N3+N1-N2 is calculated as the updated count value, and the count value of the first timer is updated to the updated count value N3+N1-N2. For example, when the flag bit indicating clock compensation is invalid, the count value of the first timer continues to increase according to the reference clock signal frequency, for example, by 1 for each clock cycle.

For example, the trigger signal is also configured to simultaneously trigger the interruption of the first processing module to perform clock compensation. For example, since the first processing module only needs to adjust the count value of the first timer when the clocks are of the same source, the first processing module only needs to trigger an interruption to interrupt the current application service, perform clock compensation, and then continue to execute the application service.

Figure 5 is a schematic diagram of the interactive process of the clock synchronization method provided by at least one embodiment of the present invention.

As shown in Figure 5, at time T0, the first processing module sends an "assert trigger" to the second processing module. At this time, the first processing module records the current count value of the first timer as the first count value and stores it in the first register when sending the trigger signal. For example, the first register is located in the first processing module and can statically store values. At the same time, the second processing module records the current count value of the second timer as the second count value and stores it in the second register when receiving the trigger signal. For example, the second register is located in the second processing module and can statically store values. In addition, the trigger signal also triggers the interruption of the first processing module at the same time.

Afterwards, at time T1, the first processing module reads the value of the second register in the second processing module to obtain the second count value, and performs clock compensation with reference to the process of step S301 and step S302 above. The specific process will not be described in detail.

In this embodiment, since the clocks are of the same source, there is a fixed phase difference between the first processing module and the second processing module. The fixed phase difference can be compensated according to the deviation between the first count value and the second count value, and the compensation only needs to be done once. No maintenance is required unless power is turned off and restarted. The implementation method is simple and effective, and synchronization failure is eliminated. The clock synchronization stage is greatly reduced. The number of communications between the first processing module and the second processing module is greatly reduced, and the influence of clock jitter and delay caused by the network line or the network on the chip is reduced, and the accuracy of clock synchronization is improved.

When the first processing module and the second processing module use non-coherent clock sources to provide reference clock signals, both the clock frequency and the clock phase need to be adjusted, and the clock frequency will drift over time. Therefore, in this case, clock synchronization needs to be performed regularly.

For example, the clock synchronization is performed periodically when the first processing module is in a working state. Here, the working state means that the first processing module has completed power-on initialization and can perform any operation such as calculation. For example, the clock synchronization performed periodically here includes recording the first count value, the second count value, and the entire process of clock compensation.

During the entire process of clock synchronization, that is, during the entire working process of the first processing module and the second processing module, the count values of the first timer and the second timer always keep monotonically increasing. Unlike the same source clock source, clock synchronization only needs to be performed once. In the case of non-same source clock sources, clock synchronization needs to be performed regularly, and the clock of the first processing module or the second processing module needs to keep monotonically increasing at all times, otherwise errors will occur in clock measurement and delay-related application services.

Therefore, in this embodiment, when performing clock synchronization, after obtaining the first count value and the second count value based on the same trigger signal record, it is necessary to determine the first processing module and the second processing module with a faster clock according to the first count value and the second count value, and select the slower one to perform clock compensation so that the clock is closer to the faster one.

Figure 6 is a flow chart of a clock synchronization method provided by at least one embodiment of the present invention.

As shown in FIG6 , after step S20, the clock synchronization method further includes step S401 and step S402.

In step S401, the magnitude relationship between the first count value and the second count value is compared.

In step S402, in response to the first count value being less than the second count value, clock compensation is performed according to the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, if the first count value is less than the second count value, it means that the clock of the first processing module is slower than the clock of the second processing module, and the clock of the first processing module needs to be adjusted to approach the clock of the second processing module.

For example, step S402 may include: determining the deviation between the first count value and the second count value; and compensating the first timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

The specific operation of clock compensation is slightly different depending on the type of clock source. The following describes the specific compensation process for different types of clock sources.

For example, for a crystal oscillator that can control the oscillation frequency of a clock source by voltage, such as a voltage-controlled crystal oscillator (VCXO) or a voltage-controlled temperature-compensated crystal oscillator (VCTCXO), the output frequency of the crystal oscillator can be controlled by inputting an adjustment voltage to the voltage control pin of the crystal oscillator, so that the oscillation frequency of the crystal oscillator continuously converges to the target oscillation frequency, and can achieve ppb (parts per billion) level accuracy.

For example, in this embodiment, the deviation between the first count value and the second count value is first obtained, for example, the deviation is the difference between the first count value and the second count value.

For example, in this embodiment, step S402 may include: compensating the first timer according to the deviation; determining the adjustment voltage according to the deviation; and compensating the first clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, the process of compensating the first timer according to the deviation is similar to that of the same source clock source. First, the current count value of the first timer is obtained as the third count value; then, the deviation and the third count value are added to obtain the updated count value; finally, the count value of the first timer is updated to the updated count value. The specific process will not be repeated here.

For example, determining the adjustment voltage based on the deviation may include: calculating the unit time frequency deviation of the first clock source relative to the second clock source based on the deviation; and determining the adjustment voltage based on the unit time frequency deviation.

For example, the unit time frequency deviation is in ppm (parts per million) or ppb. For example, the unit time frequency deviation can be the ratio of the deviation to the operating frequency of the first timer.

For voltage-controlled oscillators, for example, the capacitance of the varactor diode can be changed by adjusting the voltage, thereby "pulling" the frequency of the crystal oscillator to achieve the purpose of frequency modulation. Therefore, the adjustment voltage can be determined based on the unit time frequency deviation, and the adjustment voltage is related to the parameters of the crystal oscillator itself and the unit time frequency deviation.

For example, in some embodiments, determining the adjustment voltage based on the deviation may include: obtaining a historical frequency deviation, wherein the historical frequency deviation is the unit time frequency deviation used to calculate the adjustment voltage most recently; calculating a weighted sum of the historical frequency deviation and the unit time frequency deviation calculated based on the deviation; and determining the adjustment voltage based on the calculation result of the weighted sum.

For example, the calculation formula for adjusting the voltage is as follows: latest_ppm=(1.0-ema)*latest_ppm+ema*current_observed_ppm adj_vlt=f(latest_ppm)(Formula 1)

Among them, latest_ppm represents the historical frequency deviation, current_observed_ppm represents the unit time frequency deviation calculated based on the deviation, ema represents the weight coefficient, and here "=" represents assignment, for example, the weighted sum of the historical frequency deviation and the unit time frequency deviation calculated based on the deviation is assigned to (updated) the historical frequency deviation, adj_vlt represents the adjustment voltage, and f(*) represents the functional relationship between the adjustment voltage and the clock deviation (weighted sum).

For example, when the adjustment voltage calculation is performed for the first time, the adjustment voltage is calculated directly based on the current deviation, and the unit time frequency deviation calculated by the current deviation is used as the historical frequency deviation; when the adjustment voltage calculation is performed for the second time, the weighted sum of the unit time frequency deviation calculated by the current deviation and the historical frequency deviation is calculated, the adjustment voltage is determined based on the weighted sum, and the historical frequency deviation is updated to the weighted sum; and so on.

In this embodiment, the weight of the historical frequency deviation or the current unit time frequency deviation can be adjusted according to the weight coefficient to smoothly adjust the voltage change and the pulse change to avoid severe clock jitter.

For example, compensating the first clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located may include: inputting the adjustment voltage into the voltage control pin of the first clock source so that the oscillation frequency of the first clock source converges toward the oscillation frequency of the second clock source, and the first clock source is synchronized with the second clock source.

For example, after the adjustment voltage is input to the voltage control pin of the first clock source, the oscillation frequency of the first clock source will converge towards the oscillation frequency of the second clock source. The convergence can achieve ppb level accuracy, so the cycle of maintaining timely clock compensation can be relaxed to a longer period, such as performing clock synchronization once every 1 second. For example, when the convergence accuracy reaches 50ppb, for a system clock with an operating frequency of 100MHz, performing it once per second will produce an error of 5 cycles.

For example, the trigger signal is also configured to simultaneously trigger the interruption of the first processing module and the second processing module to perform clock compensation. For example, since the clocks are not of the same source, the first processing module and the second processing module may adjust the count value and clock frequency of their own timers. Therefore, the first processing module and the second processing module need to trigger interruption to interrupt their current application services, perform clock compensation, and then continue to execute the application service.

In the above embodiment, since the frequency of the crystal oscillator can be regulated by voltage, for example, when the clock of the first processing module is slower than the clock of the second processing module, the oscillation frequency of the first clock source is converged toward the oscillation frequency of the second clock source by voltage control. Therefore, the interval of "regular" clock synchronization can be set longer, for example, it can reach the second level, which has little impact on system performance, and does not need to frequently generate interruptions to affect system performance, nor does it need to frequently generate trigger signals for communication between the first processing module and the second processing module, and will not occupy the communication resources of the network or network line on the chip. In addition, synchronization failures are eliminated, the clock synchronization phase is greatly reduced, the number of communications between the first processing module and the second processing module is greatly reduced, and the impact of clock jitter and delay caused by network cables or on-chip networks is reduced, and the accuracy of clock synchronization is improved.

For example, for a crystal oscillator whose oscillation frequency of the clock source cannot be controlled by voltage, such as a simple XO (Crystal Oscillator) crystal oscillator, the stability of the XO crystal oscillator is completely determined by the inherent characteristics of the crystal resonator itself. In this case, the clock synchronization is still performed regularly when the first processing module is in working state. When it is determined that the first processing module needs to perform clock compensation, the first timer can be compensated. The specific process is similar to that when the clock source is the same source. First, the current count value of the first timer is obtained as the third count value; then, the deviation is added to the third count value to obtain the updated count value; finally, the count value of the first timer is updated to the updated count value to complete a clock compensation. The specific process will not be described here.

In addition, in this embodiment, the trigger signal is also configured to simultaneously trigger the interruption of the first processing module and the second processing module to perform clock compensation.

For example, in this embodiment, the interval time for executing clock synchronization is related to the frequency difference between the first clock source and the second clock source. If the frequency deviation between the first clock source and the second clock source is large, the compensation interval is shorter than the clock source capable of voltage control.

For example, at least one embodiment of the present invention also provides another clock synchronization method. Figure 7 is a schematic flow chart of another clock synchronization method provided by at least one embodiment of the present invention.

For example, the clock synchronization method is applied to the second processing module, the second processing module includes a second timer, and the count value of the second timer is used as the timing reference of the second processing module and increases sequentially. For example, the second timer is the system timer of the second processing module.

For the contents of the second processing module and the second timer, please refer to the relevant introduction of the first processing module and the first timer in the aforementioned embodiment, which will not be elaborated here.

For example, as shown in FIG. 7, the clock synchronization method provided by at least one embodiment of the present invention includes at least step S50.

In step S50, in response to receiving the trigger signal sent by the first processing module, the current count value of the second timer is recorded as the second count value. Here, the second processing module and the first processing module belong to different clock domains.

For example, the second count value is used to combine with the first count value for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The first count value is the current count value of the first timer of the first processing module when the first processing module sends a trigger signal to the second processing module. The count value of the first timer is used as the timing reference of the first processing module and increases sequentially.

For the relevant contents of the first processing module, the first timer, and the first count value, please refer to the relevant descriptions of the first processing module, the first timer, and the first count value in the aforementioned embodiment, which will not be repeated here.

For example, referring to the relevant description in the aforementioned embodiment, there are two reasons why the first processing module and the second processing module belong to different clock domains.

For example, when the first processing module and the second processing module have their own phase-locked loops, but the phase-locked loops receive the same source clock signal, as described in step S301 and step S302, the clock compensation is performed by the first processing module, and the second processing module only needs to record the count value of the second timer when receiving the same trigger signal. The second processing module does not need to be interrupted and can continue to perform the required operation. The implementation process is simple, no interruption is required, and compensation is performed once when the first processing module and the second processing module are in a powered state. No maintenance is required for non-power-off restart, and the impact on system performance is small, and the synchronization accuracy is high.

For example, the first processing module is provided with a reference clock signal by the first clock source, and the second processing module is provided with a reference clock signal by the second clock source. When the first clock source and the second clock source are non-coherent clock sources, as mentioned above, in this case, the non-coherent clock sources not only have different phases, but also different clock frequencies, and need to perform clock synchronization regularly, and the count values of the first timer and the second timer always keep monotonically increasing during the entire clock synchronization process. It should be noted that the entire clock synchronization process here does not only refer to a single clock synchronization, but also to the count values of the first timer and the second timer in multiple clock synchronizations performed regularly, which always keep monotonically increasing.

To keep the clock monotonically increasing, as mentioned above, it is necessary to first determine which of the first and second processing modules has a faster clock, and select the slower one for clock compensation so that the clock converges to the faster one.

For example, as shown in FIG7 , after step S50, the clock synchronization method further includes steps S601 to S603.

In step S601, the first count value is read from the first processing module.

In step S602, the magnitude relationship between the first count value and the second count value is compared.

In step S603, in response to the second count value being less than the first count value, clock compensation is performed according to the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, the trigger signal is also configured to simultaneously trigger the interruption of the first processing module and the second processing module to perform clock compensation.

For example, if the second count value is less than the first count value, it means that the clock of the second processing module is slower than the clock of the first processing module, and the clock of the second processing module needs to be adjusted to approach the clock of the first processing module.

For example, step S603 may include: determining the deviation between the first count value and the second count value; and compensating the second timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

As mentioned above, the specific operation of clock compensation is slightly different depending on the type of clock source.

For example, in response to the second clock source being able to use voltage to adjust the oscillation frequency, compensating the second timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, may include: compensating the second timer according to the deviation; determining the adjustment voltage according to the deviation; compensating the second clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, compensating the second clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located may include: inputting the adjustment voltage into the voltage control pin of the second clock source so that the oscillation frequency of the second clock source converges toward the oscillation frequency of the first clock source, and synchronizing the first clock source with the second clock source.

For example, the deviation can be the difference between the first count value and the second count value.

For example, the specific process of compensating the second timer according to the deviation can refer to the specific process of "compensating the first timer according to the deviation" in the aforementioned step S302 and step S402, which will not be elaborated here.

For example, the process of determining the adjustment voltage and the specific process of adjusting the second clock source using the adjustment voltage can also refer to the aforementioned description of adjusting the first clock source using the adjustment voltage, which will not be elaborated here.

Thus, the second timer is compensated by the deviation, and an adjustment voltage is calculated according to the deviation. By inputting the adjustment voltage into the voltage control pin of the second clock source, the oscillation frequency of the second clock source converges toward the oscillation frequency of the first clock source. Similarly, since the convergence can achieve ppb level accuracy, the maintenance and clock compensation cycle can also be relaxed to a longer period, for example, performing clock synchronization once every 1 second. This method has a small impact on system performance. It does not need to frequently generate interruptions to affect system performance, nor does it need to frequently generate trigger signals for communication between the first processing module and the second processing module. It will not occupy the communication resources of the network or network cable on the chip. In addition, it eliminates synchronization failures, greatly reduces the clock synchronization stage, and greatly reduces the number of communications between the first processing module and the second processing module. It reduces the impact of clock jitter and delay caused by the network cable or the network on the chip, and improves the accuracy of clock synchronization.

For example, for a crystal oscillator whose oscillation frequency of the clock source cannot be controlled by voltage, the specific execution process of its clock compensation is similar to the process of the first processing module executing clock compensation in the same scenario mentioned above, and will not be elaborated here.

For example, at least one embodiment of the present invention also provides a system clock synchronization method.

For example, the system may include a first processing module and a second processing module, the first processing module includes a first timer, the count value of the first timer serves as a timing reference of the first processing module and increases sequentially, the second processing module includes a second timer, the count value of the second timer serves as a timing reference of the second processing module and increases sequentially, and the first processing module and the second processing module belong to different clock domains.

For example, the system can be a CPU as shown in FIG1, and the first processing module and the second processing module can be any two CPU Dies or CPU Sockets in FIG1. Of course, the present invention does not impose specific restrictions on this, and it can also be other processing modules that need to execute clock synchronization.

For example, the first timer may be a system timer of the first processing module, and the second timer may be a system timer of the second processing module. For the description of the first timer and the second timer, please refer to the previous content, which will not be repeated here.

For example, the first processing module and the second processing module belong to the field of asynchronous clocks. The reasons for this are as described above and will not be elaborated here.

For example, in some embodiments, the system clock synchronization method may include: the first processing module sends a trigger signal to the second processing module, the first processing module records the current count value of the first timer when sending the trigger signal as the first count value, and the second processing module records the current count value of the second timer when receiving the trigger signal as the second count value. Here, the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, the specific process of using the first count value and the second count value for clock compensation can refer to the related description of the clock synchronization method applied to the first processing module and the clock synchronization method applied to the second processing module.

For example, in the case where the clock sources are the same but the first processing module and the second processing module have their own phase-locked loops, the first timer is compensated according to the deviation between the first count value and the second count value, so that the first clock domain and the second clock domain are synchronized. For example, the specific process of this clock synchronization can refer to the related description of the clock synchronization method applied to the first processing module and the clock synchronization method applied to the second processing module, which will not be repeated here.

FIG8A is a schematic diagram of the interactive process of the system clock synchronization method provided by at least one embodiment of the present invention. The following is combined with FIG8A to explain the execution process of the system clock synchronization method when the first clock source and the second clock source are non-co-origin clock sources.

As shown in FIG8A, at time T0, the first processing module sends an "assert trigger" to the second processing module. At this time, the first processing module records the current count value of the first timer as the first count value and stores it in the first register when sending the trigger signal. For example, the first register is located in the first processing module and can statically store values. At the same time, the second processing module records the current count value of the second timer as the second count value and stores it in the second register when receiving the trigger signal (T0'). For example, the second register is located in the second processing module and can statically store values. In addition, the trigger signal also triggers the interruption of the first processing module and the second processing module at the same time.

Afterwards, at time T1, the first processing module reads the value of the second register in the second processing module to obtain the second count value. At time T1', the second processing module reads the value of the first register in the first processing module to obtain the first count value. Here, T1 can be equal to T1' or different.

Afterwards, the first processing module and the second processing module compare the magnitude of the count value recorded by themselves and the count value read. If the count value recorded by themselves is less than the count value read, clock compensation is performed, otherwise clock compensation is not performed.

For example, for the first processing module, after obtaining the second count value, in step S401, the first count value and the second count value are compared. If the first count value is less than the second count value, refer to step S402 for clock compensation. The specific process can refer to the relevant content of step S402, which will not be repeated here.

For example, for the second processing module, after obtaining the first count value, in step S602, the first count value and the second count value are compared. If the second count value is less than the first count value, refer to step S603 to perform clock compensation. The specific process can refer to the relevant content of step S603, which will not be repeated here.

Therefore, the clock always keeps monotonically increasing during the clock synchronization process.

Afterwards, at time Tn, the first processing module again sends an "assert trigger" to the second processing module. When the first processing module sends the trigger signal (at time Tn), it records the current count value of the first timer as the first count value and stores it in the first register. When the second processing module receives the trigger signal (at time Tn'), it records the current count value of the second timer as the second count value and stores it in the second register. In addition, the trigger signal also triggers the interruption of the first processing module and the second processing module at the same time.

Afterwards, at time Tn+1, the first processing module reads the value of the second register in the second processing module to obtain the second count value. At time Tn+1’, the second processing module reads the value of the first register in the first processing module to obtain the first count value. Afterwards, the first processing module and the second processing module compare the count value recorded by themselves and the count value read. If the count value recorded by themselves is less than the count value read, clock compensation is performed, otherwise, clock compensation is not performed. The specific process is similar to that at time T0, and will not be repeated here.

For example, the difference between the Tn moment and the T0 moment can be determined based on the type of clock source, the clock frequency deviation between the first clock source and the second clock source.

In the above embodiment, since the clock sources are not the same, there is a phase difference and a clock frequency deviation between the first processing module and the second processing module, and the phase difference and the clock frequency deviation may drift over time. Therefore, it is necessary to perform clock synchronization regularly, including obtaining the first count value and the second count value through the same trigger signal, and performing clock compensation according to the first count value and the second count value. This implementation method is simple and effective, eliminating synchronization failures, greatly reducing the clock synchronization stage, greatly reducing the number of communications between the first processing module and the second processing module, reducing the number of communication ports used for clock synchronization, reducing the impact of clock jitter and delay caused by network cables or on-chip networks, and improving clock synchronization accuracy.

For example, when the trigger signal is sent from the first processing module to the second processing module, it needs to be transmitted through the communication bus between the modules, such as through a PCB (Printed Circuit Board) or substrate. The transmission rate of electrical signals in PCB/substrate is related to the dielectric constant of the material. For example, the transmission rate of electrical signals in glass cloth substrate (FR) is about half the speed of light, and the transmission rate in Rogers board is about 70% of the speed of light. Based on the transmission distance of 30cm, the deviation caused by communication between dies is at the ns level. The time difference (such as the difference between T0 and T0') is small and can be ignored for clock compensation.

For example, in some examples, it is also possible to compensate for the delay caused by the trigger signal being transmitted between processing modules, that is, to compensate for the difference between T0 and T0'.

FIG8B is a schematic block diagram of the transmission delay between compensation processing modules provided by at least one embodiment of the present invention.

As shown in FIG8B , a feedback path is established for the trigger signal on the substrate or PCB of the first processing module. For example, when the trigger signal is sent from the first timer to the second timer through the on-chip network or the interconnect bus, the trigger signal is transmitted back to the first timer through the feedback path, and clock compensation is performed according to the time when the trigger signal is transmitted back to the first timer through the feedback path.

Specifically, the current count value of the first timer when the first timer receives the feedback signal transmitted by the feedback path is recorded as the first count value, and the value of the second timer when it receives the trigger signal is recorded as the second count value, thereby compensating for the transmission delay between the processing modules.

At least one embodiment of the present invention also provides a clock synchronization device. FIG. 9A is a schematic block diagram of a clock synchronization device provided by at least one embodiment of the present invention.

For example, the clock synchronization device is used for the first processing module. For example, the first processing module includes a first timer, and the count value of the first timer serves as the timing reference of the first processing module and increases sequentially.

For the description of the first processing module, the first timer, etc., please refer to the related introduction of the clock synchronization method applied to the first processing module, which will not be elaborated here.

As shown in FIG9A , the clock synchronization device 100 may include a first recording unit 101 and a reading unit 102. These components are interconnected through a bus system and/or other forms of connection mechanisms (not shown). It should be noted that the components and structures of the clock synchronization device 100 shown in FIG9A are only exemplary and not restrictive. The clock synchronization device 100 may also have other components and structures as needed.

The first recording unit 101 is configured to send a trigger signal to the second processing module, and simultaneously record the current count value of the first timer when the trigger signal is sent as the first count value.

For example, the second processing module and the first processing module belong to different clock domains.

The reading unit 102 is configured to read the second count value from the second processing module.

For example, the second count value is the current count value of the second timer of the second processing module when the second processing module receives the trigger signal. The count value of the second timer serves as the timing reference of the second processing module and increases sequentially.

For example, the first count value and the second count value are used for clock compensation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, as shown in FIG9A , the clock synchronization device further includes a first clock compensation unit 103.

For example, in some embodiments, the first processing module includes a first phase-locked loop, the first phase-locked loop is configured to receive a first clock signal provided by a first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal, the second processing module includes a second phase-locked loop, the second phase-locked loop is configured to receive a first clock signal provided by a first clock source, and provide a second reference clock signal to the second processing module according to the first clock signal, the first phase-locked loop is different from the second phase-locked loop, and the clock compensation is performed when the first processing module is in the power-on stage.

For example, in the above embodiment, the first clock compensation unit 103 is configured to perform the following operations: determine the deviation between the first count value and the second count value; according to the deviation, compensate the first timer so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, when the first clock compensation unit 103 performs compensation on the first timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, the following operations are performed: obtaining the current count value of the first timer as the third count value; adding the deviation and the third count value to obtain an updated count value; updating the count value of the first timer to the updated count value so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, the trigger signal is also configured to simultaneously trigger an interruption of the first processing module to execute the clock compensation.

For example, in other embodiments, the first processing module is provided with a reference clock signal by a first clock source, and the second processing module is provided with a reference clock signal by a second clock source. The first clock source and the second clock source are non-cognate clock sources. The clock synchronization is performed periodically when the first processing module is in a working state. During the entire process of clock synchronization, the count values of the first timer and the second timer always keep monotonically increasing.

In the above embodiment, the first clock compensation unit 103 is configured to perform the following operations: compare the magnitude relationship between the first count value and the second count value; in response to the first count value being less than the second count value, perform clock compensation according to the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, in the above embodiment, when the first clock compensation unit 103 performs clock compensation according to the deviation between the first count value and the second count value so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, the following operations are performed: determining the deviation between the first count value and the second count value; and compensating the first timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, in the above embodiment, the first clock compensation unit 103 performs the following operations in response to the first clock source being able to adjust the oscillation frequency using voltage, and compensates the first timer according to the deviation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located: compensating the first timer according to the deviation; determining the adjustment voltage according to the deviation; and compensating the first clock source according to the adjustment voltage, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, in some examples, when the first clock compensation unit 103 determines the adjustment voltage according to the deviation, it includes performing the following operations: calculating the unit time frequency deviation of the first clock source relative to the second clock source according to the deviation; and determining the adjustment voltage according to the unit time frequency deviation.

For example, in other examples, when the first clock compensation unit 103 determines the adjustment voltage according to the deviation, it includes performing the following operations: obtaining a historical frequency deviation, wherein the historical frequency deviation is the unit time frequency deviation used to calculate the adjustment voltage most recently; calculating the weighted sum of the historical frequency deviation and the unit time frequency deviation calculated based on the deviation; and determining the adjustment voltage according to the calculation result of the weighted sum.

For example, when the first clock compensation unit 103 performs compensation on the first clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, the following operations are performed: inputting the adjustment voltage into the voltage control pin of the first clock source so that the oscillation frequency of the first clock source converges toward the oscillation frequency of the second clock source, and the first clock source and the second clock source are synchronized.

For example, in the above embodiment, the trigger signal is also configured to simultaneously trigger the interruption of the first processing module and the second processing module to perform the clock compensation.

For example, the first count value is stored in the register of the first processing module, and the second count value is stored in the register of the second processing module. The specific description of the first recording unit 101, the reading unit 102 and the first clock compensation unit 103 can refer to the description of the relevant steps of the clock synchronization method applied to the first processing module, which will not be repeated here.

For example, the clock synchronization device 100 can achieve technical effects similar to the clock synchronization method applied to the first processing module mentioned above, which will not be elaborated here.

At least one embodiment of the present invention also provides another clock synchronization device. FIG. 9B is a schematic block diagram of another clock synchronization device provided by at least one embodiment of the present invention.

For example, the clock synchronization device is used for the second processing module. For example, the second processing module includes a second timer, and the count value of the second timer serves as the timing reference of the second processing module and increases sequentially.

For the description of the second processing module, the second timer, etc., please refer to the related introduction of the clock synchronization method applied to the second processing module, which will not be elaborated here.

As shown in FIG9B , the clock synchronization device 200 may include a second recording unit 201. These components are interconnected through a bus system and/or other forms of connection mechanisms (not shown). It should be noted that the components and structures of the clock synchronization device 200 shown in FIG9B are only exemplary and not restrictive. The clock synchronization device 200 may also have other components and structures as needed.

For example, the second recording unit 201 is configured to record the current count value of the second timer as the second count value in response to receiving the trigger signal sent by the first processing module, wherein the second processing module and the first processing module belong to different clock domains.

For example, the second count value is used to combine with the first count value for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The first count value is the current count value of the first timer of the first processing module when the first processing module sends a trigger signal to the second processing module. The count value of the first timer is used as the timing reference of the first processing module and increases sequentially.

As shown in FIG9B , the clock synchronization device 200 may further include a second clock compensation unit 202.

For example, in some embodiments, the first processing module is provided with a reference clock signal by a first clock source, and the second processing module is provided with a reference clock signal by a second clock source. The first clock source and the second clock source are non-cognate clock sources. The clock synchronization is performed periodically when the first processing module is in a working state. During the entire process of clock synchronization, the count values of the first timer and the second timer always keep monotonically increasing.

In the above embodiment, the second clock compensation unit 202 is configured to perform the following operations: read the first count value from the first processing module; compare the magnitude relationship between the first count value and the second count value; in response to the second count value being less than the first count value, perform clock compensation according to the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, when the second clock compensation unit 202 performs the clock compensation according to the deviation between the first count value and the second count value so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, the following operations are performed: determining the deviation between the first count value and the second count value; and compensating the second timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, in response to the second clock source being able to adjust the oscillation frequency using voltage, the second clock compensation unit 202 performs the following operations when compensating the second timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located: compensating the second timer according to the deviation; determining the adjustment voltage according to the deviation; compensating the second clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, when the second clock compensation unit 202 performs compensation on the second clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, the following operations are performed: inputting the adjustment voltage into the voltage control pin of the second clock source so that the oscillation frequency of the second clock source converges toward the oscillation frequency of the first clock source, and the first clock source and the second clock source are synchronized.

For the specific description of the second recording unit 201 and the second clock compensation unit 202, please refer to the description of the relevant steps of the clock synchronization method applied to the second processing module, which will not be repeated here.

For example, the clock synchronization device 200 can achieve technical effects similar to the clock synchronization method applied to the second processing module mentioned above, which will not be elaborated here.

At least one embodiment of the present invention also provides an electronic device, and FIG. 9C is a schematic structural diagram of an electronic device provided by at least one embodiment of the present invention.

As shown in FIG. 9C , the electronic device 300 includes a first processing module 310 and a second processing module 320.

For example, the first processing module includes a first timer, the count value of the first timer serves as the timing reference of the first processing module and increases sequentially, the second processing module includes a second timer, the count value of the second timer serves as the timing reference of the second processing module and increases sequentially, and the first processing module and the second processing module belong to different clock domains.

For example, the first processing module is configured to send a trigger signal to the second processing module, and record the current count value of the first timer when the trigger signal is sent as the first count value.

For example, the second processing module is configured to record the current count value of the second timer when the trigger signal is received as the second count value.

For example, the first count value and the second count value are used for clock compensation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

For example, the electronic device may be a processing device such as a CPU, and the first processing module and the second processing module may be a CPU Die or a CPU Socket. Of course, the present invention is not limited thereto. It should be noted that the components and structures of the electronic device 300 shown in FIG. 9C are only exemplary and not restrictive. The electronic device 300 may also have other components and structures as needed.

For example, the specific process of executing clock synchronization between the first processing module and the second processing module can refer to the relevant description of the aforementioned system clock synchronization method, which will not be elaborated here.

For example, the electronic device 300 can achieve a technical effect similar to the aforementioned system clock synchronization method, which will not be elaborated here.

Some embodiments of the present invention also provide an electronic device. Figure 10 is a schematic block diagram of an electronic device provided by at least one embodiment of the present invention.

For example, as shown in FIG. 10 , the electronic device 400 includes a processor 410 and a memory 420. It should be noted that the components of the electronic device 400 shown in FIG. 10 are only exemplary and not restrictive. The electronic device 400 may also have other components according to actual application requirements.

For example, the processor 410 and the memory 420 may communicate with each other directly or indirectly.

For example, the processor 410 and the memory 420 can communicate through a network. The network may include a wireless network, a wired network, and/or any combination of a wireless network and a wired network. The processor 410 and the memory 420 can also communicate with each other through a system bus, which is not limited by the present invention.

For example, in some embodiments, the memory 420 is used to store computer-readable instructions non-transitorily. When the processor 410 is used to execute the computer-readable instructions, the computer-readable instructions are executed by the processor 410 to implement the clock synchronization method described in any of the above embodiments or the system clock synchronization method described in any of the above embodiments. For the specific implementation of each step of the clock synchronization method and the related explanation content, please refer to the above embodiment of the clock synchronization method. For the specific implementation of each step of the system clock synchronization method and the related explanation content, please refer to the above embodiment of the system clock synchronization method. The repetition will not be repeated here.

For example, the processor 410 can control other components in the electronic device 400 to perform the desired functions. The processor 410 can be a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The central processing unit (CPU) can be X86 or ARM architecture, etc.

For example, the memory 420 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and/or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-readable instructions can be stored on the computer-readable storage medium, and the processor 410 can run the computer-readable instructions to implement various functions of the electronic device 400. Various applications and various data can also be stored in the storage medium.

For example, in some embodiments, the electronic device 400 may be a mobile phone, a tablet computer, an electronic paper, a television, a display, a notebook computer, a digital photo frame, a navigator, a wearable electronic device, a smart home device, etc.

For example, the electronic device 400 may include a display panel, which may be used to display interactive content, etc. For example, the display panel may be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel, etc. In addition, the display panel may be not only a flat panel, but also a curved panel, or even a spherical panel.

For example, the electronic device 400 may have a touch function, that is, the electronic device 400 may be a touch device.

For example, the detailed description of the process of the electronic device 400 executing the clock synchronization method can refer to the relevant description in the embodiment of the clock synchronization method, and the detailed description of the process of the electronic device 400 executing the system clock synchronization method can refer to the relevant description in the embodiment of the above-mentioned system clock synchronization method, and the repeated parts will not be repeated.

FIG11 is a schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present invention. For example, as shown in FIG11 , one or more computer-readable instructions 510 can be stored non-transitorily on the storage medium 500. For example, when the computer-readable instruction 510 is executed by the processor, one or more steps in the clock synchronization method described above can be executed, or, when the computer-readable instruction 510 is executed by the processor, one or more steps in the system clock synchronization method described above can be executed.

For example, the storage medium 500 may be applied to the above-mentioned electronic device 400. For example, the storage medium 500 may include the memory 420 in the electronic device 400.

For example, the description of the storage medium 500 can refer to the description of the memory 420 in the embodiment of the electronic device 400, and the repeated parts will not be repeated.

In particular, according to an embodiment of the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, the computer program containing a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processing device, the above functions defined in the method of the embodiment of the present invention are executed.

It should be noted that in the context of the present invention, a computer-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium or any combination thereof. A computer-readable storage medium may be, for example, but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical memory device, a magnetic memory device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, the computer-readable signal medium may include a data signal transmitted in the baseband or as part of a carrier wave, which carries a computer-readable program code. Such a transmitted data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program used by or in conjunction with an instruction execution system, device, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

The above-mentioned computer-readable medium may be contained in the above-mentioned electronic device; or it may exist alone without being assembled into the electronic device.

Computer program code for performing operations of the present invention may be written in one or more programming languages or combinations thereof, including but not limited to object-oriented programming languages such as Java, Smalltalk, C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In situations involving remote computers, the remote computer can be connected to the user computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (such as through the Internet using an Internet service provider).

The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flow chart or block diagram may represent a module, a program segment, or a portion of a code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the boxes may also occur in a different order than the order marked in the accompanying drawings. For example, two boxes represented in succession may actually be executed substantially in parallel, and they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and/or flowchart, and combinations of boxes in the block diagram and/or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

The units involved in the embodiments of the present invention can be implemented by software or hardware. In some cases, the name of the unit does not constitute a limitation on the unit itself.

The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

According to one or more embodiments of the present invention, a clock synchronization method is provided, wherein the first processing module includes a first timer, the count value of the first timer is used as a timing reference of the first processing module and increases sequentially, and the clock synchronization method includes: sending a trigger signal to a second processing module, and recording the current count value of the first timer when the trigger signal is sent as a first count value, wherein the second processing module and the first processing module belong to different clock domains; The second processing module reads a second count value, wherein the second count value is the current count value of the second timer of the second processing module when the second processing module receives the trigger signal, and the count value of the second timer is used as the timing reference of the second processing module and increases sequentially; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, the first processing module includes a first phase-locked loop, the first phase-locked loop is configured to receive a first clock signal provided by a first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal, the second processing module includes a second phase-locked loop, the second phase-locked loop is configured to receive the first clock signal provided by the first clock source, and provide a second reference clock signal to the second processing module according to the first clock signal, the first phase-locked loop is different from the second phase-locked loop, and the clock compensation is executed when the first processing module is in the power-on stage.

According to one or more embodiments of the present invention, the clock synchronization method further includes: determining the deviation between the first count value and the second count value; and compensating the first timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, the first timer is compensated according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, including: obtaining the current count value of the first timer as the third count value; adding the deviation and the third count value to obtain an updated count value; updating the count value of the first timer to the updated count value so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, the trigger signal is also configured to simultaneously trigger an interruption of the first processing module to perform the clock compensation.

According to one or more embodiments of the present invention, the first processing module is provided with a reference clock signal by a first clock source, and the second processing module is provided with a reference clock signal by a second clock source, the first clock source and the second clock source are non-cognate clock sources, and the clock synchronization is performed periodically when the first processing module is in a working state. During the entire process of the clock synchronization, the count values of the first timer and the second timer always keep monotonically increasing.

According to one or more embodiments of the present invention, the clock synchronization method further includes: comparing the magnitude relationship between the first count value and the second count value; in response to the first count value being less than the second count value, clock compensation is performed according to the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, clock compensation is performed according to the deviation between the first count value and the second count value so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, including: determining the deviation between the first count value and the second count value; and compensating the first timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, in response to the first clock source being able to adjust the oscillation frequency using voltage, the first timer is compensated according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, including: compensating the first timer according to the deviation; determining an adjustment voltage according to the deviation; and compensating the first clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, determining the adjustment voltage according to the deviation includes: calculating the unit time frequency deviation of the first clock source relative to the second clock source according to the deviation; and determining the adjustment voltage according to the unit time frequency deviation.

According to one or more embodiments of the present invention, determining the adjustment voltage according to the deviation includes: obtaining a historical frequency deviation, wherein the historical frequency deviation is the unit time frequency deviation used to calculate the adjustment voltage most recently; calculating the weighted sum of the historical frequency deviation and the unit time frequency deviation calculated based on the deviation; and determining the adjustment voltage according to the calculation result of the weighted sum.

According to one or more embodiments of the present invention, the first clock source is compensated according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, including: inputting the adjustment voltage into the voltage control pin of the first clock source so that the oscillation frequency of the first clock source converges toward the oscillation frequency of the second clock source, and the first clock source and the second clock source are synchronized.

According to one or more embodiments of the present invention, the trigger signal is also configured to simultaneously trigger the interruption of the first processing module and the second processing module to perform the clock compensation.

According to one or more embodiments of the present invention, the first count value is stored in a register of the first processing module, and the second count value is stored in a register of the second processing module.

According to one or more embodiments of the present invention, a clock synchronization method is provided for a second processing module, wherein the second processing module includes a second timer, and the count value of the second timer is used as a timing reference of the second processing module and increases sequentially. The clock synchronization method includes: in response to receiving a trigger signal sent by the first processing module, recording the current count value of the second timer as a second count value, wherein the second processing module and the first processing module are different. The second count value is used to combine with the first count value to perform clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The first count value is the current count value of the first timer of the first processing module when the first processing module sends a trigger signal to the second processing module. The count value of the first timer is used as the timing reference of the first processing module and increases sequentially.

According to one or more embodiments of the present invention, the first processing module is provided with a reference clock signal by a first clock source, and the second processing module is provided with a reference clock signal by a second clock source, the first clock source and the second clock source are non-cognate clock sources, and the clock synchronization is performed periodically when the first processing module is in a working state. During the entire process of the clock synchronization, the count values of the first timer and the second timer always keep monotonically increasing.

According to one or more embodiments of the present invention, the clock synchronization method further includes: reading the first count value from the first processing module; comparing the magnitude relationship between the first count value and the second count value; in response to the second count value being less than the first count value, performing the clock compensation according to the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, the clock compensation is performed according to the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, including: determining the deviation between the first count value and the second count value; and compensating the second timer according to the deviation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, in response to the second clock source being able to adjust the oscillation frequency using voltage, the second timer is compensated according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, including: compensating the second timer according to the deviation; determining an adjustment voltage according to the deviation; and compensating the second clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, the second clock source is compensated according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, including: inputting the adjustment voltage into the voltage control pin of the second clock source so that the oscillation frequency of the second clock source converges toward the oscillation frequency of the first clock source, and the first clock source and the second clock source are synchronized.

According to one or more embodiments of the present invention, a system clock synchronization method is provided, wherein the system includes a first processing module and a second processing module, the first processing module includes a first timer, the count value of the first timer is used as a timing reference of the first processing module and increases sequentially, the second processing module includes a second timer, the count value of the second timer is used as a timing reference of the second processing module and increases sequentially, the first processing module and the second processing module belong to different clock domains, and the system clock is synchronized. The synchronization method includes: the first processing module sends a trigger signal to the second processing module, the first processing module records the current count value of the first timer when sending the trigger signal as the first count value, and the second processing module records the current count value of the second timer when receiving the trigger signal as the second count value; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, a clock synchronization device is used for a first processing module, wherein the first processing module includes a first timer, and the count value of the first timer is used as a timing reference of the first processing module and increases in sequence. The clock synchronization device includes: a first recording unit, configured to send a trigger signal to a second processing module, and record the current count value of the first timer when the trigger signal is sent as a first count value, wherein the second processing module and the first processing module belong to different Clock domain; a reading unit configured to read a second count value from the second processing module, wherein the second count value is the current count value of the second timer of the second processing module when the second processing module receives the trigger signal, and the count value of the second timer is used as the timing reference of the second processing module and increases sequentially; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, a clock synchronization device is provided for a second processing module, wherein the second processing module includes a second timer, and the count value of the second timer is used as a timing reference of the second processing module and increases in sequence. The clock synchronization device includes: a second recording unit, configured to respond to receiving a trigger signal sent by the first processing module, and record the current count value of the second timer as a second count value, wherein the second processing module is synchronized with the first processing module. The processing modules belong to different clock domains; wherein the second count value is used to combine with the first count value for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located; the first count value is the current count value of the first timer of the first processing module when the first processing module sends a trigger signal to the second processing module; the count value of the first timer is used as the timing reference of the first processing module and increases sequentially.

According to one or more embodiments of the present invention, an electronic device includes a first processing module and a second processing module, wherein the first processing module includes a first timer, the count value of the first timer is used as a timing reference of the first processing module and increases sequentially, the second processing module includes a second timer, the count value of the second timer is used as a timing reference of the second processing module and increases sequentially, the first processing module and the second processing module belong to different clock domains, wherein the The first processing module is configured to send a trigger signal to the second processing module, and record the current count value of the first timer when sending the trigger signal as the first count value, and the second processing module is configured to record the current count value of the second timer when receiving the trigger signal as the second count value; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located.

According to one or more embodiments of the present invention, an electronic device includes: a memory that non-temporarily stores computer executable instructions; a processor that is configured to execute the computer executable instructions, wherein the computer executable instructions, when executed by the processor, implement the clock synchronization method described in any embodiment of the present invention or the system clock synchronization method described in any embodiment of the present invention.

According to one or more embodiments of the present invention, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the clock synchronization method described in any embodiment of the present invention or the system clock synchronization method described in any embodiment of the present invention is implemented.

The above description is only a preferred embodiment of the present invention and an explanation of the technical principle used. Those skilled in the art should understand that the disclosure scope involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above public concept. For example, the above features are replaced with the technical features disclosed in the present invention (but not limited to) with similar functions to form a technical solution.

Furthermore, although the operations are depicted in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in a sequential order. Multiplexing and parallel processing may be advantageous in certain circumstances. Likewise, although several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the invention. Certain features described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments, either individually or in any suitable subcombination.

Although the subject matter has been described using language specific to structural features and/or methodological logic acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Regarding this invention, there are a few points that need to be explained:

(1) The drawings of the embodiments of the present invention only involve the structures involved in the embodiments of the present invention. Other structures can refer to the usual design.

(2) In the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other to obtain new embodiments.

The above is only a specific implementation method of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the above-mentioned claim.

S10, S20: Steps

Claims (19)

A clock synchronization method is used for a first processing module, wherein the first processing module includes a first timer, the count value of the first timer is used as a timing reference of the first processing module and increases in sequence, the clock synchronization method includes: sending a trigger signal to a second processing module, and recording the current count value of the first timer when the trigger signal is sent as a first count value, wherein the second processing module and the first processing module belong to different clock domains; reading a second count value from the second processing module, wherein the second count value is the current count value of the second timer of the second processing module when the second processing module receives the trigger signal, and the count value of the second timer is used as the timing reference of the second processing module and increases sequentially; wherein the first count value and the second count value are used for clock compensation, so that the first clock domain where the first processing module is located is The first processing module includes a first phase-locked loop, the first phase-locked loop is configured to receive a first clock signal provided by a first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal, and the second processing module includes a second phase-locked loop, the second phase-locked loop is configured to receive the first clock signal provided by the first clock source , and provides a second reference clock signal for the second processing module according to the first clock signal, the first phase-locked loop is different from the second phase-locked loop, responds to the first clock signal which is different from the first phase-locked loop and the second phase-locked loop but receives the same source, and the clock compensation is performed when the first processing module is in the power-on stage, wherein the power-on stage refers to the first processing module just being powered on but before performing any specific operation. The clock synchronization method as described in claim 1, wherein the clock synchronization method further comprises: determining the deviation between the first count value and the second count value; and compensating the first timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The clock synchronization method as described in claim 2, wherein the first timer is compensated according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, comprising: obtaining the current count value of the first timer as the third count value; adding the deviation and the third count value to obtain an updated count value; updating the count value of the first timer to the updated count value so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The clock synchronization method as described in claim 1, wherein the first processing module is provided with a reference clock signal by a first clock source, and the second processing module is provided with a reference clock signal by a second clock source, the first clock source and the second clock source are non-coherent clock sources, and the clock synchronization is performed periodically when the first processing module is in a working state, and during the entire process of the clock synchronization, the count values of the first timer and the second timer always keep monotonically increasing. The clock synchronization method as described in claim 4, wherein the clock synchronization method further comprises: comparing the magnitude relationship between the first count value and the second count value; in response to the first count value being less than the second count value, performing clock compensation according to the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The clock synchronization method as described in claim 5, wherein clock compensation is performed according to the deviation between the first count value and the second count value so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, comprising: determining the deviation between the first count value and the second count value; and compensating the first timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The clock synchronization method as described in claim 6, wherein, in response to the first clock source being able to adjust the oscillation frequency using voltage, the first timer is compensated according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, comprising: compensating the first timer according to the deviation; determining an adjustment voltage according to the deviation; and compensating the first clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The clock synchronization method as described in claim 7, wherein the first clock source is compensated according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, including: inputting the adjustment voltage into the voltage control pin of the first clock source so that the oscillation frequency of the first clock source converges toward the oscillation frequency of the second clock source, and the first clock source and the second clock source are synchronized. A clock synchronization method is provided for a second processing module, wherein the second processing module includes a second timer, the count value of the second timer is used as the timing reference of the second processing module and increases in sequence, and the clock synchronization method includes: in response to receiving a trigger signal sent by the first processing module, recording the current count value of the second timer as the second count value, wherein the second processing module and the first processing module belong to different clock domains; wherein the second count value is used to combine with the first count value for clock compensation, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, the first count value is the current count value of the first timer of the first processing module when the first processing module sends a trigger signal to the second processing module, and the count value of the first timer is used as the second clock domain of the second processing module. The timing reference of the first processing module is a timing reference of a processing module and increases in sequence; wherein the first processing module includes a first phase-locked loop, the first phase-locked loop is configured to receive a first clock signal provided by a first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal, and the second processing module includes a second phase-locked loop, the second phase-locked loop is configured to receive the first clock signal provided by the first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal According to the first clock signal, a second reference clock signal is provided for the second processing module. The first phase-locked loop is different from the second phase-locked loop, and responds to the first clock signal which is different from the first phase-locked loop and the second phase-locked loop but receives the same source. The clock compensation is performed when the first processing module is in the power-on stage, wherein the power-on stage refers to the first processing module just being powered on but before performing any specific operation. The clock synchronization method as described in claim 9, wherein the first processing module is provided with a reference clock signal by a first clock source, and the second processing module is provided with a reference clock signal by a second clock source, the first clock source and the second clock source are non-coherent clock sources, and the clock synchronization is performed periodically when the first processing module is in a working state, and during the entire process of the clock synchronization, the count values of the first timer and the second timer always keep monotonically increasing. The clock synchronization method as described in claim 10, wherein the clock synchronization method further comprises: reading the first count value from the first processing module; comparing the magnitude relationship between the first count value and the second count value; in response to the second count value being less than the first count value, performing the clock compensation according to the deviation between the first count value and the second count value, so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The clock synchronization method as described in claim 11, wherein the clock compensation is performed according to the deviation between the first count value and the second count value so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, comprising: determining the deviation between the first count value and the second count value; and compensating the second timer according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. The clock synchronization method as described in claim 12, wherein, in response to the second clock source being able to adjust the oscillation frequency using voltage, the second timer is compensated according to the deviation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, comprising: Compensating the second timer according to the deviation; determining an adjustment voltage according to the deviation; compensating the second clock source according to the adjustment voltage so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located. A system clock synchronization method, wherein the system includes a first processing module and a second processing module, the first processing module includes a first timer, the count value of the first timer is used as a timing reference of the first processing module and increases sequentially, the second processing module includes a second timer, the count value of the second timer is used as a timing reference of the second processing module and increases sequentially, the first processing module and the second processing module belong to different clocks The system clock synchronization method includes: the first processing module sends a trigger signal to the second processing module, the first processing module records the current count value of the first timer when sending the trigger signal as the first count value, and the second processing module records the current count value of the second timer when receiving the trigger signal as the second count value; wherein the first count value and the second count value are used for clock compensation, so that the first The first processing module includes a first phase-locked loop, the first phase-locked loop is configured to receive a first clock signal provided by a first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal, and the second processing module includes a second phase-locked loop, the second phase-locked loop is configured to receive a first clock signal provided by the first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal. A first reference clock signal is provided for the second processing module according to the first clock signal. The first phase-locked loop is different from the second phase-locked loop, and responds to the first clock signal which is different from the first phase-locked loop and the second phase-locked loop but receives the same source. The clock compensation is performed when the first processing module is in the power-on stage, wherein the power-on stage refers to the first processing module just being powered on but before performing any specific operation. A clock synchronization device is used for a first processing module, wherein the first processing module includes a first timer, the count value of the first timer is used as a timing reference of the first processing module and increases in sequence, and the clock synchronization device includes: a first recording unit, configured to send a trigger signal to a second processing module, and simultaneously record the current count value of the first timer when the trigger signal is sent as a first count value, wherein the second processing module is connected to the first processing module The processing module belongs to a different clock domain; the reading unit is configured to read a second count value from the second processing module, wherein the second count value is the current count value of the second timer of the second processing module when the second processing module receives the trigger signal, and the count value of the second timer is used as the timing reference of the second processing module and increases sequentially; wherein the first count value and the second count value are used for clock compensation, so that the first The first processing module includes a first phase-locked loop, the first phase-locked loop is configured to receive a first clock signal provided by a first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal, and the second processing module includes a second phase-locked loop, the second phase-locked loop is configured to receive the first clock signal provided by the first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal. The first processing module receives a first clock signal and provides a second reference clock signal for the second processing module according to the first clock signal. The first phase-locked loop is different from the second phase-locked loop and responds to the first clock signal which is different from the first phase-locked loop and the second phase-locked loop but receives the same source. The clock compensation is performed when the first processing module is in the power-on stage, wherein the power-on stage refers to the first processing module just being powered on but before performing any specific operation. A clock synchronization device is used for a second processing module, wherein the second processing module includes a second timer, the count value of the second timer is used as the timing reference of the second processing module and increases in sequence, and the clock synchronization device includes: a second recording unit, configured to respond to receiving a trigger signal sent by the first processing module, record the current count value of the second timer as the second count value, wherein the second processing module and the first processing module are connected A processing module belongs to a different clock domain; wherein the second count value is used to combine with the first count value to perform clock compensation so that the first clock domain where the first processing module is located is synchronized with the second clock domain where the second processing module is located, and the first count value is the current count value of the first timer of the first processing module when the first processing module sends a trigger signal to the second processing module, and the count value of the first timer is used to make is the timing reference of the first processing module and is sequentially increased; wherein the first processing module includes a first phase-locked loop, the first phase-locked loop is configured to receive a first clock signal provided by a first clock source, and provide a first reference clock signal for the first processing module according to the first clock signal, the second processing module includes a second phase-locked loop, the second phase-locked loop is configured to receive the first clock signal provided by the first clock source, And according to the first clock signal, a second reference clock signal is provided to the second processing module. The first phase-locked loop is different from the second phase-locked loop, and responds to the first clock signal which is different from the first phase-locked loop and the second phase-locked loop but receives the same source. The clock compensation is performed when the first processing module is in the power-on stage, wherein the power-on stage refers to the first processing module just being powered on but before performing any specific operation. An electronic device includes a first processing module and a second processing module, wherein the first processing module includes a first timer, the count value of the first timer is used as the timing reference of the first processing module and increases sequentially, the second processing module includes a second timer, the count value of the second timer is used as the timing reference of the second processing module and increases sequentially, the first processing module and the second processing module belong to different clock domains, wherein the first processing module is configured to send a trigger signal to the second processing module, and record the current count value of the first timer when sending the trigger signal as the first count value, and the second processing module is configured to record the current count value of the second timer when receiving the trigger signal as the second count value; wherein the first count value and the second count value are used for clock compensation, so that the first processing module where the first processing module is located A first clock domain is synchronized with a second clock domain where a second processing module is located; wherein the first processing module includes a first phase-locked loop, the first phase-locked loop is configured to receive a first clock signal provided by a first clock source, and provide a first reference clock signal to the first processing module according to the first clock signal, and the second processing module includes a second phase-locked loop, the second phase-locked loop is configured to receive the first clock signal provided by the first clock source signal, and provides a second reference clock signal for the second processing module according to the first clock signal, the first phase-locked loop is different from the second phase-locked loop, responding to the first clock signal which is different from the first phase-locked loop and the second phase-locked loop but receives the same source, the clock compensation is performed when the first processing module is in the power-on stage, wherein the power-on stage refers to the first processing module just being powered on but before performing any specific operation. An electronic device, comprising: a memory, non-transitory storage of computer executable instructions; a processor, configured to execute the computer executable instructions, wherein, when the computer executable instructions are executed by the processor, the clock synchronization method as described in any one of claim items 1-13 or the system clock synchronization method as described in claim item 14 is implemented. A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the clock synchronization method described in any one of claim items 1-13 or the system clock synchronization method described in claim item 14 is implemented.

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