TWI873008B - Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof - Google Patents

Abstract

A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N x analog values corresponding to the N x levels of their drain current (I _D) or threshold voltage (V _T) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.

Description

Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and method of operating the same

The present invention relates to non-volatile memory devices, and more particularly to the use of multi-level silicon-oxide-nitride-oxide-silicon (SONOS) based charge trapping non-volatile memory (NVM) devices for analog operations including neuromorphic computing in artificial intelligence (AI) applications.

Cross-references to related applications

This application claims priority to and the benefit of U.S. Provisional Application No. 62/940,547, filed on November 26, 2019, pursuant to 35 U.S.C. §119(e), which is incorporated herein by reference in its entirety.

Non-volatile memory is widely used to store data in computer systems and typically includes a memory array having a large number of memory cells arranged in rows and columns. In some embodiments, each of the memory cells may include at least a non-volatile element (such as a charge trapping field effect transistor (FET), a floating gate transistor) that is programmed or erased by applying a voltage of appropriate polarity, magnitude, and duration between a control/memory gate and a substrate or drain/source region. For example, in an n-channel charge-trapping FET, a positive bias of the gate to the substrate causes electrons to tunnel from the channel via the Fowler Nordheim (FN) tunneling mechanism and be trapped in the charge-trapping dielectric layer, raising the critical voltage (V _T ) of the transistor. A negative bias of the gate to the substrate causes holes to tunnel from the channel and be trapped in the charge-trapping dielectric layer, lowering the V _T of the SONOS transistor.

In certain embodiments, a SONOS-based memory array is used and operates as a digital data storage device in which binary (0 and 1) data is stored based on two respective _VT or drain current ( _ID ) levels or values of the SONOS cells.

There is a demand for using NVM technologies, such as SONOS, for analog memory and processing because they have multiple _VT and _ID (more than two) levels that can be configured to achieve high accuracy. SONOS memory cells offer low latency, low power, and low noise operation, which is suitable for analog processing, including edge inference computing, such as neuromorphic computing in artificial intelligence (AI) applications.

Therefore, the object of the present invention is to provide optimized bias conditions, operation (erase, programming, inhibit, etc.) procedures, and SONOS-based analog NVM devices and systems to achieve tuning of multiple fine _VT / _ID levels with tight and widely distributed (low distribution standard deviation "σ").

According to an embodiment of the present invention, a method for operating a semiconductor device may include obtaining the semiconductor device, the semiconductor device including multi-stage memory transistors arranged in rows and columns, wherein the multi-stage memory transistors include charge trapping transistors based on silicon-oxide-nitride-oxide-silicon (SONOS), which are configured to store one of N analog values, the N analog values corresponding to N levels of drain current ( _ID ) and critical voltage ( _VT ), and wherein N is a natural number greater than 2; selecting at least one of the multi-stage memory transistors to perform a write procedure of a target value, wherein the target value is one of the N analog values and corresponds to a target _ID range, the target _ID range ranging from a target ID to a target ID. The invention relates to a method for controlling the memory transistors of the present invention to extend _a target _ID lower limit (LL) to a target upper limit (UL); performing a partial programming operation on at least one of the multi-level memory transistors to reduce an ID level, wherein a first verification read is performed after the partial programming operation to determine how the reduced _ID level is compared with a target _ID average value; performing a partial erasure operation on at least one of the multi-level memory transistors to increase the _ID level, wherein a second verification read is performed after the partial erasure operation to determine how the increased _ID level is compared with the target _ID average value; and determining that the writing process of the target value is completed when the _ID level of the at least one of the multi-level memory transistors falls within the target _ID range.

In one embodiment, the method may also include a step of inhibiting at least one of the multi-level memory transistors by further programming and erasing operations after the writing process of the target value is completed, wherein the inhibition includes reducing the magnitude of the gate-to-drain voltage or the gate-to-substrate voltage of the at least one of the multi-level memory transistors.

In one embodiment, the partial programming operation may include at least one of a soft programming operation and a refill programming operation, wherein the partial programming operation is configured to lower the _ID level of the at least one of the multi-stage memory transistors and increase the _VT level of the at least one of the multi-stage memory transistors, and wherein the multi-stage memory transistors that are not selected to perform the partial programming operation are inhibited.

In one embodiment, the partial programming operation is performed for a relatively short duration compared to the programming operation, wherein the programming operation is configured to reduce the _ID level of the multi-level memory transistor to a fully programmed _ID level regardless of the starting _ID level of the multi-level memory transistor.

In one embodiment, the partial erase operation may include a soft erase operation, a selective soft erase operation, and an anneal erase operation, wherein the partial erase operation is configured to increase the _ID level of the at least one of the multi-level memory transistors and decrease the _VT level of the at least one of the multi-level memory transistors, and wherein the multi-level memory transistors that are not selected to perform the selective soft erase operation are inhibited.

In one embodiment, the soft erase operation and the selective soft erase operation may be performed for a relatively short duration compared to an erase operation, wherein the erase operation is configured to increase the _ID level of the multi-level memory transistor to a fully erased _ID level regardless of the starting _ID level of the multi-level memory transistor.

In one embodiment, the annealing erase operation may be performed for a relatively long duration compared to the erase operation, and wherein during the erase operation, the magnitude of the gate-to-drain voltage bias of at least one of the multi-stage memory transistors is greater than that of the annealing erase operation.

In one embodiment, the method may further include a refill and anneal algorithm, including: after the write process of the target value is completed, performing the soft erase operation on the at least one of the multi-level memory transistors; verifying whether the _ID level reaches at least a target _ID +X% level, where X is in the range of 20-50; performing the refill programming operation on the at least one of the multi-level memory transistors; verifying whether the _ID level reaches at least a target _ID -Y% level, where Y is in the range of 10-20; performing the anneal erase operation on the at least one of the multi-level memory transistors; verifying the ID level of each of the at least one of the multi-level memory transistors. _D level; only selecting and executing the selective soft erase operation on the at least one of the multi-level memory transistors having an _ID level less than a target _ID lower limit and inhibiting unselected multi-level memory transistors; and verifying whether the _ID level of the at least one of the multi-level memory transistors is restored to the target _ID level range.

In one embodiment, the refill and annealing algorithm may be configured to maintain the _ID level of the at least one of the multi-stage memory transistors at the target ID level. In the _D level range, charges in shallow traps are replaced by charges in deep traps of the charge trapping layer of at least one of the multi-level memory transistors, wherein a high gate-to-drain voltage bias and a short programming pulse are applied to the at least one of the multi-level memory transistors, the refill programming operation promotes the deep trap charges, and wherein the annealing erase operation is configured to clear the shallow trap charges via Furnohan tunneling by applying a low gate-to-drain voltage bias and a long erase pulse to the at least one of the multi-level memory transistors.

In one embodiment, at least one of the multi-stage memory transistors may be arranged in the same column or the same row.

According to an embodiment of an operating method of a semiconductor device, the steps of the method may include selecting a first non-volatile memory (NVM) cell of a SONOS-based NVM array for performing a selective soft erase operation, wherein the SONOS-based NVM array includes NVM cells arranged in rows and columns, and wherein adjacent first and second rows of NVM cells are coupled to a first shared source line; generating and coupling a first negative voltage to a first SONOS word line in a first column of the SONOS-based NVM array and a positive voltage to a first bit line in the first row to apply a gate-to-drain voltage bias to a first NVM transistor in the first NVM cell to partially erase the first NVM cell by Furnohan tunneling, wherein a drain current (I The selective soft erase operation is performed by applying an inhibit voltage to a second bit line in the _second row to reduce the gate-to-drain voltage bias applied to a second _NVM transistor in a second NVM cell in the first column, the second transistor being not selected for the selective soft erase operation, wherein the inhibit voltage has the same polarity and a magnitude less than the first negative voltage, and wherein the second NVM transistor has approximately the same _ID and _VT levels before and after the selective soft erase operation.

In one embodiment, the method may include coupling a ground voltage to a second SONOS word line in a second column of the SONOS-based NVM array to deselect all NVM cells in the second column for a selective soft erase operation.

In one embodiment, the method may include generating and coupling the inhibit voltage to a first word line in the first column and a shallow positive well (SPW) node of the SONOS-based NVM array to turn off a first field effect transistor (FET) in the first NVM cell and a second FET in the second NVM cell; and coupling the positive voltage to a deep negative well (DNW) node.

In one embodiment, each of the NVM cells may include an NVM transistor configured to store one of N analog values, the N analog values corresponding to N _ID and _VT levels, where N is a natural number greater than 2, and wherein the selective soft erase operation is configured to increase the _ID level of the first NVM transistor and decrease the _VT level of the first NVM transistor so that the value stored in the first NVM transistor changes from a first value to a second value, and wherein the second value is greater than the first value.

In one embodiment, each of the N _ID and _VT levels may include a distribution in which two adjacent _ID or _VT distributions have an overlap frequency of less than 3%, and wherein the N _ID and _VT levels are linearly increasing and linearly decreasing, respectively.

According to one embodiment of a semiconductor device, the device may include a SONOS-based NVM array including NVM cells arranged in rows and columns, wherein each NVM cell includes a NVM transistor and a field effect transistor (FET), and wherein each NVM transistor is configured to store N analog values corresponding to N drain currents ( _ID ) or critical voltages (V _T) of each NVM transistor. ) level; a digital-to-analog converter (DAC) functional component that receives and converts a digital signal from an external device, wherein the converted digital signal is configured to store an analog value in at least one NVM cell in at least one row to be read; a row multiplexer (mux) functional component that is configured to select and combine the analog values read from the at least one NVM cell; and an analog-to-digital converter (ADC) functional component that is configured to convert the analog result of the row multiplexer functional component into a digital value and output the digital value.

In one embodiment, the N analog values may be written to the NVM transistors by a series of partial programming operations and selective partial erase operations, wherein the selective partial erase operation is configured to increase the _ID level of selected NVM transistors in the same row and decrease the _VT level of selected NVM transistors in the same row and simultaneously inhibit unselected NVM transistors in the same row.

In one embodiment, each of the partial programming operation and the selective partial erase operation may be followed by a read operation to verify whether the _ID level or _VT level of the selected NVM transistor reaches the target _ID level and _VT level.

In one embodiment, a plurality of the semiconductor devices may be placed on the same semiconductor die and AC-coupled to each other, each of the plurality of the semiconductor devices being configured to perform a multiply-accumulate (MAC) operation based on an analog value stored in the NVM cell and a digital input from at least one other semiconductor device of the plurality of the semiconductor devices.

In one embodiment, a first subset of the plurality of semiconductor devices outputs a digital result of the MAC operation, and wherein the digital result of the first subset is coupled to a second subset of the plurality of semiconductor devices as the digital input.

In one embodiment, the plurality of semiconductor devices may be configured to function as artificial neurons in a deep neural network (DNN) to perform neural-type computations in artificial intelligence (AI) applications.

86: Source/Source region

88: Drain/Drain area

90:NVM unit

91: Channel area

92: Charge trapping layer/nitride layer

93: Shallow positive well area (SPW)/substrate/p well area/well area

94:NV transistor

95: Channel

96: FET

97: Source region/internal node

98: Substrate

99: Deep Negative Well (DNW)

100:NVM array

200: NVM unit pair

300: 2×2 array

502: Overlapping region

710: Overlapping part

800: 2×2 array

900A:Writing operation/method/writing method

900B:Writing operation/method/writing method

902-916: Steps

918-930: Steps

1100: Write algorithm/method

1102-1120: Steps

1200: Refilling and annealing algorithm/refilling and annealing procedure/method

1202-1210: Steps

1300: Multi-level NVM device/analog NVM device

1302: Multi-level NVM array/analog NVM array

1304: Multiplexer functional components/multiplexer

1306: Analog-to-digital converter (ADC)/comparator

1310: Multi-level NVM unit

1320-1326: Digital-to-Analog Converter (DAC)

1402: System/MAC System

1504: Artificial Neuron

1600: Neural network acceleration system/NN acceleration system

1602a: Accelerator/multi-level NVM device

1602b: Multi-level NVM device

1602c: Multi-level NVM device

1604: High voltage drive

1606: Row multiplexer/row multiplexer functional components

1608:ADC

1610: Digital data flow control block

1612:DAC

1614: Low voltage driver

1616: High voltage driver

1712~1710: Steps

A more comprehensive understanding of the present invention will be obtained by referring to the detailed description of the attached drawings and the attached patent scope, wherein: [FIG. 1A] illustrates a block diagram of a cross-sectional side view of a SONOS-based non-volatile memory transistor or device; [FIG. 1B] illustrates a circuit diagram corresponding to the SONOS-based non-volatile memory transistor or device depicted in FIG. 1A; [FIG. 2] illustrates a circuit diagram according to the present invention. FIG. 3A is a schematic circuit diagram of a section of a SONOS-based non-volatile memory array according to the present invention, which illustrates an embodiment of an erase operation; FIG. 3B is a schematic circuit diagram of a section of a SONOS-based non-volatile memory array according to the present invention, which illustrates an embodiment of a program/inhibit operation; [FIG. 4] is a representative diagram according to an embodiment of the present invention, which illustrates the distribution of critical voltage and drain current of programmed (Vtp and Idp) and erased (Vte and Ide) memory transistors in a SONOS-based non-volatile memory array; [FIG. 5] is a representative diagram according to an embodiment of the present invention, which illustrates the distribution of drain current (ID) level in a multi-stage SONOS-based non-volatile memory cell; [FIG. 6] is a diagram illustrating the distribution of the ID level of each SONOS-based memory transistor in a non-volatile memory array according to an embodiment of the present invention. FIG. 7A is a diagram illustrating the distribution of captured charge in the charge trapping layer of a SONOS-based memory transistor in a non-volatile memory array according to an embodiment of the present invention; FIG. 7B is a diagram illustrating the distribution of ID of a SONOS-based memory transistor in a non-volatile memory array according to an embodiment of the present invention, showing ID standard deviation and retention (retention period) degradation; FIG. 8A is a schematic diagram of a section of a SONOS-based non-volatile memory array, illustrating the selective soft erase (soft erase) according to an embodiment of the present invention. [FIG. 8B] is a schematic diagram of a segment of a SONOS-based non-volatile memory array, illustrating a refill program/inhibit operation according to an embodiment of the present invention; [FIG. 9A] and [FIG. 9B] are schematic flow charts illustrating an embodiment of a write operation of a multi-stage SONOS-based NVM array according to the present invention; [FIG. 10] is a schematic diagram illustrating respective I/Os during a write operation of a SONOS-based memory transistor in a non-volatile memory array according to an embodiment of the present invention. [FIG. 11] is a _schematic flow chart illustrating an embodiment of a write operation of a multi-level SONOS-based NVM array according to an embodiment of the present invention; [FIG. 12] is a schematic flow chart illustrating an embodiment of a refill/anneal operation of a multi-level SONOS-based NVM array according to an embodiment of the present invention; [FIG. 13] is a representative block diagram of a multi-level SONOS-based NVM device according to the present invention; [FIG. 1 [Figure 4] is a representative block diagram illustrating an embodiment of a conventional digital multiply-accumulate (MAC) system; [Figure 15] is a representative diagram illustrating an embodiment of an artificial neuron in a deep neural network (DNN) system; [Figure 16] is a schematic diagram of an embodiment of an analog neural network (NN) accelerator device according to the present invention; and [Figure 17] is a simplified flow chart according to the present invention, which illustrates the operation method of the NN accelerator device in Figure 16.

In the following description, many specific details are described, such as specific systems, structures, methods, etc., to provide a good understanding of multiple embodiments of the subject matter of the present invention. However, it will be apparent to those skilled in the art that at least some embodiments can be practiced without these specific details. In other examples, known components or methods are not described in particular detail or presented in block diagrams to avoid unnecessary confusion of the main points of the present invention. Therefore, the specific details recorded in this specification are merely exemplary. Specific implementations may differ from these exemplary details and are still expected to be within the spirit and scope of the subject matter of the present invention.

Unless otherwise expressly stated herein, it will be apparent from the following discussion that throughout this specification, terms such as "processing", "computer computing", "calculating", "determining", etc., refer to the operation and/or process of a computer, computing system, or similar electronic computing device that manipulates and/or converts data represented as physical quantities (such as electronic quantities) in registers and/or memories within the computing system into data similarly represented as physical quantities in memories, registers, or other such similar information storage, transmission, or display devices of other data computing systems.

FIG. 1A is a block diagram illustrating a cross-sectional side view of a non-volatile memory cell, and its corresponding circuit diagram is shown in FIG. 1B. A non-volatile memory (NVM) array or device may include NVM cells having non-volatile memory transistors or devices implemented using silicon-oxide-nitride-oxide-silicon (SONOS) or floating gate technology and conventional field effect transistors (FETs) adjacent to or coupled to each other.

In one embodiment illustrated in FIG1A , the non-volatile memory transistor is a SONOS-style charge trapping non-volatile memory transistor. Referring to FIG1A , the NVM cell 90 includes a control gate (CG) or memory gate (MG) stacked NV transistor 94 formed on a substrate 98. The NVM cell 90 further includes a source region 97/drain region 88 formed in the substrate 98 on both sides of the NV transistor 94 or selectively in a shallow positive well (SPW) 93 in the substrate 98. The SPW 93 may be at least partially encapsulated in a deep negative well (DNW) 99. In one embodiment, the source region 97/drain region 88 is connected by a channel region 91 below the NV transistor 94. The NV transistor 94 includes an oxide tunneling dielectric layer, a nitride or oxynitride charge trapping layer 92, and an oxide top or blocking layer to form an ONO stack. In one embodiment, the charge trapping layer 92 can be a multi-layer stack and captures charges injected from the substrate 93 by the FN tunneling mechanism. Due at least in part to the amount of the trapped charge, the _VT and _ID values of the NV transistor 94 may change. In one embodiment, a high-K dielectric layer may form at least a portion of the blocking layer. A polysilicon (poly) or metal gate layer covering the ONO layer may be provided as a control gate (CG) or a memory gate (MG). As best shown in FIG. 1A , the NVM cell 90 further includes a FET 96 disposed adjacent to the NV transistor 94. In one embodiment, the FET 96 includes a metal or polysilicon select gate (SG) disposed overlying an oxide or high-K dielectric gate dielectric layer. The FET 96 further includes a source region 86 and a drain region 97 formed in a substrate 98 or selectively in a well region 93 of the substrate 98. As best shown in FIG1A , FET 96 and NV transistor 94 share a source/drain region 97 disposed therebetween, or referred to as internal node 97. SG is appropriately biased at _VSG to open or close the channel 95 beneath FET 96. The NVM cell 90 illustrated in FIG1A is considered a two-transistor (2T) architecture, wherein NV transistor 94 and FET 96 may be considered throughout this disclosure as a memory transistor and a select or pass transistor, respectively.

In one embodiment, FIG. 1B depicts a two-transistor (2T) SONOS NVM cell 90 having a non-volatile (NV) transistor in series with a FET 96. The NVM cell 90 is programmed (bit value “1”) when the CG is biased with VCG or when a positive pulse is applied to the CG relative to the substrate 98 or the well 93 so that electrons are injected from the inversion layer into the charge trapping layer 92 via a FN tunneling mechanism. The charge trapped in the charge trapping layer 92 creates electron depletion between the drain region 88 and the source region 97, raising the critical voltage (V _T ) required to turn on the SONOS-based NV transistor 94, placing the device in a “programmed” state. The NVM cell 90 is erased by applying an opposite bias _VCG to CG or by applying a negative pulse to CG with respect to the substrate 98 or the well 93 to cause holes to tunnel from the accumulated channel region 91 into the ONO stack via a FN tunneling mechanism. The critical voltages for programming and erasing are referred to as "Vtp" and "Vte", respectively. In one embodiment, the NV transistor 94 can also be in an inhibited state (bit value "0"), where by applying a positive voltage to the source and drain of the NVM cell 90 while the control gate (CG) is positively pulsed with respect to the substrate 98 or the well 93 (a programming condition), the previously erased cell (bit value "0") is inhibited from being programmed (bit value "1"). The critical voltage (referred to as "Vtpi") of the NV transistor 94 becomes slightly more positive due to disturbing vertical fields, but is still erased (or inhibited). In one embodiment, Vtpi is also determined by the ability of the charge trapping layer 92 of the ONO stack to retain trapped charge in the charge trapping layer 92. If the charge trapping is shallow, the trapped charge tends to be consumed and the Vtpi of the NV transistor 94 becomes more positive. In one embodiment, the Vtpi of the NV transistor 94 tends to weaken or climb with further inhibiting operations. It will be appreciated that the assignment of bit values or binary values "1" and "0" referred to herein to correspond to respective "programmed" or "erased" states of NVM cell 90 is for exemplary purposes only and is not intended to be limiting. The assignments may be reversed or have other arrangements in other embodiments. In other embodiments, as will be discussed below, NVM cell 90 may be configured to store multiple levels of analog values (other than "0" and "1") by manipulating its critical voltage levels or drain current levels.

In other embodiments, the NV transistor 94 may be a floating gate MOS field effect transistor (FGMOS) or a device. Generally speaking, the FGMOS is structurally similar to the SONOS-based NV transistor 94 mentioned above, with the main difference being that the FGMOS includes a polysilicon (poly) floating gate that can be capacitively coupled to the output of the device, rather than a nitride or oxynitride charge trapping layer 92. Therefore, the FGMOS device may be described with reference to FIGS. 1A and 1B and operated in a similar manner.

Similar to the SONOS-based NV transistor 94, the FGMOS device can be programmed by applying an appropriate bias V _CG between the control gate and the source and drain regions, raising the critical voltage (V _T ) necessary to turn on the FGMOS device. The FGMOS device can be erased by applying an opposite bias V _CG on the control gate.

In one embodiment, source/drain region 86 may be considered the "source" of NVM cell 90 and is coupled to VSL, while source/drain region 88 may be considered the "drain" and is coupled to VBL. Optionally, SPW 93 is coupled to V _SPW and DNW 99 is coupled to V _DNW .

FET 96 can avoid hot carrier electron injection and junction collapse during programming or erase operations. FET 96 can also avoid large currents flowing between source 86 and drain 88, which may cause high energy consumption and parasitic voltage drops in the memory array. Preferably, as shown in Figure 1A, FET 96 and NV transistor 94 can both be n-type or n-channel transistors, where source/drain regions 86, 88, 97 and DNW 99 are doped with n-type material, and SPW 93 and/or substrate 98 are doped with p-type material. It will be appreciated that the NVM cell 90 may also additionally or alternatively include a P-type or p-channel transistor, wherein the source/drain regions and the well region may be doped oppositely or differently, depending on implementation by one of ordinary skill in the art.

The memory array is formed by fabricating a grid of memory cells (such as NVM cells 90) arranged in rows and columns, and connecting the memory array to peripheral circuits (such as address decoders) and comparators (such as analog-to-digital converter (ADC) and digital-to-analog converter (DAC) functional components) via a plurality of horizontal and vertical control lines. Each memory cell includes at least one non-volatile semiconductor device (such as mentioned above) and may have a one transistor (1T) or two transistor (2T) architecture, as shown in FIG. 1A .

FIG. 2 is a schematic diagram of an NVM array according to one embodiment of the present invention. In the embodiment shown in FIG. 2 , the memory cell 90 has a 2T architecture and includes a pass transistor or a select transistor in addition to a non-volatile memory transistor, for example, a known MOSFET that shares a common substrate connection or internal node with the memory transistor. In one embodiment, the NVM array 100 includes NVM cells 90 configured into N columns or pages (horizontally) and M rows (vertically). NVM cells 90 in the same column can be considered to be in the same page. In some embodiments, several columns or pages can be grouped together to form a memory sector. It should be appreciated that the terms "columns" and "rows" in the memory array are used for illustrative purposes and not limiting. In one embodiment, the columns are configured horizontally and the rows are configured vertically. In other embodiments, the terms "columns" and "rows" in the memory array may be reversed or used in an opposite manner, or may be configured in any direction.

In one embodiment, the SONOS word line (WLS) is coupled to all CGs of the NVM cells 90 in the same column, and the word line (WL) is coupled to all SGs of the NVM cells 90 in the same column. In one embodiment, the bit line (BL) is coupled to all drain regions 88 of the NVM cells 90 in the same row, and the common source line (CSL) or region 86 is coupled or shared to all NVM cells in the array. In another embodiment, the CSL can be shared between two pairs of NVM cells in the same column (such as C1 and C2 as shown in Figure 3A). The CSL is also coupled to the shared source region of all NVM pairs in the same two rows.

In flash mode, a write operation can consist of performing a bulk erase operation on selected rows (pages) followed by programming or inhibiting operations on individual cells in the same row. The smallest block of NVM cells that can be erased at one time is a single page (row). The smallest block of cells that can be programmed/inhibited at one time can also be a single page.

2, NVM cells 90 may be configured in pairs, such as NVM cell pair 200. In a preferred embodiment as shown in FIGS. 3A, 3B, 8A, and 8B, NVM cell pair 200 includes two NVM cells 90 having a mirror image orientation such that the select transistors (such as C1 and C2) of each NVM cell are placed adjacent to each other. NVM cells 90 of the same NVM cell pair 200 may also share a common source region to receive a voltage signal VCSL.

FIG. 3A shows a 2×2 array 300 of the NVM array 100 to demonstrate an embodiment of an erase or hard erase (hard erase) operation according to the present invention. As previously described, the NVM array 100 may adopt a common source line (CSL) configuration. In one embodiment, a single CSL (e.g., CSL0) is shared among all NVM cells in the NVM array or at least between adjacent rows of NVM cells (e.g., C1 and C2). In one embodiment, the CSL may be set and shared between select transistors of adjacent rows of NVM cells. In the following description, for clarity and ease of explanation, it is assumed that all transistors in the 2×2 array 300 of the NVM array 100 are N-type transistors. It should be understood that, without loss of generality, a P-type configuration may be described by reversing the improvisation of the applied voltage, and such a configuration is within the scope of the intended embodiments of the present disclosure. In addition, the voltages and pulse durations used below are selected for ease of illustration and represent only one exemplary embodiment of the present invention. Different voltages may be applied in different embodiments.

FIG. 3A illustrates an exemplary embodiment of a section of an NVM array 100, which may be part of a larger memory array of memory cells. In FIG. 3A, a 2×2 memory array 300 includes at least four memory cells C1, C2, C3, and C4 arranged in two rows and two columns. While the NVM cells C1-C4 may be arranged in two adjacent rows (sharing a common source line CSL0), they may be arranged in two adjacent columns or two partially adjacent columns. Each of the NVM cells C1-C4 may be structurally similar to the NVM cell 90 described above.

Each of the NVM cells C1-C4 may include a SONOS-based memory transistor and a select transistor. Each of the memory transistors includes a drain coupled to a bit line (e.g., BL0 and BL1), a source coupled to the drain of the select transistor, and coupled to a single common source line (CSL0) through the select transistor. Each memory transistor further includes a control gate coupled to a SONOS word line (e.g., WLS0). Each of the select transistors includes a source coupled to the common source line (e.g., CSL0) and a select gate coupled to a word line (e.g., WL0).

3A, for example, for an erase operation, page 0 is selected to be erased and page 1 (unselected) is not. As previously described, a single page may be the smallest block of NVM cells 90 that may be erased in one operation. Therefore, all NVM cells including C1 and C2 in the selected row (page 0) are erased at once by applying appropriate voltages to the SONOS word line (WLS0) shared by all NVM cells, the substrate connection, and all bit lines in the NVM array 100. In one embodiment, a negative voltage _VNEG is applied to WLS0, and a positive voltage _VPOS is applied to the substrate or p-well region via the SPW and deep n-well region DNW in page 0, to all bit lines including BL0 and BL1, and a common source line including CSL. Therefore, a full erase voltage (V _NEG -V _POS ) is applied between the CG and substrate/P-well regions of the memory transistors in C1 and C2 for a pulse duration (Te ~ 10ms) to erase any previously trapped charge (if any) therein. In one embodiment, all word lines including WL0 and WL1 are coupled to the supply voltage V _PWR .

Still referring to FIG. 3A , when a page (row) is not selected (e.g., page 1) for the erase operation, a positive voltage V _POS is applied to WLS1, so that the CG of the memory transistors including C3 and C4 in page 1 is approximately 0V (V _POS -V _POS ) to the substrate/P-well region. Therefore, the state of the NVM cells of page 1 remains unchanged (not erased).

Table I describes exemplary bias voltages that may be used for a bulk erase operation of page/row 0 of a non-volatile memory having a 2T architecture and including memory cells having N-type SONOS transistors and CSLs, similar to the 2×2 array 300.

FIG3B shows an exemplary embodiment of a segment 2×2 array 300 of the NVM array 100 during a programming operation or hard programming operation. Referring to FIG3B , for example, NVM cell C1 is the target cell to be programmed or written to a logical “1” state (i.e., programmed to an “OFF” state), while NVM cell C2 shown in FIG3A , which may have been erased to a logical “0” state by a previous erase operation, remains in a logical “0” or “ON” state. It will be appreciated that C1 and C2, which are shown as two adjacent cells for illustration purposes, may also be two separate NVM cells on the same row (e.g., row 0). These two goals (programming C1 and inhibiting C2) are achieved by applying a first or positive high voltage (V _POS ) to WLS0 in page or column 0 of the NVM array 100, a second or negative high voltage (V _NEG ) is applied to BL0 to bias the memory transistors in C1 when programming the selected memory cell, and an inhibit voltage (V _INHIB ) is applied to BL1 and DNW to bias the memory transistors of C2 when inhibiting programming of the unselected memory cells, and a common voltage is applied to the shared substrate or P-well region SPW of all NVM cells and the word lines (WL1 and WL2) coupled to the second or negative high voltage (V _NEG ). In one embodiment, the common source line CSL0 between C1 and C2 or between all NVM cells 90 may be at a third high voltage or CSL voltage ( _VCSL ) or allowed to float. In one embodiment, the third high voltage _VCSL may have a voltage level or absolute value less than _VPOS or _VNEG . In one embodiment, _VCSL may be generated by its own dedicated circuit, which includes a DAC in the memory device. _VCSL may have a voltage level or absolute value approximately the same as the tolerance voltage _VMARG , which will be discussed in further detail below. When _VPOS is applied to the memory transistor of C2 via WLS0, the positive _VINHIB at BL1 is passed to its channel. This voltage reduces the gate to drain/channel voltage bias on the memory transistors of C2, reducing the programming field so that the shift from the critical voltage of Vte is small. The charge tunneling that still occurs is called suppression interference and is quantized as (Vte-Vtpi). In one embodiment, as a result of the programming operation, all NVM cells of page 0, which includes C1 and C2, can achieve a binary state of "1" (programmed-Vtp) or "0" (suppressed-Vtpi) depending on the bit line voltage received by the NVM cells. NVM cells in unselected pages (such as page 1) can remain in a binary state of "0" (erase-Vte).

Additionally, as described in detail below, a selected margin voltage (V _MARG ) having a voltage level or absolute magnitude less than V _NEG is applied to WLS1 in an unselected row or page (e.g., page 1) to reduce or substantially eliminate bit line disturbances of the programmed state in the unselected NVM cell C4 due to programming of the selected C1. In one embodiment, the absolute voltage level or magnitude of V _MARG may be the same as V _CSL .

Table II shows exemplary bias voltages that may be used to program a non-volatile memory having a 2T architecture and including memory cells having N-type SONOS transistors and CSLs.

Generally, the tolerance voltage (VMARG) has the same polarity as the second highest voltage or VENG, but is higher or more positive than VNEG by a voltage at least equal to the critical voltage (VT) of the memory transistor for which programming state bit line interference is reduced.

FIG4 shows the Vtp and Vte and the program drain current ( _IDP ) and erase drain current ( _IDE ) distributions in an exemplary SONOS-based NVM array, such as NVM array 100. A typical write operation includes an erase or hard erase operation as shown in FIG3A and followed by a hard program/inhibit operation as described in FIG3B. In one embodiment, after a reliable read operation, the NVM cell can be determined to be in one of the two different binary states ("0" or "1"). The erase operation as in FIG. 3A may also be considered a hard erase because it causes the _VT / _ID of the erased NVM cells (e.g., C1 and C2 in FIG. 3A) to move to the erase _VT / _ID level (fully erased), regardless of the starting _VT / _ID levels of these cells. Similarly, the program operation as in FIG. 3B may be considered a hard program operation. In one embodiment, there may be no verify or read operations between the hard erase and hard program/inhibit operations.

FIG. 5 is a schematic diagram showing a plurality of respective drain current ( _ID ) levels of NVM memory cells in a SONOS-based NVM analog device according to an embodiment of the present invention. In one embodiment, the _ID of the NVM cell may be determined or verified by applying a predetermined voltage to the CG of the SONOS transistor via WLS. In other embodiments, the _ID may be determined by other methods known and familiar in the art. Similar to _VT , the _ID may be used to determine the binary state of the NVM cell 90 in an embodiment in which the NVM array 100 may be used as a digital memory device, such as NOR flash memory, EEPROM, etc. In other embodiments, the NVM array 100 can be used as an analog device by storing one of a plurality of (more than two) analog values. Referring to Figures 4 and 5, instead of using hard programming and erase operations as described in Figures 3A and 3B to write one of the two binary values ("0" and "1") into the NVM cells 90 in the NVM array 100, a series of partial programming and partial erase operations are used to write multiple (more than two) _ID or _VT levels (corresponding to the replenished charges in the charge trapping layer 92) into the NVM cells 90. In an embodiment, by manipulating the voltage difference or bias applied to the CG and the drain or substrate and the pulse duration, the partial program and partial erase operations may cause (or guide) the _VT / _ID of the target NVM cell to move toward a programmed _VT / _ID level and an erased _VT / _ID level, respectively. The partial program and partial erase operations may include but are not limited to a soft program operation, a refill programming operation, a soft erase (row) operation, a selective soft erase (cell) operation, and an anneal erase (row) operation, which will be further described below.

In one embodiment, the preferred embodiment is shown in FIG. 5 , in the analog configuration/mode, the NVM cell 90 can be configured to present or store one of 2 ⁿ (4, 8, 16 ... 128, etc.) values according to its _ID level, where n is a natural number greater than 1. In another embodiment, the NVM cell 90 can be configured to present one of any number of values greater than two. In one embodiment, _ID 1 to _ID 2 ⁿ are the average _ID value of the 1st _ID distribution to the average _ID value of the 2nth _ID distribution, respectively. In each _ID distribution, there is a minimum _ID limit and a maximum _ID limit (see _ID 1). The 1st _ID distribution may be similar to the stylized unit distribution σ3 in FIG. 4 and the ^2nth _ID distribution may be similar to the unit distribution σ4 in FIG. 4 (see FIG. 4 ). In an embodiment, the average _ID level or average _VT level and their upper and lower limits may be predetermined according to system design and requirements. In one embodiment, the operable _ID range of the NVM array 100 may be approximately ( _ID2n - ^ID1 ), and for example, (1.60μA-50nA=1,550nA). It should be understood that the operable _ID range of 1,550nA is only _an example and may be any other value according to the NVM cell, operating _voltage and pulse duration, and system requirements/design. In one embodiment, by writing a specific _ID level in the operable _ID range into the NVM cell 90, such as 1.60μA to 50nA, the NVM array 100 may be used as an analog memory device. In one embodiment, one skilled in the art will appreciate that the same concept can also be applied to writing multiple (more than two) _VT levels into NVM cell 90.

In one embodiment, to achieve multiple separated _ID levels within a small operable _ID range, each _ID distribution may be required to have a tight distribution (low standard deviation (sigma) σ) so that adjacent _ID distributions are clearly separated, especially when n is high. For accurate and efficient read/verify operations, the different levels of _ID may also be linearly increasing so that _ΔID is approximately constant, as shown in FIG5. SONOS-based cells, such as NVM cell 90, are suitable candidates for analog memory with multiple levels due to their intrinsically low _ID / _VT standard deviation and low power consumption ( _VCC = 0.81V-1.21V). Furthermore, since both programming and erase operations (both hard and soft) in SONOS-based cells are achieved using FN tunneling mechanisms, tunneling of very small _ID / _VT levels with very low standard deviations is possible. Furthermore, SONOS-based cells have high endurance with minimal degradation over a temperature range of -40°C to 125°C, which can meet the requirements of most consumer, industrial, and automotive applications. In one embodiment, there may be an overlap region 502 of _ID values between adjacent _ID distributions. In order to reliably and accurately read the _ID level of NVM cell 90, the _ID distribution standard deviation σ may be reduced to less than about 8 nA or other current value so that the overlap area 502 is kept below 1% to 3% of the distribution. Depending on the spacing between the _ID levels, the standard deviation may be higher or lower. In some cases, a standard deviation of 50 nA is sufficient to keep the overlap area below 1% to 3% of the distribution.

FIG6 is a graph illustrating 16 (2 ⁴ ) _ID levels of an NVM cell according to one embodiment of the present invention. Preferably, as shown in FIG6 , the _ID levels are separated, well separated (low standard deviation), and increase linearly to maintain high functionality of the multi-stage NVM cell as an analog device.

As previously described, known writing processes (such as hard erase and hard program processes) may not be accurate enough to write a specific _ID / _VT level among multiple (more than two) levels into an NVM cell. In one embodiment, a series of hard program operations, hard erase operations, partial program operations, and partial erase operations may be required to write the exact _ID / _VT level into an NVM cell (such as NVM cell 90).

FIG7A is a diagram illustrating the distribution of trap density from the covalent band to the conduction band in the charge-trapping nitride layer of a SONOS transistor according to the present invention. FIG7B is a diagram illustrating the potential effects of _ID distribution in a multi-level NVM cell due to _ID and retention period degradation. While the Beginning-of-Life (BOL) standard deviation of a SONOS transistor 94 may be very low, severe degradation may occur during retention, especially under high temperature conditions. Thus, as shown in FIG. 7B , the _ID distributions (e.g., _ID 1 and _ID 2) may become wider (with increased standard deviation) and adjacent _ID distributions may have more overlap 710 (e.g., greater than 3%), which may result in incorrect/wrong readings of levels or values. In one embodiment, the standard deviation degradation may be due to the fact that the charges trapped in the “shallow” traps in the nitride layer 92 are lost during retention, while the charges trapped in the “deep” traps remain trapped. The loss of the trapped charges during retention may also cause the _ID levels to shift upward, such as _ID 8 and _ID 8′ in FIG. 7B . While the Beginning-of-Life (BOL) standard deviation of the SONOS transistor 94 may be very low, severe degradation may occur during retention, especially under high temperature conditions. Referring to FIG. 7A , according to a learned write algorithm that uses only hard erase operations and hard program operations (such as in NOR flash memory or EEPROM), the charge tends to be trapped in both shallow traps and deep traps. In one embodiment, when a write algorithm using a series of partial erase/program operations (such as soft erase, soft program, selective soft erase, anneal erase, and refill program operations) is used, more charge is trapped in the deep traps to guide the _ID / _VT of the NVM cell to the respective target values, as shown in FIGS. 9A, 9B, 11, and 12, and may help to redistribute the charge from the shallow traps to the deep traps. In one embodiment, the partial erase operation and the partial program operation may empty the charge from the shallow traps and fill the charge into the deep traps. As a result, when the target _ID / _VT is maintained at the same level, the standard deviation degradation of both the _ID / _VT of the NVM cell and the retention period of the NVM cell may be improved.

The retention period and _ID / _VT standard deviation degradation may also be improved by changes in the manufacturing process, so that the density of shallow traps in the charge trapping layer is reduced. In one embodiment, the manufacturing process improvement may include smoothing the shallow trench isolation (STI) corners in the SONOS transistor, optimizing the doping profile in the channel, improving the oxide layer, etc.

Soft erase operation:

In one embodiment, the operating voltages coupled to the nodes for soft erase are similar to those in the hard erase operation described above in FIG. 3A. Therefore, the full erase voltage bias of 8V (V _NEG -V _POS ) is still applied between the CG and the substrate/drain. Unlike the hard erase operation, the duration of the WLS pulses (e.g., WLS0, WLS1) of the soft erase pulses is significantly shorter (Tes~20μs), compared to Te~10ms of the hard erase operation. Although the CG to drain voltage bias is the same (e.g., -8V), the soft erase pulse may only increase (e.g., from L4 to L2 in FIG. 10 ) but will not move the _ID of the NVM cells in the selected row 0 (e.g., C1, C2) to the erase _ID level. In one embodiment, the soft erase operation may only be performed on the entire selected row.

Annealing erase operation:

A general purpose of an anneal erase operation is to release the charge trapped in shallow traps to improve post-retention performance. Table III records exemplary bias voltages that may be used for an anneal erase operation of page/row 0 of a non-volatile memory having a 2T-architecture and including memory cells having N-type SONOS transistors and CSLs (such as the 2×2 array 300 shown in FIG. 3A ).

In one embodiment, unlike the erase operation and the soft erase operation, a soft erase voltage bias (V _NEG -V _AEPOS ) is applied between the CG and the substrate/drain as V _AEPOS , which may have a smaller value compared to V _POS . However, the soft or lower erase voltage (e.g., 6V versus 8V) is applied to the CG for a longer pulse duration, Tae ~ 50ms. In one embodiment, the soft erase pulse with a longer pulse duration may help remove charges in shallow traps, which are closer to the conduction band. In one embodiment, the anneal erase operation may be performed only on the entire selected row.

Selective Soft Erase:

FIG. 8A illustrates a 2×2 array 800 of the NVM array 100 to demonstrate an embodiment of a selective soft erase operation according to the present invention. In one embodiment, the 2×2 array 800 is similar to the 2×2 array 300 as shown in FIGS. 3A and 3B . Hereinafter, for clarity and ease of description, it is assumed that all transistors in the 2×2 array 800 are N-type transistors. It should be understood that, without loss of generality, a P-type configuration may be described by reversing the polarity of the applied voltage, and such a configuration is within the scope of the intended embodiments described herein. Furthermore, the voltages used in the following description are selected for ease of description and represent only one exemplary embodiment of the subject matter of the present invention. Other voltages may be used in different embodiments.

8A, a 2×2 memory array 800 includes at least four memory cells C1, C2, C3, and C4 arranged in two rows and two columns. Although the NVM cells C1-C4 may be placed in two adjacent rows (common source line CSL0), they may be placed in two adjacent columns or in two non-adjacent columns. Each of the NVM cells C1-C4 may be similar in structure to the NVM cell 90 described above. Referring to FIGS. 3A, 3B, and 5, a hard erase operation as depicted in FIG. 3A may raise the _ID of the erased NVM cell to an erase _ID level as shown in FIG. 5, and a hard program operation similarly to a program _ID level as shown in FIG. 5. In one embodiment, the erase _ID level and the program _ID level may be distributed beyond the operating range of _ID 1 to _ID 2n of the NVM array 100. In other embodiments, one of the erase _ID level and the program _ID level may fall within the operating range.

8A, for example, page 0 is selected for partial erase/inhibit and page 1 is not (not selected) for a selective soft erase (SSE)/inhibit operation. Different from the previously described embodiments of the hard, soft, and anneal erase operations, where a single page or row is the minimum erase block of NVM cells 90, a single NVM cell/bit or multiple NVM cells/bits in the same row (e.g., page 0) may be selected for a selective soft erase operation. Alternatively, the unselected NVM cells (e.g., C2) may be inhibited. Thus, by applying appropriate voltages to the SONOS word line (WLS0) shared with all NVMs in row 0, the substrate connections, and to all bit lines in the NVM array 100, only the selected NVM cell(s) including C1 in the selected row (page 0) have their _ID levels increased (partially erased). In one embodiment, a selective soft erase (SSE) negative voltage _VSSENEG is applied to WLS0, and a SSE positive voltage _VSSEPOS is applied to BL0 and DNW of all NVM cells in page 0. In one embodiment, _VSSENEG has a smaller absolute magnitude than _VNEG used in the hard erase operation in FIG. 3A, and _VSSEPOS has a larger absolute magnitude than _VPOS in FIG. 3A. _VEINHIB is applied to WL0, SPW, BL1, and WL1 to inhibit soft erase operations of unselected NVM cells (such as C2) to prevent their _ID from being increased. CLS0 and WLS1 are coupled to ground or 0V. In one embodiment, the SG of all NVM cells C1 to C4 are at least partially turned off (WL=-1.4V), which are normally turned on for hard erase operations.

In one embodiment, despite the smaller absolute magnitude of V _SSENEG , a relatively fully erased voltage bias is applied only between the CG and BL0 of the memory transistor in C1 (V _SSENEG -V _SSEPOS = -7.2V). The voltage difference between the CG and BL1 in the unselected C2 is only (V _SSENEG -V _EINHIB = -0.9V). Therefore, only the _ID of the selected C1 may increase, but the _ID of the unselected C2 in the same selected column 0 will not increase. In one embodiment, the pulse duration of the selected erase operation coupled to WLS0 (Tsse ~ 20μs) is shorter than the duration in the hard erase operation (Te ~ 10ms). The shorter SSE pulse may not have enough time to erase all the charge previously trapped in NVM cell C1 (if any). In one embodiment, all word lines including WL0 and WL1 and SPW are coupled to _VEINHIB so that the unselected NVM cells C2, C3, and C4 may not be partially erased like NVM cell C1. In one embodiment, the general concept of the selected erase operation is to apply a relatively high erase voltage bias (e.g., 7.2V) for a short time period (20μs) to reduce the trapped charge only in the selected NVM cells of the same column. In one embodiment, Tae>Te>Tsse and Tse. In one embodiment, more than one NVM cell in the same row (adjacent or non-adjacent) may be selected to perform SSE operations, while more than one NVM cell in the same row may be inhibited so that their _ID levels remain relatively unchanged.

Table IV records exemplary bias voltages that may be used for a selective soft erase operation of page/column 0 and row 0 (only C1) of a non-volatile memory having a 2T-architecture and including memory cells having N-type SONOS transistors and CSLs, similar to the 2×2 array 800.

Soft programmed operation:

In one embodiment, the operating voltages coupled to the various nodes for soft programming (SP)/inhibit operation are similar to the hard programming/inhibit operation as described above in FIG. 3B, except that the voltage coupled to the selected WLS (e.g., WLS0) is reduced. In one embodiment, V _SPPOS has a smaller value than V _POS in the hard programming operation so that the programming voltage applied to the CG of the selected C1 can be reduced. Therefore, a soft programming voltage bias of 6V (V _NEG -V _SPPOS ) is applied between the CG and the BL/substrate/P-well region. Unlike the hard programming operation, the WLS pulse duration (Tsp~10μs) of the soft programming pulse is significantly shorter than the duration Tp~5ms of the hard programming operation. With a smaller CG to drain voltage difference (e.g., 6V vs. 8V) and a shorter soft programming pulse time (10μs vs. 5ms), the soft programming operation may only reduce but not move the _ID of the selected NVM cell C1 to the programmed _ID level (e.g., from L3 to L2 in FIG. 10 ). In one embodiment, unselected NVM cells, such as C2 on the same column and unselected columns, such as C3 and C4, may be inhibited.

Refilling programmed operation:

FIG8B illustrates an exemplary embodiment of a segment 2×2 array 800 of the NVM array 100 during a refill programming (RP)/inhibit operation. Referring to FIG8B , for example, NVM cell C1 is the target cell to be partially programmed (to reduce or move the _ID level toward the programmed _ID shown in FIG5 ), while NVM cell C2 is inhibited. It will be appreciated that while C1 and C2 are illustrated as two adjacent cells for purposes of illustration, C1 and C2 may also be two separate cells on the same row (e.g., row 0). Typically the purpose of a refill programming operation is to fill charge in deep traps (see FIG7A ), using a high programming voltage bias to improve the post retention performance. Table V records exemplary bias voltages that may be used for a refill programming operation of page/row 0 of a non-volatile memory having a 2T-architecture and including memory cells having N-type SONOS transistors and CSLs, similar to the 2×2 array 800 shown in FIG. 8B .

In one embodiment, unlike the soft programming operation, a harder programming voltage bias (V _RPPOS -V _RPNEG ) is applied between the CG and substrate/drain as V _RPPOS , which may have a value equal to or higher than V _POS , and V _RPNEG may have a value equal to or higher than V _NEG . Thus, the resulting programming voltage bias applied to the CG of the selected C1 is equal to but slightly higher than the voltage bias in the hard programming operation as described in FIG. 3B (e.g., 9V versus 8V). However, the harder programming pulse is only applied to the selected CG(s) for a very short duration of Trp ~ 5μs. The brief refill programming pulse may reduce the _ID of C1 but not fully program it. In one embodiment, Tp>Tsp>Trp. The hard programming pulse of the refill programming operation may help fill the charge into deep traps, which have energy levels between the covalent band and the conduction band as shown in FIG. 7A. In one embodiment, similar to the hard programming and soft programming operations, the unselected NVM cells C2, C3, C4, ..., etc. may be suppressed. In one embodiment, the refill programming operation may be performed before or after the anneal erase operation. The refill programming operation may restore the _ID of the selected NVM cell by refilling the charge in the deep traps after the charge was emptied from the shallow traps during the previous anneal erase operation.

Table V describes exemplary bias voltages that may be used to refill an NVM cell C1 programmed in a non-volatile memory having a 2T-architecture and including a memory cell having an N-type SONOS transistor and a CSL.

It should be understood that the voltages and voltage ranges used in the hard erase, hard program, partial erase and partial program operations described above are examples selected for erase and represent only exemplary embodiments of the present invention and should not be considered limiting. Other voltages may also be used in different embodiments without losing the generality of the present invention.

9A and 9B are representative flow charts illustrating methods of writing operations 900A and 900B of a multi-level NVM cell according to an embodiment of the present invention. FIG. 10 is a representative diagram illustrating multiple _ID or _VT levels of NVM cells in an analog NVM array according to an embodiment of the present invention. As described above, the writing methods 900A and 900B can be applied to adjust multiple _VT and _ID levels of NVM cells. It should be understood that for the purpose of clarity and simplicity, the methods 900A and 900B are described below only from the perspective of _ID . 9A and 9B , the main purpose of the write operations 900A and 900B is to accurately write the desired or predetermined _ID or _VT level (or target value) to one or more selected cells or bits, such as the SONOS-based NVM cell 90 in the NVM array 100 or the analog NVM array 1302 in FIG. 13 , through a series of partial programming operations, partial erase operations, and verification operations. In one embodiment, the written _ID may have to fall within a relatively narrow _ID distribution range (low standard deviation) to maintain the functionality of the analog memory with multiple _ID levels. Referring to FIG. 9A and FIG. 13 , the method 900A begins at a wake-up phase. In one embodiment, in step 902, a hard programming operation similar to the embodiment described in FIG. 3B may be performed throughout the analog NVM array 1302 to reduce leakage current in unselected NVM cells. It should be appreciated that a single or multiple rows and columns of NVM cells may be selected to perform write operations 900A and 900B. For example, NVM cells in row A, row X and row A, row Y in the multi-level NVM array 1302 of FIG. 13 are selected for write operations to achieve a target _ID2 level, as shown in FIG. 10. Subsequently, a series of hard erase operations (FIG. 3A) and hard program operations (FIG. 3B) may be performed in the selected row A in steps 904 and 906, respectively. In one embodiment, the _IDs of the NVM cells in row A may be first moved to the erased _ID level and then to the programmed _ID level, as shown in FIG. 10. Steps 904 and 906 may be repeated X times, for example 5 times (in step 908), and the wake-up phase may prepare the selected row A for the upcoming operation. After the wake-up phase, the NVM cells in the selected row A may be at the fully programmed _ID level (L1). In one embodiment, there may not be any authentication or read operations during the wake-up phase.

9A and 10, in step 910, a soft erase operation is performed on selected bits on row A, so that the _ID of these NVM cells is raised from level L1 to the erased _ID level. Subsequently, unlike the write operation of binary NVM cells, a verification operation similar to a conventional read operation can be performed after each partial programming operation or partial erase operation to check the _ID level of the selected bits. In step 912, a verification step is performed on selected bits in row X and row Y to check how much the soft erase operation in step 910 raises the _ID level of these bits respectively. If the _ID of the bits in both row X and row Y is greater than the lower limit of the target _ID (i.e., _ID 2LL), the method may proceed to a fine tuning phase, which is described in detail in FIG. 9B. In step 914, if the _ID of the bits in both is determined to be less than _ID 2LL, the method 900A may return to step 910 to perform additional soft erase operations to further boost or increase the _ID of the bits in both row X and row Y. In step 916, if only one of the _IDs of the selected bits in both row X and row Y is determined to be below _ID 2LL, a soft programming operation may be performed on the bit above _ID 2LL (lowering its _ID ), while the bit below _ID 2LL is inhibited so that the two selected bits are at the same _ID level. The method 900A may then return to step 910 to perform other soft erase operations to further advance the _IDs of the bits in both row X and row Y toward the target _ID level. In one embodiment, step 912, step 914, and step 916 may be repeatedly performed many times until the _ID levels of all selected bits (e.g., bits at row A, row X, and bits at row A, row Y) are raised to a lower limit greater than the target _ID level, such as the L2 level or the L3 level in FIG. 10 , by the soft erase operation in step 910 and the subsequent verification in step 912. In one embodiment, the above steps may be performed for all bits on the selected row A.

9B , the write method 900B performs the fine tuning phase, wherein a series of soft programming operations and selective soft erase operations are performed on one or more selected bits after each verification operation to guide the _ID of each of these bits toward a target _ID level (e.g., _ID 2). In one embodiment, a verification operation or a read operation may be performed on all bits to determine whether the _ID of any bit exceeds the target _ID upper limit (e.g., _ID 2UL in FIG. 10 ). If both of the selected bits (e.g., row X and row Y) are determined to be below _ID 2UL, the fine tuning phase proceeds to step 922. In step 920, if the _ID of any selected bits is determined to be greater than _ID 2UL (e.g., L3 level), a soft programming operation (FIG. 8B) will be performed on these bits to slightly reduce the _ID of these bits back to within the _ID 2 distribution limit. Other selected bits may be suppressed. In one embodiment, steps 918 and 920 may be repeated multiple times until all selected bits are determined to have an _ID level below _ID 2UL.

In a verification step 922, all selected bits (e.g., row X and row Y) are read to determine if any of the bits have their _ID shifted below _ID 2LL (e.g., L4 level) due to the previous soft programming/inhibit operation in step 920. If all selected bits are determined to be greater than _ID 2LL, the trimming phase may proceed to step 926. If any selected bits are determined to be shifted below _ID 2LL, a selective soft erase operation ( FIG. 8A ) may be performed only on those bits to steer the _ID of those bits toward _{the ID} 2 distribution. As discussed above, unlike a hard or soft erase operation that may be performed on all bits in a column, a selective soft erase operation may be performed only on a single bit or multiple bits in a selected column. In one embodiment, the selected bits that are not subjected to the selective erase operation may be suppressed (the _ID is not substantially changed). Steps 922 and 924 may be repeated a number of times until the _IDs of all selected bits are directed to exceed _ID 2LL.

In a verification step 926, all selected bits (e.g., row X and row Y) are read to determine if any bit's _ID has shifted by more than _ID 2UL (overcalibrated) due to the selective soft erase/inhibit operation previously performed in step 924. If any selected bits are determined to have shifted by more than _ID 2UL, a soft programming operation (FIG. 8B) may be performed only on those bits to guide the _ID of those bits back into the _ID 2 distribution range. In one embodiment, the selected bits that were not subjected to the soft programming operation may be inhibited.

In one embodiment, in the verification step 926, if all selected bits are determined to be below _ID 2UL, the fine tuning phase can terminate at step 930. All selected bits (e.g., row A, row X and row A, row Y) are determined to have the target _ID , which is above _ID 2LL and below _ID 2UL. The write methods 900A and 900B can be performed on other rows, such as row B, with the same or different target _ID levels. In one embodiment, the write operation can be repeated until the entire analog NVM array 1302 is programmed to the target _ID level.

In other embodiments, the fine tuning phase may loop back to step 922 to check if any selected bits were overcorrected by the soft programming operation in step 928. Depending on system requirements, steps 922 (verify), 924 (SE), and 926 (verify), 928 (SP) may be configured to be repeated a number of times before the fine tuning phase proceeds to write end step 930. The repeated verification may be advantageous in certain embodiments, particularly in multi-level NVM arrays with a high number of _ID levels (closely spaced adjacent target _ID levels).

FIG. 11 is a schematic flow chart illustrating another embodiment of a write algorithm according to the present invention. In one embodiment, the write algorithm 1100 may be applied to write two bits in the same row (e.g., row A, row X and row A, row Y in FIG. 13 ) to achieve two different target _IDs (e.g., row X1 ₂ , row Y1 ₀ ). Referring to FIG. 11 , in step 1104 (wake-up phase), the method 1100 begins and multiple cycles of hard program and erase operations or strong program and erase operations ( FIGS. 3A and 3B ) may be performed on the bits in row X, row Y. Then, in step 1106, a hard erase operation may be performed on the bits of row X and row Y so that their _ID level reaches I _1. In another embodiment, the hard erase operation may push the bits of row X and row Y beyond I ₁ to reach the erased _ID level. Then, by comparing the bits of row X to the I ₂ average, partial programming operations such as soft programming (in step 1108) and verification or reading (in step 1109) may be repeated many times until at least the bits of row X reach I _2. Then, in step 1110, the bits of row X may be inhibited from undergoing programming or erase operations because the bits of row X have reached their target I ₂ . Then, in step 1112, a selective erase operation may be performed on the uninhibited bits (i.e., the bits of row Y) to push their _ID to I ₃ . In one embodiment, row Y may require multiple selective erase operations to reach I ₃ . Then, partial programming operations such as soft programming (in step 1114) and verification or reading (in step 1116) may be repeated multiple times until the bits of row Y reach their target level I ₀ . In step 1118, once the bits of row Y are determined to have reached their target I ₀ , the bits of row Y, similar to the bits of row X, may be inhibited from additional programming/erase operations by comparing the bits of row Y to the I ₀ average. In one embodiment, as shown in the present embodiment, I ₂ <I ₀ <I ₃ <I ₁ . To determine whether a bit has reached its target ID level, the bit can be compared to the average level of the target _ID . In another embodiment, the lower and upper bound algorithm described in detail in FIG. 9A including FIG. 9B can be used, such as step 920, step 924 and step 926. In another embodiment, the write algorithm can use the same steps to write other bits in the selected row or other rows.

The write algorithm in FIG. 11 illustrates the basic concept of writing analog values to an NVM array, such as the multi-level NVM array 1302. In yet another embodiment, more than one bit may be written to the targets I ₂ and I ₀ because a soft program operation and a selective soft erase operation may be selectively performed on one or more bits in the same row. In yet another embodiment, instead of using a soft program operation (in steps 1106 and 1114) to steer or trim bits to individual target _IDs of bits, a selective soft erase operation may be employed in addition or in lieu thereof. The example in Figure 11 starts with the erase _ID level (after step 1106), but can also start with the programmed _ID level (pushing all bits to I ₂ or to the programmed _ID level) when a hard programming operation is performed instead in step 1106.

As described above, SONOS-based cells such as NVM cell 90 are suitable for use in multi-level analog memory devices due to their high endurance of 1K cycles and low power consumption. SONOS-based NVM arrays may also have the advantage of low random telegraph noise (RTN) of less than 3nA. In one embodiment, the retention period specification of multi-level NVM devices may be more stringent than the retention period specification of binary NVM devices (such as NOR flash memory, EEPROM, etc.) because the spacing of more than two adjacent _VT / _ID levels representing more than two analog values is close. Importantly, data retention performance and _VT / _ID standard deviation degradation may need to be improved to avoid read errors or read failures for multiple levels in multi-level NVM cells. One of the major contributing factors that adversely affect retention and _VT / _ID standard deviation is the loss of charge (such as electrons and holes) from shallow traps in the charge trapping layer 92 of the SONOS transistor 94 (preferably shown in Figures 1, 7A, and 7B) during retention.

FIG. 12 is a representative flow chart illustrating a method of a refill and anneal algorithm according to an embodiment of the present invention. Referring to FIG. 9B , writing the analog value to the target multi-level NVM cell may be considered completed at step 930. In an embodiment, the refill and anneal algorithm 1200 may be performed on one or more than one bit or an entire column of programmed bits. Using the same example as shown in FIG. 9A and FIG. 9B , in step 930, the bit in column A, row X and the bit in column A, row Y may be written and stored with the target _ID2 value. In one embodiment, in order to improve the retention period performance and minimize the V _T / _ID standard deviation degradation, it may be beneficial to replace the shallow trapped charge with the deep trapped charge (holes or electrons). In one embodiment, the refill and anneal process 1200 may be performed on bits that have been programmed to their target _ID level. In step 1202, the method 1200 begins by performing a soft erase operation on selected bits (e.g., row A, row X, and row A row Y) to increase their _ID values to an average + X% level of the target _ID (e.g., _ID 2 + 20% to 50%). This is followed by a verification step to ensure that the selected bits are at or above an average + 20% to 50% level of the target _ID . In one embodiment, the soft erase operation may empty charges primarily in shallow traps to increase the _ID value. Subsequently, in step 1206, a refill programming operation as described above and preferably shown in FIG. 8B may be performed on the selected bits to reduce the ID value of the bits to a level of -Y% of the target ID average value ( _ID 2-10% to 20%). This is followed by a verification step to ensure that the selected bits are at or below the target _ID average value -10% to 20%. In one embodiment, the short and strong refill programming pulse (e.g., 9V CG to drain) may utilize charge stored primarily in deep traps to refill some of the charge removed in the previous soft erase operation in step 1202. Step 1202 and step 1206 may be repeated multiple times to enhance the replacement of charge in the shallow traps with charge in the deep traps. It will be appreciated that _ID 2-10% to 20% and _ID 2+20% to 50% are examples for illustrative purposes. Other offset percentages may be applicable as long as they swing the _ID value of the selected bit from one side of its target _ID average value to the other.

The method 1200 may then proceed to perform an anneal erase operation as described above on the selected bits in step 1208. In one embodiment, the anneal erase operation may empty the charge mainly in the shallow traps to increase the _ID value from the _ID 2-10% level as a result of step 1206. As described above, the soft (6V CG to drain) and long (~50ms) anneal erase pulse may further allow sufficient time to empty the main charge in the shallow traps. A verification step may then follow to ensure that at least one or more of the selected bits are at or below the target _ID floor level (e.g., _ID 2LL). Then, in step 1210, the method 1200 may continue to perform a selective soft erase operation on bits below _ID 2LL. Bits having _ID values greater than _ID 2LL may be suppressed due to the previous anneal erase operation (in step 1208). A verification operation may be performed to ensure that all bits are partially erased to achieve an ID level greater than _ID 2LL. At the end of step 1210, all selected bits (e.g., column A, row X and column A, row Y) may be restored to the target _ID level (e.g., _ID 2) with most of the charge in deep traps due to the series of refill programming and anneal erase operations.

In yet another embodiment, step 1202 (soft erase operation) and step 1206 (refill programming operation) in the refill and annealing process 1200 may be performed additionally or alternatively after step 918 in the write algorithm 900B in FIG. 9B .

FIG. 13 is a simplified block diagram illustrating an embodiment of a multi-level or analog NVM device 1300 according to the subject matter of the present invention. In one embodiment, the analog NVM array 1302 may be similar to the NVM array 100 of FIG. 2 , where the multi-level NVM cells 1310 are arranged in N columns and M rows. Each multi-level NVM cell 1310 may have a 2T architecture (SONOS transistors and FET transistors) and share CSLs with neighboring cells in the same column. In one embodiment, other connections, such as WLS, WL, BL, SPW, DNW, etc., may also be arranged similarly to the NVM array 100 of FIG. 1A , FIG. 1B , and FIG. 2 . The multi-level NVM cells 1310 may also be configured to have more than two different _ID / _VT levels (see FIG. 10), such as 2 ⁴ =16 or 0 to 15 levels. In one embodiment, each analog NVM cell 1310 may store analog values 0-15, which correspond to its _ID / _VT level when read. In one embodiment, the multiple different _ID / _VT levels and their corresponding analog values may be predetermined. The analog values may be written to the analog NVM cells 1310 using one or more write methods/algorithms as described and described in FIGS. 9A to 12, using a series of partial programming/inhibition operations, partial erase/inhibition operations, and verification steps, etc. For example, the bit of Row A, Col. X is written with the value 10 ( _ID / _VT level = 10); the bit of Row A, Row Y is written with the value 5; the bit of Row B, Row X is written with the value 8; and the bit of Row C, Row Z is written with the value 2. In an embodiment, the multi-level NVM cell 1310 can be written with any analog value within a predefined _ID / _VT level range (e.g., 16 _ID / _VT levels from 0 to 15). The aforementioned stored values can be used in the exemplary operating methods described below in the present specification, which are used for illustrative purposes and should not be considered limiting.

In one embodiment, the values stored by the multi-level NVM cells 1310 may be combined to store one analog value. For example, two multi-level NVM cells 1310 may be configured to have 8 levels, with one cell storing values 0 to 7 and the other cell storing values -8 to -1. When the two cells are read in one operation, the combined two cells may be considered to have 16 levels (from -8 to 7), which represent 16 analog values instead of only 8. In other embodiments, more than two multi-level NVM cells 1310 may be combined to achieve a greater number of levels without the need for additional partitioning of the operating _ID / _VT range of the multi-level NVM cells 1310. In an embodiment, the combined cells may be placed on adjacent rows in the same column or dispersed in the analog NVM array 1302 according to some predetermined algorithms.

13, an analog NVM array 1302 may be coupled to a row multiplexer function 1304 via its bit lines (e.g., BL.X, BL.Y). In one embodiment, the row multiplexer function 1304 may have multiplexers, capacitors, transistors, and other semiconductor devices. During a read operation, the value 10 of the bit in column A, row X may be read to the row multiplexer function 1304 via BL.X, similar to the read operation of the digital NVM array. In one embodiment, multiple bits on the same row, such as column A, row X and column B, row X, may be selected in a read operation such that the value read out is the sum of the two selected bits (10+8=18). In other embodiments, multiple bits in the same column, such as column A, row X and column A, row Y, may be selected for the same read operation. The row multiplexer function 1304 may be configured to simultaneously select row X and row Y for reading and add or subtract the two values (10+5=15 or 10-5=5). In other embodiments, the NVM device 1300 may be configured to perform a multiplication function. For example, the bits of column A, row X may be read 7 times for calculation (7×10=70). The multiplication (M×stored value) may be performed by using M×multiple pulses on the WL (coupled to the SG) or by extending (M times) the pulse duration of a WL pulse. In one embodiment, as an example, an analog value of "7" may be input from an external device via a digital-to-analog converter (DAC) 1320, which may be coupled to the WL and to the columns of the SG. Preferably, each DAC 1320-1326 may be coupled to one WL or multiple WLs as shown in FIG. 13. One of the functional components of the DAC 1320-1326 is configured to be used for the selected column of the read operation. It will be appreciated that the number, configuration, and coupling to the NVM array 1302 of the DACs shown in FIG. 13 is only one example for illustrative purposes. Other configurations are possible without changing the general teachings of the embodiments of the present invention, depending on system requirements and design. In various implementations, the DACs 1320-1326, the analog NVM array 1302, and the row multiplexer functional unit 1304 may be configured with or without a CPU or GPU to perform simple arithmetic functions, such as addition, multiplication, etc., as described in the examples above. In one embodiment, the analog NVM device 1300 may perform the functions of both a data storage device and an inference device.

The analog results from the row multiplexer function 1304 may then be input to an analog-to-digital converter (ADC) or comparator 1306, where the analog read results may be converted to digital data and output. In one embodiment, all or part of the analog NVM array 1302 may be refreshed or have its analog values rewritten periodically, such as every 24 hours or every 48 hours or other duration. The refresh operation may minimize the potential effects of _ID / _VT level shift or attenuation of the programmed multi-stage NVM cells due to retention period, _ID / _VT degradation (as shown in FIG. 7B ), or other causes. In other embodiments, the analog NVM array 1302 may include a reference cell (not shown) where the common effects of potential _ID / _VT level offsets may be subtracted from the multi-level NVM cells 1310.

Figures 14 and 15 are representative block diagrams illustrating the Von-Neumann architecture and artificial neurons of a multiply-accumulate (MAC) system according to an embodiment disclosed herein, respectively. Artificial intelligence (AI) can be defined as the ability of a machine to perform cognitive functions performed by the human brain, such as reasoning, perception, and learning. Machine learning can use algorithms to find patterns in data and use models that recognize these patterns to make predictions about any new data or patterns. At the core of AI applications or machine learning, there is a MAC or dot product operation, where two numbers (an input value and a weight value) may be taken, multiplied, and the result added to an accumulator. The artificial neuron 1504 in FIG. 15 may be part of a deep neural network (DNN), which represents an example of a MAC operation. DNNs mimic the function of the human brain by implementing a massively parallel computing (biomimetic computing) architecture that connects low-power computing elements (neurons) and adaptive memory elements (synapses) together. One of the reasons for the rapid growth of machine learning is the availability of graphics processing units (GPUs). In MAC applications, such as in system 1402, GPUs can perform the necessary operations more quickly than conventional CPUs. One of the disadvantages of using GPUs for MAC operations is that GPUs tend to use floating-point arithmetic, which may far exceed the requirements of relatively simple machine learning algorithms, such as MAC operations. Furthermore, AI applications, especially those computing at the edge, may require the MAC to operate with high power efficiency to reduce power requirements and heat generation. Existing systems based on the digital von Neumann architecture, such as the MAC system 1402, may also cause major bottleneck issues between the GPU and the memory due to frequent access to the memory, where the GPU performs calculations and the memory only stores data (weight values, input values, output values, etc.). Therefore, it is necessary to consider the use of low-power memory devices that can be configured to perform as inference devices and data storage devices at the same time.

FIG. 16 is a representative block diagram illustrating a neural network acceleration system according to an embodiment of the present invention. In one embodiment, a SONOS-based analog device may have a unique ability to store analog values of weights locally and process each non-volatile memory element in parallel, which may largely eliminate the energy consumption of large data movement as illustrated in FIG. 14. Each NVM unit strips a binary level (1 bit) and may have multiple levels (e.g., 4-bit-8-bit), and each _ID / _VT level may represent a multiple-bit weight value (such as _Wi in FIG. 15) for inference. In one embodiment, the greater the number of levels, the higher the training accuracy and the lower the inference error rate. The key performance and stability of typical analog memories for bio-inspired computing are the standard deviation of the cell _ID / _VT , retention period, and noise at all levels. As described above, SONOS-based NVM devices, such as the analog NVM device 1300 in FIG. 13 , may be good candidates for performing both storage and inference functions in artificial neurons of DNN systems.

16 , a neural network acceleration system 1600 may include a plurality of analog NVM devices or accelerators 1602 disposed in a single substrate or package or die and coupled to each other via a bus system. Each accelerator 1602 may be similar to the analog NVM device 1300 in FIG. 13 and may operate similarly. In one embodiment, the NVM device 1602 may be configured to perform MAC operations. Each analog NVM device 1602 may function as an artificial neuron 1504 as shown in FIG. 15 in a DNN system. In one embodiment, a SONOS array 1602 may have a plurality of SONOS-based NVM cells (not shown in FIG. 16 ) configured in rows and columns. In other embodiments, the SONOS array 1602 may include a plurality of SONOS NVM blocks or arrays. Each NVM cell may be configured to store a weight value from 0 to ²ⁿ -1 or other values written using the writing algorithms or combinations thereof as depicted and shown in Figures 9A to 12. In other embodiments, the analog value of each NVM cell may be written by other writing algorithms.

As part of the bio-inspired computing algorithm, each multi-stage NVM device 1602 (such as accelerator 1602a) can execute the following MAC equation, where xi is the input from other multi-stage NVM devices 1602 or external devices, wi is the stored weight value, b is a constant and f is the activation function: f(Σ _i xiwi + b ) .................(1)

Preferably, as shown in FIG. 16 , xi can be a digital input from other analog NVM devices, such as 1602b and 1602c or other analog NVM devices. The digital input xi can then be converted into an analog signal by DAC 1612, and then can be coupled to a low voltage driver 1614 and/or a high voltage driver 1616. In one embodiment, the low voltage driver can generate a control signal corresponding to the analog signal from DAC 1612 through the WL of the NVM cell (to control the SG). The high voltage driver 1604 can generate a control signal to the BLs and a high voltage driver to the WLS to control the CG of the NVM cell.

An embodiment of MAC operation in analog NVM device 1602a can be illustrated using the example of FIG. 13 , where i can be set to 3. Referring to FIG. 13 , digital input xi can be coupled to DACs 1320-1326 with x1=3, x2=5, x3=1. The selected weight values are stored in the bits of column A, row X (w1=10), column B, row X (w2=8), and column C, row Z (w3=2), respectively. The weight value selection may be based on the address received from other analog NVM devices 1602 or from an external device (e.g., a processor, CPU, GPU, etc.). The constant b can be selected as the analog value stored in column A, row Y (b=5). To calculate x1×w1, column A and row X (stored value=10) may be selected for reading. The reading may be repeated x1=3 times to calculate x1×w1. Similarly, column B, row X (weight value=8) may be selected for x2=5 readings to calculate x2×w2 and column C, row Z (weight value=2) may be selected for x3=1 reading to calculate x3×w3. Alternatively, column A, row X and column B, row X may be selected simultaneously for reading 3 times (to accumulate the combined weight values), and only column A, row X may be selected for an additional 2 readings. The bit located at column A, row Y (b=5) may be selected for reading. As previously described, the row multiplexer 1304 or 1606 can be configured to add these results together to calculate the MAC result of 3×10+5×8+1×2+2=74. It should be understood that the above algorithm is only an example of using a SONOS-based NVM device (such as the inference NVM device 1300 and 1602) to calculate the MAC result, which is used for illustrative purposes and should not be considered limiting. Depending on the system design and requirements, the MAC weight values (wi) can be stored, organized and read in a variety of ways to calculate the MAC result. In one embodiment, the activation function (f) can be an algorithm that can indicate or prioritize the MAC output of the analog NVM device 1602 from the perspective of the entire neural network. For example, the MAC result of the previous example (result = 74) is considered unimportant and is assigned a low priority. In some embodiments, the output signal may be reduced or increased according to its priority and the execution may be performed in the row multiplexer function 1606 or the ADC 1608.

Subsequently, in one embodiment, the MAC result in the form of an analog signal may be converted into a digital signal by ADC 1306 or 1608. The digital signal may then be output to another or other analog NVM devices 1602 as xi for their own MAC operations. In one embodiment, similar to a DNN, the bionic operations performed by all analog NVM devices 1602 may be performed in parallel. The digital MAC output of each analog NVM device 1602 may be transmitted to other analog NVM devices as digital input. In some embodiments, the multiple analog NVM devices 1602 may be divided into multiple subsets. The digital input of one subset of analog NVM devices 1602 may be propagated to the next subset without repetition. The digital output of the last subset can be output to an external device as the bionic computing or machine learning result.

In one embodiment, command and control circuitry (not shown in FIG. 16 ) including digital data flow control block 1610 is programmable and configured to direct data flow in analog NVM device 1602. The command and control circuitry may also provide control of high voltage and low voltage controllers 1614 and 1616 to provide various operating voltage signals to SONOS array 1602 via SONOS word lines, word lines, bit lines, CSL, etc., including but not limited to V _POS , V _SEPOS , V RPPOS , V NEG , V _SENEG , V _CSL , V _MARG , V _INHIB , etc. as depicted in at least FIG. 3A , FIG. 3B , FIG. _8A , _FIG . 8B .

It should be understood by those skilled in the art that the neural network acceleration system 1600 and the analog NVM device 1602 in FIG. 16 are simplified rather than fully described for the purpose of illustration. In particular, the analog NVM device 1602 may include processing functional components, column decoders, row decoders, sense amplifiers, or other components, and the instruction and control circuits are not shown or described in detail herein.

17 is a representative flow chart showing an embodiment of a method of operation of a NN acceleration system 1600 featuring a SONOS-based NVM array/unit according to the present invention. In one embodiment, in step 1702, analog weight values (wi) and other constant values (e.g., b) are written to a SONOS-based NVM array in a NN accelerator using methods as previously described. In some embodiments, in optional step 1712, the NVM array may be periodically refreshed to obtain better retention period and narrower _ID / _VT standard deviation. Subsequently, in step 1704, the NVM array of one accelerator may be configured to perform MAC operations based on at least the weight values stored from other accelerators. In step 1706, after the MAC operation is completed, an accelerator may output its results and propagate them to one or more connected accelerators as digital inputs for their own MAC operations. In one embodiment, steps 1704 and 1706 may be repeated many times in parallel mode. In step 1710, the output may be transmitted to an external device, such as a CPU, GPU, as a result of the neural model calculation in machine learning for AI applications.

Thus, embodiments of SONOS-based multi-level non-volatile memory and methods of operating the same have been described herein, which are similar to the methods of operating analog memory devices and MAC devices in biomimetic computing systems (such as DNNs). Although the disclosure is described with reference to specific exemplary embodiments, it is apparent that various modifications and changes may be made to such embodiments without departing from the broader spirit and scope of the disclosure. Therefore, the contents of the specification and drawings should be regarded as illustrative only and not limiting.

The "Abstract of the Invention" of this disclosure is provided to comply with 37 C.FR.§1.72(b), which requires an "Abstract of the Invention" to enable the reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. It should be understood that the Abstract of the Invention should not be used to interpret or limit the scope or meaning of the claims. In addition, in the aforementioned "embodiments," it can be seen that various different features are grouped together in a single embodiment for the purpose of disclosure simplicity. The method of this disclosure should not be interpreted as reflecting an intention that the embodiments to be listed as patent claims need to have more features than those expressly cited in each claim of the claims. On the contrary, as shown in the claims below, the subject matter of the invention also exists in a portion of all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the "implementations", wherein each claim in the claims is itself a separate embodiment.

Reference to an embodiment description means that a particular feature, structure, or characteristic described in conjunction with that embodiment is incorporated into at least one embodiment of the circuit or method. The term "an embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment.

90:NVM unit

100:NVM array

200: NVM unit pair

300: 2×2 array

Claims (21)

A semiconductor device, comprising: a non-volatile memory (NVM) array including multi-stage transistors arranged in rows and columns based on charge capture, wherein the multi-stage transistors are configured to store one of N analog values, the N analog values corresponding to N levels of drain current ( _ID ) and critical voltage ( _VT ), wherein N is a natural number greater than 2, and wherein at least one of the multi-stage memory transistors is selected for a target value writing procedure, wherein the target value is one of the N analog values and corresponds to a target ID range, the target ID range ranging from a target I _D to a target I _D. a write circuit configured to perform the write procedure, the write procedure including performing a partial programming operation on at least one of the multi-level memory transistors for reducing _{the ID} level and performing a partial erasing operation on at least one of the multi-level memory transistors for increasing the ID level; and a read circuit configured to perform a first verification read after the partial programming operation to determine how the reduced _ID level is compared with a target _ID average value, the read circuit further configured to perform a second verification read after the partial erasing operation to determine how the increased _ID level is compared with the target _ID average value, and wherein when the ID level of the at least one of the multi-level memory transistors falls within the target _ID level, the read circuit performs a verification read after the partial erasing operation to determine how the increased _ID level is compared with the target _ID average value. _D , it is determined that the writing process of the target value is completed. A semiconductor device as claimed in claim 1, wherein each of the multi-stage transistors includes a charge trapping layer of nitride or oxynitride, and the N analog values correspond to the amount of charge trapped therein. A semiconductor device as claimed in claim 1, wherein each of the multi-stage transistors includes a metal gate layer, and the metal gate layer is disposed above a high-K dielectric gate dielectric layer. A semiconductor device as claimed in claim 1, wherein the write circuit is further configured to apply a predetermined voltage to at least one of a word line, a bit line and a source line during the partial programming operation and the partial erasing operation, and wherein the word line, the bit line and the source line are coupled to the multi-stage transistor. A semiconductor device as claimed in claim 2, wherein the write circuit is further configured to inhibit at least one of the multi-level memory transistors from performing further operations of changing the _ID level by reducing the magnitude of the voltage difference across the charge trapping layer of the nitride or nitride oxide of at least one of the multi-level memory transistors after the write process of the target value is completed. A semiconductor device as claimed in claim 1, wherein the partial programming operation includes at least one of a soft programming operation and a refill programming operation, wherein the partial programming operation is configured to reduce the _ID level of at least one of the multi-level memory transistors and increase the _VT level of at least one of the multi-level memory transistors, and wherein the partial erase operation includes at least one of a soft erase operation, a selective soft erase operation and an annealing erase operation, wherein the partial erase operation is configured to increase the _ID level of at least one of the multi-level memory transistors and reduce the _VT level of at least one of the multi-level memory transistors. A semiconductor device as claimed in claim 1, wherein the partial programming operation is performed for a relatively short duration compared to the programming operation, wherein regardless of the starting _ID level of the multi-level memory transistor, the programming operation is configured to reduce the _ID level of the multi-level memory transistor to a fully programmed _ID level. A semiconductor device as claimed in claim 6, wherein the soft erase operation and the selective soft erase operation are performed for a relatively short duration compared to the erase operation, wherein regardless of the starting _ID level of the multi-level memory transistor, the erase operation is configured to increase the _ID level of the multi-level memory transistor to a fully erased _ID level. A semiconductor device as claimed in claim 8, wherein the annealing erase operation is performed for a relatively long duration compared to the erase operation, and wherein during the erase operation, the magnitude of the voltage difference across the charge trapping layer of the nitride or nitride oxide of at least one of the multi-level memory transistors is greater than that of the annealing erase operation. The semiconductor device of claim 1, wherein the write circuit is further configured to execute a refill and annealing algorithm to maintain the ID level of the at least one of the multi-stage memory transistors at the target _ID level after the write process of the target value is completed. In the _D level range, charges in shallow traps are replaced with charges in deep traps of the charge trapping layer of the nitride or oxynitride of at least one of the multi-level memory transistors, wherein the refill programming operation of the refill and anneal algorithm promotes deep trapped charges by applying a high voltage difference across the charge trapping layer of the nitride or oxynitride and applying a short programming pulse to the at least one of the multi-level memory transistors, and wherein the anneal erase operation of the refill and anneal algorithm is configured to clear shallow trapped charges through Furnohan tunneling by applying a low voltage bias across the charge trapping layer of the nitride or oxynitride and applying a long erase pulse to the at least one of the multi-level memory transistors. A semiconductor inference device, comprising: a non-volatile memory (NVM) array, comprising NVM cells arranged in rows and columns, wherein each of the NVM cells comprises a charge trap transistor, and wherein each of the charge trap transistors is configured to store one of N analog values, the N analog values corresponding to a drain current ( _ID ) and a critical voltage ( _V ), wherein the N analog values stored represent N weight values for a multiply-accumulate (MAC) operation, wherein N is a natural number greater than 2; a digital-to-analog converter (DAC) functional component configured to receive and convert digital inputs from an external device, wherein each of the digital inputs is configured so that a weight value is stored in at least one NVM unit selected and read; a multiplexer (mux) functional component configured to generate an analog MAC result based on a conversion result of the digital input and a read result of the weight value; and an analog-to-digital converter (ADC) functional component configured to convert the analog MAC result of the multiplexer (mux) functional component into a digital value and output the digital value. A semiconductor inference device as claimed in claim 11, wherein two adjacent NVM cells are configured to store a single weight value, wherein the single weight value is based on analog values respectively stored in the two adjacent NVM cells, and wherein the range of the single weight value is 2×N. A semiconductor inference device as claimed in claim 11, wherein the digital input includes address information of the at least one NVM cell selected. A semiconductor inference device as claimed in claim 11, wherein a plurality of the semiconductor inference devices are arranged on the same semiconductor die and are communicatively coupled to each other, and each of the plurality of the semiconductor inference devices is arranged to perform the MAC operation based on the weight value stored in the NVM unit and the digital input from at least one other semiconductor inference device among the plurality of the semiconductor inference devices. A semiconductor inference device as claimed in claim 14, wherein a first subset of the plurality of semiconductor inference devices outputs a digital result of a MAC operation, and wherein the digital result of the first subset is coupled to a second subset of the plurality of semiconductor inference devices as its digital input. A semiconductor inference device as claimed in claim 14, wherein a plurality of the semiconductor inference devices are configured to function as artificial neurons in a deep neural network (DNN) system to perform neural-type computations in artificial intelligence (AI) applications. A method of operating a multiply-accumulate (MAC) device, comprising: coupling a plurality of non-volatile memory (NVM) devices of the MAC device to a bus system, wherein each of the plurality of NVM devices comprises NVM cells arranged in rows and columns, and wherein each of the NVM cells comprises a charge trap transistor, the charge trap transistor being configured to store one of N analog values, the N analog values corresponding to a drain current ( _ID ) and a critical voltage ( _V ), wherein the stored N analog values represent N multiply-accumulate (MAC) weight values, wherein N is a natural number greater than 2; writing one of the N weight values into each NVM unit in the plurality of NVM devices; receiving a set of digital inputs (x1, x2 . . . to xi) at a first NVM device in the plurality of NVM devices through the bus system, wherein i is a natural number; converting the set of digital inputs into a set of analog values using a digital-to-analog converter (DAC) functional component; based on the set of digital inputs Outputting a set of weight values (w1, w2... to wi) stored in the corresponding NVM unit to the multiplexer function component of the first NVM device; generating an analog MAC result (x1w1+x2w2+...+xiwi) of the set of analog values and the set of MAC weight values; converting the analog MAC result into a digital MAC value; and transmitting a digital MAC result based on the digital MAC value to a second NVM device, wherein the digital MAC result is one of a set of digital inputs of the second NVM device. The method of claim 17 further comprises: periodically performing a refresh operation on the NVM element in at least one of the plurality of NVM devices to verify that the MAC weight value stored therein remains unchanged. The method of claim 17, wherein the first NVM device is one of a first set of NVM devices, and the second NVM device is one of a second set of NVM devices, and wherein the digital MAC result output from the second set of NVM devices is not transmitted to the first set of NVM devices. The method of claim 17, wherein the aforementioned writing of the weight value in the N weight values comprises: performing a series of operations, which includes at least one of programming, erasing, partial programming, partial erasing, soft erasing, selective soft erasing, annealing erasing, refill programming, and verification reading. The method of claim 17, further comprising: Generating the digital MAC result based on the digital MAC value, comprising: adding a constant value to the digital MAC value; and performing an activation function algorithm on the sum of the constant value and the digital MAC value.

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