TWI872474B - Carrier for double-sided polishing, and double-sided polishing method and apparatus for silicon wafer using same - Google Patents

Abstract

[Problem]Provided are a double-side polishing carrier capable of extending the life of the carrier by improving wear resistance, and a method and apparatus for polishing both sides of silicon wafers using the carrier. [Means for solving]The double-sided polishing carrier 10 according to the present invention comprises a substantially cylindrical carrier body 11 made of a resin laminated plate including a fiber base material and a wafer holding hole 12 formed in the carrier body 11. The fiber exposure rate of the main surface of the carrier body 11 is less than 50%.

Description

Double-side polishing carrier and double-side polishing method and device for silicon wafer using the same

The present invention relates to a double-side polishing carrier and a double-side polishing method and device for silicon wafers using the carrier.

Silicon wafers are widely used as substrate materials for semiconductor devices. Silicon wafers are manufactured by sequentially performing outer ring grinding, slicing, grinding, etching, double-side grinding, single-side grinding, and cleaning on silicon single crystal ingots. Among them, the double-side grinding step is a necessary step to process the wafer to a predetermined thickness and to improve the flatness of the wafer. It is implemented using a double-side grinding device that grinds both sides of the wafer at the same time.

The double-side polishing device uses a double-side polishing carrier that holds the wafer during polishing. The materials of the double-side polishing carrier are metal carriers and resin carriers. Metal carriers have a long life due to their high wear resistance, but there are problems such as scratches on the wafer end surface and melting of metal components. Although resin carriers will not scratch the wafer end surface and melt the metal components, they have low wear resistance and short life.

Patent document 1 describes a method of performing double-sided polishing while holding a silicon wafer using a resin double-sided polishing carrier. The double-sided polishing carrier is composed of a resin laminated plate in which a hydrophilic fiber substrate is impregnated with a wet resin, and the average contact angle of the surface and back surfaces contacting the polishing cloth to pure water is greater than 45° and less than 60°. In addition, the surface exposure rate of the fiber substrate is greater than 50%. According to the resin carrier described in patent document 1, the polishing rate of the silicon wafer can be increased.

Furthermore, Patent Document 2 states that before the carrier is placed in a double-sided grinder to actually process the wafer, a two-stage carrier grinding (pre-treatment) consisting of a primary grinding using a slurry doped with abrasive grains and a secondary grinding using a slurry not doped with abrasive grains is performed using a device other than the wafer grinding device. [Prior Art Document] [Patent Document]

[Patent Document 1] International Publication No. 2018/105306 [Patent Document 2] Japanese Patent Publication No. 2017-104958

[The problem that the invention wants to solve]

However, the known double-sided polishing carrier described in Patent Document 1 has a surface exposure rate of more than 50% of the fiber substrate. Therefore, even if the polishing rate is increased, the carrier wears quickly, resulting in an increase in the frequency of carrier replacement, which leads to a problem of increased production costs. In addition, the change in wafer flatness quality is generally the largest right after the carrier is replaced. Therefore, the higher the frequency of carrier replacement, the more wafers that do not meet the required flatness quality. In addition, the resin carrier containing a glass fiber substrate has a higher probability of scratching the wafer surface due to the wear of the glass fiber.

Therefore, the purpose of the present invention is to provide: a double-sided polishing carrier that can achieve a long life by improving wear resistance, and a double-sided polishing method and device for a silicon wafer using the carrier. [Means for solving the problem]

To solve the above-mentioned problem, the double-sided polishing carrier of the present invention is a double-sided polishing carrier for holding the silicon wafer when the silicon wafer is polished on both sides, and comprises: a roughly disc-shaped carrier body formed by a resin laminate containing a fiber substrate, and a wafer holding hole formed in the above-mentioned carrier body; the fiber exposure rate of the main surface of the above-mentioned carrier body is less than 50%.

According to the present invention, by reducing the fiber exposure rate of the main surface of the carrier body to less than 50%, the wear resistance can be improved. Therefore, the frequency of carrier replacement can be reduced to improve productivity and the yield of silicon wafers that meet the required flatness quality can be improved.

In the present invention, the flatness of the carrier body is preferably less than 5 μm. Thus, by using a carrier with a flatness of less than 5 μm and a fiber exposure rate of less than 50%, the wear resistance of the carrier can be ensured and the flatness quality of the wafer can be improved.

In the present invention, the thickness of the carrier body is preferably thinner than the thickness of the silicon wafer before grinding, and the thickness difference is 5-20μm. Even if the thickness of the carrier gradually decreases due to repeated use of the carrier in the double-sided grinding step, resulting in the difference between the thickness of the silicon wafer before grinding and the thickness of the carrier varying within the range of 5-20μm, the fiber exposure rate of the carrier is still maintained at less than 50%, thereby preventing the carrier wear rate from increasing rapidly.

Preferably, the resin laminate has a multi-layer structure in which a plurality of composite sheets are stacked, wherein the fiber substrate contains a wet resin; the resin is epoxy, phenol or aromatic amide; the fiber substrate is glass fiber fabric, carbon fiber fabric or organic fiber fabric; and the multi-layer structure has more than 3 layers.

Furthermore, the double-side polishing method of the silicon wafer of the present invention includes: the step of preparing a carrier for double-side polishing; and after loading the silicon wafer on the above-mentioned double-side polishing carrier arranged between the upper platen and the lower platen to which the polishing cloth has been respectively adhered, supplying slurry between the above-mentioned upper platen and the above-mentioned lower platen while rotating the above-mentioned upper platen and the above-mentioned lower platen respectively, to perform double-side polishing on the above-mentioned silicon wafer; wherein the above-mentioned double-side polishing carrier has: a roughly disc-shaped carrier body composed of a resin laminate containing a fiber substrate, and a wafer holding hole formed in the above-mentioned carrier body; the fiber exposure rate of the main surface of the above-mentioned carrier body is less than 50%.

According to the present invention, the wear rate of the carrier can be prevented from increasing rapidly due to the increase in the fiber exposure rate, so that the life of the carrier can be prolonged. Therefore, the productivity can be improved by reducing the frequency of carrier replacement, and the yield of silicon wafers that meet the required flatness quality can be improved.

The double-side polishing method of the silicon wafer of the present invention preferably further includes the step of pre-polishing the carrier for double-side polishing in such a manner that the flatness of the carrier body is less than 5 μm and the fiber exposure rate is less than 50% before the step of performing double-side polishing on the silicon wafer. Thus, by using a carrier with a flatness of less than 5 μm and a fiber exposure rate of less than 50%, the wear resistance of the carrier can be ensured and the flatness quality of the wafer can be improved.

In the present invention, in the step of pre-grinding the double-sided grinding carrier, it is preferable to adjust the thickness of the carrier body in such a way that it is thinner than the pre-grinding thickness of the silicon wafer and the thickness difference becomes 5 to 10 μm. In addition, in the step of double-sided grinding of the silicon wafer, it is preferable to use the double-sided grinding carrier whose thickness difference with the pre-grinding thickness of the silicon wafer is within a range of 20 μm or less. Even if the thickness of the carrier gradually decreases due to repeated use of the carrier in the double-sided grinding step, and the difference between the pre-grinding thickness of the silicon wafer and the thickness of the carrier changes within a range of 5 to 20 μm, the fiber exposure rate of the carrier is still maintained at less than 50%, thereby preventing the wear rate of the carrier from increasing rapidly.

Furthermore, the double-sided polishing device of the present invention comprises: an upper platen and a lower platen to which polishing cloths are respectively adhered, and a double-sided polishing carrier arranged between the upper platen and the lower platen and holding a silicon wafer; wherein the double-sided polishing carrier comprises: a roughly disc-shaped carrier body composed of a resin laminate containing a fiber substrate, and a wafer holding hole formed in the carrier body; the fiber exposure rate of the main surface of the carrier body is less than 50%.

According to the present invention, the wear rate of the carrier can be prevented from increasing rapidly due to the increase in the fiber exposure rate, so that the life of the carrier can be extended. Therefore, productivity can be improved by reducing the frequency of carrier replacement, and the yield of silicon wafers that meet the required flatness quality can be improved. [Effect of the invention]

According to the present invention, a double-side polishing carrier having a longer life by improving wear resistance and a double-side polishing method and device for a silicon wafer using the carrier can be provided.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 and FIG. 2 show the structure of a double-side polishing device according to an embodiment of the present invention, FIG. 1 is a schematic cross-sectional view, and FIG. 2 is a schematic plan view.

As shown in Fig. 1 and Fig. 2, the double-side polishing device 1 has an upper platen 2 and a lower platen 3 which are disposed opposite to each other in the vertical direction, and polishing cloths 4 are respectively adhered to the polishing surfaces of the upper platen 2 and the lower platen 3. The polishing cloth 4 can be, for example, a non-woven cloth impregnated with urethane resin or a foamed polyurethane pad.

A slurry supply device 5 is provided above the upper platen 2 for supplying slurry between the upper platen 2 and the lower platen 3. The slurry supply device 5 supplies slurry from a nozzle 6 inserted into a through hole 2a of the upper platen 2. The slurry may be an inorganic alkaline aqueous solution containing colloidal silica.

A sun gear 7 is provided at the center between the upper fixed plate 2 and the lower fixed plate 3, and an inner gear 8 is provided at the outer ring, forming a planetary gear type double-sided grinding device. The upper fixed plate 2, the lower fixed plate 3, the sun gear 7 and the inner gear 8 have the same central axis of rotation and can rotate independently of each other.

A plurality of (here, three) double-side polishing carriers 10 (hereinafter referred to as "carriers") are arranged between the upper plate 2 and the lower plate 3. Each carrier 10 is arranged between the sun gear 7 and the inner gear 8, and the outer ring gear of the carrier 10 is engaged with both the sun gear 7 and the inner gear 8. When the upper plate 2 and the lower plate 3 are driven to rotate by a driving source (not shown), they are linked to the sun gear 7 and the inner gear 8 and rotate together. In this way, the carrier 10 rotates between the upper plate 2 and the lower plate 3 while revolving around the sun gear 7. At this time, since the silicon wafer W is locked and held in the wafer holding hole provided in the carrier 10, both surfaces are polished simultaneously by the upper and lower polishing pads 4. In the polishing step, slurry is supplied from the nozzle 6 through the through hole 2a.

FIG. 3 is a schematic plan view of the structure of the carrier 10 .

As shown in FIG3 , the carrier 10 comprises: a carrier body 11 having a roughly disc-shaped shape, a wafer holding hole 12 (hereinafter referred to as “holding hole”) for holding a silicon wafer W, and an outer ring tooth 13 provided on the outer ring portion of the carrier body 11. The holding hole 12 is a circular opening formed in a manner of penetrating from one main surface (the surface or top) of the carrier body 11 to the other main surface (the back or bottom), and the diameter of the holding hole 12 is roughly equal to the diameter of the silicon wafer W. Because the center position of the holding hole 12 is offset from the center position of the carrier 10, the silicon wafer W in the holding hole 12 rotates eccentrically when the carrier 10 rotates. In the present embodiment, the number of holding holes 12 formed in the carrier 10 is only one, but a plurality of holding holes 12 may also be provided.

FIG. 4 is a cross-sectional view showing the cross-sectional structure of the resin laminate constituting the carrier 10.

As shown in FIG. 4 , the carrier body 11 of the double-sided polishing carrier 10 is composed of a composite sheet 20 (FRP sheet) in which a fiber substrate 21 contains a wet resin 22, and a multi-layer structure resin laminate is formed. The fiber substrate 21 is preferably made of glass fiber woven cloth, carbon fiber woven cloth, etc. The resin 22 is preferably made of epoxy, phenol, aromatic amide, etc. The resin laminate is preferably formed of three or more layers of the composite sheet 20, preferably a five-layer structure as shown in the figure.

In this embodiment, the fiber exposure rate of the main surface of the carrier 10 (carrier body 11) is less than 50%. That is, in the double-sided polishing step, a carrier 10 with a fiber exposure rate of less than 50% is used, and a carrier 10 with a fiber exposure rate of more than 50% is not used. The reason is that if the fiber exposure rate reaches more than 50%, the wear resistance of the carrier will be sharply reduced, resulting in a shortened carrier life.

The fiber exposure rate of the carrier 10 used in the double-sided polishing step is ideally 0%. However, it is extremely difficult to frequently use a carrier 10 with a fiber exposure rate of 0%. Usually, a resin laminate is made by hot-pressing a plurality of composite sheets 20 to form an integral body. During hot pressing, the resin on the outermost surface will flow off, so even if the moisture content of the resin to the fiber substrate is increased, the thickness of the resin on the outermost surface will not be increased.

In addition, because the flatness of a new carrier is poor after it is completed and not used, pre-grinding (pre-treatment) of the new carrier is performed before actual use (refer to Figure 5). Specifically, pre-grinding is performed in such a way that the difference in thickness between the silicon wafer to be processed before grinding is 5~10μm and the flatness of the carrier is less than 5μm. If this pre-treatment is performed, the fiber substrate 21 will definitely be exposed on the main surface of the carrier 10, and the fiber exposure rate will reach more than 50% based on the grinding amount. If the fiber exposure rate reaches more than 50%, the wear rate of the carrier will increase sharply, resulting in a shortened carrier life.

However, in the present embodiment, the fiber exposure rate of the main surface of the carrier used in the double-sided grinding step is maintained at less than 50%, and when pre-grinding is performed on a completely new carrier that has never been used, the grinding amount is adjusted in such a way as to maintain the fiber exposure rate of less than 50%, not only immediately after the pre-grinding, but also when the thickness reaches the lower limit due to repeated use of the carrier. This can improve the wear resistance of the carrier and extend its life.

FIG. 6 is a flow chart of a method for polishing both sides of a silicon wafer according to an embodiment of the present invention.

As shown in FIG6 , the double-side polishing method of the present embodiment of the present invention first prepares an unused carrier 10 (step S1). As described above, the carrier 10 is manufactured by hot pressing a plurality of (e.g., 5) composite sheets 20 to form a resin laminate, and then punching the composite sheets 20 to form a predetermined shape including a retaining hole 12 and an outer ring tooth 13.

Next, in order to adjust the thickness of the carrier 10 and improve the flatness, the carrier is pre-grinded (pre-processed) (step S2). The pre-grinding of the carrier is to use a device other than the wafer grinding device to grind the carrier using abrasive slurry. In addition, during the pre-grinding of the carrier, the grinding amount is set in such a way that the fiber exposure rate is less than 50%. For example, the grinding amount is set to be 5~10μm thinner than the thickness of the wafer before grinding (for example, 785μm) and the grinding process is performed. In this way, a carrier in which the flatness of the carrier in one set is adjusted to less than 5μm and the fiber exposure rate is less than 50% is obtained. Because the flatness of the carrier in one set becomes less than 5μm, of course the flatness of each carrier is also less than 5μm.

Next, the pre-polished carrier 10 is used to perform a double-sided polishing step (step S3) on the silicon wafer W. The silicon wafer to be processed is polished on both sides in accordance with the target thickness and flatness. After the polishing process is completed, the silicon wafer W is removed from the carrier and sent to the next processing step (single-sided polishing step).

The carrier 10 is reusable and can be used repeatedly until the predetermined thickness reaches the lower limit (steps S4N, S5, S6, S3). If the carrier is used in the double-sided polishing step, the carrier thickness will also decrease. The carrier itself will also wear out by repeatedly performing wafer polishing. In particular, because the resin carrier wears more severely than the metal carrier, the number of times it can be reused is reduced, resulting in reduced productivity.

In order to perform double-sided polishing on the wafer W, a carrier 10 thinner than the wafer W must be used. However, when a carrier 10 that is very thin relative to the target thickness of the wafer W is used, the required flatness of the wafer cannot be ensured. Therefore, the lower limit of the thickness of the carrier that can be used in the double-sided polishing step is set near the target thickness of the wafer, and the too-thin carrier below the lower limit is excluded (discarded) from the use object (steps S4Y, S7). The lower limit of the thickness of the carrier is, for example, set to the thickness of the wafer before polishing (e.g., 785μm) minus 20μm.

Furthermore, carriers with a fiber exposure rate of 50% or more on the main surface of the carrier are also excluded from continuous use (steps S5Y and S7). Generally, the fiber exposure rate of a carrier increases with the number of uses, and the wear rate of a carrier with a fiber exposure rate of 50% or more is very fast. However, because the carrier of this embodiment is formed in such a way that the fiber exposure rate is often less than 50% even if it is repeatedly used from a predetermined upper limit of thickness to a lower limit of thickness, the wear rate of the carrier can be suppressed to achieve a long life.

As described above, the double-side polishing method of the silicon wafer of the present embodiment uses a double-side polishing carrier composed of a resin laminate to perform double-side polishing on the silicon wafer, and the fiber exposure rate of the main surface of the carrier is less than 50%, thereby improving the wear resistance and achieving a longer life of the carrier.

The above is a description of the preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention, and of course, all of these are also included in the scope of the present invention.

For example, in the above-mentioned embodiment, a double-sided polishing device that can load three resin carriers is exemplified, but the structure of the double-sided polishing device is not particularly limited, and various devices that can use resin carriers can be adopted. In addition, there are no particular limitations on the number of wafers that can be loaded in the carrier and the shape of the carrier. [Example]

<Relationship between carrier flatness and wafer flatness quality> The effect of carrier flatness on wafer flatness quality was evaluated. The double-side polishing device used a carrier that can load 5 wafers with a diameter of 500 mm. The carrier has a single wafer holding hole and can load 1 wafer with a diameter of 300 mm. The wafer used was a p-type silicon single crystal wafer with a diameter of 300 mm. The polishing pad used was a urethane polishing pad without abrasive grains. The slurry used was an inorganic alkaline aqueous solution with a pH of 11 to 12 and containing silicon dioxide abrasive grains with a particle size of 60 to 110 nm.

After the carriers are pre-polished, the thickness of the carriers is measured using a laser displacement meter to obtain the flatness of the carriers within a batch. The flatness of the carriers within a batch is measured at a point 1.01r (mm) from the center of the carrier holding hole in the four directions of up, down, left, and right.

The flatness calculation method of the carrier is shown in Figure 7. The direction from the center C of the holding hole toward the center of the carrier is set as the reference direction (θ=0°), and the thickness measurement values _X1 , _X2 , X3, and _X4 are obtained at four locations near the outer circle in the four directions of θ=0°, 90°, 180°, and ₂₇₀ °. The distance from the center C of the holding hole 12 to the thickness measurement point is set to 1.01r (mm). r is the radius of the wafer holding hole.

From the measurement values obtained at 4 locations on each of the 5 carriers, a total of 20 locations, the difference ΔX=X _max -X _min between the maximum value X _max and the minimum value X _min was taken as the carrier flatness (μm) within one batch.

Next, measure the ESFQR (Edge Site flatness Front reference least Square Range) of the silicon wafer after double-sided polishing. Focus on the flatness evaluation index (site flatness) of the wafer edge where flatness is easily deteriorated, indicating the size of the edge roll off. The flatness of the wafer edge is set to an annular outer ring area that is set to a range of 2~32mm (sector length 30mm) from the outermost circle of the wafer, and further divide it equally in the circumferential direction to obtain unit areas (sites), and then obtain it according to each unit area (site). The ESFQR measurement is performed using a wafer flatness measurement device (Wafer Sight manufactured by KLA-Tencor). The measurement conditions are as follows: the measurement range is set to 296mm (excluding the outermost 2mm), the number of sectors (number of sites) when measuring the edge is set to 72, and the sector length is set to 30mm. The relationship between the carrier flatness and the EFSQR of the polished wafer is shown in Figure 8. In addition, ESFQR is the average value of the measured values of 5 wafers in one batch.

As shown in Figure 8, it is known that if the flatness of the carrier is greater than 5μm, the ESFQR of the wafer will deteriorate rapidly. This phenomenon can be considered to be due to the large variation in carrier thickness (flatness) within a batch, which leads to variations in the polishing state of the wafers within a batch.

<Relationship between carrier fiber exposure rate and carrier wear rate> Next, the effect of the carrier fiber exposure rate on the carrier wear rate was evaluated. The carrier material is composed of 5 layers of structural resin laminated boards, which are made of 5 sheets of glass fiber cloth substrates moistened with epoxy resin.

The fiber exposure rate on the main surface of the carrier is determined by randomly selecting 10 locations in the outer ring area within 50 mm from the outer ring end of the carrier wafer holding hole as observation locations, taking CCD microscope images of each observation location, and then binarizing the captured images to calculate the area ratio of the fiber portion. Figures 9(a) and (b) show an example of CCD microscope images of the carrier surface. Figure 9(a) shows the image before binarization, and Figure 9(b) shows the image after binarization. The image size of each measured location is 2.8×2.1 (mm). The fiber exposure rate on the carrier surface is adjusted by adjusting the grinding amount during the step of pre-grinding the carrier to adjust the carrier thickness or flatness.

The carrier wear rate is calculated from the reduction in carrier thickness per unit time (the difference in thickness before and after polishing) after loading a dummy silicon wafer slightly thinner than the carrier thickness and polishing both sides of the carrier using a silicon wafer polishing slurry containing colloidal silica. The results are shown in Figure 10. In Figure 10, the longitudinal carrier wear rate is a relative value when the fiber exposure rate is 90% and the reference value is set to 100.

As shown in Figure 10, when the fiber exposure rate is below 42%, the carrier wear rate is a low value below 27, but when the fiber exposure rate is around 50%, the carrier wear rate increases rapidly, and when the fiber exposure rate reaches 60% or more, the carrier wear rate is close to about 100. On the contrary, it is known that the carrier wear rate begins to decrease rapidly when the fiber exposure rate is lower than 60%, and when the fiber exposure rate is 50%, the carrier wear rate is less than half of the carrier wear rate when the fiber exposure rate is 90%. Accordingly, the reason why the carrier is easily worn when the fiber exposure rate reaches more than 50% can be considered to be due to the corrosion of the glass fiber exposed on the surface of the carrier by the high alkaline polishing slurry.

<Relationship between carrier fiber exposure rate and number of wafers processed> For a carrier thickness specification set in consideration of a certain wafer thickness and flatness specification, the number of wafers processed when the carrier is repeatedly used from the upper limit to the lower limit is evaluated. The results are shown in Figure 11.

As shown in FIG11 , when the fiber exposure rate is below 42%, the number of wafers processed is about 400, but when the fiber exposure rate is 48%, the number of wafers processed is reduced to 250, and when the fiber exposure rate is above 60%, the number of wafers processed is reduced to about 100.

As mentioned above, the fiber exposure rate of the carrier affects the wear rate of the carrier, so it is best to maintain the fiber exposure rate less than 50%, which can extend the life of the carrier.

1: Double-sided polishing device 2: Upper platen 2a: Through hole 3: Lower platen 4: Polishing cloth 5: Slurry supply device 6: Nozzle 7: Sun gear 8: Inner gear 10: Double-sided polishing carrier 11: Carrier body 12: Wafer holding hole 13: Outer ring gear 20: Composite sheet 20a: Composite sheet 20b: Composite sheet 21: Fiber substrate 22: Resin W: Silicon wafer

Figure 1 is a schematic cross-sectional view of the structure of the manufacturing device of the embodiment of the present invention; Figure 2 is a schematic plan view of the structure of the single crystal manufacturing device of the embodiment of the present invention; Figure 3 is a schematic plan view of the structure of the carrier; Figure 4 is a cross-sectional view of the cross-sectional structure of the resin laminate constituting the carrier; Figure 5 is a schematic diagram for explaining the pre-grinding (pre-treatment) of the carrier; Figure 6 is a flow chart for explaining the double-sided grinding method of the silicon wafer of the embodiment of the present invention; Figure 7 is a schematic diagram for explaining the flatness calculation method of the carrier; Figure 8 is a relationship diagram between the flatness of the carrier and the flatness of the outer ring of the wafer (ESFQR); In FIG9 , FIG9 (a) and (b) are CCD microscope images of the carrier surface, FIG9 (a) is the image before binarization, and FIG9 (b) is the image after binarization; FIG10 is a relationship diagram between the fiber exposure rate and the wear rate of the carrier; and FIG11 is a relationship diagram between the fiber exposure rate of the carrier and the number of wafers processed.

10: Carrier for double-sided grinding

11: Vehicle body

12: Wafer holding hole

13: Outer ring teeth

Claims (9)

A double-sided polishing carrier is a double-sided polishing carrier for holding a silicon wafer when the silicon wafer is polished on both sides, and comprises: a roughly disc-shaped carrier body, which is composed of a resin laminate containing a fiber substrate; and a wafer holding hole, which is formed in the carrier body; wherein the fiber exposure rate of the main surface of the carrier body is less than 50%, and the flatness of the carrier body near the periphery of the wafer holding hole is less than 5μm, and is obtained based on the difference between the maximum and minimum values of the thickness measurement value of the carrier body. A double-sided polishing carrier as claimed in claim 1, wherein the distance from the center of the wafer holding hole to the thickness measuring point is 1.01r (mm) (where r is the radius of the wafer holding hole). As for the double-sided polishing carrier of claim 2, the thickness of the carrier body is thinner than the thickness of the silicon wafer before polishing, and the thickness difference is 5~20μm. A double-sided polishing carrier as claimed in any one of claims 1 to 3, wherein the resin laminate has a multi-layer structure of a plurality of laminated sheets of a composite sheet containing a wet resin on the fiber substrate; The resin is epoxy, phenol or aromatic amide; The fiber substrate is glass fiber woven fabric, carbon fiber woven fabric or organic fiber woven fabric. A method for polishing both sides of a silicon wafer comprises: A step of preparing a carrier for polishing both sides; and After loading a silicon wafer on the carrier for polishing both sides arranged between an upper platen and a lower platen to which polishing cloths have been respectively attached, supplying slurry between the upper platen and the lower platen while rotating the upper platen and the lower platen to polish both sides of the silicon wafer; Wherein, the carrier for polishing both sides comprises: A roughly disc-shaped carrier body composed of a resin laminate containing a fiber substrate, and A wafer holding hole formed in the carrier body; Furthermore, the fiber exposure rate of the main surface of the carrier body is less than 50%, and the flatness of the carrier body near the periphery of the wafer holding hole is less than 5μm, and is obtained based on the difference between the maximum and minimum values of the thickness measurement value of the carrier body. The method for double-side polishing of a silicon wafer as claimed in claim 5, wherein, before the step of performing double-side polishing on the silicon wafer, the method further includes: performing a pre-polishing step on the carrier for double-side polishing in such a manner that the flatness of the carrier body is less than 5 μm and the fiber exposure rate is less than 50%. In the double-sided polishing method of claim 6, the step of pre-polishing the double-sided polishing carrier is to adjust the thickness of the carrier body in a manner that is thinner than the pre-polishing thickness of the silicon wafer and the thickness difference becomes 5-10 μm. In the double-side polishing method of claim 7, the step of performing double-side polishing on the silicon wafer is performed using the double-side polishing carrier having a thickness difference of less than 20 μm from the thickness of the silicon wafer before polishing. A double-sided polishing device comprises: an upper platen and a lower platen, each of which has a polishing cloth attached thereto, and a double-sided polishing carrier, which is disposed between the upper platen and the lower platen and holds a silicon wafer; wherein the double-sided polishing carrier comprises: a substantially disc-shaped carrier body composed of a resin laminate containing a fiber substrate, and a wafer holding hole formed in the carrier body; and the fiber exposure rate of the main surface of the carrier body is less than 50%, and the flatness of the carrier body near the periphery of the wafer holding hole is less than 5μm, and is obtained based on the difference between the maximum and minimum values of the thickness measurement value of the carrier body.

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