TWI872367B - Manufacturing method of semiconductor device and warpage balance tape - Google Patents

Abstract

A warpage balance tape includes a shrinkage layer and an adhesive layer. The material of the shrinkage layer includes polyetherimide, polyetheretherketone, or a combination thereof. The glass transition temperature of the shrinkage layer is lower than 250 degrees Celsius. The melting point temperature of the shrinkage layer is higher than 300 degrees Celsius. The adhesive layer is formed on the shrinkage layer. The raw materials for forming the adhesive layer include oligomers and monomers. The oligomers have a weight average molecular weight ranging from 100,000 to 2,000,000.

Description

Method for manufacturing semiconductor device and warp-balancing tape

The present invention relates to a warp-balancing tape, and more particularly to a method for manufacturing a semiconductor device and the warp-balancing tape used in the manufacturing method.

At present, semiconductor materials are widely used in many electronic devices, such as microelectromechanical systems, complementary metal oxide semiconductors, three-dimensional integrated circuits (3DIC), memory chips, logic chips, power chips, radio frequency chips, diodes, interposers, etc. With the advancement of technology, semiconductor devices continue to develop in the direction of being thin, small, high-performance, and energy-saving.

When manufacturing semiconductor devices, it is usually necessary to perform many deposition processes. Deposition processes are used, for example, to deposit metals, semiconductors, or insulating layers. In order to reduce the production cost of semiconductor devices, many manufacturers are committed to developing methods that can perform deposition processes on a large area. However, as the substrate used in the deposition process increases, the possibility of the substrate warping after the deposition process also increases, thereby reducing the production yield.

The present invention provides a method for manufacturing a semiconductor device and a warp balancing tape, which can improve the problem of substrate warp and thus improve the production yield of the semiconductor device.

Some embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising the following steps: attaching at least one warp balancing tape to a first surface of a substrate, wherein each warp balancing tape includes a shrinkage layer and an adhesive layer. The material of the shrinkage layer includes polyetherimide, polyetheretherketone or a combination thereof. The adhesive layer is formed on the shrinkage layer. The raw materials for forming the adhesive layer include oligomers and monomers. The weight average molecular weight of the oligomer is between 100,000 and 2 million. The substrate and the warp balancing tape are heated, and a rewiring structure is formed on the second surface of the substrate. The substrate and the warp balancing tape are cooled, and the warp balancing tape shrinks in a first direction.

Some embodiments of the present invention provide a warp-balancing tape, including a shrinkage layer and an adhesive layer. The material of the shrinkage layer includes polyetherimide, polyetheretherketone or a combination thereof. The glass transition temperature of the shrinkage layer is lower than 250 degrees Celsius. The melting point temperature of the shrinkage layer is higher than 300 degrees Celsius. The adhesive layer is formed on the shrinkage layer. The raw materials for forming the adhesive layer include oligomers and monomers. The weight average molecular weight of the oligomer is between 100,000 and 2 million.

Based on the above, the problem of substrate warping after the rewiring structure is formed can be improved by shrinking the warp-balancing tape.

FIG1 is a schematic cross-sectional view of a warp-balancing tape according to an embodiment of the present invention. Referring to FIG1 , the warp-balancing tape 10 includes a shrink layer 12 and an adhesive layer 14. The adhesive layer 14 is formed on the shrink layer 12. In some embodiments, before the warp-balancing tape 10 is used, the warp-balancing tape 10 is disposed on a release layer 20, wherein the adhesive layer 14 faces the release layer 20. When the warp-balancing tape 10 is to be used, the warp-balancing tape 10 is torn off from the release layer 20, and then the warp-balancing tape 10 is attached to other locations.

In some embodiments, the material of the shrink layer 12 includes polyetherimide (PEI), polyetheretherketone (PEEK) or a combination thereof. In some embodiments, the shrink layer 12 is, for example, a rollable material layer, and the shrink layer 12 is manufactured by, for example, drawing, coating or other suitable processes. The thickness T1 of the shrink layer 12 is, for example, 25 microns to 200 microns.

In some embodiments, when the shrink layer 12 is heated to a temperature above the glass transition temperature (Tg), the amorphous molecular chains in the shrink layer 12 are easy to slide with each other, making the shrink layer 12 soft and flexible. Therefore, heating the shrink layer 12 to a temperature above the glass transition temperature helps to reduce the stress on the object after the shrink layer 12 expands. However, if the shrink layer 12 is heated to a temperature above the melting point (Tm), the shrink layer 12 will melt. Therefore, in a temperature range above the glass transition temperature of the shrink layer 12 and below the melting point of the shrink layer 12, the processing of the object can be better performed. Generally speaking, when manufacturing semiconductor devices, the process temperature when depositing a metal layer or an insulating layer is between 150 and 230 degrees Celsius. In some embodiments, the glass transition temperature of the shrinkage layer 12 is lower than 250 degrees Celsius, such as 130 degrees Celsius to 180 degrees Celsius or 180 degrees Celsius to 230 degrees Celsius. The melting point temperature of the shrinkage layer 12 is higher than 300 degrees Celsius. For example, the melting point temperature of the shrinkage layer 12 is 322.85 degrees Celsius.

Table 1 provides the glass transition temperature, thermal shrinkage rate and water content of polyimide (PI), polyetherimide and polyetheretherketone. The thermal shrinkage rate in Table 1 is measured by heating the polymer layer from room temperature (e.g. 23 degrees Celsius) to 150 degrees Celsius for 30 minutes, cooling it to room temperature, and then measuring the thermal shrinkage rate of the polymer layer, where the "+" value represents expansion and the "-" value represents shrinkage. Table 1 characteristic Test equipment ( conditions ) PI PEI PEEK Tg( ℃ ) DSC >300 217 143 Thermal expansion coefficient (ppm/ ℃ ) JIS K 7197/1991 20~30 (@100~200℃) 50~80 (@50~100℃) 30~70 (@50~100℃) Machine direction (MD) thermal shrinkage (%) JIS K 7133.1999 -0.029 -0.1 +0.1 Transverse direction (TD) thermal shrinkage (%) JIS K 7133.1999 -0.029 -0.1 -0.3 Moisture content (%) JIS K 7209-A/2000 (23℃ 24hrs) 1.6 0.6 0.2

From Table 1, it can be seen that polyimide has better heat resistance, while polyetherimide and polyetheretherketone have higher thermal shrinkage rate in the TD direction than polyimide. In order to make the warp balance tape 10 shrink sufficiently when it is cooled from high temperature to room temperature, polyetherimide or polyetheretherketone is preferably used as the material of the shrinkage layer 12. The shrinkage rate of polyimide is low and cannot achieve the effect of improving the process yield of the present invention.

In some embodiments, the raw materials for forming the adhesive layer 14 include oligomers, monomers, initiators, and additives. In some embodiments, the adhesive layer 14 is manufactured by, for example, coating or other suitable processes. The thickness T2 of the adhesive layer 14 is, for example, 20 microns to 100 microns. In some embodiments, the cured adhesive layer 14 includes acrylic resin or other suitable materials.

The oligomer constitutes the main body of the adhesive layer 14, and the oligomer determines the main viscosity of the adhesive layer 14. In some embodiments, in the raw materials of the adhesive layer 14, the weight ratio of the oligomer is greater than or equal to 40 wt%, for example, 40 wt%, 50 wt%, 60 wt%, 70 wt%, 80 wt% or any range from 40 wt% to 80 wt%. In some embodiments, the oligomer includes polyester acrylate, polyurethane acrylate, polyether acrylate or a combination thereof. Table 2 compares the properties of adhesive layers containing different oligomers. Table 2 Epoxy Acrylate Polyester acrylate Polyurethane acrylate Polyether acrylate Hardening rate quick middle slow middle Flexibility middle middle good Difference Elasticity Difference good good good Chemical resistance Excellent middle good middle hardness high middle Low Low Yellowing resistance Difference Difference middle Excellent

As can be seen from Table 2, in order to avoid the adhesive layer 14 being too hard, the oligomer in the adhesive layer 14 is preferably polyester acrylate, polyurethane acrylate, polyether acrylate or a combination thereof. In some embodiments, the higher the weight average molecular weight of the oligomer, the softer the texture of the adhesive layer 14. For example, in order to make the adhesive layer 14 soft, the weight average molecular weight of the oligomer is between 100,000 and 2,000,000, and preferably between 500,000 and 1,500,000.

It should be noted that Table 2 provides the effects of different oligomers on the properties of the adhesive layer 14, but it is not intended to limit the present application. In fact, the properties of the adhesive layer 14 may also vary due to other factors.

The monomers in the raw materials of the adhesive layer 14 are suitable for adjusting the viscosity and will participate in the polymerization reaction. The amount of monomers will also affect the performance of the adhesive layer 14 after curing. In some embodiments, in the raw materials of the adhesive layer 14, the weight ratio of the monomers is 20 wt% to 50 wt%, for example, 20 wt%, 30 wt%, 40 wt%, 50 wt% or any range from 20 wt% to 50 wt%. In some embodiments, the monomers include monofunctional monomers, difunctional monomers, multifunctional monomers or combinations thereof.

In some embodiments, the monofunctional monomer is, for example, Isodecyl acrylate (IDA), tetrahydrofurfuryl acrylate (THFA), isobornyl acrylate (IBOA) or 2-phenoxy ethyl acrylate (PHEA), wherein the chemical structures of Isodecyl acrylate, tetrahydrofurfuryl acrylate, isobornyl acrylate and 2-phenoxy ethyl acrylate are shown in the following chemical formulas 1, 2, 3 and 4, respectively. Chemical formula 1 Chemical formula 2 Chemical formula 3 Chemical formula 4

In some embodiments, the bifunctional monomer is, for example, hexanediol diacrylate (HDDA) or polyethylene glycol (600) diacrylate (PEG (600) DA), wherein the chemical structures of hexanediol diacrylate and polyethylene glycol (600) diacrylate are shown in Chemical Formula 5 and Chemical Formula 6, respectively. Chemical Formula 5 Chemical formula 6

In some embodiments, the multifunctional monomer is, for example, trimethylolpropane triacrylate (TMPTA) or dipentaerythritol hexaacrylate (DPHA), wherein the chemical structures of trimethylolpropane triacrylate and dipentaerythritol hexaacrylate are shown in Chemical Formula 7 and Chemical Formula 8, respectively. Chemical Formula 7 Chemical formula 8

Table 3 compares the effect of increasing the number of monomer functional groups on the properties of the adhesive layer 14 and the effect of increasing the chain length of the monomer on the properties of the adhesive layer 14. Table 3 Polymerization reaction rate hardness Shrinkage rate Adhesion Flexibility Chemical resistance Increased number of functional groups Increase Increase Increase Reduce Reduce Increase Increased chain length Reduce Reduce Reduce Increase Increase Reduce

It can be seen from Table 3 that in order to obtain an adhesive layer 14 with a relatively high shrinkage rate, the monomer is preferably a bifunctional monomer, a multifunctional monomer or a combination thereof. In some embodiments, a low molecular weight (e.g., a molecular weight of 100 to 1000) monomer is selected to dilute the raw materials of the adhesive layer 14. In addition, the low molecular weight monomer can also improve the wettability between the adhesive layer 14 and the shrinkage layer 12, and increase the chemical resistance of the adhesive layer 14 after curing.

It should be noted that Table 3 provides the effects of adjusting the monomer on the properties of the adhesive layer 14, but it is not intended to limit the present application. In fact, the properties of the adhesive layer 14 may also change due to other factors.

The initiator in the raw material of the adhesive layer 14 is suitable for initiating polymerization and bridging reactions. For example, one or more photoinitiators are used to cause monomers and oligomers to undergo polymerization and bridging reactions. In some embodiments, the photoinitiator includes a free radical photoinitiator. In some embodiments, in the raw material of the adhesive layer 14, the weight ratio of the photoinitiator is less than or equal to 10wt%, such as 9wt%, 8wt%, 7wt%, 6wt%, 5wt%, 4wt%, 3wt%, 2wt%, 1wt% or any value below 10wt%. In some embodiments, the photoinitiator is suitable for absorbing ultraviolet light to initiate polymerization reactions.

In some embodiments, polyester acrylate resin, polyurethane acrylate resin or polyether acrylate resin uses a free radical photoinitiator, such as 1-hydroxycyclohexyl phenyl ketone or phenyl bis(2,4,6-trimethylbenzoyl)-phosphine oxide, whose chemical structures are shown in Chemical Formula 9 and Chemical Formula 10 respectively. Chemical Formula 9 Chemical formula 10

In some embodiments, the raw materials of the adhesive layer 14 also include additives. The additives include, for example, surfactants, stabilizers, dyes, solvents or other materials. In some embodiments, the additives include, for example, conductive particles, conductive fibers, conductive polymers or other suitable conductive materials, so that the adhesive layer 14 has an anti-static function. In some embodiments, the additive includes a difunctional acrylic oligomer (such as an aliphatic urethane diacrylate oligomer), which can improve the bridging properties of the adhesive layer 14, further enhance the chemical resistance and heat resistance of the adhesive layer 14, and reduce the problem of residual glue generated after the adhesive layer 14 is torn off. In some embodiments, the additive includes a difunctional monomer (e.g., ethoxylated bisphenol A diacrylate, 1,6-hexanediol diacrylate, or a combination thereof), which can further enhance the bridging strength of the adhesive layer 14. In some embodiments, in the raw material of the adhesive layer 14, the weight ratio of the additive is 0wt% to 10wt%, such as 9wt%, 8wt%, 7wt%, 6wt%, 5wt%, 4wt%, 3wt%, 2wt%, 1wt% or any value less than 10wt%.

The release layer 20 can be any release material. For example, the release layer 20 is polyethylene terephthalate (PET), polyolefins (PO) or release paper. The thickness of the release layer 20 is, for example, 25 microns to 175 microns.

The adhesive layer 14 is located between the release layer 20 and the shrink layer 12. In some embodiments, after the release layer 20 is covered on the adhesive layer 14, the adhesive layer 14 is irradiated with light (such as ultraviolet light) to make the adhesive layer 14 adhere to the shrink layer 12 better.

In some embodiments, the raw materials for forming the adhesion layer include oligomers, monomers, photoinitiators, and additives, wherein the weight ratio of the oligomers is 52 wt% to 65 wt%, the weight ratio of the monomers is 20 wt% to 33 wt%, the weight ratio of the photoinitiators is less than 1% to 5 wt%, and the weight ratio of the additives is less than 1% to 10 wt%.

In the aforementioned embodiment, the oligomer includes polyurethane acrylate, the monomer includes isobornyl acrylate and 2-phenoxyethyl acrylate, the photoinitiator includes 1-hydroxycyclohexylphenyl ketone and diphenyl (2,4,6-trimethylbenzoyl) phosphine oxide, and the additive includes 1,6-hexanediol diacrylate.

Table 4 provides a comparison of the composition and relative shrinkage rate of Example 1, Example 2 and Example 3. It can be seen from Table 4 that the shrinkage layer of Example 1 has a larger relative shrinkage rate. Table 4 Composition Embodiment 1 Embodiment 1 Embodiment 2 Oligomer Polyurethane acrylate 55wt% 64 wt% 63 wt% Single Isobornyl acrylate 15 wt% 15 wt% 15 wt% Single 2-Phenoxyethyl acrylate 15 wt% 15 wt% 15 wt% Photoinitiator 1-Hydroxycyclohexylphenyl ketone 3 wt% 3 wt% 3 wt% Photoinitiator Diphenyl (2,4,6-trimethylbenzoyl) phosphine oxide 2 wt% 2 wt% 2 wt% Additives 1,6-Hexanediol diacrylate 10 wt% 1 wt% Additives Polydipentaerythritol hexaacrylate 2 wt% Relative shrinkage rate big Small middle

Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5 and Fig. 6 are cross-sectional schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 2B, Fig. 3B and Fig. 4B are top schematic diagrams of the structures of Fig. 2A, Fig. 3A and Fig. 4A, respectively.

2A and 2B, a substrate 100 is provided. The substrate 100 is, for example, a carrier substrate, and its material includes glass, semiconductor, metal or other suitable materials. The substrate 100 includes a first surface 100b and a second surface 100a opposite to the first surface 100b. In some embodiments, the thickness of the substrate 100 is 700 microns to 1100 microns. In some embodiments, the shape of the substrate 100 is rectangular, circular, elliptical or other geometric shapes.

At least one warp balancing tape (for example, the first warp balancing tape 10a) is attached to the first surface 100b of the substrate 100. The first warp balancing tape 10a includes a shrinkage layer 12 and an adhesive layer 14, and the shrinkage layer 12 is bonded to the substrate 100 through the adhesive layer 14. In this embodiment, the features of the first warp balancing tape 10a can be referred to the warp balancing tape 10 in FIG. 1 and the related description thereof, which will not be repeated here.

In this embodiment, the second surface 100a of the substrate 100 has a release layer 102. The first surface 100b is opposite to the second surface 100a. The release layer 102 includes, for example, an organic material. The method of forming the release layer 102 includes coating, scraping or other suitable processes. In some embodiments, the release layer 102 is formed after the first warp balancing tape 10a is attached to the substrate 100, but the present invention is not limited thereto.

In this embodiment, the first warp balancing tape 10a is attached to the first surface 100b of the substrate 100. Then, the first warp balancing tape 10a is cut along the cutting line CL on the substrate 100 so that the first warp balancing tape 10a is aligned with the substrate 100. In other words, in this embodiment, the first warp balancing tape 10a having an area (or width) larger than the substrate 100 is attached to the substrate 100, and then the first warp balancing tape 10a is cut so that the first warp balancing tape 10a and the substrate 100 have the same area (or width), but the present invention is not limited thereto. In other embodiments, the first warp-balancing tape 10 a is first cut into small pieces with an area (or width) smaller than or equal to that of the substrate 100 , and then the small pieces of the first warp-balancing tape 10 a are attached to the substrate 100 .

In some embodiments, after the first warp balancing tape 10a is attached to the substrate 100, the first warp balancing tape 10a is placed on a suction cup or other working platform (not shown). In some embodiments, the suction cup absorbs the shrinkage layer 12 of the first warp balancing tape 10a by electrostatic force, vacuum force or other means.

3A and 3B , the substrate 100 and the first warp balance tape 10 a are heated, and a redistribution structure RDL is formed on the second surface 100 a of the substrate 100 .

In some embodiments, the method of forming the redistribution structure RDL includes depositing multiple conductive layers 112, 122, 132, 142 and multiple insulating layers 110, 120, 130 on the second surface 100a of the substrate 100. In this embodiment, the conductive layer 112 and the insulating layer 110 are deposited on the release layer 102. In some embodiments, the bottom conductive layer 112 is an under bump metallurgy (UBM). In some embodiments, a micro bump 152 is formed on the top conductive layer 142.

In some embodiments, the method of depositing the conductive layers 112, 122, 132, 142 includes, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, sputtering, or other suitable deposition processes. For example, in some embodiments, a seed layer is first formed by physical vapor deposition, and then a metal material is formed on the seed layer by electroplating, and finally the seed layer and the metal material thereon are patterned by lithography and etching processes to obtain a conductive layer. In some embodiments, the method of depositing the insulating layers 110, 120, 130 includes, for example, physical vapor deposition, chemical vapor deposition, spin coating or other suitable deposition processes. In some embodiments, the pattern of the insulating layer is defined by a lithography process and an etching process.

In some embodiments, the process of forming the conductive layers 112, 122, 132, 142 and the insulating layers 110, 120, 130 includes a high temperature process (eg, a process with a temperature higher than 150 degrees Celsius).

During or after forming the RDL structure, the substrate 100, the RDL structure, and the first warp balance tape 10a are cooled, for example, from a high temperature of more than 150 degrees Celsius to room temperature. Since the thermal expansion coefficient of the conductive layers 112, 122, 132, 142 and/or the insulating layers 110, 120, 130 is higher than that of the substrate 100, when the substrate 100 is cooled from high temperature to room temperature, the second surface 100a of the substrate 100 may produce a shrinkage force that causes the substrate 100 to bend upward due to the shrinkage of the conductive layers 112, 122, 132, 142 and the insulating layers 110, 120, 130. In some embodiments, the redistribution structure RDL shrinks in the first direction D1 and generates a shrinkage force F1, and shrinks in the second direction D2 and generates a shrinkage force F2, as shown in FIG. 3B .

In some embodiments, since the thermal expansion coefficient of the first warp-balancing tape 10a is higher than that of the substrate 100, the first warp-balancing tape 10a contracts in the first direction D1 and the second direction D2, respectively, and generates contraction forces F1' and F2' (not shown in the figure). The contraction forces F1' and F2' can prevent the contraction forces F1 and F2 from causing the substrate 100 to tend to warp upward, or even to tend to warp downward. In some embodiments, the thermal expansion coefficient of the contraction layer 12 of the first warp-balancing tape 10a during the high-temperature process is greater than that of the substrate 100 during the high-temperature process. In some embodiments, the thermal expansion coefficient of the shrinkage layer 12 of the first warp-balancing tape 10a during a high temperature process is greater than the thermal expansion coefficients of the conductive layers 112, 122, 132, 142 and the insulating layers 110, 120, 130 during a high temperature process.

It should be noted that this embodiment takes the formation of four conductive layers and three insulating layers as an example, but the present invention is not limited thereto. The number of conductive layers and insulating layers can be adjusted according to actual needs.

Table 5 provides the effects of using a warp balancing tape comprising a shrink layer 12 of different materials (polyimide (PI), polyetherimide (PEI), and polyetheretherketone (PEEK)) on different processes. Table 5 Process Reference characteristics/ impact PI PEI PEEK Lamination process of stress balance film Operational/equipment investment cost High equipment cost Low equipment cost Low equipment cost PVD Vacuum Process Moisture absorption rate/vacuum value Low vacuum value Vacuum value High vacuum value Electroplating process of metal layer Chemical resistance/pollution plating bath Excellent chemical resistance Excellent chemical resistance Excellent chemical resistance High temperature deposition process for insulating layer Temperature resistance/shrinkage rate of shrinkage layer Low shrinkage Shrinkage rate High shrinkage rate Etching process Acid resistance/etching agent resistance Excellent acid resistance Excellent acid resistance Excellent acid resistance Photoresist removal process Alkali resistance/stripping resist resistance Good alkali resistance Good alkali resistance Excellent alkali resistance

It can be seen from Table 5 that when polyetherimide or polyetheretherketone is used as the shrinkage layer 12, the warp-balancing tape can have a better shrinkage rate, thereby generating larger shrinkage forces F1' and F2', thereby preventing the substrate 100 from warping upward. In addition, when polyetherimide or polyetheretherketone is used as the shrinkage layer 12, since polyetherimide or polyetheretherketone has a lower moisture absorption rate, a higher vacuum degree can be obtained in the vacuum process, so that the adhesion of the thin film (such as the seed layer) formed by the PVD process is higher.

4A and 4B , one or more chips 210 are bonded to the micro bumps 152. For example, pads (not shown) of the chip 210 are connected to the redistribution structure RDL through the micro bumps 152.

The bottom filling material 220 is formed around the pads of the chip 210 and the micro-bumps 152 to protect the contacts between the chip 210 and the redistribution structure RDL. Then, the encapsulation material 230 is formed to encapsulate the chip 210 on the redistribution structure RDL. The encapsulation material 230 contacts the chip 210 and the redistribution structure RDL.

5 , the substrate 100 and the first warp balancing tape 10 a are taken up from the suction cup or the working platform, and then the first warp balancing tape 10 a is removed from the substrate 100 .

6 , the chip 210 and the redistribution structure RDL are removed from the substrate 100 . In some embodiments, the release layer 102 is irradiated with a laser to separate the conductive layer 112 and the insulating layer 110 of the redistribution structure RDL from the substrate 100 .

Next, a connection terminal 240 is formed on the conductive layer 112. The connection terminal 240 is, for example, a solder ball or other suitable material. At this point, the semiconductor device 1 is substantially completed. In some embodiments, a single separation process is performed to separate the semiconductor device 1 into a plurality of package structures, but the present invention is not limited thereto.

In this embodiment, one warp balancing tape is used in the process of manufacturing the semiconductor device 1, but the present invention is not limited thereto. In other embodiments, multiple warp balancing tapes may be used in the process of manufacturing the semiconductor device 1.

FIG7 is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. It should be noted that the embodiment of FIG7 uses the component numbers and partial contents of the embodiments of FIG2A to FIG4B, FIG5, and FIG6, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The steps of FIG. 7 correspond to the steps of FIG. 3A , and the main difference between the embodiment of FIG. 7 and the embodiment of FIG. 3A is that in the embodiment of FIG. 7 , the first warp balancing tape 10a and the second warp balancing tape 10b are attached to the first surface 100b of the substrate 100. Specifically, after the first warp balancing tape 10a is attached to the first surface 100b of the substrate 100, the second warp balancing tape 10b is attached to the shrinkage layer 12 of the first warp balancing tape 10a.

In the present embodiment, since the first warp balancing tape 10a and the second warp balancing tape 10b will shrink after being cooled from the high temperature process, attaching the first warp balancing tape 10a and the second warp balancing tape 10b to the first surface 100b of the substrate 100 can enhance the shrinkage force F1' generated by the first warp balancing tape 10a and the second warp balancing tape 10b, and further offset the influence of the shrinkage force F1 generated when the redistribution structure RDL is cooled down on the substrate 100.

In some embodiments, the shrinkage layer 12 of the first warp balancing tape 10a and the shrinkage layer 12 of the second warp balancing tape 10b may have different materials and/or different thicknesses, so as to adjust the shrinkage rates of the first warp balancing tape 10a and the second warp balancing tape 10b when the temperature drops.

FIG8 is a bottom view schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. It must be noted that the embodiment of FIG8 uses the component numbers and partial contents of the embodiments of FIG2A to FIG4B, FIG5, and FIG6, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

8 , the first warp balancing tape 10a, the second warp balancing tape 10b, the third warp balancing tape 10c, and the fourth warp balancing tape 10d are attached to the first surface of the substrate 100. In this embodiment, the first warp balancing tape 10a, the second warp balancing tape 10b, the third warp balancing tape 10c, and the fourth warp balancing tape 10d are directly in contact with the first surface of the substrate 100.

Fig. 9A is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 9B is a bottom view schematic diagram of the structure of Fig. 9A.

It must be noted that the embodiment of FIG. 9A and FIG. 9B uses the component numbers and part of the content of the embodiment of FIG. 2A to FIG. 4B, FIG. 5, and FIG. 6, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, and will not be repeated here.

9A and 9B , the first warp balancing tape 10a and the second warp balancing tape 10b are attached to the first surface 100b of the substrate 100. In this embodiment, the first warp balancing tape 10a and the second warp balancing tape 10b are directly in contact with the first surface 100b of the substrate 100.

In some embodiments, the short side of the first warp balancing tape 10a and the short side of the second warp balancing tape 10b are parallel to the first direction D1, and the long side of the first warp balancing tape 10a and the long side of the second warp balancing tape 10b are parallel to the second direction D2. In some embodiments, the machine direction MD (film drawing direction) of the first warp balancing tape 10a and the second warp balancing tape 10b is parallel to the second direction D2, and the transverse direction TD of the first warp balancing tape 10a and the second warp balancing tape 10b is parallel to the first direction D1. In some embodiments, since the warp balancing tape has different shrinkage rates in the machine direction MD and the transverse direction TD, the arrangement directions of the first warp balancing tape 10a and the second warp balancing tape 10b can be adjusted according to the requirements. For example, when the shrinkage force generated by the subsequently formed rewiring structure in the first direction D1 is expected to be greater than the shrinkage force generated in the second direction D2, if the shrinkage force of the warp balancing tape in the transverse direction TD is greater, the transverse direction TD of the warp balancing tape is made parallel to the first direction D1. Furthermore, when the shrinkage force generated by the subsequently formed redistribution structure in the second direction D2 is expected to be greater than the shrinkage force generated in the first direction D1, if the shrinkage force of the warp balancing tape in the transverse direction TD is greater, the transverse direction TD of the warp balancing tape is made parallel to the second direction D2.

Fig. 10A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 10B is a schematic bottom view of the structure of Fig. 10A.

It should be noted that the embodiment of FIG. 10A and FIG. 10B uses the component numbers and part of the content of the embodiment of FIG. 9A and FIG. 9B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, and will not be repeated here.

In the embodiment of FIGS. 10A and 10B , after the first warp balancing tape 10a and the second warp balancing tape 10b are attached to the first surface 100b of the substrate 100 , the third warp balancing tape 10c and the fourth warp balancing tape 10d are attached to the first warp balancing tape 10a and the second warp balancing tape 10b .

In this embodiment, the long side of the third warp balancing tape 10c and the long side of the fourth warp balancing tape 10d are parallel to the short side of the first warp balancing tape 10a and the short side of the second warp balancing tape 10b, but the present invention is not limited thereto. In other embodiments, the long side of the third warp balancing tape 10c and the long side of the fourth warp balancing tape 10d are parallel to the long side of the first warp balancing tape 10a and the long side 10b of the second warp balancing tape.

1: semiconductor device 10: warp balance tape 10a: first warp balance tape 10b: second warp balance tape 10c: third warp balance tape 10d: fourth warp balance tape 12: shrinkage layer 14: adhesive layer 100: substrate 100b: first surface 100a: second surface 102: release layer 110,120,130: insulating layer 112,122,132,142: conductive layer 152: microbump 210: chip 220: bottom filling material 230: packaging material 240: connection terminal D1: first direction D2: Second direction F1, F2, F1’: Contraction force MD: Mechanical direction RDL: Redistribution structure T1, T2: Thickness TD: Transverse direction

FIG. 1 is a schematic cross-sectional view of a warp-balancing tape according to an embodiment of the present invention. FIG. 2A, FIG. 3A, FIG. 4A, FIG. 5 and FIG. 6 are schematic cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2B, FIG. 3B and FIG. 4B are schematic top views of the structures of FIG. 2A, FIG. 3A and FIG. 4A, respectively. FIG. 7 is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 8 is a schematic bottom view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9A is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9B is a schematic bottom view of the structure of FIG. 9A. FIG. 10A is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 10B is a bottom view schematic diagram of the structure of FIG. 10A .

10: Warp balance tape

12: Contraction layer

14: Adhesive layer

20: Release layer

T1, T2: thickness

Claims (5)

A method for manufacturing a semiconductor device comprises: attaching at least one warp balancing tape to a first surface of a substrate, wherein each of the warp balancing tapes comprises: a shrinkage layer, wherein the shrinkage layer is made of polyetherimide, polyetheretherketone or a combination thereof; and an adhesive layer formed on the shrinkage layer, wherein the adhesive layer is made of an oligomer and a monomer, wherein the weight average molecular weight of the oligomer is between 100,000 and 2,000,000, wherein the adhesive layer is located between the substrate and the shrinkage layer, and the substrate comprises glass, a semiconductor or a metal; and The at least one warp balancing tape is heated and a rewiring structure is formed on the second surface of the substrate; and the substrate and the at least one warp balancing tape are cooled, and the at least one warp balancing tape shrinks in a first direction, wherein attaching the at least one warp balancing tape to the first surface of the substrate includes: attaching the first warp balancing tape and the second warp balancing tape to the first surface of the substrate; and attaching the third warp balancing tape and the fourth warp balancing tape to the first warp balancing tape and the second warp balancing tape. The manufacturing method as described in claim 1, wherein: when the substrate and the at least one warp balancing tape are cooled, the rewiring structure shrinks in the first direction, and the at least one warp balancing tape shrinks in the first direction. The manufacturing method as described in claim 1, wherein attaching the at least one warp balancing tape to the first surface of the substrate comprises: attaching a first warp balancing tape to the first surface of the substrate; and cutting the first warp balancing tape on the substrate. A manufacturing method as described in claim 1, wherein the long side of the third warp balancing tape and the long side of the fourth warp balancing tape are parallel to the long side of the first warp balancing tape and the long side of the second warp balancing tape. A manufacturing method as described in claim 1, wherein the long side of the third warp balancing tape and the long side of the fourth warp balancing tape are parallel to the short side of the first warp balancing tape and the short side of the second warp balancing tape.

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