TWI871964B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure includes a semiconductor substrate, an insulating layer, a first conductive pillar, a low-k dielectric layer, and a second conductive pillar. The insulating layer covers the semiconductor substrate. The first conductive pillar is embedded in the semiconductor substrate and the insulating layer. The low-k dielectric layer covers the insulating layer. The second conductive pillar penetrates the low-k dielectric layer and the insulating layer and is in contact with the first conductive pillar, in which the second conductive pillar has a first portion in the low-k dielectric layer and a second portion in the insulating layer, and the second portion has a width tapering from top to bottom.

Description

Semiconductor structure and method for manufacturing the same

The present disclosure relates to a semiconductor structure and a method for manufacturing the same.

Semiconductor components are indispensable for many modern applications. With the advancement of electronic technology, the size of semiconductor components has become smaller and smaller, while providing better functions and containing a larger number of integrated circuits. Semiconductor components are miniaturized, and semiconductor components with different types, sizes and functions are integrated and packaged in a single module. Moreover, many manufacturing steps can be performed to integrate various types of semiconductor devices. However, the manufacturing and integration of these semiconductor components involve many complex steps. The increased complexity of manufacturing and integration of these semiconductor components may cause defects. For example, when forming an opening in a multi-layer insulating layer, the sidewalls of the opening may be uneven because the etching rate of the etchant is different for different materials, which may cause a void to exist between the conductive structure filled in the opening and the substrate, resulting in reduced circuit reliability. In addition, the conductive structure filled in the recessed sidewalls of adjacent openings will increase the resistive-capacitive delay (RC delay) between the conductive structures due to the closer distance. Therefore, there is an urgent need to improve the process of manufacturing semiconductor components to overcome the above defects and enhance their performance.

The present disclosure provides a semiconductor structure, which includes a semiconductor substrate, an insulating layer, a first conductive column, a low-k dielectric layer and a second conductive column. The insulating layer covers the semiconductor substrate. The first conductive column is embedded in the semiconductor substrate and the insulating layer. The low-k dielectric layer covers the insulating layer. The second conductive column passes through the low-k dielectric layer and the insulating layer and contacts the first conductive column. The second conductive column has a first portion located in the low-k dielectric layer and a second portion located in the insulating layer, and the width of the second portion gradually decreases from top to bottom.

In some embodiments, the low-k dielectric layer has a k-value less than 3.5.

In some embodiments, the side walls of the first portion are substantially vertical.

In some embodiments, the insulating layer includes oxide, and the low-k dielectric layer includes carbon-doped oxide (CDO).

The present disclosure provides a method for manufacturing a semiconductor structure, which includes the following operations. A semiconductor substrate, an insulating layer and a first conductive column are received, wherein the insulating layer is located on the semiconductor substrate, and the first conductive column is embedded in the semiconductor substrate and the insulating layer. A low-k dielectric layer is formed to cover the insulating layer. A patterned photoresist structure is formed on the low-k dielectric layer. The low-k dielectric layer and the insulating layer are etched by a plasma process to form a groove in the low-k dielectric layer and the insulating layer to expose a portion of the first conductive column, wherein the plasma process applies a source power and intermittently applies a bias power. A second conductive column is formed in the trench, wherein the second conductive column is electrically connected to the first conductive column.

In some embodiments, in the plasma process, the gas used to generate plasma includes carbon tetrafluoride (CF ₄ ), a suppressant, and a diluent gas.

In some embodiments, the flow ratio of carbon tetrafluoride, inhibitor and dilution gas is 3-4:1-3:1-2, and the flow rate of carbon tetrafluoride is higher than the flow rate of the inhibitor.

In some embodiments, the inhibitor comprises trifluoromethane.

In some embodiments, the power supply power is 1500 W to 5000 W, and the bias power is 100 W to 700 W.

In some embodiments, etching a low-k dielectric layer and an insulating layer by a plasma process includes: repeatedly performing an operation including: turning on a bias power supply for 0.2 seconds to 0.5 seconds to apply bias power, and turning off the bias power supply for 0.5 seconds to 0.8 seconds.

Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

The following multiple implementations are described and disclosed in detail with the attached drawings. For clarity, many practical details will be described together in the following description. However, it should be understood that these practical details are not intended to limit the content of this disclosure. In other words, in some implementations of the content of this disclosure, these practical details are not necessary. In addition, to simplify the drawings, some known structures and components will be shown in schematic form in the drawings.

Although a series of operations or steps are used below to illustrate the methods disclosed herein, the order in which these operations or steps are shown should not be construed as a limitation of the present disclosure. For example, certain operations or steps may be performed in a different order and/or simultaneously with other steps. Furthermore, not all operations, steps, and/or features shown must be performed to implement the present disclosure. Furthermore, each operation or step described herein may include a number of sub-steps or actions.

The present disclosure provides a method for manufacturing a semiconductor structure. Figures 1 to 7 are cross-sectional schematic diagrams of various embodiments of the present disclosure at intermediate stages of manufacturing a semiconductor structure.

As shown in FIG. 1 , a semiconductor substrate 110, an insulating layer 120 and a plurality of first conductive pillars 130 are received, wherein the insulating layer 120 is located on the semiconductor substrate 110, and the first conductive pillars 130 are embedded in the semiconductor substrate 110 and the insulating layer 120. A low-k dielectric layer 140 is formed to cover the insulating layer 120. A sacrificial layer 150 is formed to cover the low-k dielectric layer 140. A photoresist structure 160 is formed to cover the sacrificial layer 150. In some embodiments, the photoresist structure 160 includes a photoresist lower layer 162, an anti-reflective coating 164, and a photoresist layer 166, wherein the anti-reflective coating 164 covers the photoresist lower layer 162, and the photoresist layer 166 covers the anti-reflective coating 164. In some embodiments, forming the photoresist structure 160 includes: forming the photoresist lower layer 162 to cover the sacrificial layer 150. Forming the anti-reflective coating 164 to cover the photoresist lower layer 162. Forming the photoresist layer 166 having a hole H1 to cover the anti-reflective coating 164, so that a portion of the anti-reflective coating 164 is exposed through the hole H1. The photoresist structure 160 of the present disclosure is not limited to the above embodiments.

In some embodiments, the semiconductor substrate 110 includes an insulating layer 112, an insulating layer 114, and semiconductor elements disposed in the insulating layer 112 and the insulating layer 114. In some embodiments, the semiconductor substrate 110 includes a semiconductor element electrically connected to the first conductive pillar 130, such as a metal-oxide-semiconductor field-effect transistor 116 (MOSFET) embedded in the insulating layer 112, or a plurality of capacitors 118 of a dynamic random access memory (DRAM) embedded in the insulating layer 114. The capacitor 118 can be electrically connected to the first conductive pillar 130 via an upper electrode plate 119. The MOSFET can be connected to a peripheral circuit, for example. The capacitors 118 can be used as a cell array of a DRAM.

In some embodiments, the insulating layer 120 includes an oxide (e.g., silicon dioxide, doped silicon oxide, silicon alkoxide), silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, undoped silicate glass, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), or a combination thereof. For example, tetraethoxysilane (TEOS) can be used as a precursor for forming silicon dioxide. In some embodiments, the dielectric constant of the low-k dielectric layer 140 is less than or equal to 3.5. For example, the dielectric constant is between 2.4 and 3.5, such as 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.0, 3.1, 3.2, 3.3, 3.4 or 3.5. In some embodiments, the low-k dielectric layer 140 includes a carbon-doped oxide (CDO), such as a black diamond (BD) layer. Compared to general insulating materials, such as silane oxide, the low-k dielectric layer 140 can reduce the RC delay between conductive structures. In some embodiments, the sacrificial layer 150 includes an insulating oxide, such as silane oxide, silicon dioxide or a combination thereof. The sacrificial layer 150 can prevent the low-k dielectric layer 140 (eg, BD) from contacting oxygen. In other embodiments, the sacrificial layer 150 can be referred to as a capping layer.

As shown in FIGS. 2 and 3 , a patterned photoresist structure 160B is formed on the sacrificial layer 150, wherein the patterned photoresist structure 160B has a hole H3 exposing the sacrificial layer 150. First, referring to FIG. 2 , the photoresist pattern is transferred to the anti-reflective coating 164 through the photoresist layer 166 having the hole H1. More specifically, the anti-reflective coating 164 is etched to form a hole H2 in the photoresist layer 166 and the anti-reflective coating 164. The patterned photoresist structure 160A includes a photoresist lower layer 162, an anti-reflective coating 164, and a photoresist layer 166, and has the hole H2. In some embodiments, the anti-reflective coating 164 is etched by plasma. In some embodiments, the pressure for etching the anti-reflective coating 164 is 5 mTorr to 15 mTorr, such as 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15 mTorr. In some embodiments, the power for etching the anti-reflective coating 164 is 350 W to 1050 W, such as 350, 400, 500, 600, 700, 800, 900, 1000 or 1050 W. In some embodiments, no bias is applied during plasma etching. In some embodiments, the gas used to generate plasma includes carbon tetrafluoride (CF ₄ ) and trifluoromethane (CHF ₃ ). In some embodiments, the gas further includes oxygen.

Referring to FIG. 3 , the photoresist lower layer 162 exposed through the hole H2 is etched to form a hole H3 in the photoresist layer 166, the anti-reflective coating 164, and the photoresist lower layer 162. In other words, after etching the photoresist lower layer 162, a patterned photoresist structure 160B having the hole H3 is formed. In some embodiments, the photoresist lower layer 162 is etched by plasma. In some embodiments, the pressure for etching the photoresist lower layer 162 is 1.5 mTorr to 10 mTorr, such as 1.5, 2, 4, 6, 8, or 10 mTorr. In some embodiments, the power of the power source for etching the photoresist lower layer 162 is 500 W to 1500 W, such as 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400 or 1500 W. In some embodiments, the gas used to generate plasma includes oxygen, hydrogen and nitrogen. In some embodiments, the gas further includes a diluent gas, such as argon.

4, the sacrificial layer 150 exposed through the hole H3 is etched to expose the low-k dielectric layer 140. During the etching process, the top photoresist layer 166 may be removed, as shown in FIG. 4. After etching the sacrificial layer 150, a hole H4 is formed in the anti-reflective coating layer 164, the photoresist lower layer 162, and the sacrificial layer 150. In some embodiments, the sacrificial layer 150 is etched by plasma. In some embodiments, the pressure for etching the sacrificial layer 150 is 5 mTorr to 20 mTorr, such as 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 or 20 mTorr. In some embodiments, the power for etching the sacrificial layer 150 is 200 W to 2000 W, such as 200, 400, 600, 800, 1000, 1200, 1400, 1600, 1800 or 2000 W. In some embodiments, no bias is applied during plasma etching. In some embodiments, the gas used to generate plasma includes carbon tetrafluoride (CF ₄ ) and trifluoromethane (CHF ₃ ). In some embodiments, the gas further includes a diluent gas, such as argon.

As shown in FIG. 5 , the low-k dielectric layer 140 and the insulating layer 120 exposed through the hole H4 are etched by a plasma process, and a trench T is formed in the low-k dielectric layer 140 and the insulating layer 120 to expose a portion of the first conductive pillar 130. During the etching process, the top anti-reflective coating 164 and a portion of the photoresist lower layer 162 may be removed, as shown in FIG. 5 . The plasma process applies power and intermittently applies bias power, in other words, the plasma process intermittently applies a pulse bias. The trench T has a first trench T1 located in the low-k dielectric layer 140 and a second trench T2 located in the insulating layer 120. The sidewalls of the first trench T1 are substantially vertical. The "sidewalls are substantially vertical" herein includes two states: the sidewalls are vertical and the sidewalls are slightly inclined. The overall aperture of the first trench T1 may vary slightly, and the aperture may decrease from top to bottom. The aperture of the second trench T2 decreases from top to bottom. In other words, the second trench T2 substantially has a tapered profile. In some embodiments, the angle A between the bottom surface of the second trench T2 and the sidewalls is 75 degrees to 85 degrees, such as 75, 76, 77, 78, 79, 80, 81, 82, 83, 84 or 85 degrees, but is not limited thereto. In some embodiments, an angle B between the sidewall of the first trench T1 and the sidewall of the second trench T2 is 155 to 170 degrees, for example, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169 or 170 degrees, but is not limited thereto. When the etching rate of the low-k dielectric layer 140 by the plasma is higher than the etching rate of the insulating layer 120, the intermittent application of bias power during the plasma etching can reduce the impact of the plasma on the low-k dielectric layer 140, thereby preventing the sidewall of the first trench T1 of the low-k dielectric layer 140 from being recessed, thereby making it difficult for a void to appear between the conductive structure to be filled in later and the sidewall. In other words, by intermittently applying bias power, the first trench T1 with a substantially similar aperture size as shown in FIG. 5 can be formed. Accordingly, the shape of the trench T can facilitate the filling of the conductive structure, and the semiconductor structure of the present disclosure can have good electrical performance and reliability, and the RC delay between the conductive structures in the adjacent trenches T will not increase. On the other hand, assuming that the bias power is not applied intermittently during the plasma etching, since the etching rate of the plasma for the low-k dielectric layer 140 (e.g., BD layer) is higher than the etching rate for the insulating layer 120 (e.g., silicon dioxide layer), the sidewall of the trench in the low-k dielectric layer 140 may be concave, and it is impossible to form a profile that allows the conductive material to be easily filled. The recessed trench sidewalls reduce the distance between the conductive structures in the subsequent adjacent trenches, resulting in an increase in RC delay, which has an adverse effect on the electrical performance of the semiconductor structure.

In some embodiments, the power supply power is 1500 W to 5000 W, such as 1500, 2000, 2500, 3000, 3500, 4000, 4500 or 5000 W. The power supply frequency is, for example, 60 MHz. In some embodiments, the bias power is 100 W to 700 W, such as 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650 or 700 W. The bias power supply frequency is, for example, 2 MHz. In some embodiments, etching the low-k dielectric layer 140 and the insulating layer 120 by a plasma process includes: repeatedly performing an operation, the operation including: turning on a bias power supply for 0.2 seconds to 0.5 seconds to apply bias power, and turning off the bias power supply for 0.5 seconds to 0.8 seconds. The on time is, for example, 0.2, 0.3, 0.4, or 0.5 seconds. The off time is, for example, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, or 0.8 seconds. In some embodiments, the pressure of the etching process is 5 mTorr to 20 mTorr, for example, 5, 10, 15, or 20 mTorr. However, the plasma process parameters of the present disclosure are not limited thereto, and the plasma process parameters can be adjusted according to the material and thickness of the low-k dielectric layer 140 and the insulating layer 120.

In some embodiments, in the plasma process, the gas used to generate plasma includes an etchant, an inhibitor, and a diluent gas. In some embodiments, the etchant includes carbon tetrafluoride (CF ₄ ). In some embodiments, the flow ratio of carbon tetrafluoride, inhibitor, and diluent gas is 3~4:1~3:1~2, and the flow rate of carbon tetrafluoride is higher than the flow rate of the inhibitor. In some embodiments, the inhibitor includes trifluoromethane (CHF ₃ ). In some embodiments, the flow rate of the gas is 50 sccm to 500 sccm, for example, 50, 100, 150, 200, 250, 300, 350, 400, 450, or 500 sccm. In some embodiments, in the plasma process, the diluent gas includes nitrogen, argon, or a combination thereof. When the etching rate of the low-k dielectric layer 140 by plasma is higher than the etching rate of the insulating layer 120, during the plasma etching, the inhibitor can adhere to the sidewall of the trench T, reducing the erosion of the low-k dielectric layer 140 by plasma, avoiding the sidewall of the first trench T1 of the low-k dielectric layer 140 from being recessed, thereby making it difficult for voids to appear between the conductive structure filled in later and the sidewall. Accordingly, the semiconductor structure of the present disclosure can have good electrical performance and reliability, and the RC delay between the conductive structures in adjacent trenches T will not increase.

For example, the low-k dielectric layer 140 and the insulating layer 120 can be etched by a plasma process, wherein the low-k dielectric layer 140 is a BD layer and the insulating layer 120 is a silicon dioxide layer. The gas used to generate plasma includes carbon tetrafluoride, trifluoromethane and nitrogen. The plasma process applies a power supply of 1500 W to 5000 W, and intermittently applies a bias power of 100 W to 700 W. For example: repeatedly performing an operation, the operation includes: turning on the bias power for 0.2 seconds to 0.5 seconds to apply the bias power, and turning off the bias power for 0.5 seconds to 0.8 seconds.

In some embodiments, as shown in FIG. 5 , a portion of the first conductive pillar 130 protrudes from the insulating layer 120. In other words, a portion of the sidewall of the first conductive pillar 130 is exposed through the trench T. In other embodiments, the upper surface of the first conductive pillar 130 is substantially coplanar with the insulating layer 120 (not shown).

As shown in FIGS. 6 to 7 , a second conductive column 620 is formed in the trench T, wherein the second conductive column 620 is electrically connected to the first conductive column 130. Referring to FIG. 6 , the photoresist lower layer 162 is removed to form a conductive layer 610 to fill the trenches in the insulating layer 120, the low-k dielectric layer 140, and the sacrificial layer 150, and to cover the upper surface of the sacrificial layer 150. In some embodiments, the conductive layer 610 is formed by electroplating. In some embodiments, the conductive layer 610 is a metal layer. For example, the conductive layer 610 includes copper, cobalt, tungsten, ruthenium, platinum, nickel, combinations thereof, or other suitable metal materials. In some embodiments, before forming the conductive layer 610, a barrier layer (not shown) is formed to cover the insulating layer 120, the low-k dielectric layer 140, and the sacrificial layer 150, so that the barrier layer may be disposed between the conductive layer 610 and the first conductive pillar 130. The barrier layer may include a metal, an alloy, or a metal stack, such as titanium, tantalum, titanium nitride, tantalum nitride, or a combination thereof.

Referring to FIG. 7 , a planarization process is performed to remove a portion of the conductive layer 610 and the sacrificial layer 150 to form the semiconductor structure 700 shown in FIG. 7 . The planarization process is, for example, chemical-mechanical polishing (CMP). In some embodiments, the planarization process removes a portion of the low-k dielectric layer 140.

As shown in FIG. 7 , the semiconductor structure 700 includes a semiconductor substrate 110, a first conductive pillar 130, an insulating layer 120, a low-k dielectric layer 140, and a second conductive pillar 620. The first conductive pillar 130 is embedded in the semiconductor substrate 110, wherein a portion of the first conductive pillar 130 protrudes from the upper surface S1 of the semiconductor substrate 110. The insulating layer 120 covers the first conductive pillar 130 and the semiconductor substrate 110. The low-k dielectric layer 140 covers the insulating layer 120, wherein the trench T passes through the low-k dielectric layer 140 and the insulating layer 120, exposing a portion of the first conductive pillar 130, the trench T has a first trench T1 located in the low-k dielectric layer 140 and a second trench T2 located in the insulating layer 120, the sidewall of the first trench T1 is substantially vertical, and the aperture of the second trench T2 decreases from top to bottom. The second conductive pillar 620 is located in the trench T and is electrically connected to the first conductive pillar 130.

In some embodiments, as shown in FIG. 7 , a portion of the first conductive pillar 130 is embedded in the second conductive pillar 620. In other embodiments, the upper surface of the first conductive pillar 130 is substantially coplanar with the insulating layer 120 (not shown).

In summary, the present disclosure discloses a semiconductor structure and a method for manufacturing the same. When etching trenches in an insulating layer and a low-k dielectric layer, when the etching rate of the plasma for the low-k dielectric layer is higher than the etching rate for the insulating layer, the sidewalls of the trenches in the low-k dielectric layer can be prevented from being recessed by applying bias power intermittently during the plasma process, thereby forming a trench having substantially vertical sidewalls. Thus, the shape of the trenches disclosed in the present disclosure can facilitate the filling of conductive structures, making it difficult for voids to appear between conductive columns and sidewalls, and preventing the resistance and capacitance delays between adjacent conductive columns from increasing. The semiconductor structure disclosed herein can have good electrical performance and reliability.

Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It is obvious to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the attached patent applications.

110: semiconductor substrate 112, 114, 120: insulating layer 116: metal oxide semiconductor field effect transistor 118: capacitor 119: upper electrode 130: first conductive column 140: low dielectric constant dielectric layer 150: sacrificial layer 160: photoresist structure 160A, 160B: patterned photoresist structure 162: photoresist lower layer 164: anti-reflective coating 166: photoresist layer 610: conductive layer 620: second conductive column 700: semiconductor structure A, B: angle H1, H2, H3, H4: hole S1: upper surface T: trench T1: First groove T2: Second groove

By reading the detailed description of the following implementation methods and referring to the attached figures, the present disclosure can be more fully understood. Figures 1 to 7 are cross-sectional schematic diagrams of various implementation methods according to the present disclosure at the intermediate stage of manufacturing a semiconductor structure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

110:Semiconductor substrate

112, 114, 120: Insulation layer

116: Metal oxide semiconductor field effect transistor

118: Capacitor

119: Upper electrode plate

130: First conductive column

140: Low-k dielectric layer

620: Second conductive column

700:Semiconductor structure

S1: Upper surface

T: Groove

T1: First groove

T2: Second groove

Claims (10)

A semiconductor structure includes: a semiconductor substrate; an insulating layer covering the semiconductor substrate; a first conductive column embedded in the semiconductor substrate and the insulating layer; a low-k dielectric layer covering the insulating layer; and a second conductive column passing through the low-k dielectric layer and the insulating layer and contacting the first conductive column, wherein the second conductive column has a first portion located in the low-k dielectric layer and a second portion located in the insulating layer, and a width of the second portion gradually decreases from top to bottom. A semiconductor structure as described in claim 1, wherein a dielectric constant of the low-k dielectric layer is less than 3.5. A semiconductor structure as described in claim 1, wherein a side wall of the first portion is substantially vertical. A semiconductor structure as described in any one of claims 1 to 3, wherein the insulating layer comprises an oxide and the low-k dielectric layer comprises a carbon-doped oxide. A method for manufacturing a semiconductor structure includes: receiving a semiconductor substrate, an insulating layer and a first conductive column, wherein the insulating layer is located on the semiconductor substrate, and the first conductive column is embedded in the semiconductor substrate and the insulating layer; forming a low-k dielectric layer to cover the insulating layer; forming a patterned photoresist structure on the low-k dielectric layer; etching the low-k dielectric layer and the insulating layer by a plasma process, and forming a photoresist structure on the low-k dielectric layer and the insulating layer; A trench is formed in the insulating layer to expose a portion of the first conductive column, wherein the plasma process applies a power source and intermittently applies a bias power; and a second conductive column is formed in the trench, wherein the second conductive column passes through the low-k dielectric layer and the insulating layer, contacts the first conductive column, and has a first portion located in the low-k dielectric layer and a second portion located in the insulating layer, and a width of the second portion gradually decreases from top to bottom. The method as described in claim 5, wherein in the plasma process, the gas used to generate a plasma includes carbon tetrafluoride, an inhibitor and a diluent gas. The method as described in claim 6, wherein the flow ratio of the carbon tetrafluoride, the inhibitor and the dilution gas is 3~4:1~3:1~2, and the flow rate of the carbon tetrafluoride is higher than the flow rate of the inhibitor. A method as described in claim 6 or claim 7, wherein the inhibitor comprises trifluoromethane. The method as described in claim 5, wherein the power source power is 1500W to 5000W, and the bias power is 100W to 700W. The method as described in claim 5, wherein etching the low-k dielectric layer and the insulating layer by the plasma process includes: repeatedly performing an operation, the operation including: turning on a bias power supply for 0.2 seconds to 0.5 seconds to apply the bias power, and turning off the bias power supply for 0.5 seconds to 0.8 seconds.

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