TWI871875B - Tiled display panel - Google Patents

Abstract

A tiled display panel is provided. The tiled display panel includes a plurality of substrates, a plurality of liquid crystal pixels, a plurality of LED pixels, a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines. Each substrate has a display area and a border area. The liquid crystal pixels are arranged in the display area. The LED pixels are arranged in the border area. The first gate lines span the display area along a first direction and receives a plurality of gate signals. The second gate lines and the third gate lines span the display area and the boundary area along a second direction perpendicular to the first direction. Each of the second and third gate lines is electrically connected to one or the first gate lines, part of the liquid crystal pixels, and part of the LED pixels.

Description

Spliced display panel

The present invention relates to a display panel, and in particular to a spliced display panel.

Due to the physical limitations of semiconductor technology, the size of panels that can be mass-produced by LCD panel factories is still limited. The main reason is that the larger the size of the panel, the higher the cost and the lower the yield, resulting in a lower supply of panels. However, with the significant benefits of LCD panels in advertising and marketing, the market demand for large panels is increasing. Therefore, the feasible way to realize large panels is to use existing panels to further assemble them into large panels.

With the advancement of packaging technology, the borders of LCD panels have become very narrow, but when the panels are spliced together, the splicing lines between the panels can still be seen, making the picture discontinuous and affecting the viewing experience. Therefore, how to achieve seamless splicing of spliced display panels is an important issue to improve the viewing experience.

The present invention provides a spliced display panel, which can shorten the non-displaying frame of the liquid crystal panel to achieve the purpose of seamless splicing of the spliced display panel.

The spliced display panel of the present invention comprises a plurality of substrates, a plurality of liquid crystal pixels, a plurality of light-emitting diode pixels, a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines. Each substrate has a display area and at least one boundary area, and the boundary areas are respectively located between the display area and the splicing boundaries of the spliced substrates. The liquid crystal pixel array is arranged in the display area. The light-emitting diode pixel array is arranged in the boundary area. The first gate line crosses the display area along a first direction and receives a plurality of gate signals. The second gate lines cross the display area and the border area along a second direction perpendicular to the first direction, and each second gate line electrically connects one of the first gate lines, a portion of the liquid crystal pixels, and a portion of the light-emitting diode pixels. The third gate lines cross the display area and the border area along a second direction perpendicular to the first direction, and each third gate line is located between two adjacent second gate lines and electrically connects one of the first gate lines, a portion of the liquid crystal pixels, and a portion of the light-emitting diode pixels.

Based on the above, in the spliced display panel of the embodiment of the present invention, the liquid crystal pixel can write the data voltage based on the gate signal transmitted by the second gate line; and the LED pixel can write the data voltage and light up based on the gate signal transmitted by the second gate line, and can be extinguished based on another gate signal transmitted by the third gate line. In this way, the liquid crystal pixel and the LED pixel can be driven normally, and the seamless splicing effect can be achieved through the advantage of the LED pixel without borders.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless expressly defined as such in this document.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". " or "means" and/or". As used herein, the terms "and/or" include any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and/or "include" specify the presence and/or parts of the features, regions, entireties, steps, operations, elements, components and/or parts, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and/or combinations thereof.

FIG. 1 is a system schematic diagram of a display device according to an embodiment of the present invention. 1 , in the present embodiment, the display device 10 includes a plurality of spliced display panels 100, a plurality of control substrates (such as 11 and 11 ′), and a plurality of film substrates (such as 12 and 12 ′), wherein the spliced display panel 100 includes a plurality of substrates (herein, two substrates 101 and 102 are taken as examples), a plurality of liquid crystal pixels PXCX, a plurality of light-emitting diode pixels (taking a plurality of red light-emitting diode pixels PDR, a plurality of green light-emitting diode pixels PDG, and a plurality of blue light-emitting diode pixels PDB as examples), a plurality of first gate lines LX1_1 to LX1_m, a plurality of second gate lines LX2_1 to LX2_p, and a plurality of third gate lines LX3_1 to LX3_p. The liquid crystal pixel PXCX is driven by voltage, and the red light emitting diode pixel PDR, the green light emitting diode pixel PDG, and the blue light emitting diode pixel PDB are driven by current. In addition, the film substrate (such as 12 and 12') is used to electrically connect the spliced display panel 100 and the control substrate (such as 11 and 11').

In the present embodiment, each substrate (such as 101, 102) has a display area (such as 110 and 110'), at least one boundary area (such as 120 and 120'), and a fan-in area (such as 130 and 130'), wherein the number of boundary areas (such as 120 and 120') depends on the splicing requirements of the substrates (101, 102), and the boundary areas (such as 120 and 120') are respectively located between the display area (such as 110 and 110') and the splicing boundary Etile of the substrates 101 and 102. The liquid crystal pixels PXCX are arrayed in the display area (such as 110 and 110'), and the red light emitting diode pixels PDR, the green light emitting diode pixels PDG, and the blue light emitting diode pixels PDB are arrayed in the boundary area (such as 120 and 120').

Taking the substrate 101 as an example, the first gate lines LX1_1 to LX1_m cross the display region 110 along the first direction D1 and receive a plurality of gate signals G(1) to G(m) enabled in sequence. The second gate lines LX2_1 to LX2_p cross the display region 110 and the boundary region 120 along the second direction D2 perpendicular to the first direction D1. Each second gate line LX2_1~LX2_p is electrically connected to one of the first gate lines LX1_1~LX1_m (for example, through a perforation), a row (or a portion) of liquid crystal pixels PXCX, a row (or a portion) of red LED pixels PDR, green LED pixels PDG, and blue LED pixels PDB, so as to transmit gate signals G(1)~G(m) to the liquid crystal pixels PXCX, the red LED pixels PDR, the green LED pixels PDG, and the blue LED pixels PDB.

The third gate lines LX3_1-LX3_p cross the display area 110 and the boundary area 120 along a second direction D2 perpendicular to the first direction D1. Each of the third gate lines LX3_1-LX3_p is located between two adjacent second gate lines (such as LX2_1-LX2_p) and is electrically connected to one of the first gate lines LX1_1-LX1_m. The gate signals G(1)~G(m) are transmitted to the red LED pixels PDR, the green LED pixels PDG, and the blue LED pixels PDB (for example, through perforations) and a row (or part) of red LED pixels PDR, green LED pixels PDG, and blue LED pixels PDB.

According to the above, the liquid crystal pixel PXCX can write the data voltage based on the gate signal (such as G(1)~G(m)) transmitted by the second gate line (such as LX2_1~LX2_p); and the red light-emitting diode pixel PDR, the green light-emitting diode pixel PDG, and the blue light-emitting diode pixel PDB can write the data voltage and light up based on the gate signal (such as G(1)~G(m)) transmitted by the second gate line (such as LX2_1~LX2_p), and can be extinguished based on another gate signal (such as G(1)~G(m)) transmitted by the third gate line (such as LX3_1~LX3_p). Thereby, the liquid crystal pixel PXCX and the red light-emitting diode pixel PDR, the green light-emitting diode pixel PDG, and the blue light-emitting diode pixel PDB can be driven normally, and through the advantage of the red light-emitting diode pixel PDR, the green light-emitting diode pixel PDG, and the blue light-emitting diode pixel PDB having no borders, a seamless splicing effect is achieved.

In this embodiment, a control circuit (e.g., a timing controller) may be configured on the control substrate (e.g., 11 and 11'), and a driving circuit (e.g., a gate driver and a source driver) may be configured on the film substrate (e.g., 12 and 12'). Further, the circuits on the control substrate 11 and the film substrate 12 are used to drive the liquid crystal pixels PXCX, the red light-emitting diode pixels PDR, the green light-emitting diode pixels PDG, and the blue light-emitting diode pixels PDB on the substrate 101, and the circuits on the control substrate 11' and the film substrate 12' are used to drive the liquid crystal pixels PXCX, the red light-emitting diode pixels PDR, the green light-emitting diode pixels PDG, and the blue light-emitting diode pixels PDB on the substrate 102.

In this embodiment, m and p can be a positive integer, and m can be different from p. For example, m can be greater than p.

In this embodiment, the first gate lines (eg, LX1_1-LX1_m) electrically connected to each third gate line (eg, LX3_1-LX3_p) and the first gate lines (eg, LX1_1-LX1_m) electrically connected to the adjacent second gate lines (eg, LX2_1-LX2_p) may be separated by at least two first gate lines (eg, LX1_1-LX1_m). Specifically, the first gate lines (e.g., LX1_1-LX1_m) electrically connected to the second gate lines (e.g., LX2_1-LX2_p) and the third gate lines (e.g., LX3_1-LX3_p) corresponding to the same pixel row are separated by at least two first gate lines (e.g., LX1_1-LX1_m) (i.e., at least three horizontal scanning times when the data of the red LED pixel PDR, the green LED pixel PDG, and the blue LED pixel PDB are written and lit).

For example, taking the substrate 101 as an example, the second gate line LX2_1 of the first pixel row is electrically connected to the first gate line LX1_1, and the third gate line LX3_1 of the first pixel row is electrically connected to the first gate line LX1_5.

In this embodiment, the material of the substrates 101 and 102 includes one of a P-type amorphous silicon (a-Si) substrate, an N-type amorphous silicon substrate, an indium gallium zinc oxide (IGZO) substrate, and a low temperature polycrystalline silicon (LTPS) substrate.

In the embodiment of the present invention, the red LED pixels PDR, the green LED pixels PDG, and the blue LED pixels PDB may be arranged in sequence. For example, starting from the tile boundary Etile, the first row may be the red LED pixels PDR, the second row may be the green LED pixels PDG, and the third row may be the blue LED pixels PDB; or the red LED pixels PDR, the green LED pixels PDG, and the blue LED pixels PDB may be arranged in sequence. The pixel PDB may be arranged obliquely, for example, the first row is red LED pixel PDR, green LED pixel PDG, blue LED pixel PDB arranged in sequence, the second row is green LED pixel PDG, blue LED pixel PDB, red LED pixel PDR arranged in sequence, the third row is blue LED pixel PDB, red LED pixel PDR, green LED pixel PDG arranged in sequence, and so on for the rest. Furthermore, the arrangement of the colors (i.e., color filters) of the liquid crystal pixels PXCX is substantially aligned with the arrangement of the red light-emitting diode pixels PDR, the green light-emitting diode pixels PDG, and the blue light-emitting diode pixels PDB, but the embodiments of the present invention are not limited thereto.

In the embodiment of the present invention, three adjacent red LED pixels PDR, green LED pixels PDG, and blue LED pixels PDB can be integrated into a LED chip Dled to facilitate transfer to a substrate (such as 101, 102).

In this embodiment, in order to match the number of first gate lines LX1_1 to LX1_m with the number of second gate lines LX2_1 to LX2_p and third gate lines LX3_1 to LX3_p, some of the first gate lines LX1_1 to LX1_m are not electrically connected to the second gate lines LX2_1 to LX2_p and third gate lines LX3_1 to LX3_p, or some of the first gate lines LX1_1 to LX1_m can be omitted, but the embodiment of the present invention is not limited thereto.

FIG. 2 is a circuit diagram of a liquid crystal pixel according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 2, in this embodiment, the liquid crystal pixel PXCX is a liquid crystal pixel PXCXa, and the liquid crystal pixel PXCXa includes a switching transistor Tcx, a first pixel capacitor Cx1, and a second pixel capacitor Cx2. The switching transistor Tcx has a first end for receiving a pixel data voltage Data, a control end for receiving a gate signal G(n), and a second end, where n is a guide number. The first pixel capacitor Cx1 is coupled between the second end of the switching transistor Tcx and the first common end CF-COM. The second pixel capacitor Cx2 is coupled between the second end of the switching transistor Tcx and the second common end Array-COM.

FIG3 is a circuit diagram of a light-emitting diode pixel according to an embodiment of the present invention. Referring to FIG1 and FIG3, in this embodiment, the red light-emitting diode pixel PDR, the green light-emitting diode pixel PDG, and the blue light-emitting diode pixel PDB are exemplified by the light-emitting diode pixel PDXa, and the light-emitting diode pixel PDXa includes a light-emitting diode XLED, transistors T11 to T13 (corresponding to the first transistor to the third transistor), and a capacitor C11 (corresponding to the first capacitor), wherein the transistors T11 to T13 are exemplified by N-type transistors, and the light-emitting diode XLED can be a red light-emitting diode, a green light-emitting diode, or a blue light-emitting diode.

The light-emitting diode XLED has an anode and a cathode receiving a system low voltage VSS. The transistor T11 has a first end receiving a pixel data voltage Data, a control end receiving a gate signal G(n), and a second end. The transistor T12 has a first end receiving a system high voltage VDD, a control end coupled to the second end of the transistor T11, and a second end coupled to the anode of the light-emitting diode XLED. The transistor T13 has a first end receiving a gate low voltage VGL, a control end receiving a gate signal G(n+x) (corresponding to a second gate signal), and a second end coupled to the control end of the transistor T12, wherein x is a positive integer greater than 2. The capacitor C11 is coupled between the control end of the transistor T12 and the second end of the transistor T12.

FIG4 is a circuit diagram of a light-emitting diode pixel according to another embodiment of the present invention. Referring to FIG1 and FIG4, in this embodiment, the red light-emitting diode pixel PDR, the green light-emitting diode pixel PDG, and the blue light-emitting diode pixel PDB are exemplified by the light-emitting diode pixel PDXb, and the light-emitting diode pixel PDXb includes a light-emitting diode XLED, transistors T21 to T26 (corresponding to the fourth transistor to the ninth transistor), and a capacitor C21 (corresponding to the second capacitor), wherein the transistors T21 to T26 are exemplified by P-type transistors, and the light-emitting diode XLED can be a red light-emitting diode, a green light-emitting diode, or a blue light-emitting diode.

The light-emitting diode XLED has an anode and a cathode receiving a system low voltage VSS. The transistor T21 has a first end receiving a pixel data voltage Data, a control end receiving a gate signal G(n), and a second end. The transistor T22 has a first end, a control end coupled to the second end of the transistor T21, and a second end. The capacitor C21 is coupled between the first end of the transistor T21 and the control end of the transistor T22. The transistor T23 has a first end receiving a reference voltage Vref, a control end receiving a gate signal G(n), and a second end coupled to the first end of the transistor T22.

The transistor T24 has a first end receiving the system high voltage VDD, a control end receiving the light emitting signal EM, and a second end coupled to the first end of the transistor T22. The transistor T25 has a first end coupled to the second end of the transistor T22, a control end receiving the light emitting signal EM, and a second end coupled to the anode of the light emitting diode XLED. The transistor T26 has a first end coupled to the control end of the transistor T22, a control end receiving the gate signal G(n+x), and a second end receiving the gate high voltage VGH.

In summary, in the spliced display panel of the embodiment of the present invention, the liquid crystal pixel can write the data voltage based on the gate signal transmitted by the second gate line; and the LED pixel can write the data voltage and light up based on the gate signal transmitted by the second gate line, and can be extinguished based on another gate signal transmitted by the third gate line. In this way, the liquid crystal pixel and the LED pixel can be driven normally, and the seamless splicing effect can be achieved through the advantage of the LED pixel without borders.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10: Display device 11 and 11': Control substrate 12 and 12': Thin film substrate 100: Spliced display panel 101, 102: Substrate 110 and 110': Display area 120 and 120': Boundary area 130 and 130': Fan-in area Array-COM: Second common terminal C11, C21: Capacitor CF-COM: First common terminal Cx1: First pixel capacitor Cx2: Second pixel capacitor D1: First direction D2: Second direction Data: Pixel data voltage Dled: Light-emitting diode chip EM: Light-emitting signal Etile: Splicing boundary G(1)~G(m), G(n), G(n+x): Gate signal LX1_1~LX1_m: First gate line LX2_1~LX2_p: second gate line LX3_1~LX3_p: third gate line PDB: blue light-emitting diode pixel PDG: green light-emitting diode pixel PDR: red light-emitting diode pixel PDXa, PDXb: light-emitting diode pixel PXCX, PXCXa: liquid crystal pixel T11~T13, T21~T26: transistor Tcx: switch transistor VDD: system high voltage VGL: gate low voltage Vref: reference voltage VSS: system low voltage XLED: light-emitting diode

FIG. 1 is a system schematic diagram of a display device according to an embodiment of the present invention. FIG. 2 is a circuit schematic diagram of a liquid crystal pixel according to an embodiment of the present invention. FIG. 3 is a circuit schematic diagram of a light-emitting diode pixel according to an embodiment of the present invention. FIG. 4 is a circuit schematic diagram of a light-emitting diode pixel according to another embodiment of the present invention.

10: Display device

11 and 11’: Control board

12 and 12’: Thin film substrate

100:Spliced display panel

PXCX: LCD pixel

PDR: Red LED pixel

PDG: Green diode pixel

PDB: Blue LED pixel

LX1_1~LX1_m: first gate line

LX2_1~LX2_p: Second gate line

LX3_1~LX3_p: The third gate line

101, 102: Substrate

110 and 110’: Display area

120 and 120’: Border area

130 and 130’: Fan-in area

D1: First direction

D2: Second direction

G(1)~G(m): Gate signal

Etile: stitching borders

Dled: light-emitting diode chip

Claims (7)

A spliced display panel includes: A plurality of substrates, each of which has a display area and at least one boundary area, wherein the at least one boundary area is located between the display area and a splicing boundary of the substrates; A plurality of liquid crystal pixels are arranged in an array in the display area; A plurality of light-emitting diode pixels are arranged in an array in the at least one boundary area; A plurality of first gate lines cross the display area along a first direction and receive a plurality of gate signals; A plurality of second gate lines cross the display area and the at least one boundary area along a second direction perpendicular to the first direction, wherein each of the second gate lines electrically connects one of the first gate lines, part of the liquid crystal pixels, and part of the light-emitting diode pixels; A plurality of third gate lines span the display area and the at least one boundary area along the second direction, each of the third gate lines is located between two adjacent second gate lines, and is electrically connected to one of the first gate lines and a portion of the light-emitting diode pixels. In the spliced display panel as claimed in claim 1, the first gate line to which each of the third gate lines is electrically connected and the first gate line to which the adjacent second gate line is electrically connected are separated by at least two first gate lines. A spliced display panel as described in claim 1, wherein each of the liquid crystal pixels comprises: a switch transistor having a first end for receiving a pixel data voltage, a control end for receiving a first gate signal among the gate signals, and a second end; a first pixel capacitor coupled between the second end of the switch transistor and a first common end; and a second pixel capacitor coupled between the second end of the switch transistor and a second common end. The spliced display panel as described in claim 1, wherein each of the LED pixels comprises: a LED having an anode and a cathode receiving a system low voltage; a first transistor having a first end receiving a pixel data voltage, a control end receiving a first gate signal among the gate signals, and a second end; a second transistor having a first end receiving a system high voltage, a control end coupled to the second end of the first transistor, and a second end coupled to the anode of the LED; A third transistor having a first end receiving a gate low voltage, a control end receiving a second gate signal among the gate signals, and a second end coupled to the control end of the second transistor; and a first capacitor coupled between the control end of the second transistor and the second end of the second transistor. A spliced display panel as described in claim 1, wherein each of the LED pixels comprises: A LED having an anode and a cathode receiving a system low voltage; A fourth transistor having a first end receiving a pixel data voltage, a control end receiving a first gate signal among the gate signals, and a second end; A fifth transistor having a first end, a control end coupled to the second end of the fourth transistor, and a second end; A second capacitor coupled between the first end of the fourth transistor and the control end of the fifth transistor; A sixth transistor having a first end receiving a reference voltage, a control end receiving the first gate signal, and a second end coupled to the first end of the fifth transistor; a seventh transistor having a first end for receiving a system high voltage, a control end for receiving a light-emitting signal, and a second end coupled to the first end of the fifth transistor; an eighth transistor having a first end coupled to the second end of the fifth transistor, a control end for receiving the light-emitting signal, and a second end coupled to the anode of the light-emitting diode; and a ninth transistor having a first end coupled to the control end of the fifth transistor, a control end for receiving a second gate signal among the gate signals, and a second end for receiving a gate high voltage. A spliced display panel as described in claim 1, wherein the materials of the substrates include one of a P-type amorphous silicon (a-Si) substrate, an N-type amorphous silicon (a-Si) substrate, an indium gallium zinc oxide (IGZO) substrate, and a low-temperature polycrystalline silicon (LTPS) substrate. In the spliced display panel as described in claim 1, the LED pixels include a plurality of red LED pixels, a plurality of green LED pixels, and a plurality of blue LED pixels.

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