TWI871589B - Method for preparing memory device having word line with protrusion - Google Patents

Abstract

The present disclosure provides a method for preparing a memory device. The method includes forming a first bottom cell within a bottom substrate, comprising: forming a first bottom capacitor within the bottom substrate; forming a first bottom word line on the bottom substrate and extending along a first direction; and forming a first bottom channel layer surrounded by the first bottom word line. The method also includes forming a first top cell within a top substrate, comprising: forming a first top capacitor within the top substrate; forming a first top word line on the top substrate and extending along the first direction; and forming a first top channel layer surrounded by the first top word line. The method further includes forming a common bit line between the first bottom cell and the first top cell and extending along a second direction substantially perpendicular to the first direction.

Description

Method for preparing memory device with protruding word line

This application claims priority to and the benefit of U.S. formal application Nos. 17/824,011 and 17/824,507, filed on May 25, 2022, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method for preparing a memory device, and more particularly to a method for preparing a memory device with a protruding word line.

With the rapid development of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Advances in IC materials and design techniques have produced generations of ICs, each of which is smaller and more complex than the previous generation.

A dynamic random access memory (DRAM) device is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, DRAMs are arranged in a square array with one capacitor and transistor per cell. Vertical transistors for 4F ² DRAM cells have been developed, where F represents the minimum feature width or critical dimension (CD) of lithography. However, recently, as the word line pitch continues to shrink, DRAM manufacturers face a huge challenge in shrinking the memory cell area. For example, the channel of the bit line can easily contact the word line, causing a short circuit due to overlay errors in the lithography process.

The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present case.

One aspect of the present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed in the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed in the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protrusion protruding toward the second metallization layer.

Another aspect of the present disclosure provides another memory element. The memory element includes a bottom substrate, a first bottom unit, a top substrate, a first top unit and a common bit line. The first bottom unit includes a first bottom capacitor disposed in the bottom substrate. The first bottom unit also includes a first bottom word line disposed on the bottom substrate and extending along a first direction. The first bottom unit further includes a first bottom channel layer surrounded by the first bottom word line. The first top unit includes a first top capacitor disposed in the top substrate. The first top unit also includes a first top word line disposed on the top substrate and extending along the first direction. The first top unit further includes a first top channel layer surrounded by the first top word line. The common bit line is disposed between the first bottom unit and the first top unit and extends along a second direction substantially perpendicular to the first direction.

Another aspect of the present disclosure provides a method for preparing a memory element. The preparation method includes providing a substrate. The preparation method also includes forming a conductive layer on the substrate. The preparation method further includes patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction. The first metallization layer has a first protrusion protruding toward the second metallization layer. In addition, the preparation method also includes forming a first channel layer in the first metallization layer and forming a second channel layer in the second metallization layer.

In some embodiments, the first top word line is formed between the first top capacitor and the common bit line.

In some embodiments, the first top word line is formed between the first top capacitor and the first bottom word line.

In some embodiments, forming the first top word line includes forming a protrusion that protrudes toward the second top word line.

In some embodiments, the preparation method further includes forming a second bottom unit, which includes: forming a second bottom word line on the bottom substrate and extending along the first direction; and forming a second bottom channel layer surrounded by the second bottom word line; wherein the first bottom word line includes a protrusion protruding toward the second bottom word line.

In some embodiments, the second bottom word line includes a protrusion protruding toward the first bottom word line.

In some embodiments, the protrusion of the first bottom word line and the protrusion of the second bottom word line are arranged alternately along the second direction.

In some embodiments, the first bottom channel layer and the second bottom channel layer are arranged alternately along the second direction.

In some embodiments, the first top word line has a protrusion.

In some embodiments, the protrusion of the first bottom word line overlaps the protrusion of the first top word line along a third direction, and the third direction is substantially perpendicular to the first direction and the second direction.

In some embodiments, the first top channel layer overlaps the protrusion of the first top word line along the second direction.

In some embodiments, the preparation method further includes: forming a second top unit, which includes: forming a second top word line on the top substrate and extending along the first direction; and forming a second top channel layer surrounded by the second top word line; wherein the second top word line includes a protrusion protruding toward the first top word line.

In some embodiments, the first top word line has a first sidewall and a second sidewall opposite to the first sidewall, the second sidewall faces the second top word line, and a first distance between the first sidewall and the first top channel layer is different from a second distance between the second sidewall and the first top channel layer.

In some embodiments, the second top word line has a third sidewall and a fourth sidewall, the third sidewall faces the first top word line, and a third distance between the third sidewall and the second top channel layer is different from a fourth distance between the fourth sidewall and the second top channel layer.

The disclosed embodiment provides a memory device. The memory device may include a word line having a protrusion. The protrusion may make the stacking error of the word line pattern relatively large to form an opening (in which a channel layer is formed), which may prevent electrical leakage between the word line and the channel layer.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

The embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would be routinely made by one of ordinary skill in the art to which the present disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numeral.

It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, or portions, these elements, components, regions, layers, or portions are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion without departing from the teachings of the present inventive concept.

The terms used herein are only used to describe specific embodiments and are not intended to limit the concepts of the present invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprise" and "include", when used in this specification, indicate the presence of the features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.

FIG. 1A is a top view illustrating a memory device 100 according to some embodiments of the present disclosure.

In some embodiments, the memory element 100 may include a cell region in which a memory element is formed, such as the structure shown in FIG. 1A and FIG. 1B. The memory element may include, for example, a dynamic random access memory (DRAM) element, a one-time programming (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory elements. In some embodiments, the DRAM may include, for example, transistors, capacitors, and other components.

During a read operation, the word line can be enabled to turn on the transistor. The enabled transistor allows the voltage on the capacitor to be read by the sense amplifier through the bit line. During a write operation, when the word line is enabled, the data to be written can be provided on the bit line.

In some embodiments, the memory device 100 may include a peripheral area (not shown) for forming a logic element (e.g., a system on chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) element, a sensor element, a microelectromechanical system (MEMS) element, a signal processing element (e.g., a digital signal processing (DSP) element), a front-end element (e.g., an analog front-end (AFE) element), or other elements.

As shown in FIG. 1A , the memory device 100 may include a substrate 102 , a plurality of metallization layers 116 - 1 and 116 - 2 , a plurality of metallization layers 120 - 1 and 120 - 2 , a plurality of gate dielectrics 104 - 1 and 104 - 2 , a plurality of channel layers 106 - 1 and 106 - 2 , and a dielectric layer 112 .

The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like. The substrate 102 may include an elementary semiconductor, including silicon or germanium in single crystal form, polycrystalline form, or amorphous form, a composite semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium sulfide, an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP, any other suitable material, or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy having a gradient Ge feature, wherein the composition of Si and Ge changes from one ratio to another ratio depending on the location of the feature. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the silicon germanium alloy can be mechanically stretched by another material in contact with the silicon germanium alloy. In some embodiments, the substrate 102 can have a multi-layer structure, or the substrate 102 can include a multi-layer compound semiconductor structure.

The substrate 102 may have a plurality of doped regions (not shown) therein. In some embodiments, p-type and/or n-type dopants may be doped in the substrate 102. In some embodiments, the p-type dopant includes boron (B), other Group III elements, or any combination thereof. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), other Group V elements, or any combination thereof.

Each of the metallization layers 116-1 and 116-2 may extend along the Y axis. Each of the metallization layers 116-1 and 116-2 may be parallel. In some embodiments, each of the metallization layers 116-1 and 116-2 may be physically separated. The metallization layers 116-1 and 116-2 may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), etc., and/or combinations thereof. In some embodiments, the metallization layers 116-1 and 116-2 may be referred to as word lines.

The metallization layer 116-1 may include a sidewall 116s1 and a sidewall 116s2 opposite thereto. The sidewall 116s2 of the metallization layer 116-1 may face the metallization layer 116-2. In some embodiments, the metallization layer 116-1 may have a protrusion 116-1p. In some embodiments, the protrusion 116-1p of the metallization layer 116-1 may face the metallization layer 116-2. In some embodiments, the sidewall 116s2 of the metallization layer 116-1 may protrude toward the metallization layer 116-2, thereby defining the protrusion 116-1p.

The metallization layer 116-2 may include a sidewall 116s3 and a sidewall 116s4 opposite to the sidewall 116s3. The sidewall 116s3 of the metallization layer 116-2 may face the metallization layer 116-1. In some embodiments, the metallization layer 116-2 may have a protrusion 116-2p. In some embodiments, the protrusion 116-2p of the metallization layer 116-2 may face the metallization layer 116-1. In some embodiments, the sidewall 116s3 of the metallization layer 116-2 may protrude toward the metallization layer 116-1, thereby defining the protrusion 116-2p.

In some embodiments, the protrusions 116-1p of the metallization layer 116-1 and the protrusions 116-2p of the metallization layer 116-2 may be staggered. In some embodiments, the protrusions 116-1p of the metallization layer 116-1 and the protrusions 116-2p of the metallization layer 116-2 are arranged alternately along the X-axis. In some embodiments, the protrusions 116-1p of the metallization layer 116-1 may not overlap with the protrusions 116-2p of the metallization layer 116-2 along the X-axis. In other embodiments, the protrusions 116-1p of the metallization layer 116-1 may partially overlap with the protrusions 116-2p of the metallization layer 116-2 along the X-axis. In some embodiments, the protrusions 116-1p and/or 116-2p may have a semicircular or semi-elliptical profile when viewed from a top view. However, the present disclosure is not intended to be limiting.

The metallization layers 120-1 and 120-2 may be disposed on the metallization layers 116-1 and 116-2. Each of the metallization layers 120-1 and 120-2 may extend along the X-axis. Each of the metallization layers 120-1 and 120-2 may be parallel. Each of the metallization layers 120-1 and 120-2 may be physically separated. In some embodiments, the metallization layers 120-1 and 120-2 may be located at a higher level than the metallization layers 116-1 and 116-2. The metallization layers 120-1 and 120-2 may include conductive materials such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, etc., and/or combinations thereof. In some embodiments, metallization layers 120-1 and 120-2 may be referred to as bit lines.

In some embodiments, gate dielectrics 104-1 and 104-2 may be disposed on sidewalls (not shown) of word lines (e.g., 116-1 and 116-2). In some embodiments, gate dielectric 104-1 may be embedded in metallization layer 116-1. In some embodiments, gate dielectric 104-2 may be embedded in metallization layer 116-2. In some embodiments, gate dielectric 104-1 may be surrounded by metallization layer 116-1. In some embodiments, gate dielectric 104-2 may be surrounded by metallization layer 116-2. In some embodiments, each of the gate dielectrics 104-1 and 104-2 may overlap with the metallization layer 120-1 or 120-2 along the Z-axis.

In some embodiments, the gate dielectrics 104-1 and 104-2 may include silicon oxide ( _SiOx ), silicon nitride ( _SixNy ), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. The _high -k dielectric material may have a dielectric constant (k value) greater than 4. The high dielectric material may include ferrite ( _HfO2 ), zirconium oxide ( _ZrO2 ), lumen oxide ( _La2O3 ), yttrium oxide _{( Y2O3} ), aluminum _{oxide ( Al2O3} ), titanium oxide ( _TiO2 ), or other suitable materials. Other suitable materials are also within the scope of the present disclosure. In some embodiments, the gate dielectrics 104 - 1 and 104 - 2 may include rings having circular, elliptical, oval, or other contours.

In some embodiments, each of the channel layers 106-1 and 106-2 may be disposed on a sidewall of the gate dielectric 104-1 or 104-2 (not shown). In some embodiments, each of the channel layers 106-1 and 106-2 may be embedded in the gate dielectric 104-1 or 104-2. In some embodiments, each of the channel layers 106-1 and 106-2 may be surrounded by the gate dielectric 104-1 or 104-2. In some embodiments, each of the channel layers 106-1 and 106-2 may be in contact with the gate dielectric 104-1 or 104-2. In some embodiments, each of the channel layers 106-1 and 106-2 may overlap with the metallization layer 120-1 or 120-2 along the Z axis. In some embodiments, each of the channel layers 106-1 and 106-2 may be completely surrounded by the gate dielectric 104-1 or 104-2 from a top view.

In some embodiments, each of the channel layers 106-1 and 106-2 may be disposed on a sidewall of the metallization layer 116-1 or 116-2 (not shown). In some embodiments, each of the channel layers 106-1 and 106-2 may be embedded in the metallization layer 116-1 or 116-2. In some embodiments, each of the channel layers 106-1 and 106-2 may be surrounded by the metallization layer 116-1 or 116-2.

In some embodiments, channel layers 106-1 and 106-2 may be staggered. In some embodiments, channel layer 106-1 may be arranged in an alternating manner with channel layer 106-2 along the X-axis. In some embodiments, channel layer 106-1 may overlap with protrusion 116-1p of metallization layer 116-1 along the X-axis. In some embodiments, channel layer 106-2 may overlap with protrusion 116-2p of metallization layer 116-2 along the X-axis.

A distance D1 may be provided between the sidewall 116s1 of the metallization layer 116-1 and the channel layer 106-1 along the X-axis. A distance D2 may be provided between the sidewall 116s2 of the metallization layer 116-1 and the channel layer 106-1 along the X-axis. In some embodiments, the distance D1 may be different from the distance D2. In some embodiments, the distance D2 may be greater than the distance D1.

A distance D3 may be provided between the sidewall 116s3 of the metallization layer 116-2 and the channel layer 106-2 along the X-axis. A distance D4 may be provided between the sidewall 116s4 of the metallization layer 116-2 and the channel layer 106-2 along the X-axis. In some embodiments, the distance D3 may be different from the distance D4. In some embodiments, the distance D3 may be greater than the distance D4.

In some embodiments, sidewall 116s1 of metallization layer 116-1 may have relatively straight edges. In some embodiments, sidewall 116s4 of metallization layer 116-2 may have relatively straight edges. Metallization layer 116-1s of metallization layer 116-1 may have a distance D5 from sidewall 116s4 of metallization layer 116-2 along the X-axis. In some embodiments, distance D5 may be substantially uniform or constant along the Y-axis.

There may be a distance D6 between the sidewall 116s2 of the metallization layer 116-1 and the sidewall 116s3 of the metallization layer 116-2 along the X-axis. In some embodiments, the distance D6 may vary along the Y-axis.

The material of the channel layers 106-1 and 106-2 may include an amorphous semiconductor, a polycrystalline semiconductor and/or a metal oxide. The semiconductor may include, but is not limited to, germanium (Ge), silicon (Si), tin (Sn), antimony (Sb). The metal oxide may include, but is not limited to: indium oxide; tin oxide; zinc oxide; dual component metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, or In-Ga-based oxides. Three-component metal oxides, such as In-Ga-Zn-based oxides (also denoted as IGZO), In-Al-Zn-based oxides, In-S-based oxides (also denoted as ITO), In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Z n-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide or In-Lu-Zn-based oxide; and four-component metal oxides, such as In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide or In-Hf-Al-Zn-based oxide, but the present disclosure is not limited to this.

In some embodiments, the dielectric layer 112 may be disposed on a sidewall of the metallization layer 116-1 or 116-2 (not shown). In some embodiments, the dielectric layer 112 may be disposed between the metallization layers 116-1 and 116-2. In some embodiments, each of the gate dielectrics 104-1 and 104-2 may be physically separated from the dielectric layer 112. In some embodiments, each of the gate dielectrics 104-1 and 104-2 may be physically separated from the dielectric layer 112 by the metallization layer 116-1 or 116-2.

In some embodiments, each of the channel layer 106-1 or 106-2 can be physically separated from the dielectric layer 112. In some embodiments, the channel layer 106-1 or 106-2 can be physically separated from the dielectric layer 112 by the gate dielectrics 104-1 and 104-2 and the metallization layer 116-1 or 116-2.

The dielectric layer 112 may include silicon oxide ( _SiOx ), silicon nitride _{( SixNy} ), silicon oxynitride (SiON), or other suitable materials. In some embodiments, the material of the dielectric layer 112 may be different from the material of the gate dielectrics 104-1 and 104-2. In some embodiments, the material of the dielectric layer 112 may be the same as the material of the gate dielectrics 104-1 and 104-2, but with different quality or film density.

FIG. 1B is a cross-sectional view of the memory device 100 of FIG. 1A taken along line AA′, illustrating some embodiments of the present disclosure.

As shown in FIG. 1B , the memory device 100 may further include a plurality of capacitors 108 - 1 and 108 - 2 , a dielectric layer 110 , a dielectric layer 114 , and a contact plug 118 .

In some embodiments, capacitor 108-1 may be electrically connected to metallization layer 120-1 through contact plug 118 and channel layer 106-1. In some embodiments, capacitor 108-2 may be electrically connected to metallization layer 120-2 through contact plug 118 and channel layer 106-2.

In some embodiments, capacitors 108-1 and 108-2 may be embedded in substrate 102. In some embodiments, each of capacitors 108-1 and 108-2 may include a first electrode, a capacitor dielectric, and a second electrode (not shown). In some embodiments, each of capacitors 108-1 and 108-2 may have a circular, elliptical, oval, or similar outline from a top view. In some embodiments, the capacitor dielectric may surround the first electrode. In some embodiments, the second electrode may surround the first electrode. In some embodiments, the second electrode may surround the capacitor dielectric. In some embodiments, the capacitor dielectric may be disposed between the first electrode and the second electrode.

The first electrode and/or the second electrode may include a semiconductor material or a conductive material. The semiconductor material may include polysilicon or other suitable materials. The conductive material may include tungsten, copper, aluminum, tantalum or other suitable materials.

The capacitor dielectric may include a dielectric material such as silicon oxide, tungsten oxide, zirconium oxide, copper oxide, aluminum oxide, einsteinium oxide, or the like.

In some embodiments, a contact plug 118 may be disposed between the capacitor 108-1 and the channel layer 106-1. The contact plug 118 may include a semiconductor material or a conductive material.

The dielectric layer 110 may be disposed on the substrate 102. The dielectric layer 110 may include _silicon oxide ( _SiOx ), silicon nitride ( _SixNy ), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material (k<4), or other suitable materials. The dielectric layer 110 may also be referred to as a lower dielectric.

The dielectric layer 114 may be disposed on the metallization layers 116-1 and 116-2. The dielectric layer 114 may include silicon oxide ( _SiOx ), silicon nitride ( _SixNy ), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material (k<4), or other suitable materials. In _some embodiments, the metallization layers 120-1 and 120-2 may be disposed on the dielectric layer 114. The dielectric layer 114 may also be referred to as an upper dielectric.

In some embodiments, each of the gate dielectrics 104-1 and 104-2 may penetrate the dielectric layer 114. In some embodiments, each of the gate dielectrics 104-1 and 104-2 may penetrate the dielectric layer 110. In some embodiments, each of the gate dielectrics 104-1 and 104-2 may penetrate the metallization layer 116-1 or 116-2.

In some embodiments, each of the channel layers 106-1 and 106-2 may penetrate the dielectric layer 114. In some embodiments, each of the channel layers 106-1 and 106-2 may penetrate the dielectric layer 110. In some embodiments, each of the channel layers 106-1 and 106-2 may penetrate the metallization layer 116-1 or 116-2.

In some embodiments, the word line (e.g., metallization layer 116-1 or 116-2), gate dielectric 104-1 or 104-2, and channel layer 106-1 or 106-2 may be included in a transistor. During a read operation, the word line (e.g., metallization layer 116-1 or 116-2) may be enabled, turning on the transistor, which may be formed in a peripheral area. The enabled transistor allows the voltage on the capacitor (e.g., capacitor 108-1 or capacitor 108-2) to be read by a sense amplifier via a bit line (e.g., metallization layer 120-1 or 120-2). During a write operation, when a word line (eg, metallization layer 116-1 or 116-2) is activated, data to be written may be provided to a bit line (eg, metallization layer 120-1 or 120-2).

In this embodiment, the metallization layer 116-1 may have a protrusion 116-1p, and the channel layer 106-1 may be partially surrounded by the protrusion 116-1p. The protrusion 116-1p may allow a relatively large overlay error when patterning the metallization layer 116-1, which may prevent leakage between the metallization layer 116-1 and the channel layer 106-1.

In this embodiment, the protrusion 116 - 1 p of the metallization layer 116 - 1 may face the metallization layer 116 - 2 , and the protrusion 116 - 2 p of the metallization layer 116 - 2 may face the metallization layer 116 - 1 , thereby reducing the size of the memory device 100 .

FIG. 2A and FIG. 2B illustrate a memory device 200 of some embodiments of the present disclosure, wherein FIG. 2A is a top view and FIG. 2B is a cross-sectional view along line BB' of FIG. 2A. It should be noted that some elements or features are omitted in FIG. 2A for the sake of brevity. The memory device 200 is similar to the memory device 100 shown in FIG. 1A and FIG. 1B, and the differences between the two are as follows.

As shown in FIG. 2A , the memory device 200 may include a substrate 202 , a plurality of metallization layers 216 - 1 and 216 - 2 , a plurality of gate dielectrics 204 - 1 and 204 - 2 , a plurality of channel layers 206 - 1 and 206 - 2 , and a dielectric layer 212 .

Each of the metallization layers 216-1 and 216-2 may extend along the Y axis. Each of the metallization layers 216-1 and 216-2 may be parallel. In some embodiments, each of the metallization layers 216-1 and 216-2 may be physically separated. The material of the metallization layers 216-1 and 216-2 may be the same or similar to the material of the metallization layer 116-1. In some embodiments, the metallization layers 216-1 and 216-2 may be referred to as top word lines. In some embodiments, the metallization layers 116-1 and 116-2 (as shown in FIG. 2B ) may be referred to as bottom word lines.

In some embodiments, the material of substrate 202 can be the same or similar to the material of substrate 102. In some embodiments, substrate 202 can also be referred to as a top substrate. In some embodiments, substrate 102 (as shown in FIG. 2B ) can also be referred to as a bottom substrate.

The metallization layer 216-1 may include a sidewall 216s1 and a sidewall 216s2 opposite thereto. The sidewall 216s2 of the metallization layer 216-1 may face the metallization layer 216-2. In some embodiments, the metallization layer 216-1 may have a protrusion 216-1p. In some embodiments, the protrusion 216-1p of the metallization layer 216-1 may face the metallization layer 216-2. In some embodiments, the sidewall 216s2 of the metallization layer 216-1 may protrude toward the metallization layer 216-2, thereby defining the protrusion 216-1p.

The metallization layer 216-2 may include a sidewall 216s3 and a sidewall 216s4 opposite thereto. The sidewall 216s3 of the metallization layer 216-2 may face the metallization layer 216-1. In some embodiments, the metallization layer 216-2 may have a protrusion 216-2p. In some embodiments, the protrusion 216-2p of the metallization layer 216-2 may face the metallization layer 216-1. In some embodiments, the sidewall 216s3 of the metallization layer 216-2 may protrude toward the metallization layer 216-1, thereby defining the protrusion 216-2p.

In some embodiments, the protrusions 216-1p of the metallization layer 216-1 and the protrusions 216-2p of the metallization layer 216-2 may be staggered. In some embodiments, the protrusions 216-1p of the metallization layer 216-1 may be arranged alternately with the protrusions 216-2p of the metallization layer 216-2 along the X-axis. In some embodiments, the protrusions 216-1p of the metallization layer 216-1 may not overlap with the protrusions 216-2p of the metallization layer 216-2 along the X-axis. In other embodiments, the protrusions 216-1p of the metallization layer 216-1 may partially overlap with the protrusions 216-2p of the metallization layer 216-2 along the X-axis. In some embodiments, the protrusions 216-1p and/or 216-2p may have a semicircular or semi-elliptical profile when viewed from a top view. However, the present disclosure is not intended to be limiting.

In some embodiments, metallization layer 216-1 may be disposed on metallization layer 120-1. In some embodiments, metallization layer 216-2 may be disposed on metallization layer 120-2. In some embodiments, each of metallization layers 216-1 and 216-2 may be located at a higher level than metallization layers 120-1 and 120-2.

In some embodiments, gate dielectrics 204-1 and 204-2 may be disposed on the sidewalls of the word line (not shown). In some embodiments, gate dielectric 204-1 may be embedded in metallization layer 216-1. In some embodiments, gate dielectric 204-2 may be embedded in metallization layer 216-2. In some embodiments, gate dielectric 204-1 may be surrounded by metallization layer 216-1. In some embodiments, gate dielectric 204-2 may be surrounded by metallization layer 216-2. In some embodiments, each of the gate dielectrics 204-1 and 204-2 may overlap with the metallization layer 120-1 or 120-2 along the Z-axis.

In some embodiments, the material of gate dielectrics 204-1 and 204-2 may be the same or similar to the material of gate dielectric 104-1. In some embodiments, gate dielectrics 204-1 and 204-2 may be referred to as top gate dielectric layers, while gate dielectrics 104-1 and 104-2 (as shown in FIG. 2B) may be referred to as bottom gate dielectric layers.

In some embodiments, each of the channel layers 206-1 and 206-2 may be disposed on a sidewall of the gate dielectric 204-1 or 204-2 (not shown). In some embodiments, each of the channel layers 206-1 and 206-2 may be embedded in the gate dielectric 204-1 or 204-2. In some embodiments, each of the channel layers 206-1 and 206-2 may be surrounded by the gate dielectric 204-1 or 204-2. In some embodiments, each of the channel layers 206-1 and 206-2 may be in contact with the gate dielectric 204-1 or 204-2.

In some embodiments, each of the channel layers 206-1 and 206-2 may be disposed on a sidewall of the metallization layer 216-1 or 216-2 (not shown). In some embodiments, each of the channel layers 206-1 and 206-2 may be embedded in the metallization layer 216-1 or 216-2. In some embodiments, each of the channel layers 206-1 and 206-2 may be surrounded by the metallization layer 216-1 or 216-2.

In some embodiments, the material of channel layers 206-1 and 206-2 can be the same or similar to the material of channel layer 106-1. In some embodiments, channel layers 206-1 and 206-2 can be referred to as top channel layers, while channel layers 106-1 and 106-2 (as shown in FIG. 2B) can be referred to as bottom channel layers.

In some embodiments, channel layers 206-1 and 206-2 may be staggered. In some embodiments, channel layer 206-1 may be arranged in an alternating manner with channel layer 206-2 along the X-axis. In some embodiments, channel layer 206-1 may not overlap with channel layer 206-2 along the X-axis. In some embodiments, channel layer 206-1 may overlap with protrusion 216-1p along the X-axis. In some embodiments, channel layer 206-2 may overlap with protrusion 216-2p along the X-axis.

In some embodiments, each of the channel layers 206-1 and 206-2 may overlap with the metallization layer 120-1 or 120-2 along the Z-axis. In some embodiments, each of the channel layers 206-1 and 206-2 may be completely surrounded by the gate dielectric 204-1 or 204-2 from a top view.

A distance D7 may be provided between the sidewall 216s1 of the metallization layer 216-1 and the channel layer 206-1 along the X-axis. A distance D8 may be provided between the sidewall 216s2 of the metallization layer 216-1 and the channel layer 206-1 along the X-axis. In some embodiments, the distance D7 may be different from the distance D8. In some embodiments, the distance D8 may be greater than the distance D7.

A distance D9 may be provided between the sidewall 216s3 of the metallization layer 216-2 and the channel layer 206-2 along the X-axis. A distance D10 may be provided between the sidewall 216s4 of the metallization layer 216-2 and the channel layer 206-2 along the X-axis. In some embodiments, the distance D9 may be different from the distance D10. In some embodiments, the distance D9 may be greater than the distance D10.

In some embodiments, the sidewall 216s1 of the metallization layer 216-1 may have a relatively straight edge. In some embodiments, the sidewall 216s4 of the metallization layer 216-2 may have a relatively straight edge. There may be a distance D11 between the metallization layer 216-1s of the metallization layer 216-1 and the sidewall 216s4 of the metallization layer 216-2 along the X-axis. In some embodiments, the distance D11 may be substantially uniform or constant along the Y-axis.

There may be a distance D12 between the sidewall 216s2 of the metallization layer 216-1 and the sidewall 216s3 of the metallization layer 216-2 along the X-axis. In some embodiments, the distance D12 may vary along the Y-axis.

In some embodiments, dielectric layer 212 may be disposed on a sidewall of metallization layer 216-1 or 216-2. In some embodiments, dielectric layer 212 may be disposed between metallization layers 216-1 and 216-2. In some embodiments, each of gate dielectrics 204-1 and 204-2 may be physically separated from dielectric layer 212. In some embodiments, each of gate dielectrics 204-1 and 204-2 may be physically separated from dielectric layer 212 by metallization layer 216-1 or 216-2. In some embodiments, the material of dielectric layer 212 may be the same or similar to the material of dielectric layer 112.

In some embodiments, each of the channel layer 206-1 or 206-2 can be physically separated from the dielectric layer 212. In some embodiments, the channel layer 206-1 or 206-2 can be physically separated from the dielectric layer 212 by the gate dielectrics 204-1 and 204-2 and the metallization layer 216-1 or 216-2.

As shown in FIG. 2B , memory element 200 may include cells 140-1, 140-2, 240-1, and 240-2. Each cell 240-1 and 240-2 may be located at a higher level than cells 140-1 and 140-2. In some embodiments, each cell 140-1 and 140-2 may also be referred to as a bottom cell. In some embodiments, each of cells 240-1 and 240-2 may also be referred to as a top cell.

The cell 140-1 may include a capacitor 108-1, a channel layer 106-1, a metallization layer 116-1, a contact plug 118-1, and a metallization layer 120-1.

The cell 140-2 may include a capacitor 108-2, a channel layer 106-2, a metallization layer 116-2, a contact plug 118-2, and a metallization layer 120-2.

The cell 240-1 may include a capacitor 208-1, a channel layer 206-1, a metallization layer 216-1, a contact plug 218-1, and a metallization layer 120-1.

The cell 240-2 may include the capacitor 208-2, the channel layer 206-2, the metallization layer 216-2, the contact plug 218-2, and the metallization layer 120-2.

In some embodiments, protrusion 216-1p of metallization layer 216-1 may partially or completely overlap protrusion 116-1p of metallization layer 116-1 along the Z axis. In some embodiments, protrusion 216-2p of metallization layer 216-2 may partially or completely overlap protrusion 116-2p of metallization layer 116-2 along the Z axis.

In some embodiments, metallization layers 120-1 and 120-2 may be disposed within dielectric layer 150. In some embodiments, metallization layer 120-1 may be disposed between cells 140-1 and 240-1. In some embodiments, metallization layer 120-1 may be disposed between channel layers 106-1 and 206-1.

In some embodiments, the metallization layer 120-1 can be disposed between the channel layer 106-1 and 206-1. In some embodiments, the metallization layer 120-1 can be disposed between the metallization layer 116-1 and 216-1. In some embodiments, the metallization layer 120-1 can be disposed between the capacitor 108-1 and 208-1. In some embodiments, the metallization layer 120-1 can be disposed between the channel layer 106-1 and the capacitor 208-1. In some embodiments, the metallization layer 120-1 can be used as a common bit line for the cells 140-1 and 240-1. In some embodiments, the metallization layer 120-2 can be used as a common bit line for the cells 140-2 and 240-2.

In this embodiment, metallization layer 120-1 can be used as a common bit line. Therefore, the size of memory element 200 can be reduced. In addition, the capacitance of memory element 200 can be increased.

FIG. 3 is a flow chart illustrating a method 300 for fabricating a memory device according to some embodiments of the present disclosure.

The preparation method 300 begins with operation 302, where a substrate may be provided. In some embodiments, a first capacitor and a second capacitor may be formed in the substrate. In some embodiments, a contact plug may be formed in the substrate and on the first capacitor and the second capacitor. In some embodiments, a first dielectric layer may be formed on the substrate. In some embodiments, a conductive layer may be formed on the first dielectric layer. In some embodiments, a second dielectric layer may be formed on the conductive layer.

The preparation method 300 continues with operation 304, in which a certain patterning process may be performed to remove the first dielectric layer, the second dielectric layer, and a portion of the conductive layer, thereby forming a first word line and a second word line. A plurality of openings may be formed to expose a top surface of the substrate.

In some embodiments, the conductive layer may be patterned to form a first protrusion of the first word line. In some embodiments, the conductive layer may be patterned to form a second protrusion of a second word line. In some embodiments, the first protrusion may face the second word line. In some embodiments, the second protrusion may face the first word line.

The fabrication method 300 continues with operation 306 where a third dielectric layer may be formed to fill the opening.

The preparation method 300 continues with operation 308, where the second dielectric layer, the first word line and the second word line and a portion of the first dielectric layer can be removed. An opening can be formed in the first word line. An opening can be formed in the second word line.

The fabrication method 300 continues with operation 310, where a first gate dielectric and a first channel layer may be formed in the opening of the first word line. The second gate dielectric and the second channel layer may be formed in the opening of the second word line.

The fabrication method 300 continues with operation 312, where a first bit line and a second bit line may be formed on the first channel layer and the second channel layer, respectively, thereby forming a memory device.

Preparation method 300 is merely an example and is not intended to limit the present disclosure beyond the scope explicitly mentioned in the scope of the application. Additional operations may be provided before, during, or after each operation of preparation method 300, and some operations described may be replaced, eliminated, or reordered for other embodiments of the method. In some embodiments, preparation method 300 may include further operations not depicted in FIG. 3. In some embodiments, preparation method 300 may include one or more operations described in FIG. 3.

4A to 9A and 4B to 9B illustrate one or more stages of a memory device fabrication method according to some embodiments of the present disclosure, wherein 4A to 9A are top views, and 4B to 9B are cross-sectional views taken along line AA' of 4A to 9A, respectively. It should be noted that, for the sake of brevity, some elements are illustrated in the cross-sectional views but not in the top views.

As shown in FIGS. 4A and 4B , a substrate 102 may be provided. In some embodiments, capacitors 108-1 and 108-2 may be formed in the substrate 102. In some embodiments, contact plugs 118 may be formed in the substrate 102 and on the capacitors 108-1 and 108-2. In some embodiments, a dielectric layer 110 may be formed on the substrate 102. In some embodiments, a conductive layer 116 may be formed on the dielectric layer 110. In some embodiments, a dielectric layer 114 may be formed on the conductive layer 116. The dielectric layer 110 and the dielectric layer 114 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), or other suitable processes. The conductive layer 116 may be formed by sputtering, PVD, or other suitable processes.

As shown in FIGS. 5A and 5B , a patterning process may be performed to remove a portion of the dielectric layer 110, the dielectric layer 114, and the conductive layer 116. Thus, metallization layers 116-1 and 116-2 are formed. A plurality of openings 116-r1 may be formed to expose the upper surface of the substrate 102. The patterning process may include lithography, etching, or other suitable processes. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process may include, for example, dry or wet etching.

In some embodiments, the conductive layer 116 may be patterned to form a protrusion 116-1p of the metallization layer 116-1. In some embodiments, the conductive layer 116 may be patterned to form a protrusion 116-2p of the metallization layer 116-2. In some embodiments, the protrusion 116-1p may face the metallization layer 116-2. In some embodiments, the protrusion 116-2p may face the metallization layer 116-1.

6A and 6B , a dielectric layer 112 may be formed to fill the opening 116 - r1 . The dielectric layer 112 may be formed by CVD, ALD, PVD, LPCVD or other suitable processes.

As shown in FIGS. 7A and 7B , dielectric layer 114, metallization layers 116-1 and 116-2, and a portion of dielectric layer 110 may be removed. An opening 116r2-1 may be formed in metallization layer 116-1. An opening 116r2-2 may be formed in metallization layer 116-2. In some embodiments, openings 116r2-1 and 116r2-2 may be staggered. In some embodiments, opening 116r2-1 may not overlap with opening 116r2-2 along the X-axis. In other embodiments, opening 116r2-1 may partially overlap with opening 116r2-2 along the X-axis.

As shown in FIG8A and FIG8B , a gate dielectric 104-1 and a channel layer 106-1 may be formed in the opening 116r2-1. A gate dielectric 104-2 and a channel layer 106-2 may be formed in the opening 116r2-2. The manufacturing techniques of the gate dielectrics 104-1 and 104-2 and the channel layers 106-1 and 106-2 may include CVD, ALD, PVD, LPCVD or other suitable processes.

9A and 9B , metallization layers 120-1 and 120-2 may be formed on dielectric layer 112, thereby forming memory device 100. The fabrication techniques of metallization layers 120-1 and 120-2 may include sputtering, PVD or other suitable processes.

In the present embodiment, the word line (e.g., 116-1 and/or 116-2) has a protrusion (e.g., 116-1p and 116-2p). When the word line is patterned to form an opening (e.g., 116r2-1 and/or 116r2-2) in the channel layer (e.g., 106-1 and/or 106-2) therein, the protrusion can allow a relatively large overlay error. Therefore, leakage between the word line and the channel layer can be prevented.

One aspect of the present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed in the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed in the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protrusion protruding toward the second metallization layer.

Another aspect of the present disclosure provides another memory element. The memory element includes a bottom substrate, a first bottom unit, a top substrate, a first top unit and a common bit line. The first bottom unit includes a first bottom capacitor disposed in the bottom substrate. The first bottom unit also includes a first bottom word line disposed on the bottom substrate and extending along a first direction. The first bottom unit further includes a first bottom channel layer surrounded by the first bottom word line. The first top unit includes a first top capacitor disposed in the top substrate. The first top unit also includes a first top word line disposed on the top substrate and extending along the first direction. The first top unit further includes a first top channel layer surrounded by the first top word line. The common bit line is disposed between the first bottom unit and the first top unit and extends along a second direction substantially perpendicular to the first direction.

Another aspect of the present disclosure provides a method for preparing a memory element. The preparation method includes providing a substrate. The preparation method also includes forming a conductive layer on the substrate. The preparation method further includes patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction. The first metallization layer has a first protrusion protruding toward the second metallization layer. In addition, the preparation method also includes forming a first channel layer in the first metallization layer and forming a second channel layer in the second metallization layer.

The disclosed embodiment provides a memory device. The memory device may include a word line having a protrusion. The protrusion may make the stacking error of the word line pattern relatively large to form an opening (in which a channel layer is formed), which may prevent electrical leakage between the word line and the channel layer.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure defined by the scope of the patent application. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

100: memory element 102: substrate 104-1: gate dielectric 104-2: gate dielectric 106-1: channel layer 106-2: channel layer 108-1: capacitor 108-2: capacitor 110: dielectric layer 112: dielectric layer 114: dielectric layer 116: conductive layer 116-1: metallization layer 116-1p: protrusion 116-2: metallization layer 116-2p: protrusion 116-r1: opening 116r2-1: opening 116r2-2: opening 116s1: sidewall 116s2: sidewall 116s3: sidewall 116s4: sidewall 118: contact plug 118-1: contact plug 118-2: contact plug 120-1: metallization layer 120-2: metallization layer 140-1: cell 140-2: cell 150: dielectric layer 200: memory element 202: substrate 204-1: gate dielectric 204-2: gate dielectric 206-1: channel layer 206-2: channel layer 208-1: capacitor 208-2: capacitor 212: dielectric layer 216-1: metallization layer 216-1p: protrusion 216-2: metallization layer 216-2p: protrusion 216s1: side wall 216s2: side wall 216s3: side wall 216s4: side wall 218-1: contact plug 218-2: contact plug 240-1: unit 240-2: unit 300: preparation method 302: operation 304: operation 306: operation 308: operation 310: operation 312: operation 314: operation A-A': line B-B': line D1: distance D2: distance D3: distance D4: distance D5: distance D6: distance D7: distance D8: distance D9: distance D10: distance D11: distance D12: distance X: axis Y: axis Z: axis

When referring to the embodiments and the scope of the patent application together with the drawings, a more comprehensive understanding of the disclosure of the present application can be obtained. The same element symbols in the drawings refer to the same elements. FIG. 1A is a top view illustrating a memory element of some embodiments of the present disclosure. FIG. 1B is a cross-sectional view of the memory element of FIG. 1A along the line A-A' of some embodiments of the present disclosure. FIG. 2A is a top view illustrating a memory element of some embodiments of the present disclosure. FIG. 2B illustrates a cross-sectional view of the memory element of FIG. 2A along the line B-B' of some embodiments of the present disclosure. FIG. 3 is a flow chart illustrating a method for preparing a memory element of some embodiments of the present disclosure. FIG. 4A illustrates one or more stages of a method for preparing a memory element of some embodiments of the present disclosure. FIG. 4B is a cross-sectional view taken along line AA' of FIG. 4A according to some embodiments of the present disclosure. FIG. 5A illustrates one or more stages of a method for preparing a memory element according to some embodiments of the present disclosure. FIG. 5B is a cross-sectional view taken along line AA' of FIG. 5A according to some embodiments of the present disclosure. FIG. 6A illustrates one or more stages of a method for preparing a memory element according to some embodiments of the present disclosure. FIG. 6B is a cross-sectional view taken along line AA' of FIG. 6A according to some embodiments of the present disclosure. FIG. 7A illustrates one or more stages of a method for preparing a memory element according to some embodiments of the present disclosure. FIG. 7B is a cross-sectional view taken along line AA' of FIG. 7A according to some embodiments of the present disclosure. FIG. 8A illustrates one or more stages of a method for preparing a memory device according to some embodiments of the present disclosure. FIG. 8B illustrates a cross-sectional view of FIG. 8A along line AA' according to some embodiments of the present disclosure. FIG. 9A illustrates one or more stages of a method for preparing a memory device according to some embodiments of the present disclosure. FIG. 9B illustrates a cross-sectional view of FIG. 9A along line AA' according to some embodiments of the present disclosure.

100:Memory device

102: Base

104-1: Gate dielectric

104-2: Gate dielectric

106-1: Channel layer

106-2: Channel level

112: Dielectric layer

116-1: Metallization layer

116-1p: Protrusion

116-2: Metallization layer

116-2p: protrusion

116s1: Side wall

116s2: Side wall

116s3: Side wall

116s4: Side wall

120-1: Metallization layer

120-2: Metallization layer

A-A': line

D1: Distance

D2: Distance

D3: Distance

D4: Distance

D5: Distance

D6: Distance

X: axis

Y: axis

Z: axis

Claims (12)

A method for preparing a memory element includes: forming a first bottom unit in a bottom substrate, including: forming a first bottom capacitor in the bottom substrate; forming a first bottom word line on the bottom substrate and extending along a first direction; and forming a first bottom channel layer surrounded by the first bottom word line; forming a first top unit in a top substrate, including: forming a first top capacitor in the top substrate; forming a first top word line on the top substrate and extending along the first direction; and forming a first bottom channel layer surrounded by the first top word line. A first top channel layer; a common bit line is formed between the first bottom unit and the first top unit and extends along a second direction substantially perpendicular to the first direction; a second bottom unit is formed, including: a second bottom word line is formed on the bottom substrate and extends along the first direction; and a second bottom channel layer is formed surrounded by the second bottom word line; wherein the first bottom word line includes a protrusion protruding toward the second bottom word line, and the protrusion of the first bottom word line and the protrusion of the second bottom word line are arranged alternately along the second direction. A method for preparing a memory device as described in claim 1, wherein the first top word line is formed between the first top capacitor and the common bit line. A method for preparing a memory device as described in claim 1, wherein the first top word line is formed between the first top capacitor and the first bottom word line. A method for preparing a memory device as described in claim 1, wherein forming the first top word line includes forming a protrusion. A method for preparing a memory device as described in claim 1, wherein the second bottom word line includes a protrusion protruding toward the first bottom word line. A method for preparing a memory device as described in claim 1, wherein the first bottom channel layer and the second bottom channel layer are arranged alternately along the second direction. A method for preparing a memory device as described in claim 1, wherein the first top word line has a protrusion. A method for preparing a memory device as described in claim 7, wherein the protrusion of the first bottom word line overlaps with the protrusion of the first top word line along a third direction, and the third direction is substantially perpendicular to the first direction and the second direction. A method for preparing a memory device as described in claim 7, wherein the first top channel layer overlaps with the protrusion of the first top word line along the second direction. The method for preparing a memory element as described in claim 7 further includes: forming a second top unit, including: forming a second top word line on the top substrate and extending along the first direction; and forming a second top channel layer surrounded by the second top word line; wherein the second top word line includes a protrusion protruding toward the first top word line. A method for preparing a memory device as described in claim 10, wherein the first top word line has a first sidewall and a second sidewall opposite to the first sidewall, the second sidewall faces the second top word line, and a first distance between the first sidewall and the first top channel layer is different from a second distance between the second sidewall and the first top channel layer. A method for preparing a memory device as described in claim 11, wherein the second top word line has a third sidewall and a fourth sidewall, the third sidewall faces the first top word line, and a third distance between the third sidewall and the second top channel layer is different from a fourth distance between the fourth sidewall and the second top channel layer.