TWI871246B - Vertical super junction power semiconductor device - Google Patents

Abstract

A vertical super junction power semiconductor device includes a semiconductor substrate, a semiconductor layer, a well and a first pillar within the semiconductor, a source within the well, two gate components, a filler and a source contact metal layer. The semiconductor layer has a trench recessed downwardly from a top surface thereof. The well and the source are proximate to the top surface and are divided by the trench into two spaced-apart well regions and source regions, respectively. Each well region has a first doping portion and second doping portion contacting the trench, and each second doping portion is located inside the corresponding one of the first doping portion. Each source region is located inside the corresponding one of the first doping portion and contacted with the corresponding one of the second doping portion. The first pillar has two pillar regions located on opposite sides of the trench, and each pillar region extends downwardly from the corresponding one of the first doping region. The gate components is located on opposite sides of the trench. The filler fills in the trench, and is composed of poly silicon or oxide. The source contact metal layer covers and contacts a top end of the filler, the source and the well. A depth of each pillar region is less than or equal to 3/4 of the semiconductor layer thickness.

Description

Vertical superjunction power semiconductor device

The present invention relates to a power semiconductor device, in particular to a vertical superjunction power semiconductor device.

Environmental pollution problems brought about by the evolution of technology have always been an important topic of concern to government agencies and the technology industry. In order to save energy and reduce environmental pollution caused by carbon emissions, industries such as the fifth generation wireless system (5G) and the geostationary earth orbit system are all committed to improving component efficiency to reduce power consumption. In the aforementioned systems, power semiconductor devices play a very important role, because the power processor (converter/inverter) of the aforementioned system needs to use a large number of power semiconductor devices to perform the opening and closing actions of the circuit. As is known to those who are familiar with power semiconductor devices, conduction loss and switching loss are generated during the on-off operation of the power semiconductor device.

As described in the previous paragraph, power is lost in power semiconductor devices between the on and off of the power processor. Generally speaking, during the on period, power semiconductor devices need to have a low on resistance (Ron) to reduce power consumption in the resistor, and during the off period, power semiconductor devices need to have a low reverse leakage current to reduce additional power loss. However, traditional silicon (Si) crystal power semiconductor devices can no longer meet the aforementioned electrical characteristics. Based on the energy bandwidth of third-generation semiconductors (such as SiC), it helps to resist high breakdown voltages; therefore, vertical power semiconductors and vertical super junction power semiconductor devices composed of SiC have been developed one after another. The vertical superjunction power semiconductor device can make its internal electric field distribution range wider under the reverse bias operation condition to increase its reverse breakdown voltage (i.e., increase the ability to resist reverse leakage current), thereby reducing the on-resistance. Therefore, the vertical superjunction power semiconductor device has been widely used in the above-mentioned system in recent years.

Referring to FIG. 1 , a conventional vertical power semiconductor device (hereinafter referred to as Case 1) 1 includes a semiconductor substrate 11 with N-type carriers, a drain contact (drain The semiconductor substrate 11 includes a semiconductor epitaxial layer 13 and a semiconductor contact layer 12, a semiconductor epitaxial layer 13 formed on the semiconductor substrate 11 and having N-type carriers, a well 14 disposed in the semiconductor epitaxial layer 13 and close to an upper surface 131 of the semiconductor epitaxial layer 13 and having P-type carriers, a source 15 disposed in the well 14 and close to the upper surface 131 of the semiconductor epitaxial layer 13 and having N-type carriers, two gate units 17 disposed on the upper surface 131 of the semiconductor epitaxial layer 13, and a source contact layer 18 on the upper surface 131 of the semiconductor epitaxial layer 13 and partially covering the gate units 17 and connected to the source 15. The well 14 has a first doped region 141 and a second doped region 142 in the first doped region 141. The source 15 is located at opposite sides of the second doped region 142. Each gate unit 17 has a gate dielectric layer 171 covering the upper surface 131 of the semiconductor epitaxial layer 13, the first doped region 141 and partially covering the source 15, a gate 172 stacked on each gate dielectric layer 171, and an insulating layer 173 covering each gate 172.

Referring to FIG. 2 , a conventional vertical superjunction power semiconductor device (hereinafter referred to as Case 2) 10 is substantially the same as Case 1. Case 2 differs from Case 1 in that it further includes a column 16 extending from the well 14 toward the semiconductor substrate 11 and having P-type carriers. The opposite sides of the column 16 contact the semiconductor epitaxial layer 13. A structure similar to Case 2 can also be seen in the technology disclosed in the Republic of China's new patent case No. TWM409532 (hereinafter referred to as Case 3).

Although the structures of the previous cases 2 and 3 can make the internal electric field distribution range wider under the reverse bias operation condition to increase the reverse breakdown voltage, thereby reducing the on-resistance, however, during the actual operation of the previous cases 2 and 3, the N-type carriers drifting in the semiconductor epitaxial layer 13 are easily blocked by the pillar 16. Therefore, there is still room for improvement in the contribution of the previous cases 2 and 3 to reducing the on-resistance.

As can be seen from the above description, improving the structure of vertical superjunction power semiconductor devices to effectively reduce on-resistance is a problem to be solved by relevant industry players in the relevant technical field.

Therefore, an object of the present invention is to provide a vertical superjunction power semiconductor device that can effectively reduce on-resistance.

Therefore, the vertical superjunction power semiconductor device of the present invention includes: a semiconductor substrate containing a first type of carrier, a semiconductor layer formed on the semiconductor substrate, a well, a source, a first column, two gate components, a filling body, and a source contact metal layer.

The semiconductor layer contains first type carriers and includes a trench recessed from a top surface of the semiconductor layer toward the semiconductor substrate.

The well is located in the semiconductor layer and close to the top surface and contains the second type carriers, and is divided into two well regions separated from each other by the trench region. Each well region includes a first doping portion contacting the trench and a second doping portion in each corresponding first doping portion. And each second doping portion contacts the trench.

The source is located in the semiconductor layer and close to the top surface and contains first type carriers, and is divided into two source regions spaced apart from each other by the trench region. Each source region is located in a first doping portion corresponding to the source region and contacts a second doping portion corresponding to the source region.

The first column is located in the semiconductor layer and includes two column regions located at opposite sides of the trench and containing second type carriers. Each column region extends from the first doped portion corresponding to each other toward the semiconductor substrate.

The two gate components are arranged on the top surface of the semiconductor layer at intervals and located on opposite sides of the trench. Each gate component includes a dielectric layer covering the top surface of the semiconductor layer, a first doping portion corresponding to each and partially covering a source region corresponding to each, a gate layer stacked on the dielectric layer corresponding to each, and an insulating film covering the gate layer corresponding to each.

The filling body is filled in the trench and is made of polysilicon or oxide.

The source contact metal layer covers and contacts a top edge of the filling body, the source regions and the second doping parts. In the present invention, a depth of each column region in the semiconductor layer is less than or equal to three quarters of a thickness of the semiconductor layer.

The effect of the present invention is that the depth of each column region of the first column occupies at most three quarters of the thickness of the semiconductor layer, which can increase the drift width of the first type carrier in the semiconductor layer during operation of the device to reduce the probability of the first type carrier being blocked by each first column, thereby reducing the on-resistance (Ron).

Before the present invention is described in detail, it should be noted that similar components are represented by the same reference numerals in the following description.

Referring to FIG. 3 , a first embodiment of the vertical superjunction power semiconductor device of the present invention includes a semiconductor substrate 2 containing a first type of carrier, a semiconductor layer 3 formed on the semiconductor substrate 2, a well 4, a source 5, a first pillar 61, two gate components 7, a filler, a source contact metal layer 8, and a drain contact metal layer 9 formed under the semiconductor substrate 2. It should be noted that, as is known to those familiar with power semiconductor devices, the most common power semiconductor device is a transistor. The basic structure of the transistor includes a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a source in the semiconductor layer, a well, a dielectric layer on the semiconductor layer, a gate and an insulating layer, a source contact contacting the source and the well, and a drain contact under the semiconductor substrate. It should be known that a power semiconductor device is composed of a plurality of transistors arranged in a two-dimensional array. Therefore, in the first embodiment of the present invention, only two gate components 7 are used as an example for explanation, but it is not limited to this. The applicant describes them together here.

The semiconductor layer 3 contains the first type of carriers and includes a trench 30 recessed from a top surface 31 of the semiconductor layer 3 toward the semiconductor substrate 2. In the first embodiment of the present invention, the semiconductor layer 3 is a silicon carbide (SiC) epitaxial layer made by MOCVD or MBE, and the semiconductor substrate 2 is a silicon carbide substrate.

The well 4 is located in the semiconductor layer 3 and close to the top surface 31 of the semiconductor layer 3 and contains the second type carriers, and is divided into two well regions 41 separated from each other by the trench 30. Specifically, the two well regions 41 are located on opposite sides of the trench 30. Each well region 41 includes a first doping portion 411 contacting the trench 30, and a second doping portion 412 in each corresponding first doping portion 411. And each second doping portion 412 contacts the trench 30.

The source 5 is located in the semiconductor layer 3 and close to the top surface 31 and contains the first type of carriers, and is divided into two source regions 51 spaced apart from each other by the trench 30. The two source regions 51 are located on opposite sides of the trench 30. Specifically, each source region 51 is located in the first doping portion 411 corresponding to the source region 51 and contacts the second doping portion 412 corresponding to the source region 51.

The first column 61 is located in the semiconductor layer 3 and includes two column regions 611 on opposite sides of the trench 30 and containing the second type carrier. Specifically, each column region 611 extends from the first doping portion 411 corresponding to each column region 611 toward the semiconductor substrate 2. In the first embodiment of the present invention, the first type carrier and the second type carrier are respectively described as N-type carriers and P-type carriers, but are not limited thereto. Each column region 611, the first doping portion 411 and the second doping portion 412 of each well region 41 each have a doping concentration. Specifically, the doping concentration of each column region 611 is less than the doping concentration of the first doping portion 411 of each well region 41, and the doping concentration of the first doping portion 411 of each well region 41 is less than the doping concentration of the second doping portion (P+) 412 of each well region 41. In other words, the second doping portion (P+) 412 of each well region 41 is a heavily doped portion.

The two gate components 7 are disposed on the top surface 31 of the semiconductor layer 3 at intervals and are located on opposite sides of the trench 30. Each gate component 7 includes a dielectric layer 71 covering the top surface 31 of the semiconductor layer 3, a first doping portion 411 corresponding to each gate component 7 and partially covering a source region 51 corresponding to each gate component 7, a gate layer 72 stacked on the dielectric layer 71 corresponding to each gate component 72, and an insulating film 73 covering the gate layer corresponding to each gate component 73. In the first embodiment of the present invention, each gate layer 72 is illustrated as a polycrystalline silicon layer, but is not limited thereto.

The filling body is filled in the trench 30 of the semiconductor layer 3 and is made of polysilicon S or oxide O. In the first embodiment of the present invention, the filling body is made of polysilicon S.

The source contact metal layer 8 covers and contacts a top edge of the filling body (polysilicon S), the source regions 51 and the second doping portions 412. Specifically, the filling body (polysilicon S) in the trench 30 contacts the first doping portions 411. In some embodiments, the column regions 611 of the first column 61 contact the polysilicon S, and a depth of each column region 611 in the semiconductor layer 3 is less than or equal to three quarters of a thickness of the semiconductor layer 3. In the first embodiment of the present invention, a depth of each column region 611 in the semiconductor layer 3 is less than or equal to one half of the thickness of the semiconductor layer 3.

From the detailed description of the first embodiment of the present invention and referring to FIG. 3 , it can be seen that the polysilicon S filled in the trench 30 can also serve as a current path when the first embodiment is in operation, so as to reduce the forward resistance (i.e., on-resistance) of the first embodiment when it is turned on. In addition, when the first embodiment is in operation, the depth of each column region 611 only occupies half of the thickness of the semiconductor layer 3, which can increase the drift width of the N-type carriers in the semiconductor layer 3 to reduce the probability of the N-type carriers being blocked by each column region 611, thereby reducing the on-resistance. Therefore, it can be expected that the first embodiment has the ability to resist reverse leakage current. The relevant electrical test results of the first embodiment will be described later.

4 , a second embodiment of the vertical superjunction power semiconductor device of the present invention is substantially the same as the first embodiment, except that the first column 61 further includes a connection region 612 connected to the column regions 611, and the column regions 611 and the connection region 612 cover a bottom edge of the polysilicon S.

5 , a third embodiment of the vertical superjunction power semiconductor device of the present invention is substantially the same as the first embodiment, except that the filling body of the third embodiment is composed of oxide O, and the third embodiment further includes a second pillar 62 located in the semiconductor layer 3. The second pillar 62 contains second-type carriers (i.e., P-type carriers) and extends from a bottom edge of the oxide O toward the semiconductor substrate 2. The oxide O applicable to the third embodiment of the present invention may be silicon dioxide (SiO ₂ ), helium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), or titanium dioxide (TiO ₂ ). In the third embodiment of the present invention, the oxide O is described by taking SiO ₂ as an example, but is not limited thereto, and the second column 62 is located in the semiconductor layer 3 at a depth less than or equal to one-half of the thickness of the semiconductor layer 3, and the second column 62 has a doping concentration substantially equal to the doping concentration of each column region 611. Through the design of the second column (containing P-type carriers) 62 located at the bottom of the oxide O, the third embodiment can reduce the potential and electric field at a PN junction and an edge of the trench 30 during operation.

6 , a fourth embodiment of the vertical superjunction power semiconductor device of the present invention is substantially the same as the first embodiment, except that the filling body of the fourth embodiment is made of oxide O, and the column regions 611 of the first column 61 are in contact with the oxide O.

As shown in FIG. 7a, FIG. 7b, FIG. 7c and FIG. 7d, the forward currents of the embodiments are higher than that of the previous case 2. This shows that the design of each column region 611 of the first column 61 of the embodiments makes it difficult for the N-type carriers drifting in the semiconductor layer 3 to be blocked, so as to reduce the on-resistance (Ron) when it is turned on. Therefore, the on-resistance (Ron) of the embodiments is lower than that of the previous case 2. In addition, since polysilicon S can also serve as the current path of the first embodiment and the second embodiment when they are in operation; therefore, the forward currents of the first embodiment and the second embodiment are higher than those of the third embodiment and the fourth embodiment.

As shown in FIG. 8a, FIG. 8b, FIG. 8c and FIG. 8d, the reverse bias voltages of the embodiments are between 1800 V and 2160 V, which are all higher than the reverse bias voltage of the prior art 1 (only about 1400 V). The analysis results of FIG. 8a, FIG. 8b, FIG. 8c and FIG. 8d illustrate that the structural design of each column region 611 of the first column 61 of the embodiments of the present invention can disperse its electric field and potential during operation, so that its ability to resist reverse leakage current is better than that of the prior art 1. In addition, since the ability of polysilicon S to disperse electric field and potential is better than that of oxide O, the ability of oxide O to resist reverse leakage current is better than that of polysilicon S. Therefore, the breakdown voltages of the first and second embodiments are higher than those of the third and fourth embodiments, and the reverse leakage currents of the third and fourth embodiments are lower than those of the first and second embodiments.

Metal oxide semi-conductor field effect transistor (MOSFET) is easy to generate voltage surge during the switching process of on and off. It is well known that the larger the voltage surge generated by MOSFET during switching, the easier it is to burn out MOSFET. As shown in Figures 9a, 9b, 9c and 9d, the voltage surges of the embodiments are all lower than that of the previous case 1. The analysis results of Figures 9a, 9b, 9c and 9d illustrate that the structural design of each column region 611 of the first column 61 of the embodiments of the present invention can disperse its electric field and potential during operation, so that its ability to resist voltage surges is better than that of the previous case 1. In addition, since the ability of oxide O to resist voltage surges is better than that of polysilicon S. Therefore, the voltage surges of the third embodiment and the fourth embodiment are lower than those of the first embodiment and the second embodiment.

It can be seen from the equipotential line distribution diagrams of the first, second, third and fourth embodiments shown in Figures 10a, 10b, 10c and 10d, respectively, and the equielectric field line distribution diagrams of the first, second, third and fourth embodiments shown in Figures 11a, 11b, 11c and 11d, respectively, that since the ability of polysilicon S to disperse electric field and potential is better than that of oxide O, the equipotential lines and equielectric field line distribution density at a P-N junction and a trench edge of the first and second embodiments of the present invention are lower than the equipotential line distribution density at a P-N junction and a trench edge of the third and fourth embodiments. In addition, since the third embodiment has the second column 62 disposed at the bottom of the oxide O, when the third embodiment is in operation, the second column (P-type doping) 62 located at the bottom of the oxide O can disperse the potential and electric field at the P-N junction and the edge of the trench 30. Therefore, the vertical superjunction power semiconductor device of the third embodiment has a better ability to disperse the potential and electric field than the fourth embodiment.

In summary, the polysilicon S or oxide O filled in the trench 30 of the vertical superjunction power semiconductor device of the present invention, the structural design of each column region 611 of the first column 61 and the second column 62 can disperse the potential and electric field of the power semiconductor device to reduce the on-resistance (Ron), so that it has the ability to resist reverse leakage current and voltage surge, and can indeed achieve the purpose of the present invention.

However, the above is only an embodiment of the present invention and should not be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the present patent.

1: Traditional vertical power semiconductor device 10: Traditional vertical superjunction power semiconductor device 11: Semiconductor substrate 12: Drain contact layer 13: Semiconductor epitaxial layer 131: Upper surface 14: Well 141: First doped region 142: Second doped region 15: Source 16: Pillar 17: Gate cell 171: Gate dielectric layer 172: Gate 173: Insulating layer 18: Source contact layer 2: Semiconductor substrate 3: Semiconductor layer 30: Trench 31: Top surface 4: Well 41: Well area 411: First doping area 412: Second doping area 5: Source 51: Source area 61: First column 611: Column area 612: Connection area 62: Second column 7: Gate assembly 71: Dielectric layer 72: Gate layer 73: Insulating film 8: Source contact metal layer 9: Drain contact metal layer S: Polysilicon O: Oxide

Other features and effects of the present invention will be clearly presented in the implementation method of the reference figures, in which: FIG. 1 is a front view schematic diagram illustrating a conventional vertical power semiconductor device (previous case 1); FIG. 2 is a front view schematic diagram illustrating a conventional vertical superjunction power semiconductor device (previous case 2); FIG. 3 is a front view schematic diagram illustrating a first embodiment of the vertical superjunction power semiconductor device of the present invention; FIG. 4 is a front view schematic diagram illustrating a second embodiment of the vertical superjunction power semiconductor device of the present invention; FIG. 5 is a front view schematic diagram illustrating a third embodiment of the vertical superjunction power semiconductor device of the present invention; FIG. 6 is a front view schematic diagram illustrating a fourth embodiment of the vertical superjunction power semiconductor device of the present invention; Figure 7a is a forward current versus forward voltage curve diagram, illustrating the electrical performance of the first embodiment of the present invention and the previous case 2; Figure 7b is a forward current versus forward voltage curve diagram, illustrating the electrical performance of the second embodiment of the present invention and the previous case 2; Figure 7c is a forward current versus forward voltage curve diagram, illustrating the electrical performance of the third embodiment of the present invention and the previous case 2; Figure 7d is a forward current versus forward voltage curve diagram, illustrating the electrical performance of the fourth embodiment of the present invention and the previous case 2; Figure 8a is a reverse leakage current versus reverse bias curve diagram, illustrating the electrical performance of the first embodiment of the present invention and the previous case 1; FIG8b is a reverse leakage current versus reverse bias curve diagram, illustrating the electrical performance of the second embodiment of the present invention and the previous case 1; FIG8c is a reverse leakage current versus reverse bias curve diagram, illustrating the electrical performance of the third embodiment of the present invention and the previous case 1; FIG8d is a reverse leakage current versus reverse bias curve diagram, illustrating the electrical performance of the fourth embodiment of the present invention and the previous case 1; FIG9a is a voltage spike versus time curve diagram, illustrating the voltage surge resistance of the first embodiment of the present invention and the previous case 1; FIG9b is a voltage spike versus time curve diagram, illustrating the voltage surge resistance of the second embodiment of the present invention and the previous case 1; Figure 9c is a voltage surge versus time curve diagram, illustrating the voltage surge resistance of the third embodiment of the present invention and the prior art 1; Figure 9d is a voltage surge versus time curve diagram, illustrating the voltage surge resistance of the fourth embodiment of the present invention and the prior art 1; Figure 10a is an equipotential line distribution diagram, illustrating the equipotential line distribution at a P-N junction and a trench edge of the first embodiment of the present invention; Figure 10b is an equipotential line distribution diagram, illustrating the equipotential line distribution at a P-N junction and a trench edge of the second embodiment of the present invention; Figure 10c is an equipotential line distribution diagram, illustrating the equipotential line distribution at a P-N junction and a trench edge of the third embodiment of the present invention; Figure 10d is an equipotential line distribution diagram, illustrating the equipotential line distribution at a P-N junction and a trench edge of the fourth embodiment of the present invention; Figure 11a is an equielectric field line distribution diagram, illustrating the equielectric field line distribution at the P-N junction and the trench edge of the first embodiment of the present invention; Figure 11b is an equielectric field line distribution diagram, illustrating the equielectric field line distribution at the P-N junction and the trench edge of the second embodiment of the present invention; Figure 11c is an equielectric field line distribution diagram, illustrating the equielectric field line distribution at the P-N junction and the trench edge of the third embodiment of the present invention; and Figure 11d is a diagram of isoelectric field line distribution, illustrating the isoelectric field line distribution at the P-N junction and the trench edge of the fourth embodiment of the present invention.

2: Semiconductor substrate

3: Semiconductor layer

30: Ditch

31: Top

4: Well

41: Well area

411: First Mixture

412: Second mixed part

5: Source

51: Source region

61: The First Pillar

611: Column area

7: Gate assembly

71: Dielectric layer

72: Gate layer

73: Insulation film

8: Source contacts the metal layer

9: Drain contacts the metal layer

S: Polysilicon

Claims (8)

A vertical superjunction power semiconductor device comprises: A semiconductor substrate containing a first type of carrier; A semiconductor layer formed on the semiconductor substrate and containing the first type of carrier and including a trench recessed from a top surface of the semiconductor layer toward the semiconductor substrate; A well located in the semiconductor layer and close to the top surface and containing a second type of carrier and divided into two well regions separated from each other by the trench region, each well region including a first doping portion contacting the trench and a second doping portion in each corresponding first doping portion, and each second doping portion contacts the trench; A source electrode, located in the semiconductor layer and close to the top surface, containing the first type of carriers and divided into two source regions separated from each other by the trench region, each source region is located in the first doping portion corresponding to each other and contacts the second doping portion corresponding to each other; A first column, located in the semiconductor layer and including two column regions located on opposite sides of the trench and containing the second type of carriers, each column region extends from the first doping portion corresponding to each other toward the semiconductor substrate; Two gate components are arranged on the top surface of the semiconductor layer and located on opposite sides of the trench at intervals, each gate component includes a dielectric layer covering the top surface of the semiconductor layer, a first doping portion corresponding to each and partially covering a source region corresponding to each, a gate layer stacked on the dielectric layer corresponding to each, and an insulating film covering the gate layer corresponding to each; A filling body filled in the trench and composed of polysilicon; and A source contact metal layer covers and contacts a top edge of the filling body, the source regions and the second doping portions; Wherein, a depth of each column region in the semiconductor layer is less than or equal to three quarters of a thickness of the semiconductor layer. A vertical superjunction power semiconductor device as described in claim 1, wherein the depth of each column region in the semiconductor layer is less than or equal to half the thickness of the semiconductor layer. A vertical superjunction power semiconductor device as described in claim 1, wherein the column regions of the first column contact the polysilicon. A vertical superjunction power semiconductor device as described in claim 1 or 3, wherein the first column further includes a connection region connected to the column regions, and the column regions and the connection region cover a bottom edge of the polysilicon. A vertical superjunction power semiconductor device comprises: A semiconductor substrate containing a first type of carrier; A semiconductor layer formed on the semiconductor substrate and containing the first type of carrier and including a trench recessed from a top surface of the semiconductor layer toward the semiconductor substrate; A well located in the semiconductor layer and close to the top surface and containing a second type of carrier and divided into two well regions separated from each other by the trench region, each well region including a first doping portion contacting the trench and a second doping portion in each corresponding first doping portion, and each second doping portion contacts the trench; A source electrode, located in the semiconductor layer and close to the top surface, containing the first type of carriers and divided into two source regions separated from each other by the trench region, each source region is located in the first doping portion corresponding to each other and contacts the second doping portion corresponding to each other; A first column, located in the semiconductor layer and including two column regions located on opposite sides of the trench and containing the second type of carriers, each column region extends from the first doping portion corresponding to each other toward the semiconductor substrate; Two gate components are arranged on the top surface of the semiconductor layer and located on opposite sides of the trench at intervals, each gate component includes a dielectric layer covering the top surface of the semiconductor layer, the first doping portion corresponding to each other and partially covering the source region corresponding to each other, a gate layer stacked on the dielectric layer corresponding to each other, and an insulating film covering the gate layer corresponding to each other; A filling body filled in the trench and composed of oxide; and A source contact metal layer covering and contacting a top edge of the filling body, the source regions and the second doping portions; Wherein, the depth of each column region in the semiconductor layer is less than or equal to three quarters of the thickness of the semiconductor layer. The vertical superjunction power semiconductor device as described in claim 5 further comprises a second column, wherein the second column contains second type carriers and is located in the semiconductor layer and extends from a bottom edge of the oxide toward the semiconductor substrate. A vertical superjunction power semiconductor device as described in claim 6, wherein a depth of the second pillar in the semiconductor layer is less than or equal to half of the thickness of the semiconductor layer. A vertical superjunction power semiconductor device as described in claim 5, wherein the column regions of the first column contact the oxide.