TWI870932B - Ic package - Google Patents

Abstract

An IC packagecomprises a substrate; a semiconductor die with a top surface, wherein the semiconductor die is stacked over the substrate; a vapor chamber stacked over the semiconductor die, wherein the vapor chamber comprises a proximal portion and a distal portion, the proximal portion covers the top surface of the semiconductor die; and an encapsulating case encapsulating the substrate, the semiconductor die and the vapor chamber, wherein the proximal portion of the vapor chamber is within the encapsulating case, and the distal portion of the vapor chamber extends from a wall of the encapsulating case.

Description

Integrated circuit packaging

The present invention relates to an integrated circuit package with a heat dissipation structure, and in particular to an integrated circuit package using a very thin vapor chamber.

Nowadays, electronic devices (such as smart phones and notebooks) have been widely used, and these electronic devices include various electronic components to provide multiple functions. For example, a laptop or handheld device may include a graphics processing unit (GPU) IC that provides a graphical user interface (GUI) through a display module. In addition, the laptop or handheld device may also include a communication processor IC for communicating with other electronic devices, and a central processing unit (CPU) IC for computing and processing data. Laptops or handheld devices also require high-capacity storage ICs (such as dynamic memory or static memory) to store data. However, a typical problem with these ICs is that the heat energy generated during operation cannot be effectively dissipated, resulting in a high temperature state. If an integrated circuit operates at excessively high temperatures for a long period of time, the reliability and service life of the integrated circuit may be reduced.

Furthermore, to meet the requirements of high performance computing (HPC), most of the above-mentioned integrated circuits (including CPU, GPU and/or memory IC, such as HBM) are stacked together and packaged in a housing or package in the form of 2.5D integrated circuit chips or 3D integrated circuit chips. For these 2.5D integrated circuit chips or 3D integrated circuit chips, the heat dissipation problem may become very serious. In particular, in 3D integrated circuit chips or 2.5D integrated circuit chips, multiple heat sources along the heat flow paths in the stacked chips may generate local hot spots, which may exceed the allowable junction temperature of these ICs during operation. Therefore, some high-performance 3D integrated circuit chips or 2.5D integrated circuit chips may be burned out due to heat generation exceeding 1000W when operating at high frequencies.

Worse still, the above-mentioned integrated circuit components may generate electromagnetic waves, and the electromagnetic waves generated by these integrated circuit components may interfere with other electronic devices and cause malfunctions. Therefore, it is generally necessary to set an electromagnetic shielding layer on the integrated circuit components to electromagnetically shield the electromagnetic waves. The electromagnetic shielding layer can electromagnetically shield the electromagnetic waves generated by the components. However, the traditional electromagnetic shielding layer may not be an effective thermal conductor and worsen the heat dissipation of those electromagnetically shielded integrated circuit components.

Therefore, the present invention provides a new integrated circuit package to solve the problems of the prior art. An embodiment of the present invention provides an IC package. Such an IC package includes a substrate; a semiconductor bare chip having a top surface, the semiconductor bare chip stacked on the substrate; a temperature averaging plate stacked on the semiconductor bare chip, wherein the temperature averaging plate includes a proximal portion and a distal portion, the proximal portion covers the top surface of the semiconductor bare chip; and a package body encapsulating the substrate, the semiconductor bare chip and the temperature averaging plate, wherein the proximal portion of the temperature averaging plate is located in the package body, and the distal portion of the temperature averaging plate extends outward from an outer wall of the package body.

On the other hand, the temperature equalizer is an ultra-thin temperature equalizer with a thickness of 0.3mm to 0.6mm.

On the other hand, the temperature averaging plate is an ultra-thin temperature averaging plate with a thickness of less than 1 mm, the proximal portion of the temperature averaging plate is sealed in the package body, and the distal portion of the temperature averaging plate is not sealed in the package body.

On the other hand, the package body includes a molding material, the proximal portion of the temperature evaporator is sealed by the molding material, and there is no molding material between the temperature evaporator and the semiconductor bare chip.

On the other hand, the package body is a metal shell, the metal shell covers the substrate, the semiconductor bare chip and the temperature plate, and the temperature plate further includes a transition portion between the distal portion and the proximal portion, the transition portion is integrated with the metal shell, or there is a waterproof material seal between the transition portion and the metal shell.

On the other hand, the end portion covers most or all of the top surface of the semiconductor bare chip, and the temperature vapor chamber is stacked on the semiconductor bare chip through a thermal interface material (TIM) or a thermal adhesive layer.

On the other hand, the integrated circuit package further includes a support column located between the temperature vapor chamber and the substrate, and the height of the support column is greater than the height of the semiconductor bare chip.

On the other hand, the integrated circuit package further includes a set of isolation structures formed in the vapor chamber; and a set of capillary structures formed in the vapor chamber and between the set of isolation structures.

On the other hand, the isolation structure group extends from the distal portion to the proximal portion, and the isolation structure group passes through the outer wall of the package body.

On the other hand, the temperature averaging plate further includes a set of supporting structures connected to the set of isolation structures, wherein the set of supporting structures extends downward from the top surface of the temperature averaging plate, the set of isolation structures extends upward from the bottom surface of the temperature averaging plate, and another set of capillary structures is included between the set of supporting structures.

On the other hand, the distal portion of the vapor chamber is thermally coupled to a heat sink, or directly coupled to a liquid.

Another embodiment of the present invention provides an integrated circuit package. The integrated circuit package includes a first semiconductor chip having a first top surface; a first temperature absorbing plate stacked on the first semiconductor chip, wherein the first temperature absorbing plate includes a first proximal portion and a first distal portion. The first proximal portion covers the first top surface of the first semiconductor chip, and the thickness of the first proximal portion is less than 1 mm; and a package body, covering the first semiconductor chip and the first temperature absorbing plate, wherein the first proximal portion of the first temperature absorbing plate is sealed in the package body, and the first distal portion of the first temperature absorbing plate protrudes outward from an outer wall of the package body.

On the other hand, the thickness of the first proximal portion is between 0.3 mm and 0.8 mm.

On the other hand, the first temperature equalization plate further includes another distal portion protruding from another outer wall of the package body, and the first proximal portion is located between the first distal portion and the other distal portion.

On the other hand, the width of the distal portion and the width of the other distal portion are both greater than the width of the proximal portion.

On the other hand, the integrated circuit package further includes a second temperature evaporating plate separated from the first temperature evaporating plate and stacked on the first semiconductor chip, wherein the second temperature evaporating plate is covered by the package body; wherein the second temperature evaporating plate includes a second proximal portion and a second distal portion, the second proximal portion of the second temperature evaporating plate covers the first top surface of the first semiconductor chip, and the thickness of the second proximal portion of the second temperature evaporating plate is less than 1 mm, and the second distal portion of the second temperature evaporating plate extends outward from another outer wall of the package body.

On the other hand, the integrated circuit package further includes a second semiconductor chip vertically spaced apart from the first semiconductor chip, and the second semiconductor chip is disposed under the first semiconductor chip.

On the other hand, the integrated circuit package further includes a second semiconductor chip having a second top surface, the second semiconductor chip is horizontally separated from the first semiconductor chip; and a second temperature absorbing plate is horizontally separated from the first temperature absorbing plate and stacked on the second semiconductor chip, wherein the second semiconductor chip and the second temperature absorbing plate are covered by the package body; wherein the second temperature absorbing plate includes a second proximal portion and a second distal portion, the second proximal portion of the second temperature absorbing plate covers the second top surface of the second semiconductor chip, the second proximal portion of the second temperature absorbing plate has a thickness of less than 1 mm, and the second distal portion of the second temperature absorbing plate extends outward from another outer wall of the package body.

Another embodiment of the present invention provides an integrated circuit package. The integrated circuit package includes a substrate; a first semiconductor chip having a first top surface, the first semiconductor chip is located on the substrate; a first temperature evaporating plate stacked on the first semiconductor chip, wherein the first temperature evaporating plate includes a proximal portion and a distal portion, the proximal portion covers the first top surface of the first semiconductor chip; and a package body, covering the first semiconductor chip and the first temperature evaporating plate, wherein the proximal portion of the first temperature evaporating plate is packaged in the package body, and the distal portion of the first temperature evaporating plate protrudes outside the package body; wherein the distal portion of the first temperature evaporating plate is thermally coupled to a heat sink, or directly immersed in a liquid.

On the other hand, the package body is a metal shell, the metal shell encapsulates the first semiconductor chip and the first temperature absorbing plate, and the first temperature absorbing plate further includes a transition portion between the distal portion and the proximal portion, the transition portion is integrated with the metal shell, or there is a waterproof material seal between the transition portion and the metal shell.

On the other hand, the present invention further comprises a second semiconductor chip having a second top surface, the second semiconductor chip is horizontally separated from the first semiconductor chip and is located on the substrate, wherein the second semiconductor chip is covered by the package body; wherein the first temperature plate further comprises another proximal portion covering the second top surface of the second semiconductor chip, and the distance between the distal portion and the proximal portion is different from the distance between the distal portion and the other proximal portion.

On the other hand, the integrated circuit package further includes a second semiconductor chip having a second top surface, the second semiconductor chip is horizontally separated from the first semiconductor chip and stacked on the substrate; and a second temperature evaporating plate is horizontally separated from the first temperature evaporating plate and stacked on the second semiconductor chip, wherein the second semiconductor chip and the second temperature evaporating plate are packaged by the package body; wherein the second temperature evaporating plate includes a second proximal portion and a second distal portion, the second proximal portion of the second temperature evaporating plate covers the second top surface of the second semiconductor chip, and the thickness of the second proximal portion of the second temperature evaporating plate is less than 1 mm, and the second distal portion of the second temperature evaporating plate extends from another outer wall of the package body.

On the other hand, the second semiconductor chip includes a group of semiconductor bare chips stacked vertically together, the thickness of the second semiconductor chip is greater than the thickness of the first semiconductor chip, and the thickness of the second proximal portion of the second temperature evaporating plate is less than the thickness of the first proximal portion of the first temperature evaporating plate.

1: Learn about the temperature balancing board

12, 235: capillary structure

13: Heat source

2: Integrated circuit packaging

2121, 2122, 2123: Bare chips

210: Copper Pillar

22: Substrate

221: Bump ball

23, 23A, 23B: Temperature balancing plate

231, 231A, 231B: proximal part

232: Remote part

233: Transition section

2331: Arc

21, 211, 212, 213: semiconductor chips/bare chips

234: Isolation structure

236: Support structure

237: Top floor

238 Lower level

24: Package body

25: Thermal bonding layer

26: Support column

3: PCB board

31: Radiator

311:Liquid pipeline

32: Fan

G: Gap

Figure 1 is an example of a common temperature distribution plate.

FIG2 is a schematic diagram illustrating an embodiment of an integrated circuit package according to the present invention.

FIG3A and FIG3B illustrate an exemplary top view and a perspective view, respectively, of the integrated circuit package of FIG2.

FIG3-1A and FIG3-1B illustrate another exemplary top and perspective view of the integrated circuit package in FIG2, respectively.

FIG3-2A and FIG3-2B illustrate exemplary cross-sectional views of the temperature distribution plate along the tangent line shown in FIG3B , respectively.

FIG4 is a schematic diagram illustrating another embodiment of the integrated circuit package according to the present invention.

FIG5 is a schematic diagram illustrating another embodiment of the integrated circuit package according to the present invention.

FIG6A and FIG6B illustrate an exemplary top and perspective view, respectively, of the integrated circuit package of FIG5.

FIG. 7A and FIG. 7B are another exemplary top and perspective views of the integrated circuit package in FIG. 5 , respectively.

FIG8 is a schematic diagram illustrating another embodiment of the integrated circuit package according to the present invention.

FIG9A and FIG9B are respectively an exemplary top view and perspective view of the integrated circuit package in FIG8.

FIG10 is a schematic diagram illustrating another embodiment of the integrated circuit package according to the present invention.

FIG. 11A and FIG. 11B illustrate an exemplary top and perspective view, respectively, of the integrated circuit package of FIG. 10 .

FIG12 is a schematic diagram illustrating another embodiment of the integrated circuit package according to the present invention.

FIG13 is a schematic diagram illustrating another embodiment of the integrated circuit package according to the present invention.

FIG14 is a schematic diagram illustrating another embodiment of the integrated circuit package according to the present invention.

The advantages, spirit and features of the present invention will be described and discussed in detail with reference to the accompanying drawings and examples.

In order to make the advantages, spirit and features of the present invention easier and clearer to understand, the following will be described and discussed in detail with reference to the attached drawings and examples. It is worth noting that these examples are only representative examples of the present invention, and the specific methods, devices, conditions, materials, etc. cited therein are not intended to limit the present invention or the corresponding embodiments.

The terms used in the various embodiments disclosed in the present invention are only used for the purpose of describing specific embodiments and are not intended to limit the various embodiments disclosed in the present invention. The singular form used in the specification also includes the plural form unless the context clearly indicates otherwise. Unless otherwise specified, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by ordinary technicians in the field to which the various embodiments disclosed in the present invention belong. The above terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as the contextual meaning in the same technical field, and will not be interpreted as having an idealized meaning or an overly formal meaning unless the term is clearly defined in the various embodiments disclosed in the present invention.

In the description of this specification, the reference to the term "an embodiment", "a specific embodiment", etc. means that the specific features, structures, materials or characteristics described in the embodiment are included in at least one embodiment of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in an appropriate manner.

In the description of the present invention, unless otherwise specified or limited, it should be noted that the terms "coupling", "connection", and "setting" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal connection of two components, it can be a direct connection, or it can be an indirect connection through an intermediate medium. For those with ordinary knowledge in this field, the specific meanings of the above terms can be understood according to the specific circumstances.

Please refer to Figure 1. In the known temperature evaporating plate 1, there is a capillary structure 12 covering the inner wall of the known temperature evaporating plate 1. A small amount of liquid (such as water) is sealed in the temperature evaporating plate. When a heat source 13 (such as an IC chip) is coupled to a part of the known temperature evaporating plate 1 (where the part of the known temperature evaporating plate 1 connected to the heat source 13 can be called a hot zone), the liquid will become a vapor phase or a gas phase due to the heat generated by the heat source 13. These vapor phase gases will condense into liquid in the cold zone (the part far away from the heat source) and flow back to the hot zone close to the heat source through the capillary structure 12.

The invention is described in detail as follows. Through the special design of the temperature vapor chamber, the ultra-thin temperature vapor chamber (VTVC) can provide good thermal conductivity at a thickness of less than 1 mm (such as 0.3 mm to 0.6 mm). For example, with a suitable directional capillary structure design and sufficient space for steam/gas flow, the VTVC can have better thermal conductivity than diamond. The thermal conductivity coefficient (W/m.K) of diamond is about 2400~2500, but the thermal conductivity coefficient (W/m.K) of 0.4 mm VTVC made of copper, stainless steel and titanium can be 4000~6000, 3700~5700 and 16000~24000 respectively. Therefore, VTVC can achieve IC packaging with high heat dissipation efficiency, especially for IC chips of high-performance computing systems that easily generate high heat (such as more than 1000W). In addition, the strength of titanium is 5-10 times that of a similar structure composed of copper, and the thermal expansion coefficient is much lower than that of copper or aluminum. Therefore, a vapor chamber of appropriate material has the opportunity to be designed as a good heat sink.

FIG. 2 is an embodiment of an IC package according to the present invention, wherein a semiconductor wafer/bare die 21 is stacked on a substrate 22 (e.g., an ABF substrate) having solder balls or bump balls 221. The semiconductor wafer/bare die 21 may include a plurality of solder balls or copper pillars 210 electrically connected to the substrate 22. An ultra-thin vapor chamber 23 having a thickness of less than 1 mm (0.2 mm to 0.8 mm, such as 0.3 mm, 0.4 mm, or 0.5 mm) may be thermally coupled to the semiconductor wafer/bare die 21 via a thermal interface material (TIM) or a thermal adhesive layer 25. In one embodiment, there is no other material between the ultra-thin vapor chamber 23 and the semiconductor wafer/bare die 21 except for the TIM or thermal adhesive layer 25. In addition, the ultra-thin temperature plate 23 can cover most or all of the top surface of the semiconductor chip/bare chip 21.

Then, a package 24, such as a metal package, a mechanical package or a molded package (usually made of a molding material such as epoxy resin, phenolic resin or silica powder), packages or seals the semiconductor chip/bare chip 21, the substrate 22 and the ultra-thin temperature-maintaining plate 23 together. When the package 24 is made of a molding material, the molding material will fill the space not occupied by the semiconductor chip/bare chip 21, the substrate 22 and the ultra-thin temperature-maintaining plate 23. The solder balls or bump balls 221 of the substrate 22 are exposed outside the package 24 so as to be electrically coupled with the PCB board 3 or other circuits. In addition, one end of the ultra-thin temperature-maintaining plate 23 extends out of the package 24, and the other end of the ultra-thin temperature-maintaining plate 23, which is in contact with the semiconductor chip/bare chip 21 through the TIM or thermal adhesive layer 25, is packaged or sealed by the package 24.

The portion of the ultra-thin temperature vapor chamber 23 that contacts the semiconductor chip/bare die 21 through the TIM or thermal adhesive layer 25 may be referred to as a proximal portion 231 (or proximal region), which is also a hot zone portion of the temperature vapor chamber 23 because it contacts the semiconductor chip/bare die 21 that generates heat. On the other hand, the portion of the ultra-thin temperature vapor chamber 23 that is not encapsulated by the package body 24 is referred to as a distal portion 232 (or distal region), which is also a cold zone portion of the temperature vapor chamber 23 because it is far from the semiconductor chip/bare die 21. The transition portion 233 between the proximal portion 231 and the distal portion 232 of the temperature vapor chamber 23 may have a rounded corner or arc 2331. The temperature equalizing plate 23 of the present invention can be made of titanium, stainless steel, copper, or copper alloy.

In order to reduce the pressure from the temperature plate 23 on the semiconductor chip/bare chip 21, in another embodiment, a set of support pillars 26 may be provided. The support pillars 26 may extend downward from the temperature plate 23 or upward from the substrate 22. The height of each support pillar 26 may be greater than the height of the semiconductor chip/bare chip 21, so that when the support pillars 26 are arranged between the temperature plate 23 and the substrate 22, there is enough space between the temperature plate 23 and the semiconductor chip/bare chip 21 to accommodate the TIM or thermal adhesive layer 25. Therefore, the temperature plate 23 will not over-press the semiconductor chip/bare chip 21.

In order to effectively dissipate heat, the heat sink 31 can be coupled to the distal portion 232 of the ultra-thin temperature evaporating plate 23, and the fan 32 can be coupled to the heat sink 31 to circulate air for heat dissipation. The heat sink 31 can also be coupled to the ultra-thin temperature evaporating plate 23 using a TIM or thermal adhesive layer. Furthermore, the temperature evaporating plate 23 can be fixed to the PCB board by a buckle or a locking structure to avoid vibration of the temperature evaporating plate 23.

In another embodiment, the heat sink 31 may include a liquid pipe 311 coupled to the distal portion 232 of the ultra-thin temperature distribution plate 23, and a pump (not shown) may circulate the liquid in the liquid pipe to accelerate heat dissipation. Of course, in this example, the fan 32 may still be coupled to the heat sink 31 to circulate air for heat dissipation.

In another embodiment, the entire integrated circuit package 2 and/or the distal portion 232 of the ultra-thin temperature plate 23 can be immersed in a liquid (such as a dielectric liquid, an organic compound, a refrigerant, etc.) to speed up the heat exchange. Therefore, in this embodiment, the proximal portion 231 in the package body 24 is not directly coupled with the liquid, but the distal portion 232 extending out of the package body 24 can be directly coupled with the liquid to facilitate heat dissipation. As mentioned above, when the package body 24 is made of a molding material, the molding material will fill all spaces not occupied by the semiconductor chip/bare chip 21, the substrate 22 and the ultra-thin temperature plate 23. Therefore, the outer wall or side wall portion of the package body 24 extending from the temperature plate 23 is also sealed, and no liquid or gas will enter the package body 24 made of the molding material.

When the package 24 is made of metal or other mechanical structures, the outer wall in the package 24 (from which the temperature averaging plate 23 extends) can be integrated with the temperature averaging plate 23, or the transition portion of the temperature averaging plate 23 between the distal portion and the proximal portion can be integrated with the metal shell. In addition, the transition portion and the metal shell can also be sealed with a waterproof material (such as epoxy resin, phenolic resin) to prevent liquid or gas from entering the package 24. Therefore, the proximal end of the temperature averaging plate 23 thermally coupled to the semiconductor integrated circuit or bare chip is inside the metal package 24, but the distal end of the temperature averaging plate 23 is outside the metal package 24. The distal end of the temperature averaging plate 23 can be immersed in liquid for heat dissipation. In another embodiment, the semiconductor integrated circuit can be a packaged integrated circuit. That is, the metal package 24 covers the packaged integrated circuit IC and the temperature plate 23, the proximal end of the temperature plate 23 is thermally coupled with the packaged integrated circuit IC through TIM or thermal adhesive material, and the distal end of the temperature plate 23 extends or protrudes outside the metal package 24 and directly contacts the liquid.

In addition, the temperature plate 23 can cover most or all of the top surface of the semiconductor chip/bare chip 21. Since the temperature plate 23 of the present invention can be made of titanium, stainless steel, copper, or copper alloy, the metal temperature plate 23 covering most or all of the top surface of the semiconductor chip/bare chip 21 can play an electromagnetic shielding role to reduce the disturbing electromagnetic waves of the semiconductor chip/bare chip 21 or other integrated circuits. The temperature plate 23 can be fixed on the PCB board by a buckle or a locking structure, and the buckle or the locking structure can be a conductor to electrically connect the temperature plate 23 to the grounding area of the PCB board 3.

In the present invention, the temperature plate 23 can have a directional liquid flow between the cold zone portion (distal portion 232) and the hot zone portion (proximal portion 231). As shown in FIG3A, which is a top view and a perspective view of the integrated circuit package 2 in FIG2, a plurality of isolation structures 234 can be formed inside the temperature plate 23, and the capillary structure 235 is formed between the isolation structures 234. The distance d between the two isolation structures 234 is 1 mm to 2.5 mm, and the length of the isolation structure 234 is about 10d~20d. Therefore, when the evaporated gas in the hot zone is condensed into liquid in the cold zone, the condensed liquid will flow back from the cold zone to the hot zone along the capillary structure 235 between the isolation structure 234 (or between the isolation structure and the boundary of the temperature plate 23). In addition, the isolation structure 234 can strengthen the mechanical structure of the temperature plate 23 to avoid damage to the temperature plate 23 during the packaging process. Therefore, the isolation structure 234 can be located below the outer wall or side wall of the package body 24 (as shown in FIG. 3B), and the outer wall or side wall of the package body 24 is where the temperature plate 23 extends outward.

In another example, the isolation structure 234 can be further extended to most of the hot zone portion of the vapor chamber 23, as shown in FIG3-1A. In addition, as shown in FIG3-1B, the vapor chamber 23 can include another set of isolation structures 234 near the edge of the vapor chamber 23, and at least 1/2 of the hot zone portion is not penetrated or passed by the isolation structure 234.

FIG3-2A is a cross-sectional view of the temperature-vaporizing plate 23 along the tangent line shown in FIG3B. The temperature-vaporizing plate 23 includes a top plate or top layer portion 237 and a lower plate or lower layer portion 238, and the isolation structure 234 can be a beam-like structure (or a support/protrusion structure) extending from the lower layer portion 238. The temperature-vaporizing plate 23 can further include a support structure 236 corresponding to the isolation structure 234. The support structure 236 can be connected to the isolation structure 234 and provide support for the temperature-vaporizing plate 23. The support structure 236 also creates sufficient space for the flow of steam/gas. The support structure 236 can be a beam-like structure (or a support/protrusion structure) extending from the top layer portion 237. In another embodiment shown in FIG. 3-2B , the capillary structure 235 exists not only between the isolation structure 234 (and/or between the isolation structure 234 and the boundary of the temperature-averaging plate 23), but also between the support structure 236 (and/or between the support structure 236 and the boundary of the temperature-averaging plate 23). Therefore, it provides more liquid circulation paths.

The capillary structure of the present invention can be formed by three heating processes of drying, cracking and sintering of slurry. The slurry contains metal powder, polymer and solvent. The solvent can be an alcohol solvent, and the polymer can be a plastic polymer material, acrylic acid, synthetic fiber, nylon, natural resin, synthetic resin or a combination thereof. The metal powder can include copper powder, cupric oxide powder, cuprous oxide powder, tetracubic oxide powder, or a combination thereof. The powder sintering can be carried out in a hydrogen-containing environment, on the one hand to prevent the oxidation of the copper powder, and on the other hand to reduce the copper oxide powder to copper.

FIG. 4 shows another embodiment of the present invention. The main difference between FIG. 4 and FIG. 2 is that the thickness T2 of the distal portion 232 (or the cold zone portion) is greater than or different from the thickness T1 of the proximal portion 231 (or the hot zone portion), wherein T2 is approximately 1 mm to 10 mm, and T1 is approximately 0.3 mm to 0.8 mm (such as 0.4 mm or 0.5 mm).

For a 2.5D integrated circuit structure or a 3D integrated circuit structure, multiple semiconductor chips/bare chips are stacked together and packaged in a housing or package, so the heat dissipation problem becomes more serious. As shown in FIG. 5 , in practice, multiple semiconductor chips/bare chips (211, 212, and 213) can be stacked together in a 3D integrated circuit structure, or multiple semiconductor chips/bare chips (211 and 213) and an interposer (shown by reference numeral 212) between the semiconductor chips/bare chips 211 and 213 can be stacked in a 2.5D integrated circuit structure. These semiconductor chips and interposers (e.g., Si interposers) are stacked on a substrate 22. The semiconductor chip/bare die and interposer may include multiple through-silicon vias (TSVs) or copper pillars electrically connected to the substrate 22.

According to the present invention shown in FIG. 5 , an ultra-thin heat spreader 23 having a thickness of less than 1 mm (0.3 mm to 0.8 mm, such as 0.4 mm or 0.5 mm) is thermally coupled to the topmost semiconductor chip/bare chip 213 through a thermal interface material (TIM) or a thermal adhesive layer 25. Then, a package 24, such as a metal box or a molded package (usually made of epoxy resin, phenolic resin or silica powder, etc.) packages or seals the semiconductor chip/bare chip, the interposer, the substrate 22 and the ultra-thin heat spreader 23 together. When the package 24 is made of a molded material, the material of the molded material will fill all spaces not occupied by the semiconductor chip and the interposer (211, 212 and 213), the substrate 22 and the ultra-thin heat spreader 23.

In order to prevent the temperature vaporizer 23 from exerting excessive pressure on the semiconductor chip and the interposer (211, 212, and 213), in other embodiments, a set of support pillars 26 may be provided under the temperature vaporizer 23. The set of support pillars 26 may extend downward from the temperature vaporizer 23 or may extend upward from the substrate 22. The height of each support pillar is greater than the sum of the heights of the semiconductor chip/bare chip and the interposer (211, 212, and 213), so that when the set of support pillars 26 is arranged between the temperature vaporizer 23 and the substrate 22, there is a sufficient gap (0.01 mm to 0.1 mm) between the temperature vaporizer 23 and the semiconductor chip/bare chip 21 to accommodate the TIM or thermal adhesive layer 25. Therefore, the temperature plate 23 will not over-stress the semiconductor chip/bare chip and the interposer (211, 212, and 213).

In another embodiment, two or more ends of the ultra-thin temperature vaporizer 23 (cold zone portion or distal portion 232) may extend outside the package 24, and a portion of the ultra-thin temperature vaporizer 23 (hot zone portion or proximal portion 231) contacts the semiconductor chip/bare chip and the interposer (211, 212 and 213) through the TIM or thermal adhesive layer 25 and is packaged or sealed in the package 24. Further, the heat sink 31 can be coupled to the distal portion 232 of the ultra-thin temperature vaporizer 23, and the fan 32 can be coupled to the heat sink 31 to circulate air for heat dissipation. The heat sink 31 may also include a liquid pipeline coupled to the distal portion 232 of the ultra-thin temperature vaporizer 23, and a pump (not shown) is used to circulate the liquid in the liquid pipeline to accelerate heat dissipation.

Similarly, the entire IC package and/or the distal portion 232 of the ultra-thin temperature-averaging plate 23 in FIG. 5 can be immersed in a liquid (such as a dielectric liquid, an organic compound, a refrigerant, etc.) to accelerate heat exchange. Therefore, in this embodiment, the proximal portion 231 in the package body 24 is not directly coupled to the liquid, but the distal portion 232 extending out of the package body 24 is directly coupled to the liquid. When the package body 24 is made of a molding material, the material of the molding material will fill all the gaps not occupied by the semiconductor chip, the substrate 22 and the ultra-thin temperature-averaging plate 23. Therefore, the outer wall or side wall of the package body 24 from which the temperature-averaging plate 23 extends is also sealed, and no liquid or gas will enter the package body 24 made of the molding material. When the package 24 is made of metal or other mechanical structures, the outer wall of the package 24 (the temperature averaging plate 23 extends from the outer wall) can be integrated with the temperature averaging plate 23, or the transition portion of the temperature averaging plate 23 between the distal portion and the proximal portion can be integrated with the metal shell. In addition, the transition portion and the metal shell can also be sealed with a waterproof material (such as epoxy resin, phenolic resin) to prevent liquid or gas from entering the package 24.

In addition, the temperature plate 23 can cover most or all of the top surfaces (and/or the side walls of the semiconductor chip) of the semiconductor chip/bare chip and the interposer. Since the temperature plate 23 of the present invention can be made of titanium, stainless steel or copper, the metal temperature plate 23 covering most of the semiconductor chip/bare chip and the interposer can play an electromagnetic shielding role to reduce the electromagnetic interference generated by these semiconductor chips/bare chips and/or the interposer. The temperature plate 23 can be fixed on the PCB board by a buckle, and the buckle can be a conductor to electrically connect the temperature plate 23 to the grounding area of the PCB board.

FIG6A and FIG6B are respectively an exemplary top view and a transparent view of FIG5. As shown in FIG6A, the temperature-averaging plate 23 has a directional liquid flow from two or more cold zone portions (distal portion 232) to the hot zone portion (proximal portion 231). As shown in FIG6B, two or more isolation structures 234 are formed in the temperature-averaging plate 23, and capillary structures 235 are formed between the isolation structures 234. When the evaporated gas in the hot zone portion condenses into liquid in two or more cold zone portions, the condensed liquid will flow back to the hot zone portion from each cold zone portion along the capillary structure 235. In addition, the isolation structure 234 can enhance the mechanical strength of the temperature-averaging plate 23, so that the package body 24 will not damage, collide or distort the temperature-averaging plate 23 during the packaging process. Therefore, the isolation structure 234 can be located below the outer wall or side wall of the package body 24, and the outer wall or side wall of the package body 24 is where the temperature plate 23 extends outward, as shown in FIG. 6B.

FIG. 7A and FIG. 7B are another exemplary top view and perspective view of FIG. 5 , respectively, in which the temperature plate 23 has a directional liquid flow from two or more cold zone parts (distal part 232) to the hot zone part (proximal part 231). The main differences between FIG. 6A and FIG. 6B and FIG. 7A and FIG. 7B are: (1) the area (or width W2) of each cold zone part (distal part 232) is greater than or different from the area (or width W1) of the hot zone part (proximal part 231) in the package 24; (2) the distance d1 between the two isolation structures 234 near the hot zone part (proximal part 231) is shorter than or different from the distance d2 (<2.5mm) between the two isolation structures 234 near the cold zone part (distal part 232).

When the evaporated gas from the hot zone condenses into liquid in two or more cold zones, the condensed liquid will flow back to the hot zone from each cold zone along the capillary structure 235. Since there are two or more cold zones, the heat dissipation effect will be increased. In addition, two or more isolation structures 234 can strengthen the mechanical structure of the temperature plate 23, so that the package body 24 will not damage, collide or distort the temperature plate 23 during the packaging process.

Although FIG. 6A and FIG. 6B (and FIG. 7A and FIG. 7B) only show two cold zones (distal portions 232) in a heat spreader 23, in another embodiment, a heat spreader 23 may have directional liquid flow from two or more, such as four, cold zones (distal portions 232) to the hot zone (proximal portion 231) in the package 24. That is, the heat spreader 23 extends out of the package 24 not only from the left and right directions, but also from other directions (such as the upper and lower directions). The heat spreader 23 can cover all top surfaces and even four side walls of the semiconductor chip/bare chip and the interposer (211, 212 and 213), so it can play a better electromagnetic shielding role and reduce the electromagnetic wave interference generated by the semiconductor chip/bare chip and/or the interposer.

FIG8 shows another embodiment of an IC package with multiple ultra-thin heat spreaders according to the present invention. The difference between FIG5 and FIG8 is that there are two or more ultra-thin heat spreaders 23 covering the top surface of the semiconductor chip/bare chip 213. Along the top surface of the semiconductor chip/bare chip 213, there is a gap G between two independent ultra-thin heat spreaders 23, which can be filled with a TIM or thermal adhesive layer 25 (or the material of the molded package body). It is best to minimize the gap G as much as possible (e.g., less than 1 mm), so that most of the top surface of the semiconductor chip/bare chip 213 can be covered by two independent ultra-thin heat spreaders 23, and the heat generated from the semiconductor chip/bare chip 213 (or the semiconductor chip/bare chip and the interposer 211, 212, and 213) can be dissipated by the two ultra-thin heat spreaders 23 respectively. Of course, multiple ultra-thin heat spreaders (two or even more) in Figure 8 can also be applied to a single chip/bare chip, rather than just to the stacked chip structure in Figure 8.

The cold zone of each temperature averaging plate 23 can be coupled to a heat sink 31 (which may include a liquid pipeline), and then coupled to a fan 32. Each temperature averaging plate 23 can be fixed to the PCB board 3 by a buckle. Alternatively, the cold zone of each temperature averaging plate 23 can be immersed in a liquid (such as a dielectric liquid, an organic compound, a refrigerant, etc.) to speed up the heat exchange efficiency. Figure 9A and Figure 9B are respectively an exemplary top view and a transparent view of Figure 8. Each temperature averaging plate 23 has a directional liquid flow from the cold zone (distal portion 232) to the hot zone (proximal portion 231).

The two or more independent temperature evaporation plates in FIG8 can be applied to another IC package, in which two or more independent semiconductor chips/bare chips 211 and 212 are separated horizontally and arranged on a substrate 22, as shown in FIG10. The left temperature evaporation plate 23 in FIG10 covers most or all of the top surface of the left semiconductor chip/bare chip 211, and the heat generated by the left semiconductor chip/bare chip 211 will be dissipated from the hot zone of the left temperature evaporation plate 23 to the cold zone of the left temperature evaporation plate 23 (refer to the left part of FIG11A and FIG11B, FIG11A and FIG11B are the top and transparent views of FIG10, respectively). In addition, the right temperature plate 23 in FIG. 10 covers most or all of the top surface of the right semiconductor chip/bare chip 212, and the heat generated by the right semiconductor chip/bare chip 212 will be dissipated from the hot zone of the right temperature plate 23 to the cold zone of the right temperature plate 23 (see the right part of FIG. 11A and FIG. 11B). The gap G (e.g., >1 mm) between the two independent ultra-thin temperature plates 23 in FIG. 10 can be larger than the gap in FIG. 8, because most or all of the top surface of each semiconductor chip/bare chip 212 has been covered by an independent temperature plate 23. In another embodiment, the semiconductor chip can be a packaged semiconductor IC. The metal package 24 encapsulates the packaged semiconductor ICs and the temperature plate 23. The proximal end of each temperature plate 23 in the metal package 24 is thermally coupled with the packaged IC semiconductor via TIM or thermal adhesive material, while the distal end of each temperature plate 23 extending or protruding from the package 24 is in direct contact with the liquid.

The two or more independent temperature plate structures in FIG8 can also be applied to other IC packages, as shown in FIG12. In FIG12, the thickness of the semiconductor chip/bare chip 211 on the left is T5, and the total thickness of the semiconductor chip/bare chip 212 on the right (including multiple bare chips 2121, 2122 and 2123) is T6, where T6>T5. In this embodiment, the semiconductor chip/bare chip 211 on the left can be a multi-core processor, and the semiconductor chip/bare chip 212 on the right can be a stacked chip or HBM including multiple storage chips/bare chips stacked vertically.

The heat generated by the left semiconductor chip/bare chip 211 will be dissipated from the hot zone of the left temperature averaging plate 23A to the cold zone of the left temperature averaging plate 23A. The thickness of the left temperature averaging plate 23A, especially the thickness of the hot zone, is T3 (<1mm, such as 0.6mm). The heat generated by the right semiconductor chip/bare chip 212 (including multiple bare chips 2121, 2122 and 2123) will be dissipated from the hot zone of the right temperature averaging plate 23B to the cold zone of the right temperature averaging plate 23B. The thickness of the right temperature averaging plate 23B, especially the thickness of the hot zone, is T4 (<1mm, such as 0.3mm to 0.4mm). It is best that (T3+T5) is substantially the same as (T4+T6), so T3>T4. That is to say, different temperature averaging plates in the package 24 can have different thicknesses.

Optionally, support pillars 26 may be provided under the temperature evaporating plates 23A and 23B in FIG12 . The height of the left support pillar 26 in FIG12 is slightly higher than the height (T5) of the semiconductor chip/bare die 211, so that when the left support pillar 26 is arranged between the left temperature evaporating plate 23A and the substrate 22, there is a sufficient gap (e.g., 0.1 mm to 0.01 mm) between the left temperature evaporating plate 23A and the semiconductor chip/bare die 211 to accommodate the TIM or thermal adhesive layer 25. Therefore, the temperature evaporating plate 23A will not over-press the semiconductor chip/bare die 211. Similarly, the height of the right support column 26 in FIG. 12 is slightly higher than the height (T6) of the semiconductor chip/bare chip 212 (including multiple bare chips 2121, 2122 and 2123). Thus, when the right support column 26 is arranged between the right temperature balancing plate 23B and the substrate 22, there is a sufficient gap (e.g., 0.1 mm to 0.01 mm) between the right temperature balancing plate 23B and the semiconductor chip/bare chip 212 to accommodate the TIM or thermal adhesive layer 25.

FIG. 13 illustrates another embodiment of the present invention. The main difference between FIG. 13 and FIG. 12 is that the temperature averaging plates 23A and 23B extend upward, and the cold zone portion (or distal portion 232) is not covered by the package 24, but the side ends of the temperature averaging plates 23A and 23B are packaged by the package 24. In this embodiment, the upper surface of the temperature averaging plate 23A is the cold zone portion (or distal portion 232), and the lower surface of the temperature averaging plate 23A is the hot zone portion (or proximal portion 231), and the same is true for the temperature averaging plate 23B. The distance between the proximal portion 231 and the distal portion 232 of the temperature averaging plate 23A is T3', and the distance between the proximal portion 231 and the distal portion 232 of the temperature averaging plate 23B is T4'. Since T6>T5, it is best that (T6+T4') is the same or substantially the same as (T5+T3'), so T3'>T4'. The top surface of the temperature vaporizer 23A (and/or 23B) can be aligned or substantially aligned with the top surface of the package 24, or the top surface of the temperature vaporizer 23A (and/or 23B) can extend or protrude from the top surface of the package 24, so that the top surface of the temperature vaporizer 23A (and/or 23B) is higher than the top surface of the package 24. As described above, the cold zone portion of the temperature vaporizer 23A (and/or 23B) protruding from the top surface of the package 24 can be thermally coupled to a heat sink (which may include a liquid pipe) or directly immersed in a liquid to accelerate heat exchange. In another embodiment, the semiconductor chip can be a packaged semiconductor IC. The metal package 24 covers the packaged semiconductor ICs and the temperature plate 23. The proximal end of each temperature plate 23 in the metal package 24 is thermally coupled with the packaged semiconductor IC through TIM or thermal adhesive material, and the distal end of each temperature plate 23 extending or protruding from the package 24 is directly coupled with the liquid.

FIG. 14 illustrates another embodiment of the present invention. The main difference between FIG. 14 and FIG. 13 is that there is a single temperature plate 23 covering the semiconductor chip/bare die 211 and the semiconductor chip/bare die 212. The temperature plate 23 has a distal portion 232, a proximal portion 231A and another proximal portion 231B. The proximal portion 231A covers the semiconductor chip/bare die 211, and the other proximal portion 231B covers the semiconductor chip/bare die 212. The temperature averaging plate 23 includes a first portion, whose thickness is T3' (i.e., the distance between the distal portion 232 and the proximal portion 231A), which covers the semiconductor chip/bare chip 211; the temperature averaging plate 23 also includes a second portion, whose thickness is T4' (i.e., the distance between the distal portion 232 and another proximal portion 231B), which covers the semiconductor chip/bare chip 212. Among them, T3' (<1mm, such as 0.6mm to 0.8mm) is not equal to T4' (<1mm, such as 0.3mm to 0.5mm). Of course, whether it is Figure 13 or Figure 14, the side of each temperature averaging plate 23 can also extend out of the package 24, just like the structure of Figure 12. In addition, in Figure 13 or Figure 14, the top surface of each temperature averaging plate 23 is still covered by the package 24.

The above detailed description of the preferred specific embodiments is intended to more clearly describe the features and spirit of the present invention, but is not intended to limit the scope of the present invention by the preferred specific embodiments disclosed above. On the contrary, the purpose is to cover various changes and arrangements with equivalents within the scope of the patent application to be applied for by the present invention. Although the present invention has been disclosed in the above implementation, it is not intended to limit the present invention. Anyone familiar with this art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the patent application attached hereto.

2: Integrated circuit packaging

21: Semiconductor chip/bare chip

210: Copper Pillar

22: Substrate

221: Bump ball

23: Temperature balancing board

231: Proximal part

232: Remote part

233: Excessive part

2331: Arc

24: Package body

25: Thermal bonding layer

26: Support column

3: PCB board

31: Radiator

311:Liquid pipeline

32: Fan

Claims (20)

An integrated circuit package includes: a substrate; a semiconductor bare chip having a top surface, the semiconductor bare chip is stacked on the substrate; a temperature averaging plate stacked on the semiconductor bare chip, wherein the temperature averaging plate includes a proximal portion and a distal portion, the proximal portion covers the top surface of the semiconductor bare chip; and a package body, at least covering the semiconductor bare chip and the temperature averaging plate, wherein the proximal portion of the temperature averaging plate is located in the package body, the distal portion of the temperature averaging plate extends outward from an outer wall of the package body, the proximal portion of the temperature averaging plate is sealed in the package body, and the distal portion of the temperature averaging plate is not sealed in the package body. As described in Item 1 of the patent application scope, the temperature spreader is an ultra-thin temperature spreader with a thickness of 0.3 mm to 0.6 mm. As described in Item 1 of the patent application scope, the temperature spreader is an ultra-thin temperature spreader with a thickness of less than 1 mm. An integrated circuit package as described in item 3 of the patent application, wherein the package body comprises a molding material, the proximal portion of the temperature vapor chamber is sealed by the molding material, and there is no molding material between the temperature vapor chamber and the semiconductor bare chip. The integrated circuit package as described in item 3 of the patent application scope, wherein the package body is a metal shell, the metal shell covers the substrate, the semiconductor bare chip and the temperature plate, and the temperature plate further includes a transition portion between the distal portion and the proximal portion, the transition portion and the metal shell are integrated, or there is a waterproof material seal between the transition portion and the metal shell. An integrated circuit package as described in item 3 of the patent application, wherein the proximal portion covers most or all of the top surface of the semiconductor bare chip, and the temperature vapor chamber is stacked on the semiconductor bare chip through a thermal interface material (TIM) or a thermal adhesive layer. The integrated circuit package as described in Item 6 of the patent application further includes a support column located between the temperature-averaging plate and the substrate, and the height of the support column is greater than the height of the semiconductor bare chip. An integrated circuit package as described in Item 1 of the patent application, wherein the temperature evaporator includes: a set of isolation structures formed in the temperature evaporator; and a set of capillary structures formed in the temperature evaporator and between the set of isolation structures. An integrated circuit package as described in Item 8 of the patent application, wherein the set of isolation structures extends from the distal portion to the proximal portion, and the set of isolation structures passes through the outer wall of the package body. The integrated circuit package as described in Item 8 of the patent application, wherein the temperature vaporizer further comprises a set of supporting structures connected to the set of isolation structures, wherein the set of supporting structures extends downward from the top surface of the temperature vaporizer, the set of isolation structures extends upward from the bottom surface of the temperature vaporizer, and another set of capillary structures is further included between the set of supporting structures. An integrated circuit package as described in item 1 of the patent application, wherein the distal portion of the temperature vapor chamber is thermally coupled to a heat sink, or directly coupled to a liquid, wherein the heat sink or the liquid is located outside the package. An integrated circuit package includes: a first semiconductor chip having a first top surface; a first temperature absorbing plate stacked on the first semiconductor chip, wherein the first temperature absorbing plate includes a first proximal portion and a first distal portion, the first proximal portion covers the first top surface of the first semiconductor chip, and the thickness of the first proximal portion is less than 1 mm; and a package body covering the first semiconductor chip and the first temperature absorbing plate, wherein the first proximal portion of the first temperature absorbing plate is sealed in the package body, and the first distal portion of the first temperature absorbing plate protrudes outward from an outer wall of the package body. An integrated circuit package as described in Item 12 of the patent application, wherein the thickness of the first proximal portion is between 0.3 mm and 0.8 mm. An integrated circuit package as described in Item 12 of the patent application, wherein the first temperature vapor chamber further comprises another distal portion protruding from another outer wall of the package body, and the first proximal portion is located between the first distal portion and the other distal portion. The integrated circuit package as described in item 12 of the patent application further comprises: a second temperature averaging plate, separated from the first temperature averaging plate and stacked on the first semiconductor chip, wherein the second temperature averaging plate is covered by the package body; wherein the second temperature averaging plate comprises a second proximal portion and a second distal portion, the second proximal portion of the second temperature averaging plate covers the first top surface of the first semiconductor chip, and the thickness of the second proximal portion of the second temperature averaging plate is less than 1 mm, and the second distal portion of the second temperature averaging plate extends outward from another outer wall of the package body. The integrated circuit package as described in item 15 of the patent application scope further includes a second semiconductor chip vertically spaced apart from the first semiconductor chip, and the second semiconductor chip is disposed under the first semiconductor chip. The integrated circuit package as described in item 12 of the patent application scope further includes: a second semiconductor chip having a second top surface, the second semiconductor chip is horizontally separated from the first semiconductor chip; and a second temperature averaging plate is horizontally separated from the first temperature averaging plate and stacked on the second semiconductor chip, wherein the second semiconductor chip and the second temperature averaging plate are covered by the package body; wherein the second temperature averaging plate includes a second proximal portion and a second distal portion, the second proximal portion of the second temperature averaging plate covers the second top surface of the second semiconductor chip, the thickness of the second proximal portion of the second temperature averaging plate is less than 1 mm, and the second distal portion of the second temperature averaging plate extends outward from another outer wall of the package body. An integrated circuit package includes: a substrate; a first semiconductor chip having a first top surface, the first semiconductor chip is located on the substrate; a first temperature evaporating plate, wherein the first temperature evaporating plate includes a proximal portion and a distal portion, the proximal portion is thermally coupled to the first top surface of the first semiconductor chip; and a package body, covering the first semiconductor chip and the first temperature evaporating plate, wherein the proximal portion of the first temperature evaporating plate is packaged in the package body, and the distal portion of the first temperature evaporating plate protrudes out of the package body; wherein the distal portion of the first temperature evaporating plate is thermally coupled to a heat sink or a liquid pipe, or is directly immersed in a liquid, wherein the heat sink or the liquid pipe or the liquid is located outside the package body. The integrated circuit package as described in item 18 of the patent application, wherein the package body is a metal shell, the metal shell encapsulates the first semiconductor chip and the first temperature averaging plate, the first temperature averaging plate further comprises a transition portion between the distal portion and the proximal portion, the transition portion is integrated with the metal shell, or there is a waterproof material seal between the transition portion and the metal shell. The integrated circuit package as described in item 18 of the patent application further comprises: a second semiconductor chip having a second top surface, the second semiconductor chip being horizontally separated from the first semiconductor chip and being located on the substrate, wherein the second semiconductor chip is covered by the package body; wherein the first temperature plate further comprises another proximal portion covering the second top surface of the second semiconductor chip.