TWI870873B - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

The semiconductor memory device of the present embodiment includes a first chip and a second chip. The first chip includes: a first memory cell array including a plurality of first memory cells; and a first wiring layer electrically connected to the first memory cell array. The second chip includes a second memory cell array, the second memory cell array is electrically connected to the first wiring layer and includes a plurality of second memory cells. The first chip and the second chip are bonded at a first bonding surface. The second chip and the first memory cell array share the first wiring layer.

Description

Semiconductor memory device and manufacturing method thereof

This embodiment relates to a semiconductor memory device and a manufacturing method thereof. [Citations from related applications] This application is based on and claims the benefit of priority based on the prior Japanese Patent Application No. 2022-100704 filed on June 22, 2022, the entire content of which is incorporated herein by reference.

Semiconductor memory devices such as NAND flash memories are sometimes constructed by bonding multiple memory chips together. The multiple memory chips each have a memory cell array and a bit line connected to the memory cell array. When a complementary metal oxide semiconductor (CMOS) circuit that controls the memory cell array is shared by multiple memory chips, the parasitic capacitance of the bit line increases because the bit lines of the multiple memory chips are connected to the CMOS circuit. In addition, in order to selectively connect the bit lines of the multiple memory chips to the CMOS circuit, switches need to be set for each bit line. In this case, miniaturization of semiconductor memory devices is hindered.

One embodiment provides a semiconductor memory device that suppresses capacitance of a bit line and is suitable for miniaturization, and a method for manufacturing the same.

The semiconductor memory device of this embodiment includes a first chip and a second chip. The first chip includes: a first memory cell array including a plurality of first memory cells; and a first wiring layer electrically connected to the first memory cell array. The second chip includes a second memory cell array, which is electrically connected to the first wiring layer and includes a plurality of second memory cells. The first chip and the second chip are bonded at a first bonding surface. The second chip and the first memory cell array share the first wiring layer. The manufacturing method of the semiconductor memory device of the present embodiment includes: forming a first chip including a first memory cell array and a first wiring layer, the first memory cell array including a plurality of first memory cells, the first wiring layer being electrically connected to the first memory cell array; forming a second chip including a second memory cell array, the second memory cell array being electrically connected to the first wiring layer and including a plurality of second memory cells; bonding the first chip to the second chip in a manner that the first wiring layer is electrically connected to the second memory cell array.

The above structure can provide a semiconductor memory device which suppresses the capacitance of the bit line and is suitable for miniaturization, and a method for manufacturing the same.

Hereinafter, the embodiment of the present invention will be described with reference to the drawings. The embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratios of the various parts may not be the same as the ratios of the various parts in reality. In the specification and drawings, the same symbols are used for the same elements as those described in the drawings, and detailed descriptions are omitted as appropriate.

(First embodiment) (Structure of semiconductor memory device 100) FIG. 1 is a cross-sectional view showing a structural example of a semiconductor memory device 100 according to a first embodiment. Hereinafter, the stacking direction of the first array chip CH1 and the second array chip CH2 is defined as the Z direction. A direction intersecting the Z direction, for example, orthogonal to the Z direction, is defined as the Y direction. A direction intersecting the Z direction and the Y direction, for example, orthogonal to the X direction, is defined as the X direction.

The semiconductor memory device 100 includes: a first array chip CH1 and a second array chip CH2, each having a memory cell array; and a CMOS chip CH3, each having a CMOS circuit. The first array chip CH1 is an example of a first chip, the second array chip CH2 is an example of a second chip, and the CMOS chip CH3 is an example of a third chip.

The first array chip CH1 and the second array chip CH2 are bonded at the bonding surface B1. The bonding surface B1 is an example of a first bonding surface. The first array chip CH1 and the CMOS chip CH3 are bonded at the bonding surface B2. The bonding surface B2 is an example of a second bonding surface. FIG. 1 shows a state where the first array chip CH1 is bonded to the CMOS chip CH3, and the second array chip CH2 is bonded to the first array chip CH1.

The CMOS chip CH3 includes a substrate 30, a transistor 31, an interlayer connection point 32, a wiring 33, an interlayer insulating film 35, a bonding pad CT3, and a bonding pad 34.

The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an N-type metal oxide semiconductor (NMOS) or a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate 30. The transistor 31, for example, constitutes a CMOS circuit for controlling the memory cell arrays of the first array chip CH1 and the second array chip CH2. Semiconductor elements such as resistor elements and capacitor elements other than the transistor 31 may also be formed on the substrate 30.

The interlayer connection point 32 electrically connects the transistor 31 and the wiring 33, or the wiring 33 and the pads CT3 and 34. The wiring 33 and the pads CT3 and 34 form a multi-layer wiring structure in the interlayer insulating film 35. The pads CT3 and 34 are buried in the interlayer insulating film 35 and are exposed on the surface of the interlayer insulating film 35 in a substantially flush plane with the surface. The wiring 33 and the pads CT3 and 34 are electrically connected to the transistor 31, etc. The pads CT3 and 34 are examples of third pads. The interlayer connection point 32, the wiring 33, and the pads CT3 and 34 may be made of, for example, a low-resistance metal such as copper or tungsten. The pads CT3 and 34 are electrically connected to the pads CT4 and 17 of the first array chip CH1 at the bonding surface B2, respectively. The pads CT4 and 17 of the first array chip CH1 are examples of the fourth pad. The interlayer insulating film 35 covers and protects the transistor 31, the interlayer connection point 32, the wiring 33, and the pads CT3 and 34. The interlayer insulating film 35 may be made of, for example, an insulating film such as a silicon oxide film.

The first array chip CH1 includes a stacked body 10, a first columnar body CL1, a source layer BSL1, contact plugs 18, 19, 45, a bit line BL, pads CT1, CT4, 17, 44, 46, and an interlayer insulating film 15.

The laminate 10 is disposed above the substrate 30 and the transistor 31 (in the Z direction). The laminate 10 is formed by alternately laminating a plurality of electrode films 11 and a plurality of insulating films 12 along the Z direction. The electrode film 11 may be made of, for example, a conductive metal such as tungsten. The insulating film 12 may be made of, for example, an insulating film such as a silicon oxide film. The insulating film 12 insulates the electrode films 11 from each other. That is, the plurality of electrode films 11 are laminated in a mutually insulated state. The number of layers of each of the electrode film 11 and the insulating film 12 is arbitrary. The insulating film 12 may also be, for example, a porous insulating film or an air gap.

As shown in FIG. 16 , one or more electrode films 11 at the upper and lower ends of the multilayer body 10 in the Z direction function as a source side selection gate SGS and a drain side selection gate SGD, respectively. The electrode film 11 between the source side selection gate SGS and the drain side selection gate SGD functions as a word line WL. The word line WL is the gate electrode of the first memory cell array MCA1. The drain side selection gate SGD is the gate electrode of the drain side selection transistor STD. The source side select gate SGS is a gate electrode of the source side select transistor STS.

The semiconductor memory device 100 of FIG1 has a plurality of memory cells MC1 connected in series between a source side select transistor and a drain side select transistor (not shown in FIG1 ). The plurality of memory cells MC1 constitute a first memory cell array MCA1. The structure in which the source side select transistor, the memory cell MC1, and the drain side select transistor are connected in series is called a "memory string" or a "NAND string". The memory string is electrically connected to a bit line BL. The bit line BL is disposed above the laminate 10 and extends in the Y direction. The bit line BL is an example of a first wiring layer. In this embodiment, as described below, the first memory cell array MCA1 and the second memory cell array MCA2 share the bit line BL.

A plurality of pillars CL1 are provided in the laminate 10. The pillars CL1 extend in the laminate 10 in the lamination direction (Z direction) of the electrode film 11 and the insulating film 12 so as to penetrate the laminate 10, and are provided from the bit line BL to the source layer BSL1. A memory cell MC1 is provided at the intersection of the pillar CL1 and the electrode film 11. A first memory cell array MCA1 is formed by three-dimensionally arranging a plurality of memory cells MC1. The internal structure of the pillar CL1 will be described below. Furthermore, in the present embodiment, since the pillar CL1 has a high aspect ratio, it is formed by being divided into two sections in the Z direction. However, there is no problem even if the column CL1 is one segment.

In addition, a plurality of slits ST are provided in the laminate 10. The slits ST extend in the X direction and penetrate the laminate 10 in the Z direction. An insulating film such as a silicon oxide film is filled in the slits ST, and the insulating film is formed into a plate shape. The slits ST electrically separate the electrode film 11 of the laminate 10. Wiring can also be provided inside the insulating film in the slits ST. The wiring can be connected to the source layer BSL1 while maintaining electrical insulation from the electrode film 11.

A bit line BL is provided above the laminate 10. On the lower side of the bit line BL (the side of the CMOS chip CH3), a plurality of columns CL1 are electrically connected via an interlayer connection point VY. On the upper side of the bit line BL (the side of the second array chip CH2), a solder pad CT1 is electrically connected. The solder pad CT1 is an example of a first solder pad. The solder pad CT1 is electrically connected to the first memory cell array MCA1 via the bit line BL. The solder pad CT1 is buried in the interlayer insulating film 15 and is exposed in a substantially flush plane with the surface of the interlayer insulating film 15. In addition, the solder pad CT1 is electrically connected to the solder pad CT2 of the second array chip CH2. The bit line BL is also electrically connected to the contact plug 18. The contact plug 18 is connected to the CMOS chip CH3 via the bonding pad CT4. The bit line BL is also electrically connected to the CMOS chip CH3 via the contact plug 18.

A source layer BSL1 is provided below the multilayer body 10. The source layer BSL1 is provided corresponding to the multilayer body 10. One end of a plurality of pillars CL1 is commonly connected to the upper side of the source layer BSL1 (the side of the first memory cell array MCA1). Thus, the source layer BSL1 provides a common source potential to the plurality of pillars CL1 located in the first memory cell array MCA1, and functions as a common source electrode of the first memory cell array MCA1. The source layer BSL1 may be made of, for example, a conductive material such as doped polysilicon. Furthermore, the portion 1m of the first memory cell array MCA1 is a portion of the memory cell array, and the portion 1s of the first memory cell array MCA1 is a stepped portion of the electrode film 11 provided to connect the contact portions on each electrode film 11. The portion 1m and the portion 1s will be described later with reference to FIG. 2 .

The contact plug 19 is provided so that the interlayer insulating film 15 extends in the Z direction. One end of the contact plug 19 is electrically connected to the pad 34 of the CMOS chip CH3 via the pad 17. The other end of the contact plug 19 is electrically connected to the pad 23 of the second array chip CH2 via the pad 13.

The second array chip CH2 includes a laminate 20, a second columnar body CL2, a source layer BSL2, a contact plug 29, a contact plug 41, a conductor 42, a pad CT2, a pad 43, a metal layer 40, a bonding pad 50, and an interlayer insulating film 25.

Furthermore, the structures of the laminate 20, the second column CL2, and the source layer BSL2 may be the same as the structures of the laminate 10, the first column CL1, and the source layer BSL1, respectively. Therefore, detailed description of the laminate 20 (electrode film 21, insulating film 22), the portion 2m, the second column CL2, and the source layer BSL2 is omitted.

A source layer BSL2 is provided above the laminate body 20, and a metal layer 40 is provided above the source layer BSL2. The metal layer 40 includes, for example, a source line or a power line, and a metal material such as copper, tungsten, or aluminum may be used. The source layer BSL2 is electrically connected to the metal layer 40. A bonding pad 50 is also provided above the source layer BSL2. The bonding pad 50 may also receive power supply from outside the semiconductor memory device 100. The bonding pad 50 is connected to the pad 34 of the CMOS chip CH3 via the contact plug 29, the contact plug 19, the pad 13, the pad 23, the pad 17, and the like. Thereby, the external power supplied from the bonding pad 50 is supplied to the CMOS chip CH3.

A solder pad CT2 is provided below the laminate 20. The solder pad CT2 is an example of a second solder pad. The solder pad CT2 is connected to a plurality of second columnar bodies CL2. Thereby, the solder pad CT2 is electrically connected to the second memory cell array MCA2. The solder pad CT2 is buried in the interlayer insulating film 25 and is exposed on the surface of the interlayer insulating film 25 so as to be substantially flush with the surface. As described above, the solder pad CT2 is electrically connected to the solder pad CT1 of the first array chip CH1 at the bonding surface B1.

Below the second array chip CH2, a pad 43 is electrically connected to the upper surface of the pad 44. The pad 43 is electrically connected to the metal layer 40 provided on the upper surface of the source layer BSL2 via the conductor 42 and the contact plug 41. In the first array chip CH1, the pad 44 is electrically connected to the CMOS chip CH3 via the contact plug 45 and the pad 46. Although not shown in detail, the pad 46 is electrically connected to the transistor 31 via the contact portion or the conductor. Thereby, the metal layer 40 provided on the upper surface of the source layer BSL2 is electrically connected to the transistor 31.

Here, the case where the first memory cell array MCA1 and the second memory cell array MCA2 share the bit line BL is described in detail.

The plurality of columns CL1 of the first memory cell array MCA1 are electrically connected to the bit line BL via the interlayer connection point VY. In addition, the plurality of second columns CL2 of the second memory cell array MCA2 are connected to the bit line BL via the bonding pads CT2 and CT1. That is, the bit line BL is commonly connected to and shared by the first memory cell array MCA1 and the second memory cell array MCA2. A layer of bit lines BL is provided for the two memory cell arrays. The bit line BL is provided in the first array chip CH1, but the bit line BL is not provided in the second array chip CH2. Furthermore, as shown in FIG. 1 , when viewed from the X direction, a layer of bit lines BL appears to be one wiring line, but when viewed from above from the Z direction, a plurality of bit lines BL are arranged along the X direction.

As in the present embodiment, when the two array chips CH1 and CH2 share the bit line BL, the total extension or total stacking of the bit line BL is shortened or reduced by one layer compared to the case where the bit line BL is not shared. Thus, the parasitic capacitance of the bit line BL can be reduced. In addition, by sharing the bit line BL in the two array chips CH1 and CH2, the semiconductor memory device 100 can be miniaturized.

In this embodiment, the first array chip CH1, the second array chip CH2 and the CMOS chip CH3 are formed separately and bonded to each other. The CMOS chip CH3 is shared by the array chips CH1 and CH2 as a memory controller for controlling the memory cell arrays MCA1 and MCA2.

Fig. 2 is a schematic plan view showing the first memory cell array MCA1 or the second memory cell array MCA2. In Fig. 2, the structure of the first memory cell array MCA1 is described, but the second memory cell array MCA2 may also have the same structure.

The first memory cell array MCA1 includes a portion 1s and a portion 1m. The portion 1s is arranged in a step-like manner at the edge of the first memory cell array MCA1. The portion 1m is clamped or surrounded by the portion 1s. The slit ST is arranged from the portion 1s at one end of the first memory cell array MCA1 through the portion 1m to the portion 1s at the other end of the first memory cell array MCA1. The slit SHE is at least arranged in the portion 1m. The slit SHE is shallower than the slit ST and extends approximately parallel to the slit ST. The slit SHE is arranged to electrically separate the electrode film 11 for each drain side selection gate SGD.

The portion of the first memory cell array MCA1 sandwiched by the two slits ST shown in FIG2 is called a block. A block constitutes, for example, the smallest unit of data erasure. The slit SHE is disposed within the block. The first memory cell array MCA1 between the slit ST and the slit SHE is called a finger. The drain side selection gate SGD is divided for each finger. Therefore, when writing and reading data, one finger within the block can be selected by the drain side selection gate SGD.

Fig. 3 and Fig. 4 are schematic cross-sectional views respectively illustrating a memory cell having a three-dimensional structure. In Fig. 3 and Fig. 4, the structure of the columnar body CL1 is described, and the columnar body CL2 may also have the same structure.

As shown in FIG3 , a plurality of columns CL1 are respectively disposed in memory holes MH disposed in the laminate 10. Each column CL1 passes through the laminate 10 from the upper end to the lower end along the Z direction and is disposed in the laminate 10 and on the source layer BSL1. The plurality of columns CL1 respectively include a semiconductor body 110, a memory film 120, and a core layer 130. The column CL1 includes a core layer 130 disposed at the center thereof, a semiconductor body (semiconductor component) 110 disposed around the core layer 130, and a memory film (charge storage component) 120 disposed around the semiconductor body 110. The semiconductor body 110 extends in the stacking direction (Z direction) in the stacking body 10. The semiconductor body 110 is electrically connected to the source layer BSL1. The memory film 120 is provided between the semiconductor body 110 and the electrode film 11 and has a charge trapping portion. A plurality of pillars CL1 selected one by one from each finger portion are connected to the bit line BL in common. The pillars CL1 are provided, for example, in the region of the portion 1m.

As shown in FIG4 , the shape of the memory hole MH in the X-Y plane is, for example, a circle or an ellipse. A blocking insulating film 11a constituting a portion of the memory film 120 may be provided between the electrode film 11 and the insulating film 12. The blocking insulating film 11a is, for example, a silicon oxide film or a metal oxide film. An example of a metal oxide is aluminum oxide. A barrier film 11b may be provided between the electrode film 11 and the insulating film 12 and between the electrode film 11 and the memory film 120. For example, when the electrode film 11 is tungsten, the barrier film 11b is a laminated structure film of, for example, titanium nitride (TiN) and titanium (Ti). The blocking insulating film 11a suppresses back tunneling of charges from the electrode film 11 to the memory film 120. The barrier film 11b improves the adhesion between the electrode film 11 and the blocking insulating film 11a.

The shape of the semiconductor body 110 as a semiconductor component is, for example, a tube with a bottom. The semiconductor body 110 can be made of, for example, polycrystalline silicon. The semiconductor body 110 can be, for example, undoped silicon. In addition, the semiconductor body 110 can also be p-type silicon. The semiconductor body 110 becomes a channel for each of the drain side selection transistor STD, the memory cell MC1, and the source side selection transistor STS. One end of the multiple semiconductor bodies 110 in the same part 1m is electrically connected to the source layer BSL1.

In the memory film 120, the portion other than the blocking insulating film 11a is disposed between the inner wall of the memory hole MH and the semiconductor body 110. The shape of the memory film 120 is, for example, cylindrical. A plurality of memory cells MC1 have a memory region between the semiconductor body 110 and the electrode film 11 that becomes the word line WL, and are stacked along the Z direction. The memory film 120 includes, for example, a covering insulating film 121, a charge trapping film 122, and a tunnel insulating film 123. The semiconductor body 110, the charge trapping film 122, and the tunnel insulating film 123 extend along the Z direction, respectively.

The covering insulating film 121 is disposed between the insulating film 12 and the charge trapping film 122. The covering insulating film 121 includes, for example, silicon oxide. When the sacrificial film (not shown) is replaced with the electrode film 11 (replacement step), the covering insulating film 121 protects the charge trapping film 122 from being etched. In the replacement step, the covering insulating film 121 may be removed from between the electrode film 11 and the memory film 120. In this case, as shown in FIGS. 3 and 4, for example, a blocking insulating film 11a is not disposed between the electrode film 11 and the charge trapping film 122. In addition, when the replacement step is not used in the formation of the electrode film 11, the covering insulating film 121 may not be provided.

The charge trapping film 122 is provided between the blocking insulating film 11a and the cap insulating film 121 and the tunnel insulating film 123. The charge trapping film 122 includes, for example, silicon nitride (SiN), and has a trapping point for trapping charges in the film. The portion of the charge trapping film 122 sandwiched between the electrode film 11 as the word line WL and the semiconductor body 110 constitutes a memory region of the memory cell MC1 as a charge trapping portion. The threshold voltage of the memory cell MC1 varies depending on the presence or absence of charges in the charge trapping portion or the amount of charges trapped in the charge trapping portion. Thereby, the memory cell MC1 retains the information.

The tunnel insulating film 123 is disposed between the semiconductor body 110 and the charge trapping film 122. The tunnel insulating film 123 includes, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 123 is a barrier between the semiconductor body 110 and the charge trapping film 122. For example, when electrons are injected from the semiconductor body 110 into the charge trapping portion (writing operation) and when holes are injected from the semiconductor body 110 into the charge trapping portion (erasing operation), the electrons and holes pass through (tunnel) the barrier of the tunnel insulating film 123, respectively.

The core layer 130 is embedded in the inner space of the cylindrical semiconductor body 110. The shape of the core layer 130 is, for example, a columnar shape. The core layer 130 includes, for example, silicon oxide and is insulating.

FIG5 is a schematic plan view showing an example of the structure of the first array chip CH1. FIG5 shows an enlarged view of the area A of FIG2. FIG5 shows, in addition to the slits ST and SHE, the bit lines BL, the interlayer connection points VY, and the pads CT1 (columnar bodies CL1). Furthermore, the first array chip CH1 includes the bit lines BL, but the difference from the first array chip CH1 is that the second array chip CH2 does not include the bit lines BL. The other structures of the second array chip CH2 may be the same as those of the first array chip CH1.

A plurality of columns CL1 are arranged in a saw-tooth shape in the region between adjacent slits ST. Furthermore, the number or arrangement of the columns CL1 between adjacent slits ST is not limited thereto and may be appropriately changed. As described above, the columns CL1 each function as a part of a memory string. A plurality of bit lines BL each extend in the Y direction and are arranged in the X direction. The bit lines BL are arranged in a manner overlapping the columns CL1. In the present embodiment, two bit lines BL are arranged overlapping each column CL1.

In each finger between the slit ST and the slit SHE or between adjacent slits SHE, each pillar CL1 is connected to one bit line BL via an interlayer connection point VY. That is, in each finger, the pillar CL1 corresponds to the bit line BL one by one. Thus, when a finger is selected, the plurality of bit lines BL can transmit the data read from all the pillars CL1 included in the finger.

The bonding pad CT1 is disposed on the bit line BL (in the Z direction) and is electrically connected to the bit line BL. Therefore, when viewed from above in the Z direction, the bonding pad CT1 and the column CL1 overlap at substantially the same position.

Furthermore, in the second array chip CH2, the arrangement of the plurality of columns CL2 may be the same as the arrangement of the plurality of columns CL1. That is, when viewed from above in the Z direction, the pads CT2 and the columns CL2 overlap at substantially the same position. In addition, the second array chip CH2 shares the bit line BL with the first array chip CH1. Therefore, when viewed from above in the Z direction, the configuration relationship between the columns CL2 or the pads CT2 and the bit line BL is also the same as the configuration relationship between the columns CL1 or the pads CT1 and the bit line BL in FIG. 5. Therefore, when viewed from above in the Z direction, the pads CT2 and the columns CL2 of the second array chip CH2 overlap at substantially the same position as the pads CT1 and the columns CL1 of the first array chip CH1.

According to the above situation, in FIG5, the column CL1, the pad CT1, the column CL2 and the pad CT2 are all located at substantially the same position. Thus, the bit line BL is commonly connected to the plurality of columns CL1 and the plurality of columns CL2. That is, the first memory cell array MCA1 and the second memory cell array MCA2 share the bit line BL.

(Method for Manufacturing Semiconductor Memory Device 100) A method for manufacturing the semiconductor memory device 100 will be described with reference to Fig. 6 to Fig. 12. Fig. 6 to Fig. 12 are schematic cross-sectional views showing an example of the method for manufacturing the semiconductor memory device 100 according to the present embodiment.

First, as shown in FIG. 6 and FIG. 7 , a first array chip CH1 and a second array chip CH2 are manufactured by a semiconductor memory chip manufacturing step.

The first array chip CH1 is manufactured by forming a source layer BSL1, a first memory cell array MCA1 (first memory cell MC1), a bit line BL, a pad CT1, a pad 13, a contact plug 19, etc. on a substrate 60, and covering these components with an interlayer insulating film 15. Similarly, the second array chip CH2 is manufactured by forming a source layer BSL2, a second memory cell array MCA2 (second memory cell MC2), a pad CT2, a pad 23, a contact plug 29, etc. on a substrate 70, and covering these components with an interlayer insulating film 25.

At this time, on the surface F1 of the first array chip CH1, the pads CT1 and 13 are exposed in substantially the same plane. In addition, on the surface F2 of the second array chip CH2, the pads CT2 and 23 are exposed in substantially the same plane. Thus, when the first array chip CH1 and the second array chip CH2 are bonded together, the pads CT1 and CT2 are electrically connected, and the pads 13 and 23 are electrically connected.

FIG7 shows the state after the first array chip CH1 and the second array chip CH2 are bonded. The first array chip CH1 and the second array chip CH2 are bonded at the bonding surface B1. At the bonding surface B1, the pad CT1 is electrically connected to the pad CT2, and the pad 13 is electrically connected to the pad 23. Furthermore, the bit line BL is connected to the first memory cell array MCA1 via the column CL1. In addition, the bit line BL is connected to the second memory cell array MCA2 via the pad CT1 and the pad CT2. In this way, the bit line BL is commonly connected to the first memory cell array MCA1 and the second memory cell array MCA2.

Next, as shown in FIG8 , a dicing blade is used to remove (trim) the remaining portions of the edges of the substrates 60 and 70, the interlayer insulating films 15, and the interlayer insulating films 25. In this embodiment, trimming is performed after the first array chip CH1 and the second array chip CH2 are bonded together. Thus, the remaining portions of both the first array chip CH1 and the second array chip CH2 can be removed by trimming once, thereby simplifying the manufacturing steps.

Next, as shown in FIG9 , the substrate 60 is peeled off to expose the surface F3. Furthermore, using lithography and etching techniques, a contact hole is formed in the interlayer insulating film 15. The contact hole is formed to a depth that reaches the source layer BSL1 of the first memory cell array MCA1. Then, a metal material such as copper is buried in the contact hole to form a bonding pad CT4 and a bonding pad 17.

Next, the interlayer insulating film 15 may be polished by using a chemical mechanical polishing (CMP) method so that the bonding pads CT4 and 17 are exposed on the surface F3 in substantially the same plane.

Next, as shown in FIG. 10 and FIG. 11 , a semiconductor manufacturing process is used to manufacture a CMOS chip CH3. The CMOS chip CH3 is manufactured by forming a transistor 31, an interlayer connection point 32, a wiring 33, and a bonding pad CT3 and a bonding pad 34 on a substrate 30, and protecting these components by an interlayer insulating film 35. In addition, on the surface F4, the bonding pad CT3 and the bonding pad 34 are exposed in a substantially identical plane. Next, the array chip CH1 and the array chip CH2 are turned upside down, and the surface F3 of the first array chip CH1 is bonded to the surface F4 of the CMOS chip CH3.

FIG11 shows the state after the first array chip CH1 and the CMOS chip CH3 are bonded. The first array chip CH1 and the CMOS chip CH3 are bonded at the bonding surface B2. At the bonding surface B2, the bonding pad CT4 is electrically connected to the bonding pad CT3, and the bonding pad 17 is electrically connected to the bonding pad 34. Furthermore, the bit line BL is electrically connected to the substrate 30 of the CMOS chip CH3 without passing through the transistor.

Next, as shown in FIG12 , the substrate 70 is peeled off. Then, a metal material such as aluminum is embedded in the interlayer insulating film 25 to form a metal layer 40 and a bonding pad 50. The bonding pad 50 is formed to be connected to the contact plug 29. Thereby, the bonding pad 50 is electrically connected to the CMOS chip CH3. Thereafter, although not shown, the individual chips of the semiconductor memory device 100 are singulated through a cutting step. Through the above steps, the semiconductor memory device 100 of this embodiment is completed.

As described above, through this embodiment, the bit line BL is commonly connected (shared) with the first memory cell array MCA1 and the second memory cell array MCA2. Thereby, only one layer of bit lines BL is required for the two memory cell arrays, and the multi-layering of the bit lines BL can be suppressed. When the bit lines BL are shared, the total extension of the bit lines BL is shortened, and its parasitic capacitance can be reduced. Thereby, the operation speed of the semiconductor memory device 100 can be increased, and the power consumption of the semiconductor memory device 100 can be reduced. In addition, since the bit lines BL are shared with the two memory cell arrays MCA1 and MCA2, the miniaturization of the semiconductor memory device 100 is achieved.

In addition, since the bit line BL is shared by the two memory cell arrays MCA1 and MCA2, a switch (transistor) for selecting the bit line BL is not required. Therefore, the transistor for selecting the bit line BL can be omitted. Therefore, miniaturization of the semiconductor memory device 100 is achieved.

In addition, according to the manufacturing steps of this embodiment, trimming is performed after the first array chip CH1 and the second array chip CH2 are bonded together. Therefore, the surplus parts of the first array chip CH1 and the second array chip CH2 can be removed by one trimming, thereby simplifying the manufacturing steps.

(Second embodiment) FIG. 13 is a cross-sectional view showing a structural example of a semiconductor memory device 100 according to a second embodiment. In the second embodiment, the difference from the first embodiment is that a CMOS chip CH3 is bonded to a second array chip CH2 where no bit lines BL are provided. Accordingly, a metal layer 40 and a bonding pad 50 are provided on the first array chip CH1. The other structures of the second embodiment may be the same as those of the first embodiment.

The second array chip CH2 includes a solder pad CT5 on the surface opposite to the bonding surface B1. The solder pad CT5 is buried in the interlayer insulating film 25 and is exposed on the surface of the interlayer insulating film 25 so as to be roughly flush with the surface. The solder pad CT5 is an example of a fifth solder pad. The solder pad CT5 is electrically connected to the solder pad CT3 of the CMOS chip CH3 on the bonding surface B3. The bonding surface B3 is an example of a third bonding surface. Thereby, the second memory cell array MCA2 is electrically connected to the CMOS chip CH3 via the solder pad CT5 and the solder pad CT3. The contact plug 28 is electrically connected to the bit line BL. In addition, the contact plug 28 is connected to the CMOS chip CH3 via the solder pad CT5 and the solder pad CT3. Thereby, the bit line BL is electrically connected to the CMOS circuit of the CMOS chip CH3.

The other structures of the second embodiment may be the same as those of the first embodiment. Therefore, in the second embodiment, the first memory cell array MCA1 and the second memory cell array MCA2 are also connected to the bit line BL in common. Therefore, the second embodiment can obtain the same effect as the first embodiment. In addition, the manufacturing method of the second embodiment can be easily inferred from the manufacturing method of the first embodiment, so its detailed description is omitted. The manufacturing method of the second embodiment can obtain the same effect as the first embodiment.

(Third embodiment) FIG. 14 is a cross-sectional view showing a structural example of a semiconductor memory device 100 according to the third embodiment. In the third embodiment, the CMOS chip CH3 is not bonded to the first array chip CH1, but the CMOS circuit is incorporated into the first array chip CH1. The first array chip CH1 includes the CMOS circuit below the memory cell array MCA1. Therefore, the transistor 31 of the CMOS circuit is formed on the substrate 30, and the memory cell array MCA1 is formed above the CMOS circuit. In this way, the first array chip CH1 according to the third embodiment has the structure of both the first array chip CH1 and the CMOS chip CH3 according to the first embodiment. The transistor 31 is electrically connected to the source layer BSL1 via the interlayer connection point 32, the interlayer connection point 37, the wiring 33, and the wiring 36.

The other structures of the third embodiment can be the same as those of the first embodiment. Therefore, the third embodiment can obtain the same effect as the first embodiment.

In the manufacturing method of the third embodiment, in order to manufacture the first array chip CH1, a transistor 31 is formed above the substrate 30, and then covered with an interlayer insulating film 15. Furthermore, a source layer BSL1, a first memory cell array MCA1, a bit line BL, etc. are formed above the transistor 31.

The other manufacturing steps of the third embodiment are the same as those of the first embodiment. Therefore, the third embodiment can obtain the same effect as that of the first embodiment. In addition, in the third embodiment, the step of attaching the CMOS chip CH3 to the first array chip CH1 can be omitted. The third embodiment can also be combined with the second embodiment. That is, the CMOS circuit can also be incorporated into the second array chip CH2.

15 is a block diagram showing a configuration example of a semiconductor memory device 100 to which any of the above-described embodiments is applied. The semiconductor memory device 100 is, for example, a NAND flash memory capable of storing data in a non-volatile manner, and is controlled by an external memory controller 1002. The communication between the semiconductor memory device 100 and the memory controller 1002 supports, for example, the NAND interface specification.

As shown in FIG. 15 , the semiconductor memory device 100 includes, for example, a memory cell array MCA, a command register 1011, an address register 1012, a sequencer 1013, a driver module 1014, a column decoder module 1015, and a sense amplifier module 1016.

The memory cell array MCA includes a plurality of blocks BLK(0) to BLK(n) (n is an integer greater than or equal to 1). Block BLK is a collection of a plurality of memory cells capable of storing data non-volatilely, and is used, for example, as a unit of erasing data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array MCA. Each memory cell is associated with, for example, a bit line and a word line. The detailed structure of the memory cell array MCA will be described below.

The command register 1011 holds the command CMD received by the semiconductor memory device 100 from the memory controller 1002. The command CMD includes, for example, a command for causing the sequencer 1013 to execute a read operation, a write operation, an erase operation, and the like.

The address register 1012 holds the address information ADD received by the semiconductor memory device 100 from the memory controller 1002. The address information ADD includes, for example, a block address BA, a page address PA, and a row address CA. For example, the block address BA, the page address PA, and the row address CA are used to select a block BLK, a word line, and a bit line, respectively.

The sequencer 1013 controls the overall operation of the semiconductor memory device 100. For example, the sequencer 1013 controls the driver module 1014, the column decoder module 1015, and the sense amplifier module 1016 based on the command CMD held by the command register 1011 to perform read operations, write operations, erase operations, and the like.

The driver module 1014 generates a voltage used in a read operation, a write operation, an erase operation, etc. Then, the driver module 1014 applies the generated voltage to a signal line corresponding to the selected word line based on the page address PA held by the address register 1012, for example.

The row decoder module 1015 includes a plurality of row decoders. The row decoder selects a block BLK in the corresponding memory cell array MCA based on the block address BA held by the address register 1012. Then, the row decoder transmits, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

In a write operation, the sense amplifier module 1016 applies a required voltage to each bit line according to the write data DAT received from the memory controller 1002. In addition, in a read operation, the sense amplifier module 1016 determines the data stored in the memory cell based on the voltage of the bit line and transmits the determination result to the memory controller 1002 as the read data DAT.

The semiconductor memory device 100 and the memory controller 1002 described above can also be combined to form a semiconductor device. Examples of such semiconductor devices include memory cards such as Secure Digital (SD) TM cards, or solid state drives (SSD).

Fig. 16 is a circuit diagram showing an example of a circuit structure of a memory cell array MCA. One block BLK is extracted from a plurality of blocks BLK included in the memory cell array MCA. As shown in Fig. 16, the block BLK includes a plurality of string units SU(0) to SU(k) (k is an integer greater than or equal to 1).

Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL (0) to BL (m) (m is an integer greater than 1). Each NAND string NS includes, for example, memory cell transistors MT (0) to MT (15), and selection transistors ST (1) and ST (2). The memory cell transistor MT includes a control gate and a charge storage layer, and retains data in a non-volatile manner. The selection transistors ST (1) and ST (2) are respectively used for selecting the string unit SU during various operations.

In each NAND string NS, memory cell transistors MT (0) to MT (15) are connected in series. The drain of the selection transistor ST (1) is connected to the associated bit line BL, and the source of the selection transistor ST (1) is connected to one end of the memory cell transistors MT (0) to MT (15) connected in series. The drain of the selection transistor ST (2) is connected to the other end of the memory cell transistors MT (0) to MT (15) connected in series. The source of the selection transistor ST (2) is connected to the source line SL.

In the same block BLK, the control gates of the memory cell transistors MT(0) to MT(15) are connected in common to the word lines WL(0) to WL(15). The gates of the select transistors ST(1) in the string units SU(0) to SU(k) are connected in common to the select gates SGD(0) to SGD(k). The gates of the select transistors ST(2) are connected in common to the select gate line SGS.

In the circuit structure of the memory cell array MCA described above, the bit line BL is shared by the NAND strings NS assigned the same row address in each string unit SU. The source line SL is shared, for example, between a plurality of blocks BLK.

A collection of a plurality of memory cell transistors MT connected to a common word line WL in a string unit SU is, for example, referred to as a cell unit CU. For example, the memory capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data". Depending on the number of bits of data stored by the memory cell transistor MT, the cell unit CU may have a memory capacity of more than two pages of data.

Furthermore, the memory cell array MCA included in the semiconductor memory device 100 of the present embodiment is not limited to the circuit structure described above. For example, the number of memory cell transistors MT and the number of selection transistors ST(1) and selection transistors ST(2) included in each NAND string NS can be designed to be any number. The number of string units SU included in each block BLK can be designed to be any number.

Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their modifications are included in the invention described in the scope of the patent application and its equivalents to the same extent as they are included in the scope or subject matter of the invention.

1s, 1m: part 10, 20: laminate 11: electrode film 11a: blocking insulating film 11b: barrier film 12: insulating film 13, 17, 23, 34, 43, 44, 46, CT1, CT2, CT3, CT4, CT5: solder pad 15: interlayer insulating film 18, 19, 28, 29, 41, 45: contact plug 25: interlayer insulating film 30, 60, 70: substrate 31: transistor 32, 37: interlayer connection point 33, 36: wiring 35: interlayer insulating film 40: metal layer 42: Conductor 50: Bonding pad 100: Semiconductor memory device 110: Semiconductor body/semiconductor component 120: Memory film/charge storage component 121: Covering insulation film 122: Charge capture film 123: Tunnel insulation film 130: Core layer 1002: Memory controller 1011: Instruction register 1012: Address register 1013: Sequencer 1014: Driver module 1015: Column decoder module 1016: Sense amplifier module A: Area ADD: Address information B1, B2, B3: Bonding surface BA: Block address BL, BL (1) ~ BL (m): Bit line BLK, BLK (0) ~ BLK (n): Block BSL1, BSL2: Source layer CA: Row address CH1: First array chip/array chip CH2: Second array chip/array chip CH3: CMOS chip CL1: First column/column CL2: Second column/column CMD: Command CU: Cell unit DAT: Write data/Read data F1, F2, F3, F4: Surface MC1: First memory cell/memory cell MC2: Second memory cell MCA: Memory cell array MCA1: first memory cell array/memory cell array MCA2: second memory cell array/memory cell array MH: memory hole MT(0)~MT(15): memory cell transistor NS: NAND string PA: page address SGD(0), SGD(1): select gate SGS: source side select gate ST, SHE: slit ST(1), ST(2): select transistor SL: source line SU(0), SU(1): string unit VY: interlayer connection point WL, WL(0)~WL(15): word line X, Y, Z: direction

FIG. 1 is a cross-sectional view showing a structural example of a semiconductor memory device according to a first embodiment. FIG. 2 is a plan view showing a first memory cell array or a second memory cell array according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a memory cell of a three-dimensional structure according to the first embodiment. FIG. 4 is a schematic cross-sectional view illustrating a memory cell of a three-dimensional structure according to the first embodiment. FIG. 5 is a schematic plan view showing an enlarged area A of FIG. 2. FIG. 6 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. FIG. 7 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment following FIG. 6. FIG8 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor memory device according to the first embodiment following FIG7. FIG9 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor memory device according to the first embodiment following FIG8. FIG10 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor memory device according to the first embodiment following FIG9. FIG11 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor memory device according to the first embodiment following FIG10. FIG12 is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor memory device according to the first embodiment following FIG11. FIG13 is a cross-sectional view showing a structural example of a semiconductor memory device according to the second embodiment. FIG. 14 is a cross-sectional view showing a structural example of a semiconductor memory device according to the third embodiment. FIG. 15 is a block diagram showing a structural example of a semiconductor memory device to which any of the embodiments is applied. FIG. 16 is a circuit diagram showing an example of a circuit structure of a memory cell array.

1m:Part

10, 20: Layered body

11: Electrode film

12: Insulation film

13, 17, 23, 34, 43, 44, 46, CT1, CT2, CT3, CT4: welding pads

15: Interlayer insulation film

18, 19, 29, 41, 45: contact plugs

25: Interlayer insulation film

30: Substrate

31: Transistor

32: Interlayer connection point

33: Wiring

35: Interlayer insulation film

40:Metal layer

42: Conductor

50:Joint pad

100:Semiconductor memory device

B1, B2: fitting surface

BL: Bit Line

BSL1, BSL2: Source layer

CH1: First array chip/array chip

CH2: Second array chip/array chip

CH3: CMOS chip

CL1: First column/column

CL2: Second column/column

MC1: First memory cell/memory cell

MC2: Second memory cell

MCA1: First memory cell array/memory cell array

MCA2: Second memory cell array/memory cell array

ST: Slit

VY: Connection point between layers

X, Y, Z: direction

Claims (10)

A semiconductor memory device comprises: a first chip, comprising a first memory cell array and a first wiring layer, wherein the first memory cell array comprises a plurality of first memory cells, and the first wiring layer is electrically connected to the first memory cell array; and a second chip, comprising a second memory cell array electrically connected to the first wiring layer and comprising a plurality of second memory cells, and bonded to the first chip at a first bonding surface, and the second chip is electrically connected to the first wiring layer. The first chip shares the first wiring layer, the first chip further includes a first pad electrically connected to the first wiring layer, the second chip further includes a second pad electrically connected to the first pad and the second memory cell array, the first pad and the second pad are located at the same position when viewed from the direction of stacking the first chip and the second chip, and the first pad and the second pad are bonded at the first bonding surface. The semiconductor memory device as described in claim 1 further comprises: a third chip, comprising a plurality of transistors and a third pad electrically connected to the plurality of transistors, wherein the third pad of the third chip is bonded to a fourth pad at a second bonding surface, and the fourth pad is electrically connected to the first memory cell array of the first chip. The semiconductor memory device as described in claim 2 further includes: a third chip including a plurality of transistors and a third pad electrically connected to the plurality of transistors, wherein the third pad in the third chip is bonded to a fifth pad at a third bonding surface, and the fifth pad is electrically connected to the second memory cell array of the second chip. A semiconductor memory device as described in claim 1, wherein the first chip further includes a plurality of transistors disposed below the first memory cell array. A semiconductor memory device as described in claim 1, wherein the first wiring layer is shared as a bit line of the first memory cell array and the second memory cell array. A semiconductor memory device as described in claim 5, wherein the first wiring layer is not provided on the second chip. A method for manufacturing a semiconductor memory device includes: forming a first chip including a first memory cell array and a first wiring layer, wherein the first memory cell array includes a plurality of first memory cells, and the first wiring layer is electrically connected to the first memory cell array; forming a second chip including a second memory cell array, wherein the second memory cell array is electrically connected to the first wiring layer and includes a plurality of second memory cells; and bonding the first chip to the second chip in a manner that the first wiring layer is electrically connected to the second memory cell array. A semiconductor memory device comprises: a complementary metal oxide semiconductor circuit; a first memory cell array, arranged on the first direction side of the complementary metal oxide semiconductor circuit, comprising a plurality of first memory cells; a bit line, arranged on the first direction side of the first memory cell array, extending along a second direction intersecting the first direction; and a second memory cell array, arranged on the first direction side of the bit line, comprising a plurality of second memory cells, wherein the first memory cell array has a plurality of first blocks and a first slit, wherein the plurality of first blocks extend along the first direction. The first slit is arranged in the second direction, the first slit is arranged between the plurality of first blocks and extends along a third direction intersecting the first direction and the second direction, the second memory cell array has a plurality of second blocks and a second slit, the plurality of second blocks are arranged along the second direction, the second slit is arranged between the plurality of second blocks and extends along the third direction, and the bit line connects the first memory cell and the complementary metal oxide semiconductor circuit, and the second memory cell and the complementary metal oxide semiconductor circuit in common. The semiconductor memory device as described in claim 8 further comprises a first source disposed between the complementary metal oxide semiconductor circuit and the first memory cell array, and a second source disposed on the first direction side of the second memory cell array. A semiconductor memory device as described in claim 9, wherein the first memory cell array includes a first drain side select transistor connected to the bit line, a first source side select transistor connected to the first source, and the plurality of first memory cells disposed between the first drain side select transistor and the first source side select transistor, and the second memory cell array includes a second drain side select transistor connected to the bit line, a first source side select transistor connected to the first source, and a plurality of first memory cells disposed between the first drain side select transistor and the first source side select transistor. The second source side selection transistor of the second source, and the plurality of second memory cells disposed between the second drain side selection transistor and the second source side selection transistor, the first source side selection transistor, the plurality of first memory cells and the first drain side selection transistor are arranged along the first direction, and the second drain side selection transistor, the plurality of second memory cells and the second source side selection transistor are arranged along the first direction.