TWI870495B - Crystalline oxide etching method and trench forming method, and semiconductor device manufacturing method - Google Patents

Abstract

The crystalline oxide is etched under a pressure of 1 Pa to 10 Pa to form a trench. The trench has at least one arc portion between a bottom surface and a side surface, and a radius of curvature of the arc portion is in a range of 100 nm to 500 nm.

Description

Crystalline oxide etching method and trench forming method, and semiconductor device manufacturing method

The present invention relates to a method for etching a crystalline oxide. Furthermore, the present invention relates to a method for forming a trench in a crystalline oxide semiconductor layer. In particular, the present invention relates to a method for manufacturing a semiconductor device including the method for forming a trench.

Gallium oxide is attracting much attention as a next-generation semiconductor material. Gallium oxide is expected to be a material that has a large band gap and can realize high-voltage and high-current semiconductor devices, and various studies are being conducted with the aim of increasing reverse withstand voltage and further reducing forward rise voltage.

In recent years, semiconductor devices having trenches have been studied. For example, semiconductor devices described in Patent Documents 1 to 3 are disclosed as trench-type semiconductor devices of β-Ga ₂ O _3. Also, for example, semiconductor devices described in Patent Documents 4 and 5 are disclosed as trench-type semiconductor devices of α-Ga ₂ O ₃ .

However, when forming trenches on crystalline oxide semiconductors such as gallium oxide, it is difficult to form a circular arc portion with a curvature radius of 100 nm or more on the bottom surface of the trench, which can be expected to relax the electric field, because it has different etching characteristics from other semiconductor materials. For example, when crystalline gallium oxide is forcibly etched under existing dry etching conditions, the electric field relaxation effect cannot be fully exerted due to the formation of unevenness on the bottom surface of the trench; or the width of the inner part of the trench is wider than the width of the opening of the trench, resulting in problems such as increased on-resistance. [Prior technical literature] [Patent literature]

Patent document 1: Japanese Patent Publication No. 2019-036593 Patent document 2: Japanese Patent Publication No. 2019-079984 Patent document 3: Japanese Patent Publication No. 2019-153645 Patent document 4: WO2016/013554 Patent document 5: WO2019/013136

[Problems to be solved by the present invention]

The object of the present invention is to provide a method for industrially advantageously forming a trench having excellent semiconductor characteristics. [Method for Solving the Problem]

The inventors of the present invention have conducted in-depth research to achieve the above-mentioned purpose, and as a result, found that: by using a specific high-pressure dry etching to form a groove on a crystalline oxide semiconductor layer, the following semiconductor device has been successfully created, which includes: a crystalline oxide semiconductor layer including at least one groove; and at least one electrode electrically connected to the crystalline oxide semiconductor layer, the groove has at least one arc portion between the bottom surface and the side surface, the radius of curvature of the arc portion is in the range of 100nm to 500nm, the angle between the side surface and the first surface of the crystalline oxide semiconductor layer is greater than 90°, and the etching method can solve the above-mentioned existing problems at the same time. In addition, after obtaining the above-mentioned insights, the inventors of the present invention have completed the present invention by further repeated research.

[1] A method for etching a crystalline oxide, comprising at least: a step of etching the crystalline oxide, wherein the etching is performed at a pressure of 1 Pa to 10 Pa. [2] The etching method according to [1], wherein the etching is performed using a plasmatized etching gas. [3] The etching method according to [1] or [2], wherein the pressure is 2 Pa or more. [4] The etching method according to any one of [1] to [3], wherein the etching is performed using at least a halogen. [5] The etching method according to any one of [1] to [4], wherein the etching is performed in an inert gas environment. [6] The etching method according to any one of [1] to [4], wherein the etching is performed in a halogen gas environment. [7] The etching method according to [2], wherein the bias voltage of the plasma of the etching gas is 25 W or more. [8] The etching method according to any one of [1] to [7], wherein the crystalline oxide contains at least gallium. [9] The etching method according to any one of [1] to [8], wherein the crystalline oxide has a corundum structure. [10] The etching method according to any one of [1] to [9], wherein the crystalline oxide is layered. [11] An etching method according to any one of [1] to [10], wherein the crystalline oxide is a crystalline oxide semiconductor. [12] A method for forming a trench in a crystalline oxide semiconductor layer, comprising etching the crystalline oxide semiconductor layer to form at least one trench in the crystalline oxide semiconductor layer, wherein the etching is performed on the crystalline oxide semiconductor layer at a pressure of 1 Pa to 10 Pa. [13] A method for forming a trench according to [12], wherein the etching is performed using a plasmatized etching gas. [14] A method for forming a trench according to [12] or [13], wherein the pressure is 2 Pa or more. [15] The trench forming method according to any one of [12] to [14], wherein the etching is performed using at least a halogen. [16] The trench forming method according to any one of [12] to [15], wherein the etching is performed in an inert gas environment. [17] The trench forming method according to any one of [12] to [15], wherein the etching is performed in a halogen gas environment. [18] The trench forming method according to [13], wherein the bias voltage of the plasma of the etching gas is 25 W or more. [19] The trench forming method according to any one of [12] to [18], wherein the crystalline oxide semiconductor layer contains at least gallium. [20] A method for forming a trench according to any one of [12] to [19], wherein the crystalline oxide semiconductor layer has a corundum structure. [21] A method for manufacturing a semiconductor device, comprising the etching method according to any one of [1] to [11]. [22] A method for manufacturing a semiconductor device, comprising the method for forming a trench according to any one of [12] to [20]. [Effect of the Invention]

The etching method of the present invention can advantageously form trenches with excellent semiconductor characteristics in industry.

The crystalline oxide etching method of the present invention includes at least a step of etching the crystalline oxide, and the feature is that the etching is performed on the crystalline oxide under a pressure of 1 Pa to 10 Pa. In addition, the trench formation method of the crystalline oxide semiconductor layer of the present invention includes a step of etching the crystalline oxide semiconductor layer to form at least one trench in the crystalline oxide semiconductor layer, and the feature is that the etching is performed on the crystalline oxide semiconductor layer under a pressure of 1 Pa to 10 Pa.

In the present invention, various known etchants and etching devices can be appropriately used, and the etching can be dry etching or wet etching, preferably using plasmatized etching gas to perform the etching, and more preferably using an ICP-RIE device. In addition, in the present invention, the pressure is preferably 2Pa or more, and most preferably 5Pa or more. In addition, in the present invention, it is preferred to use at least halogen for etching, and chlorine is more preferably used. In addition, in the present invention, it is preferred to perform the etching in an inert gas environment, and more preferably in an Ar environment. In addition, in the present invention, the etching is preferably performed in a halogen gas environment, and in a chlorine gas environment, because it is easier to form grooves that are more suitable for semiconductor devices such as power devices, and therefore it is more preferred. In the present invention, preferably, the bias of the plasma of the etching gas is 25W or more. In addition, in an embodiment of the present invention, the crystalline oxide preferably contains at least gallium. In addition, in the present invention, the crystalline oxide preferably has a β-gallia structure or a corundum structure, and etching can be performed well even when it has a crystalline structure of a pseudo-stable phase. In addition, in an embodiment of the present invention, the crystalline oxide is preferably layered. In addition, in an embodiment of the present invention, the crystalline oxide is preferably a crystalline oxide semiconductor.

According to the above preferred method, for example, it is easy to produce the following semiconductor device, which includes: a crystalline oxide semiconductor layer including at least one groove; and at least one electrode electrically connected to the crystalline oxide semiconductor layer, wherein the bottom surface and the side surface of the groove have at least one arc portion, the radius of curvature of the arc portion is in the range of 100nm to 500nm, and the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer is greater than 90°.

"Radius of curvature" refers to the radius of the contact circle of the curve of the arc portion in the groove cross section. The "arc portion" is not only a part of a perfect circle, but also includes a part of an ellipse. The whole can be in the shape of an arc, for example, it can also be a part of a shape such as a rounded corner portion of a polygon. That is, the arc portion can be a portion having a curved shape in the groove cross section, as long as it is provided in at least a part between the side surface and the bottom surface. For example, an example of an arc portion is shown in FIG2. The crystalline oxide semiconductor shown in FIG2 has an arc portion 7c having two curvature radii. In FIG2, the curvature radii of R1 and R2 are both in the range of 100nm to 500nm. In the embodiment of the present invention, by setting the curvature radius to such a range, an excellent electric field relaxation effect can be achieved, and as a result, the on-resistance can be reduced. In addition, in the embodiment of the present invention, the trench may have an arc portion in the entire portion between the bottom surface 7b and the side surface 7a of the trench. In addition, in the embodiment of the present invention, the difference between the curvature radius R1 of the first arc portion 7ca between the bottom surface 7b and the first side surface 7aa of the trench 7 and the curvature radius R2 of the second arc portion 7cb between the bottom surface 7b and the second side surface 7ab of the trench is preferably in the range of 0 to 200 nm, more preferably in the range of 0 to 50 nm. In the embodiment of the present invention, it is most preferable that the curvature radius R1 of the first arc portion 7ca is equal to the curvature radius R2 of the second arc portion 7cb.

“The angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer” refers to the angle formed by the side surface 7a of the trench provided on the side of the first surface 3a of the crystalline oxide semiconductor layer 3 in the cross section of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer 3, and in the embodiment of the present invention, is usually about 90° or more. As such “the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer”, for example, the angle represented by θ (θ1, θ2) in FIG. 14 and FIG. 16b is listed. In the present invention, by having such an angle θ1 formed by the first side surface 7aa of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer 3, and an angle θ2 formed by the second side surface 7ab of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer 3, an excellent electric field mitigation effect can be achieved, and the on-resistance can be reduced. In addition, the upper limit of the "angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer" is not limited as long as it does not hinder the purpose of the present invention, and is preferably 150°. In addition, in an embodiment of the present invention, it is preferred that in a cross section of the trench, an angle (θ1) formed by a first side surface 7aa of the trench 7 and a first surface 3a of the crystalline oxide semiconductor layer is equal to an angle (θ2) formed by a second side surface 7ab of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer.

The trench is formed on the crystalline oxide semiconductor layer and is not particularly limited as long as it does not hinder the purpose of the present invention. The depth of the trench is not particularly limited, but in the present invention, the depth of the trench in the trench section is generally greater than 200nm, preferably greater than 500nm, and more preferably greater than 1μm. In addition, the upper limit of the depth of the trench is not particularly limited, and is preferably 100μm, and more preferably 10μm. In addition, the width of the trench in the trench section is not particularly limited, and is generally greater than 200nm, and preferably greater than 500nm. In addition, the upper limit of the width of the trench is not particularly limited, and is preferably 100μm, and more preferably 10μm. According to the trench in this preferred range, a semiconductor device such as a power device can exhibit better semiconductor characteristics. In addition, in the trench cross section, as an embodiment of the present invention, a trench cross section in which the width of the trench narrows toward the bottom surface is cited as a suitable example. According to this suitable example, a good interface can be formed and better electrical characteristics can be obtained, so it is preferred. In addition, it is preferred that the side surface of the trench has a taper shape, and the side surface has a taper angle relative to the first surface of the crystalline oxide semiconductor layer. In addition, the tilt angle refers to the angle formed by the imaginary plane and the side surface (having a tilt) of the trench when the first surface of the crystalline oxide semiconductor layer and the imaginary plane perpendicular to the first surface (the tilt angle is 0° because there is no tilt) are set in the trench cross section. As the tilt angle, for example, the angle represented by θ (θ3, θ4) in Figure 15 can be cited. In the present invention, it is preferred that the tilt angle is greater than 0° and is less than 45°. That is, it is preferred that the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer (for example, θ1, θ2 shown in Figures 14 and 16b) is greater than 90° and less than 135°. This preferred tilt angle enables the formation of a better trench, which results in further reduction of on-resistance.

In addition, the electrode may be a known electrode, for example, it may be any one of a Schottky electrode, an ohmic electrode, a gate electrode, a drain electrode, and a source electrode. The electrode may be a known electrode appropriately set according to the type of the semiconductor device, and examples of the electrode material include D-block metals, etc. In addition, the electrode may be, for example, an electrode called a barrier electrode. The barrier electrode is not particularly limited as long as it forms a Schottky barrier with a predetermined barrier height at the interface of the semiconductor field. The electrode material of the barrier electrode is not particularly limited as long as it can be used as a barrier electrode, and may be a conductive inorganic material or a conductive organic material. In the present invention, the electrode material is preferably a metal. The metal is not particularly limited, but it is appropriate to cite, for example, at least one metal selected from Groups 4 to 11 of the Periodic Table of Elements. As metals of Group 4 of the Periodic Table of Elements, for example, titanium (Ti), zirconium (Zr), and halogen (Hf) can be cited, among which Ti is preferred. As metals of Group 5 of the Periodic Table of Elements, for example, vanadium (V), niobium (Nb), and tungsten (Ta) can be cited. As metals of Group 6 of the Periodic Table of Elements, for example, one or more metals selected from chromium (Cr), molybdenum (Mo), and tungsten (W) can be cited, but in the present invention, Cr is a metal with better semiconductor properties such as switching properties, so it is preferred. Examples of metals of Group 7 of the Periodic Table of Elements include manganese (Mn), tectonic metal (Tc), and rhodium (Re). Examples of metals of Group 8 of the Periodic Table of Elements include iron (Fe), ruthenium (Ru), and niobium (Os). Examples of metals of Group 9 of the Periodic Table of Elements include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals of Group 10 of the Periodic Table of Elements include nickel (Ni), palladium (Pd), and platinum (Pt), among which Pt is preferred. Examples of metals of Group 11 of the Periodic Table of Elements include copper (Cu), silver (Ag), and gold (Au). As a method for forming the barrier electrode, for example, a known method can be listed, and more specifically, a dry method or a wet method can be listed. As a dry method, for example, a known method such as sputtering, vacuum evaporation, and CVD can be listed. As a wet method, for example, screen printing or die coating can be listed.

The crystalline oxide semiconductor layer is not particularly limited as long as a semiconductor region is formed in the semiconductor device. The crystalline oxide semiconductor layer (hereinafter referred to as the "semiconductor region") is not particularly limited as long as it has a semiconductor as a main component. In the present invention, the semiconductor region preferably contains a crystalline oxide semiconductor as a main component, and is more preferably an n-type semiconductor region containing an n-type semiconductor as a main component. The crystalline oxide semiconductor preferably has a β-gallia structure or a corundum structure, and more preferably has a corundum structure. In addition, the semiconductor region preferably contains at least gallium, and more preferably contains a gallium compound as a main component. It is further preferred to have an InAlGaO-based semiconductor as a main component, and most preferably contains α-Ga ₂ O ₃ or a mixed crystal thereof as a main component. In addition, when the crystalline oxide semiconductor is α-Ga ₂ O ₃ , for example, the "main component" means that α-Ga ₂ O ₃ is contained at a ratio of 0.5 or more of the atomic ratio of gallium in the metal element in the semiconductor region. In the present invention, the atomic ratio of gallium in the metal element in the semiconductor region is preferably 0.7 or more, and more preferably 0.8 or more. In addition, the semiconductor region is usually a single-phase region, and as long as it does not hinder the purpose of the present invention, it may further have a second semiconductor region composed of a different semiconductor phase or other equivalents. In addition, the semiconductor region is usually in a film shape and can be a semiconductor film. The thickness of the semiconductor film in the semiconductor region is not particularly limited, and can be less than 1 μm, or can be more than 1 μm, but in the present invention, it is preferably 1 μm to 40 μm, and more preferably 1 μm to 25 μm. The withstand voltage of a crystalline oxide semiconductor layer is improved by, for example, making it thick or reducing the carrier concentration. On the other hand, there is a trade-off problem such as increasing the thickness or reducing the carrier concentration and increasing the on-resistance. According to an embodiment of the present invention, since a crystalline oxide semiconductor layer of gallium oxide _type including α _{- Ga2O3} or β- _Ga2O3 has a groove, the groove includes a circular arc portion with a curvature radius in the range of 100nm to 500nm, and the angle between the side surface of the groove and the first surface of the crystalline oxide semiconductor layer is greater than 90° and less than 135°, the electric field relaxation effect can be fully obtained. According to the embodiment of the present invention, since the electric field relaxation effect can be fully obtained as described above, the thickness of the gallium oxide-based crystalline oxide semiconductor layer (including the drift region) can be reduced (for example, 10 μm or less), and even with such a thickness, a semiconductor device with a high withstand voltage (for example, 3000 V or more) can be realized. In addition, according to the embodiment of the present invention, the thickness of the gallium oxide-based crystalline oxide semiconductor layer (including the drift region) can be further reduced (for example, 2.0 μm or less), and even with such a thickness, a semiconductor device with a high withstand voltage (for example, 600 V or more) can be realized. In addition, in the embodiment of the present invention, the carrier concentration of the gallium oxide-based crystalline oxide semiconductor layer (including the drift region) can be set to 5.0×10 ¹⁶ /cm ³ or more, preferably 3.0×10 ¹⁷ /cm ³ or more. Although the thickness of the crystalline oxide layer or the carrier concentration is appropriately adjusted according to the required withstand voltage, in the embodiment of the present invention, as described above, a high withstand voltage can be achieved even at a thinner thickness than before or a higher carrier concentration than before, so that the on-resistance can be reduced as a result. In addition, the surface area of the semiconductor film is not particularly limited, and can be 1 mm ² or more, or 1 mm ² or less. In addition, the crystalline oxide semiconductor is usually a single crystal, but can also be a polycrystalline. In addition, the semiconductor film may be a single-layer film or a multi-layer film. When the semiconductor film is a multi-layer film, the film thickness of the multi-layer film is preferably 40 μm or less. In addition, when the semiconductor film is a multi-layer film including at least a first semiconductor layer and a second semiconductor layer, and a Schottky electrode is provided on the first semiconductor layer, the multi-layer film is preferably a multi-layer film in which the carrier concentration of the first semiconductor layer is less than the carrier concentration of the second semiconductor layer. In addition, in this case, the second semiconductor layer usually contains dopants, and by adjusting the doping amount, the carrier concentration of the semiconductor layer (including the first semiconductor layer and the second semiconductor layer) can be appropriately set.

The semiconductor film preferably contains dopants. The dopants are not particularly limited and may be known dopants. Examples of the dopants include n-type dopants or p-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium. In the present invention, the dopant is preferably Sn, Ge or Si. The content of the dopant in the composition of the semiconductor film is preferably 0.00001 atomic % or more, further preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. In the present invention, the dopant used in the first semiconductor layer is germanium, silicon, titanium, zirconium, vanadium or niobium, and the dopant used in the second semiconductor layer is tin, because the semiconductor characteristics are further improved without impairing the adhesion, which is preferred.

For example, the semiconductor film is formed using a method such as an atomization CVD method. More specifically, for example, the raw material solution is atomized (atomization step), the obtained atomized droplets (including mist) are transported to a substrate using a carrier gas (transportation step), and then the atomized droplets are thermally reacted in a film forming chamber to stack a semiconductor film containing a crystalline oxide semiconductor as a main component on the substrate (film forming step), thereby appropriately forming a semiconductor film.

(Atomization step) Regarding the atomization step, atomized droplets are generated by atomizing the raw material solution and suspending the atomized droplets. The atomization method of the raw material solution is not particularly limited as long as it can atomize the raw material solution, and can be a known method, but in the present invention, an atomization method using ultrasound is preferred. The initial velocity of the atomized droplets obtained using ultrasound is zero, and the atomized droplets are suspended in the air, so it is preferred. Since the atomized droplets are not blown out like a jet, for example, but the atomized droplets are suspended in the air and can be transported as a gas, there is no damage caused by collision energy, so it is very suitable. The droplet size is not particularly limited and may be a droplet of about several millimeters, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

(Raw material solution) The raw material solution can be atomized and is not particularly limited as long as it contains a raw material capable of forming a semiconductor region. It can be an inorganic material or an organic material. However, in the present invention, the raw material is preferably a metal or a metal compound, and more preferably contains one or more metals selected from gallium, iron, indium, aluminum, vanadium, titanium, chromium, rhodium, nickel, cobalt, zinc, magnesium, calcium, silicon, yttrium, strontium and barium.

In the present invention, as the raw material solution, a solution obtained by dissolving or dispersing the metal in the form of a complex or a salt in an organic solvent or water can be appropriately used. Examples of the complex form include acetylacetone complex, carbonyl complex, amine complex, and hydrogen complex. Examples of the salt form include organic metal salts (e.g., metal acetate salts, metal oxalate salts, metal citrate salts, etc.), metal sulfide salts, metal nitrate salts, metal phosphates, and metal halide salts (e.g., metal chloride salts, metal bromide salts, and metal iodide salts).

In addition, it is preferred to mix an additive such as a hydrohalide and an oxidizing agent in the raw material solution. Examples of the hydrohalide include hydrobromic acid, hydrochloric acid, and hydroiodic acid, but hydrobromic acid or hydroiodic acid is preferred because a better quality film can be obtained. Examples of the oxidizing agent include peroxides such as hydrogen peroxide ( _{H2O2 )} , sodium peroxide ( _{Na2O2 )} , barium peroxide ( _BaO2 ), or _{benzoyl peroxide (C6H5CO ) 2O2 ,} and organic peroxides such as hypochlorite (HClO), perchloric acid, nitric acid, ozone water, peracetic acid, and nitrobenzene.

The raw material solution may also contain dopants. Since the raw material solution contains dopants, doping can be performed well. The dopants are not particularly limited as long as they do not hinder the purpose of the present invention. Examples of the dopants include n-type dopants or p-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium. The concentration of the dopant may generally be about 1×10 ¹⁶ /cm ³ to 1×10 ²² /cm ³ , and the concentration of the dopant may be set to a low concentration of, for example, about 1×10 ¹⁷ /cm ³ or less. According to an embodiment of the present invention, the dopant may be contained at a high concentration of about 1×10 ²⁰ /cm ³ or more. In an embodiment of the present invention, the dopant is preferably contained at a carrier concentration of 1×10 ¹⁷ /cm ³ or more. In addition, as an embodiment of the present invention, the carrier concentration of the gallium oxide-based crystalline oxide semiconductor layer can be set to 1×10 ¹⁷ /cm ³ or more and 3×10 ¹⁷ /cm ³ or less in a semiconductor device having a withstand voltage of 600V.

The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as ethanol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, it is preferred that the solvent contains water, and more preferably water or a mixed solvent of water and ethanol.

(Transportation step) In the transportation step, the atomized droplets are transported into the film forming chamber by a carrier gas. The carrier gas is not particularly limited as long as it does not hinder the purpose of the present invention. For example, suitable examples include inert gases such as oxygen, ozone, nitrogen or argon, or reducing gases such as hydrogen and synthesis gas. In addition, the type of carrier gas can be one or more, and a dilution gas with a reduced flow rate (for example, a 10-fold dilution gas, etc.) can be further used as a second carrier gas. In addition, the carrier gas supply site can be not only one site, but also two or more sites. The flow rate of the carrier gas is not particularly limited, and is preferably 0.01 to 20 L/min, and more preferably 1 to 10 L/min. In the case of dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L/min, more preferably 0.1 to 1 L/min.

(Film-forming step) In the film-forming step, the semiconductor film is formed on the substrate by causing the atomized droplets to undergo a thermal reaction in the film-forming chamber. As for the thermal reaction, it is sufficient to cause the atomized droplets to undergo a reaction using heat, and the reaction conditions are not particularly limited as long as they do not hinder the purpose of the present invention. In this step, the thermal reaction is usually carried out at a temperature above the evaporation temperature of the solvent, but preferably at a temperature not too high (e.g., 1000°C), more preferably at a temperature below 650°C, and most preferably at 300°C to 650°C. In addition, as long as the purpose of the present invention is not hindered, the thermal reaction may be carried out in any of vacuum, oxygen-free environment, reducing gas environment and oxygen environment, but the thermal reaction is preferably carried out in oxygen-free environment or oxygen environment. In addition, the thermal reaction may be carried out under any of atmospheric pressure, pressure and reduced pressure, but in the present invention, the thermal reaction is preferably carried out under atmospheric pressure. In addition, the film thickness can be set by adjusting the film forming time.

(Substrate) The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is not particularly limited as long as it does not hinder the purpose of the present invention, and it can be a known substrate, an organic compound, or an inorganic compound. The shape of the substrate can be any shape, and all shapes are effective, for example, a plate such as a flat plate or a circular plate, a fiber shape, a rod shape, a cylindrical shape, a square column shape, a tube shape, a spiral shape, a sphere shape, a ring shape, etc., but in the embodiment of the present invention, a substrate is preferred. The thickness of the substrate is not particularly limited in the present invention.

The substrate is in the form of a plate and is not particularly limited as long as it serves as a support for the semiconductor film. The substrate may be an insulating substrate, a semiconductor substrate, a metal substrate or a conductive substrate, but it is preferably an insulating substrate and preferably has a metal film on the surface. As the substrate, for example, there can be cited a base substrate containing a substrate material having a corundum structure as a main component, a base substrate containing a substrate material having a β-gallia structure as a main component, a base substrate containing a substrate material having a hexagonal structure as a main component, etc. Here, the "main component" refers to a substrate material having the above-mentioned specific crystal structure, preferably containing more than 50%, more preferably more than 70%, and further preferably more than 90% in atomic ratio relative to all components of the substrate material, and it may also be 100%.

The substrate material is not particularly limited as long as it does not hinder the purpose of the present invention, and may be a known substrate material. As the substrate material having the corundum structure, for example, α-Al ₂ O ₃ (sapphire substrate) or α- Ga ₂ O ₃ may be appropriately cited, and as more suitable examples, a-plane sapphire substrate, m-plane sapphire substrate, r-plane sapphire substrate, c-plane sapphire substrate or α-type gallium oxide substrate (a-plane, m-plane or r-plane) may be cited. As the base substrate having a substrate material having a β-gallia structure as the main component, for example, a β- Ga ₂ O ₃ substrate or a mixed crystal substrate containing Ga ₂ O ₃ and Al ₂ O ₃ with Al ₂ O ₃ being greater than 0 wt % and less than 60 wt % may be cited. In addition, examples of the base substrate mainly composed of a substrate material having a hexagonal structure include a SiC substrate, a ZnO substrate, and a GaN substrate.

In the present invention, annealing treatment may be performed after the film forming step. The annealing treatment temperature is not particularly limited as long as it does not hinder the purpose of the present invention, and is generally 300°C to 650°C, preferably 350°C to 550°C. In addition, the annealing treatment time is generally 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. In addition, the annealing treatment may be performed in any environment as long as it does not hinder the purpose of the present invention, preferably in an oxygen-free environment, and more preferably in a nitrogen environment.

In addition, in the embodiment of the present invention, the semiconductor film may be directly provided on the substrate, or may be provided via other layers such as a buffer layer or a stress relaxation layer. The method for forming each layer is not particularly limited and may be a known method, but in the embodiment of the present invention, the atomization CVD method is preferred.

In addition, as a preferred embodiment, the crystalline oxide semiconductor layer preferably contains at least gallium. In addition, as a preferred embodiment, the crystalline oxide semiconductor layer preferably has a corundum structure. In the embodiments of the present invention, the semiconductor film can be used as the semiconductor region in a semiconductor device after using a known method such as peeling the semiconductor film from the substrate, or can be directly used as the semiconductor region in a semiconductor device. In addition, as a preferred embodiment, the crystalline oxide semiconductor layer preferably includes two or more of the trenches. In addition, as a preferred embodiment, the width of the trench is preferably less than 2 μm, and the crystalline oxide semiconductor layer preferably includes four or more of the trenches. The plurality of grooves are spaced apart from each other and arranged on the first surface side of the crystalline oxide semiconductor. According to this preferred embodiment, a semiconductor device that is more suitable as a power device can obtain better semiconductor characteristics. In addition, even the miniaturization of the surface-oriented semiconductor device becomes more effective. In addition, the crystalline oxide semiconductor layer has at least one arc portion between the bottom surface and the side surface of the groove, and the curvature radius of the arc portion is in the range of 100nm to 500nm. However, in the case where the crystalline oxide semiconductor layer has two or more arc portions, it is sufficient that the curvature radius of at least one arc portion is in the range of 100nm to 500nm. In the present invention, when the crystalline oxide semiconductor layer has two or more arc portions, the curvature radius of the two or more arc portions is preferably in the range of 100nm to 500nm, and the curvature radius of all the arc portions is more preferably in the range of 100nm to 500nm.

Hereinafter, embodiments of a semiconductor device that can be easily manufactured using the present invention will be described in more detail using the accompanying drawings, but the present invention is not limited to these embodiments.

In an embodiment of the present invention, at least one trench 7 is provided on the first surface 3a side of the crystalline oxide semiconductor layer 3 (also referred to as the semiconductor region). The trench 7 includes a bottom surface, a side surface, and at least one arc portion between the bottom surface and the side surface. In addition, the crystalline oxide semiconductor layer 3 is electrically connected to an electrode. The embodiment of the present invention can be applied to a semiconductor device including a trench. For example, FIG. 1 shows a junction barrier Schottky diode (JBS) as a semiconductor device of an embodiment of the present invention. The semiconductor device of FIG1 includes: a semiconductor region 3; a barrier electrode 2, which is disposed on the semiconductor region and can form a Schottky barrier between the barrier electrode 2 and the semiconductor region; and a barrier height region, which is disposed between the barrier electrode 2 and the semiconductor region 3 and can form a Schottky barrier between the barrier height region and the semiconductor region 3, wherein the barrier height of the Schottky barrier is greater than the barrier height of the Schottky barrier of the barrier electrode 2. In addition, the barrier height adjustment region 1 is buried in a trench 7, which is disposed on the first surface 3a side of the semiconductor region 3. In an embodiment of the present invention, it is preferred that a plurality of trenches 7 and a plurality of barrier height adjustment regions 1 arranged in the plurality of trenches 7 are arranged at fixed intervals, and it is more preferred that the barrier height adjustment regions are respectively arranged between the two ends of the barrier electrode and the semiconductor region. In addition, FIG. 1 is a cross-sectional view of a JBS, and the plurality of barrier height adjustment regions 1 are connected in, for example, a plan view. According to this preferred method, the JBS is constructed in a manner that has better thermal stability and adhesion, further reduces leakage current, and has better semiconductor characteristics such as withstand voltage. In addition, the semiconductor device of FIG. 1 has an ohmic electrode 4 on the second surface 3b side of the semiconductor region 3. The semiconductor device of FIG. 1 has an arc portion 7c between the bottom surface 7a and the side surface 7b of the trench 7. The radius of curvature of the arc portion is in the range of 100 nm to 500 nm, and the electric field relaxation effect is excellent, resulting in reduced on-resistance.

The method for forming each layer of the semiconductor device of FIG1 is not particularly limited as long as it does not hinder the purpose of the present invention, and may be a known method. For example, the following method may be cited: that is, after forming a film by vacuum evaporation, CVD, sputtering, or various coating techniques, directly patterning is performed by photolithography and using a patterning method or printing technology.

FIG9 shows an example of a Schottky barrier diode (SBD) according to an embodiment of the present invention. The SBD in FIG9 includes an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, a dielectric layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. In addition, the SBD in FIG9 has a trench structure having the arc portion, and a p-type semiconductor layer 102 is buried in the trench 7.

The materials of the Schottky electrode and the ohmic electrode can also be well-known electrode materials. Examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or their alloys, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, tin indium oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures thereof, etc.

For example, the Schottky electrode and the ohmic electrode can be formed by a known method such as vacuum evaporation or sputtering. More specifically, when forming a Schottky electrode, for example, a layer composed of Mo and a layer composed of Al are stacked, and the layer composed of Mo and the layer composed of Al are patterned using photolithography to form the Schottky electrode.

When a reverse bias is applied to the SBD of FIG. 9 , the depletion layer (not shown) is well expanded into the n-type semiconductor layer 101a, which is a crystalline oxide semiconductor layer, by the stress relaxation effect of the arc portion of the groove 7, thereby becoming a high-voltage SBD. In addition, when a forward bias is applied, electrons flow from the ohmic electrode 105b located on the second side of the crystalline oxide semiconductor layer opposite to the first side to the Schottky electrode 105a located on the first side of the crystalline oxide semiconductor layer. The SBD using the semiconductor structure described above is excellent when used for high voltage/high current, has a fast switching speed, and has excellent voltage resistance and reliability.

The material of the dielectric layer 104 may be, for example, GaO, AlGaO, InAlGaO, AlInZnGaO ₄ , AlN, Hf ₂ O ₃ , SiN, SiON, Al ₂ O ₃ , MgO, GdO, SiO ₂ or Si ₃ N _4. By using such an insulator for the insulator layer, the function of semiconductor characteristics at the interface can be well developed. The dielectric layer 104 is provided between the n-type semiconductor layer 101a and the Schottky electrode 105a. For example, the insulator layer can be formed by a known method such as a sputtering method, a vacuum evaporation method or a CVD method.

FIG10 shows an example of an implementation form of a trench-type Schottky barrier diode (SBD), which comprises: an n-type semiconductor layer 101a, which is a crystalline oxide semiconductor layer and has two or more trenches 7 arranged on the first side of the n-type semiconductor layer 101a; an n+ type semiconductor layer 101b; a dielectric layer 104; a Schottky electrode 105a and an ohmic electrode 105b. The trench-type SBD of FIG10 has a trench structure having the arc portion. According to this trench-type SBD, the leakage current can be greatly reduced while maintaining a higher withstand voltage, and as a result, a significant reduction in on-resistance can be achieved.

FIG11 shows an example of an implementation of a junction barrier Schottky diode (JBS) having an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, a p-type semiconductor layer 102, a dielectric layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. The JBS of FIG11 has a trench 7 having the arc portion, and the p-type semiconductor layer 102 is buried in this trench structure. According to this JBS, while maintaining a higher withstand voltage than the trench type SBD of FIG10, the leakage current can be greatly reduced, and as a result, a further reduction in on-resistance can be achieved.

An example of an implementation in which the semiconductor device is a MOSFET is shown in FIG12. The MOSFET of FIG12 is a trench MOSFET and includes: an n-type semiconductor layer 131a, which is a crystalline oxide semiconductor layer and includes a trench 7; n+ type semiconductor layers 131b and 131c; a gate insulating film 134; a gate electrode 135a; a source electrode 135b and a drain electrode 135c.

An n+ type semiconductor layer 131b having a thickness of, for example, 100nm to 100μm is formed on the drain electrode 135c, and an n- type semiconductor layer 131a having a thickness of, for example, 100nm to 100μm is formed on the n+ type semiconductor layer 131b. Furthermore, an n+ type semiconductor layer 131c is formed on the n- type semiconductor layer 131a, and a source electrode 135b is formed on the n+ type semiconductor layer 131c.

In addition, a plurality of trenches 7 are formed as grooves penetrating the n+ type semiconductor layer 131c and reaching the middle of the n+ type semiconductor layer 131a. The trenches 7 have the arc portions between the bottom and the side surfaces of the trenches 7. In the trenches 7, a gate electrode 135a is formed by embedding a gate insulating film 134 having a thickness of, for example, 10 nm to 1 μm.

In the on state of the MOSFET of FIG12, if a voltage is applied between the source electrode 135b and the drain electrode 135c, and a positive voltage relative to the source electrode 135b is applied to the gate electrode 135a, a channel layer is formed on the side surface of the n-type semiconductor layer 131a, and electrons are injected into the n-type semiconductor layer to turn on. Since the voltage of the gate electrode is set to 0V, it is impossible to form a channel layer, and the off state becomes a state where the n-type semiconductor layer is filled with a depletion layer, and is in a closed state.

When manufacturing the MOSFET of Fig. 12, a known method can be appropriately used. For example, an etching mask is set on predetermined regions of the n-type semiconductor layer 131a and the n+ type semiconductor layer 131c, and etching is performed by the above-mentioned preferred high-pressure dry etching method to form the arc portion and the groove 7 having a depth from the surface of the n+ type semiconductor layer 131c to the middle of the n-type semiconductor layer 131a. Next, after forming a gate insulating film 134 of, for example, 50 nm to 1 μm thick on the side and bottom of the trench 7 by using a known method such as thermal oxidation, vacuum evaporation, sputtering, or CVD, a gate electrode material such as polysilicon is formed in the trench 7 to a thickness less than that of the n-type semiconductor layer by using a known method such as CVD, vacuum evaporation, or sputtering. Furthermore, by using a known method such as vacuum evaporation, sputtering, or CVD, a source electrode 135b is formed on the n+ type semiconductor layer 131c, and a drain electrode 135c is formed on the n+ type semiconductor layer 131b, thereby manufacturing a power MOSFET. In addition, the electrode materials of the source electrode and the drain electrode can also be respectively known electrode materials. As the electrode materials, for example, metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or their alloys, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures thereof, etc. can be listed.

The MOSFET thus obtained has a better withstand voltage than the existing trench MOSFET. In addition, FIG. 12 shows an example of a trench-type vertical MOSFET, but the present invention is not limited thereto and can be applied to various forms of trench MOSFET. For example, the series resistance can be reduced by deepening the depth of the trench 7 in FIG. 12 to a depth that reaches the bottom surface of the n-type semiconductor layer 131a. In addition, an example of another trench MOSFET is shown in FIG. 13.

FIG13 shows an example of an implementation of a metal oxide semiconductor field effect transistor (MOSFET) having an n-type semiconductor layer 131a, a first n+ type semiconductor layer 131b, a second n+ type semiconductor layer 131c, a p-type semiconductor layer 132, a p+ type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. In addition, the p+ type semiconductor layer 132a may be a p-type semiconductor layer, and may be the same as the p-type semiconductor layer 132.

The semiconductor device is preferably a power device. In addition, as an embodiment, the semiconductor device is preferably a vertical device. The semiconductor device may be a diode or a transistor (e.g., MESFET, etc.), but a diode is preferred, and a junction barrier Schottky diode (JBS) is more preferred.

Regarding the semiconductor device, on the basis of the above matters, a known method is further used to be suitable for use as a power module, inverter or converter, and can be appropriately used in, for example, a semiconductor system using a power supply device. The power supply device can be made from or as the semiconductor device by connecting it with a wiring pattern using a known method. FIG3 uses a plurality of the power supply devices 171, 172 and a control circuit 173 to form a power supply system 170. As shown in FIG4, the power supply system can combine an electronic circuit 181 and a power supply system 182 and be used in a system device 180. In addition, an example of a power supply circuit diagram of the power supply device is shown in FIG5. FIG5 shows a power supply circuit of a power supply device composed of a power circuit and a control circuit. After the DC voltage is converted to AC by high-frequency wave through an inverter 192 (composed of MOSFETA to D), insulation and voltage conversion are performed by a transformer 193, and after rectification by a rectifier MOSFET 194 (A to B'), smoothing is achieved by a DCL 195 (smoothing coils L1 and L2), and a DC voltage is output. At this time, the output voltage is compared with the reference voltage by a voltage comparator 197, and the inverter 192 and the rectifier MOSFET 194 are controlled by a PWM control circuit 196 in such a way that the desired output voltage is obtained. [Example]

(Example 1) 1. Formation of semiconductor layer 1-1. Film forming device The atomization CVD device 19 used in the example will be described with reference to FIG. 6 . The film forming device 19 of FIG. 6 includes: a carrier gas source 22a for supplying a carrier gas; a flow regulating valve 23a for regulating the flow rate of the carrier gas sent from the carrier gas source 22a; a carrier gas (dilution) source 22b for supplying a carrier gas (dilution); a flow regulating valve 23b for regulating the flow rate of the carrier gas (dilution) sent from the carrier gas (dilution) source 22b; an atomization source 24 for storing a raw material solution 24a; a container 25 for containing water 25a; an ultrasonic oscillator 26 mounted on the bottom surface of the container 25; a film forming chamber 30; a quartz supply pipe 27 for connecting between the atomization source 24 and the film forming chamber 30; and a hot plate (heater) 28 disposed in the film forming chamber. The substrate 20 is disposed on the hot plate 28.

1-2. Preparation of raw material solution A 0.1 M aqueous solution of gallium bromide containing 10% hydrobromic acid by volume was prepared as a raw material solution.

1-3. Preparation for film formation The raw material solution 24a obtained in 1-2. above is placed in the atomization source 24. Next, a sapphire substrate is placed on a hot plate 28 as a substrate 20, and the temperature in the film forming chamber 30 is raised to 630°C by operating the hot plate 28. Next, the flow regulating valves 23a and 23b are opened, and the carrier gas is supplied from the carrier gas supply mechanisms 22a and 22b as the carrier gas source into the film forming chamber 30, and after the environment of the film forming chamber 30 is fully replaced by the carrier gas, the flow rate of the carrier gas is adjusted to 1L/min, and the flow rate of the carrier gas (diluted) is adjusted to 2L/min. In addition, nitrogen is used as the carrier gas.

1-4. Formation of semiconductor film Next, the ultrasonic oscillator 26 is vibrated at 2.4 MHz, and the vibration is transmitted to the raw material solution 24a through the water 25a, thereby atomizing the raw material solution 24a to generate mist. The mist is introduced into the film forming chamber 30 through the supercarrier gas, and the mist is reacted in the film forming chamber 30 at atmospheric pressure and 630°C, thereby forming a semiconductor film on the substrate 20. In addition, the film thickness is 4.1μm, and the film forming time is 105 minutes.

1-5. Evaluation The phase of the film obtained in the above 1-4 was analyzed using an XRD diffraction apparatus. As a result, the obtained film was found to be α-Ga ₂ O ₃ .

2. Etching Under the conditions of Table 1 below, an ICP-RIE device was used to form a groove on the semiconductor film. The grooves of the embodiments all have a circular arc portion, and the radius of curvature of the circular arc portion is within the range of 100 nm or more and 500 nm or less. A cross-sectional photograph of the groove formed as Embodiment 1 is shown in FIG7. As shown in FIG7, the radius of curvature of Embodiment 1 is 140 nm for R1 (left side) and 160 nm for R2 (right side). In addition, the side surface of the groove has a tilt angle of 60°. As can be clearly seen from FIG7, a good groove is formed. In addition, the inclination of forming such a good groove can be seen in the range of 1 Pa to 10 Pa, especially in the range of 2 Pa to 10 Pa, other than the pressure of 5 Pa.

[Table 1] Embodiment 1 Embodiment 2 Comparison Example 1 Comparison Example 2 Cl ₂ (sccm) 50 0 50 0 Ar (sccm) 0 50 0 50 BCl ₃ (sccm) 20 20 20 20 Pressure (Pa) 5 5 0.5 11 ICP input power (W) 100 1000 100 1000 Substrate bias power (bias) (W) 52 150 50 200

(Example 2) Except that etching was performed under the conditions shown in Table 1, a groove was formed in the same manner as in Example 1. A cross-sectional photograph of the obtained groove is shown in FIG8. As shown in FIG8, the radius of curvature of the arc portion of the groove is 125 nm for R1 (left side) and 298 nm for R2 (right side). As can be clearly seen from FIG8, a groove having a high-quality arc portion was formed.

[Table 2] Embodiment 3 Cl ₂ (sccm) 0 Ar (sccm) 20 BCl ₃ (sccm) 70 Pressure (Pa) 10 ICP input power (W) 500 Substrate bias power (bias) (W) 25

(Example 3) A trench is formed on a semiconductor film (referred to as a crystalline oxide semiconductor layer) in the same manner as in Example 1, except that etching is performed under the conditions shown in Table 2. A cross-sectional photograph of the obtained trench is shown in FIG16a. In addition, FIG16b shows an explanatory diagram using the same cross-sectional photograph. The radius of curvature R1 (left side) of the first arc portion 7ca of the trench 7 is 220 nm, and the radius of curvature R2 (right side) of the second arc portion 7cb is also 220 nm. Although a plurality of trenches 7 are formed on the crystalline oxide semiconductor layer 3, any trench 7 is formed with a first arc portion 7ca and a second arc portion 7cb having the same radius of curvature. The width of the trench 7 becomes narrower toward the bottom surface. In the cross section of the trench, the angle (θ1 shown in FIG. 16b) formed by the side surface 7a (first side surface 7aa) of the trench and the first surface 3a of the crystalline oxide semiconductor layer 3 is greater than 90° and less than 135°, and the angle (θ2 shown in FIG. 16b) formed by the side surface 7a (second side surface 7ab) of the trench and the first surface 3a of the crystalline oxide semiconductor layer 3 is greater than 90° and less than 135°. In addition, _SiO2 shown in FIG. 16b is a mask provided on the crystalline oxide semiconductor layer 3 for etching to form the trench, and is therefore eventually removed. In addition, the flow rate of BCl ₃ was changed to obtain a crystalline oxide semiconductor layer. The results showed that by setting the flow rate of BCl ₃ in the range of 50 sccm to 100 sccm, a groove with a better arc portion could be obtained.

According to the embodiments 1 to 3 of the present invention, in the trench cross section, the trench has an arc portion with a curvature radius in the range of 100 nm to 500 nm, and the angle formed by the side surface of the trench and the first surface of the crystalline oxide semiconductor layer is within the range of greater than 90° and less than 135°, and the electric field relaxation effect can be fully obtained. As a result, the on-resistance of the semiconductor device having the gallium oxide-based crystalline oxide semiconductor layer can be reduced. In addition, according to the embodiment 3, since the trench having an arc portion with a left-right symmetrical curvature radius can be formed on the gallium oxide-based crystalline oxide semiconductor layer, it can be expected that the on-resistance of the semiconductor device can be further reduced.

(Comparative Example 1) Except that etching was performed under the conditions shown in Table 1, a groove was formed in the same manner as in Example 1. The bottom surface of the obtained groove was convex, and there was also a corner portion between the bottom surface and the side surface, etc., forming a low-quality groove.

(Comparative Example 2) Except that etching was performed under the conditions shown in Table 1, a groove was formed in the same manner as in Example 1. The side surface of the obtained groove was dug out in an inverse tapered shape, resulting in the width of the inner part of the groove being wider than the width of the opening of the groove. In addition, although a circular arc portion was formed between the bottom surface and the side surface, the circular arc portion bulged a lot, and the radius of curvature became more than 1μm, etc., resulting in a non-quality groove. [Industrial Applicability]

The method of the present invention can be used in all fields of semiconductors (e.g., compound semiconductor electronic devices, etc.), electronic components and electrical machine components, optical/electronic photography related devices and industrial components, etc., and is particularly useful for manufacturing power devices.

1: Barrier height adjustment area 2: Barrier electrode 3: Crystalline oxide semiconductor layer (semiconductor area) 3a: First surface 3b: Second surface 4: Ohmic electrode 7: Trench 7a: Side surface of trench 7aa: First side surface of trench 7ab: Second side surface of trench 7b: Bottom surface of trench 7c: Arc portion of trench 7ca: First arc portion of the groove 7cb: Second arc portion of the groove 19: Atomization CVD device (film forming device) 20: Substrate 22a: Carrier gas supply mechanism 22b: Carrier gas (dilution) supply mechanism 23a: Carrier gas flow regulating valve 23b: Carrier gas (dilution) flow regulating valve 24: Atomization source 24a: Raw material solution 25: Container 25a: Water 26: Ultrasonic oscillator 27: Supply pipe 28: Heater 29: Exhaust port 30: Film forming chamber 101a: n-type semiconductor layer 101b: n+ type semiconductor layer 102: p-type semiconductor layer 103: Metal layer 104: Dielectric layer 105a: Schottky Electrode 105b: Ohmic electrode 131a: n-type semiconductor layer 131b: First n+ type semiconductor layer 131c: Second n+ type semiconductor layer 132: p-type semiconductor layer 132a: p+ type semiconductor layer 134: Gate insulating film 135a: Gate electrode 135b: Source electrode 135c: Drain electrode

FIG. 1 is a diagram schematically showing a type of junction barrier Schottky diode (JBS) as an example of an embodiment of a semiconductor device produced by the present invention. FIG. 2 is a diagram for explaining the radius of curvature of an arc portion in an embodiment of a semiconductor device produced by the present invention. FIG. 3 is a diagram schematically showing an example of a power supply system. FIG. 4 is a diagram schematically showing an example of a system device. FIG. 5 is a diagram schematically showing an example of a power supply circuit diagram of a power supply device. FIG. 6 is a schematic structural diagram of a film forming device (atomized CVD (chemical vapor deposition) device) used in an embodiment. FIG. 7 is a cross-sectional photograph of a trench in Embodiment 1. FIG. 8 is a cross-sectional photograph of a trench in Embodiment 2. FIG. 9 is a diagram schematically showing a type of Schottky barrier diode (SBD) as an example of an embodiment of the semiconductor device manufactured by the present invention. FIG. 10 is a diagram schematically showing a type of trench MOS Schottky barrier diode (SBD) as an example of an embodiment of the semiconductor device manufactured by the present invention. FIG. 11 is a diagram schematically showing a type of junction barrier Schottky diode (JBS) as an example of an embodiment of the semiconductor device manufactured by the present invention. FIG. 12 is a diagram schematically showing a type of MOSFET as an example of an embodiment of the semiconductor device manufactured by the present invention. FIG. 13 is a diagram schematically showing a type of MOSFET as an example of an embodiment of the semiconductor device manufactured by the present invention. FIG. 14 is a diagram for explaining the angle between the side surface of the trench and the first surface of the crystalline oxide semiconductor layer in the embodiment of the semiconductor device manufactured by the present invention. FIG. 15 is a diagram for explaining the tilt angle when the side surface of the trench in the embodiment of the semiconductor device manufactured by the present invention is tilted. FIG. 16a is a diagram showing a cross-sectional photograph of the trench of Example 3. FIG. 16b is an explanatory diagram showing the structure of the trench of Example 3.

Claims (20)

A method for etching a crystalline oxide includes at least: a step of etching the crystalline oxide, wherein the etching is performed on the crystalline oxide under a pressure of 1 Pa to 10 Pa, and the crystalline oxide has a corundum structure. According to the etching method described in claim 1, the etching is performed using a plasma-formed etching gas. According to the etching method described in claim 1, the pressure is greater than 2 Pa. An etching method according to any one of claims 1 to 3, wherein the etching is performed using at least a halogen. The etching method according to any one of claims 1 to 3, wherein the etching is performed in an inert gas environment. The etching method according to any one of claims 1 to 3, wherein the etching is performed in a halogen gas environment. According to the etching method described in claim 2, the bias voltage of the plasma of the etching gas is greater than 25W. An etching method according to any one of claims 1 to 3, wherein the crystalline oxide contains at least gallium. An etching method according to any one of claims 1 to 3, wherein the crystalline oxide is layered. An etching method according to any one of claims 1 to 3, wherein the crystalline oxide is a crystalline oxide semiconductor. A method for forming a trench in a crystalline oxide semiconductor layer includes etching the crystalline oxide semiconductor layer to form at least one trench in the crystalline oxide semiconductor layer, wherein the etching is performed on the crystalline oxide semiconductor layer under a pressure of 1 Pa to 10 Pa, and the etching is performed using a plasmatized etching gas. A method for forming a trench in a crystalline oxide semiconductor layer comprises the step of etching the crystalline oxide semiconductor layer to form at least one trench in the crystalline oxide semiconductor layer, wherein the etching is performed on the crystalline oxide semiconductor layer under a pressure of 2 Pa to 10 Pa. A method for forming a trench in a crystalline oxide semiconductor layer includes etching the crystalline oxide semiconductor layer to form at least one trench in the crystalline oxide semiconductor layer, wherein the etching is performed on the crystalline oxide semiconductor layer under a pressure of 1 Pa to 10 Pa, and at least halogen is used for the etching. A method for forming a trench in a crystalline oxide semiconductor layer includes etching the crystalline oxide semiconductor layer to form at least one trench in the crystalline oxide semiconductor layer, wherein the etching is performed on the crystalline oxide semiconductor layer under a pressure of 1 Pa to 10 Pa, and in an inert gas environment. A method for forming a trench in a crystalline oxide semiconductor layer comprises the step of etching the crystalline oxide semiconductor layer to form at least one trench in the crystalline oxide semiconductor layer, wherein the etching is performed on the crystalline oxide semiconductor layer under a pressure of 1 Pa to 10 Pa, and in a halogen gas environment. According to the trench forming method described in claim 11, the bias voltage of the plasma of the etching gas is greater than 25W. A method for forming a trench in a crystalline oxide semiconductor layer comprises the step of etching the crystalline oxide semiconductor layer to form at least one trench in the crystalline oxide semiconductor layer, wherein the etching is performed on the crystalline oxide semiconductor layer under a pressure of 1 Pa to 10 Pa, and the crystalline oxide semiconductor layer contains at least gallium. A method for forming a trench in a crystalline oxide semiconductor layer comprises the step of etching the crystalline oxide semiconductor layer to form at least one trench in the crystalline oxide semiconductor layer, wherein the etching is performed on the crystalline oxide semiconductor layer under a pressure of 1 Pa to 10 Pa, and the crystalline oxide semiconductor layer has a corundum structure. A method for manufacturing a semiconductor device, comprising an etching method according to any one of claims 1 to 10. A method for manufacturing a semiconductor device, comprising a trench forming method according to any one of claims 12 to 18.