TWI870148B - Three dimensional integrated device and method for forming the same - Google Patents

Abstract

A three-dimensional integrated device includes a stacked body having a first surface and a second surface, a cooling groove formed on the first surface and extending along the first surface of the stacked body, and a supporting substrate bonded to the first surface. The supporting substrate has a first hole and a second hole respectively exposing the two terminals of the cooling groove. The first hole and the second hole are respectively the inlet and outlet through which a cooling liquid flows into and out from the cooling groove.

Description

Three-dimensional integrated component and manufacturing method thereof

The present invention relates to the field of semiconductor technology, and more particularly to a three-dimensional integrated component and a manufacturing method thereof.

As the demand for big data processing capabilities of integrated circuits continues to grow, Moore's Law is approaching its limit, and the miniaturization of component sizes is becoming increasingly difficult. Three-dimensional stacking technology has become an effective solution to continue to improve PPAC (performance, power, area, cost) in the post-Moore era.

For three-dimensional integrated devices, as the number of internal stacked layers increases, the heat generated during operation will increase dramatically. If the heat cannot be discharged in time, the heat accumulation will seriously affect the working performance of the device.

In the prior art, when manufacturing a three-dimensional integrated component, a plurality of chips are first stacked and the formed stacked structure is bonded to a circuit substrate. Then, a heat conducting layer is formed on the surface of the stacked structure away from the circuit substrate, and a heat dissipating metal sheet is covered on the heat conducting layer. The purpose is to transfer the heat generated inside the component to the metal heat sink through the heat conducting layer, and then dissipate the heat through heat exchange between the metal heat sink and the air. Heat can be dissipated naturally by exchanging heat between the metal heat sink and the air, or forced air cooling can be achieved by accelerating the air flow. However, whether it is natural heat dissipation or forced air cooling, due to the low thermal conductivity and limited heat dissipation capacity, it may still cause heat accumulation inside the three-dimensional integrated component, which is not conducive to the normal operation of the three-dimensional integrated component.

In order to improve the heat dissipation capability of a three-dimensional integrated component, the present invention provides a three-dimensional integrated component and a method for manufacturing the three-dimensional integrated component.

On one hand, the present invention provides a three-dimensional integrated component, the three-dimensional integrated component includes a stacked body, formed by stacking at least two wafer layers, wherein the stacked body has a first surface and a second surface opposite to each other, the first surface is formed with a heat-conducting groove, and the length extension direction of the heat-conducting groove is parallel to the first surface. A carrier plate is keyed to the first surface of the stacked body, the carrier plate has a first through hole and a second through hole, the first through hole exposes a first end of the heat-conducting groove, and the second through hole exposes a second end of the heat-conducting groove, wherein the first through hole is an inlet of a heat dissipation liquid, and the second through hole is an outlet of the heat dissipation liquid.

In some embodiments, an opening of the first through hole relative to the stack is not higher than the surface of the carrier plate around the first through hole; an opening of the second through hole relative to the stack is not higher than the surface of the carrier plate around the second through hole.

In some embodiments, a solder bump is formed on the second surface, and the solder bump is electrically connected to a circuit inside the stack.

In some embodiments, the three-dimensional integrated component further includes a circuit substrate having pads, wherein the stack is bonded to the circuit substrate by soldering the solder bumps to the corresponding pads.

In some embodiments, the stack includes a first wafer layer including a first substrate and an electronic component formed on a front surface of the first substrate, wherein the thermal conductive trench is formed on a back surface of the first substrate opposite to the front surface.

In some embodiments, the electronic components include logic components and/or memory components.

In some embodiments, the thermally conductive trench has one or more channel paths between the first end and the second end.

In some embodiments, in the stack, each layer of chips includes at least one chip.

Another aspect of the present invention provides a method for manufacturing a three-dimensional integrated element, the steps of the manufacturing method comprising:

stacking at least two wafer layers to form a stacked body, wherein the stacked body has a first surface and a second surface opposite to each other;

A heat conducting groove is formed on the first surface, wherein the length extension direction of the heat conducting groove is parallel to the first surface, and the heat conducting groove has a first end and a second end in the length extension direction;

Forming a first groove and a second groove on a surface of a carrier plate;

Keying the stacking body to the supporting plate, wherein the first groove is opposite to the first end of the heat conducting groove, and the second groove is opposite to the second end of the heat conducting groove;

The bottoms of the first groove and the second groove are removed to form a first through hole in the first groove and a second through hole in the second groove, wherein the first through hole exposes the first end of the heat conductive groove and the second through hole exposes the second end of the heat conductive groove, wherein the first through hole is an inlet of a heat dissipation liquid and the second through hole is an outlet of the heat dissipation liquid.

In some embodiments, the bottoms of the first groove and the second groove may be removed by thinning or etching the carrier plate.

In some embodiments, before removing the bottom of the first groove and the second groove, the manufacturing method further includes: forming a solder bump on the second surface, the solder bump being electrically connected to a circuit inside the stack; and joining the stack to a circuit substrate, the circuit substrate having a solder pad, wherein the solder bump is soldered to the corresponding solder pad.

The three-dimensional integrated component provided by the present invention includes a stack formed by stacking at least two layers of chips and a carrier plate bonded to the first surface of the stack, wherein the first surface of the stack is formed with a heat-conducting groove, and the carrier plate has a first through hole and a second through hole, wherein the first through hole exposes the first end of the heat-conducting groove, and the second through hole exposes the second end of the heat-conducting groove, and the first through hole is the inlet of the heat-dissipating liquid, and the second through hole is the outlet of the heat-dissipating liquid. Compared with the heat dissipation method of attaching a metal heat sink adopted in the prior art, the three-dimensional integrated component can use the flow of the heat-dissipating liquid in the heat-conducting groove to carry away the heat for heat dissipation, thereby achieving the purpose of cooling the component, with higher heat conduction efficiency and stronger heat dissipation capacity, which can reduce the risk of heat accumulation inside the three-dimensional integrated component and help improve the performance of the three-dimensional integrated component.

The manufacturing method of the three-dimensional integrated element provided by the present invention is of the same concept as the three-dimensional integrated element of the present invention and has the same or similar advantages.

The following is a further detailed description of the three-dimensional integrated element and its manufacturing method of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be understood that the drawings in the specification are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented in this article is not necessarily the only order to perform these steps. Some of the steps described may be omitted and/or some other steps not described in this article may be added to the method. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the structure in the figures is inverted or oriented in another manner (eg, rotated), the exemplary term "above" may also include "below" and other orientations.

The following first describes the method for manufacturing the three-dimensional integrated element of the present invention through an embodiment.

1 and 2 , the method for manufacturing a three-dimensional integrated device of the present invention includes performing step S1: stacking at least two layers of wafers to form a stack 100, wherein the stack 100 has a first surface 100a and a second surface 100b opposite to each other.

The manufacturing method of the three-dimensional integrated element of the embodiment of the present invention can utilize the three-dimensional stacking technology to stack at least two layers of chips to form the stack 100. In the three-dimensional stacking technology, multiple active components, passive components, MEMS components or discrete chips (such as optoelectronic chips, biological chips, memory chips, logic chips, computing chips) with different functions or prepared by different processes are assembled together in three-dimensional directions (such as the X direction, Y direction, and Z direction of the orthogonal coordinate system) to form a complete circuit system. Each layer of chips can be formed separately by a separate wafer-level process. At least two layers of chips can be stacked by a wafer-level process, a chip-level process, or a chip-to-wafer process to form the stack 100. In some embodiments, in the stack 100, each layer of chips (or chip layers) is, for example, a wafer. In some embodiments, each layer of chips (or chip layers) is a chip (or die). Depending on the design, or at least one layer is a wafer and at least one layer is a chip, the number of chip layers stacked in the stack 100 may be different.

Each layer of chips in the stack 100 may include a semiconductor substrate and electronic components, interconnection layers, dielectric layers, etc. formed based on the semiconductor substrate. In order to stack at least two layers of chips, the chip layers may be stacked together by bonding or bonding (such as hybrid bonding), for example, the semiconductor substrates may be bonded or bonded in a manner of facing each other, or bonded or bonded in a manner of separating the semiconductor substrates from each other (as shown in FIG. 2 ), and the semiconductor substrate of one chip layer may be bonded or bonded to the dielectric layer of another chip layer.

According to the embodiment, as shown in FIG. 2 , through step S1, a logic wafer W1 and a memory wafer W2 are stacked to form a stack 100. The logic wafer W1, for example, includes a first substrate 101 and logic elements formed on the surface of the first substrate 101. Here, the side with the logic elements formed is referred to as the front side of the first substrate 101, and the side opposite to the front side is the back side of the first substrate 101. The logic wafer W1 may also include a first interconnect structure 102 formed on one side of the front side of the first substrate 101. The memory wafer W2, for example, includes a second substrate 103 and memory elements (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) formed on the surface of the second substrate 103. The side on which the memory elements are formed is referred to as the front side of the second substrate 103, and the side opposite to the front side is the back side of the second substrate 103. The memory wafer W2 may also include a second interconnect structure 104 formed on one side of the front side of the second substrate 103. The first interconnect structure 102 and the second interconnect structure 104 may be multi-layer electrical interconnect structures, for example, including multi-layer patterned conductive layers and conductive plugs isolated by dielectric materials, the conductive layers and conductive plugs providing connection functions between various doped regions, circuits and input/outputs of the logic wafer W1 or the memory wafer W2. It should be understood that the components and positions of the first interconnect structure 102 and the second interconnect structure 104 are only schematically shown in the attached figure, and may actually be changed according to design requirements. In order to simplify the diagram, FIG2 only shows part of the conductive layers and conductive plugs in the first interconnect structure 102 and the second interconnect structure 104.

According to an embodiment of the present invention, in step S1, the front sides of the first substrate 101 and the second substrate 103 are bonded, and the first surface 100a of the stack 100 is the back side of the first substrate 101, and the second surface 100b is the back side of the second substrate 103. The present invention is not limited thereto, for example, in another embodiment, a plurality of memory wafers and a logic wafer may be stacked to form a corresponding stack, or in yet another embodiment, a plurality of memory chips and a logic chip may be stacked to form a corresponding stack.

1, 3 to 5, the method of manufacturing a three-dimensional integrated component of the present invention includes performing step S2: forming a heat conductive trench TR on the first surface 100a of the stack 100, wherein the length extension direction of the heat conductive trench TR is parallel to the first surface 100a, and the heat conductive trench TR has a first end TR1 and a second end TR2 in the length extension direction.

The manufacturing of the thermal conductive trench TR, for example, includes the following process: forming a patterned mask layer (such as a photoresist or a hard mask) on the first surface 100a of the stack 100 to expose the area of the first surface 100a where the thermal conductive trench TR is to be formed, and then etching the first surface 100a by dry etching or wet etching to form a trench of a preset depth in the stack 100 as the thermal conductive trench TR.

In this embodiment, the stack 100 includes a stacked logic wafer W1 and a memory wafer W2. The heat-conducting trench TR is used for the subsequent flow of the heat dissipation liquid in the first surface 100a to take away the heat generated inside the three-dimensional integrated component. The heat-conducting trench TR can be extended in the first surface 100a as needed. The extension direction of the heat-conducting trench TR in the first surface 100a is its length extension direction. The first end TR1 and the second end TR2 of the heat-conducting trench TR in the length extension direction are located at different positions. The first end TR1 is used as the position where the heat dissipation liquid flows into the heat-conducting trench TR, and the second end TR2 is used as the position where the heat dissipation liquid flows out of the heat-conducting trench TR.

It should be noted that, here, the thermal conductive trench TR is formed on the first surface 100a of the stack 100 as shown in FIG. 2, i.e., the back side of the first substrate 101 in the logic wafer W1, but the present invention is not limited to this. In other embodiments, a thermal conductive trench can also be formed on one side of the memory wafer in the stack as needed.

FIG4 shows an exemplary simulated plane pattern of the heat-conducting trench TR formed on the first surface 100a of the stack 100. Referring to FIG4, the first end TR1 and the second end TR2 of the heat-conducting trench TR are, for example, two ends of the heat-conducting trench TR that are farther apart, that is, from the first end TR1 to the second end TR2, the heat dissipation fluid needs to flow a longer distance in the heat-conducting trench TR. However, it is not limited to this, and the plane configuration of the heat-conducting trench TR shown in FIG4 is only an example, and those skilled in the art can set the plane configuration of the heat-conducting trench TR and the first end TR1 and the second end TR2 of the heat-conducting trench TR as needed.

As shown in FIG4 , the heat conducting trench TR may have multiple (such as two, three, or four, etc.) channel paths between the first end TR1 and the second end TR2, so that the heat conducting trench TR can be distributed to cover a larger range of the first surface 100a. However, it is not limited thereto, and the heat conducting trench TR may have only one channel path between the first end TR1 and the second end TR2, and the one channel path may be a straight line or a curve.

1 and 5 , the method for manufacturing a three-dimensional integrated component of the present invention includes performing step S3 : forming a first groove U1 and a second groove U2 on a surface of a carrier plate 200 .

The carrier plate 200 may be a semiconductor substrate, a glass substrate, a ceramic substrate or a polymer substrate, etc. The first groove U1 and the second groove U2 are respectively opposite to the first end TR1 and the second end TR2 of the heat-conducting trench TR after the carrier plate 200 is subsequently bonded to the stacking body 100, so the positions of the first groove U1 and the second groove U2 may be determined according to the arrangement of the heat-conducting trench TR in the stacking body 100. The cross-sectional area of the first groove U1 may be larger or smaller than the area of the first end TR1 of the heat-conducting trench TR opposite thereto, and the cross-sectional area of the second groove U2 may be larger or smaller than the area of the second end TR2 of the heat-conducting trench TR opposite thereto.

Forming the first groove U1 and the second groove U2 on the surface of the carrier plate 200, for example, includes the following process: forming a patterned mask layer (such as a photoresist or a hard mask) on the surface of the carrier plate 200 to expose the area where the first groove U1 and the second groove U2 are to be formed, and then etching the carrier plate 200 by dry etching or wet etching to form the first groove U1 and the second groove U2 in the carrier plate 200. FIG. 6 shows an exemplary simulated plane pattern of the first groove U1 and the second groove U2 formed on the surface of the carrier plate 200. Referring to FIG. 6, illustratively, the cross-section of the first groove U1 and the second groove U2 is rectangular, but not limited thereto, in other embodiments, the first groove U1 and the second groove U2 may also have a circular, elliptical, triangular, square, pentagonal, hexagonal or other cross-sectional shape.

Referring to FIG. 1 and FIG. 7 , the method for manufacturing a three-dimensional integrated component of the present invention includes performing step S4: bonding the stacking body 100 to the carrier plate 200, wherein the first groove U1 is opposite to the first end TR1 of the heat conducting trench TR, and the second groove U2 is opposite to the second end TR2 of the heat conducting trench TR. FIG. 8 shows a simulated cross section of the stacking body 100, the carrier plate 200 and the heat conducting trench TR after bonding.

The stacking body 100 and the carrier plate 200 are bonded by, for example, fusion bonding. After bonding, the first groove U1 covers the first end TR1 of the heat conducting trench TR, so that the first groove U1 is connected to the first end TR1, and the second groove U2 covers the second end TR2 of the heat conducting trench TR, so that the second groove U2 is connected to the second end TR2.

FIG9 is a cross-sectional view of a method for manufacturing a three-dimensional integrated component according to an embodiment of the present invention after forming a solder bump on the second surface of the stack. Referring to FIG9 , in this embodiment, in order to connect the stack 100 to the circuit substrate, a solder bump 110 is further formed on the second surface 100b of the stack 100, and the solder bump 110 is electrically connected to the circuit inside the stack 100.

Specifically, please refer to FIG. 9 . After the stack 100 and the carrier 200 are bonded, the method for manufacturing the three-dimensional integrated device of the embodiment of the present invention may further include: using the carrier 200 for support, forming a first back dielectric layer 105 on the back side of the second substrate 103, and etching the first back dielectric layer 105 and the second substrate 103 to form a silicon through hole penetrating the second substrate 103, so that the silicon through hole exposes the second interconnect structure 104; depositing a metal material (such as copper) to form a silicon conductive film corresponding to the silicon through hole. A via is formed on the back surface 100b, and a back interconnection layer 106 is formed; a second back dielectric layer 107 is deposited, and the second back dielectric layer 107 is etched to form a via that exposes the back interconnection layer 106; a metal material (such as copper) is deposited to form a conductive hole connected to the back interconnection layer 106 corresponding to the via, and a pad 108 is formed; a passivation layer 109 is deposited, and the passivation layer 109 is etched to form a via that exposes the pad 108; a solder bump 110 connected to the pad 108 is formed in the via. One or more solder bumps 110 can be formed on the second surface 100b, and can be specifically arranged according to the integration requirements of the stack 100 and the circuit substrate.

FIG10 shows a cross section after the stacking body 100 is bonded to the circuit substrate 300. Referring to FIG10 , the stacking body 100 can then be bonded to a circuit substrate 300 so that the circuit inside the stacking body 100 is connected to the circuit substrate 300.

The circuit substrate 300 may include electronic components (such as logic components) and interconnect structures, which can provide further interconnection and support in the three-dimensional integrated component. For example, solder pads (not shown) are formed on the surface of the circuit substrate 300. When the stacking body 100 and the circuit substrate 300 are joined, each solder bump 110 formed on the stacking body 100 can be soldered to the corresponding solder pad on the circuit substrate 300.

The circuit substrate 300 may be an intermediate substrate, such as a DCB board (ceramic-based copper-clad board, also known as a DBC board), an AMB board (active metal brazing carrier board), a DPC board (direct plate copper), a HTCC board (high-temperature co-fired ceramic), or a LTCC board (low-temperature co-fired ceramic). After the stack 100 is bonded to one side of the intermediate substrate, the intermediate substrate may be connected to a PCB substrate from the other side of the intermediate substrate, but the present invention is not limited thereto. The circuit substrate 300 may also be a PCB substrate.

Please refer to FIG. 1 and FIG. 11 , the method of manufacturing a three-dimensional integrated element of the present invention includes performing step S5: removing the bottom of the first groove U1 and the second groove U2, so that the first groove U1 forms a first through hole U1a, and the second groove U2 forms a second through hole U2a. For example, the bottom of the first groove U1 and the second groove U2 can be removed by thinning (for example, mechanical grinding, chemical mechanical grinding, laser grinding or other processes) or etching (for example, dry etching process or wet etching process) the carrier plate 200. The first through hole U1a exposes the first end TR1 of the heat-conducting trench TR, and the second through hole U2a exposes the second end TR2 of the heat-conducting trench TR, wherein, as indicated by the dotted arrow, the first through hole U1a is the inlet of the heat dissipation liquid, and the second through hole U2a is the outlet of the heat dissipation liquid.

In this embodiment, after the bottom of the first groove U1 and the second groove U2 are removed by thinning or etching the carrier plate 200, the opening of the first through hole U1a relative to the stacking body 100 (i.e., the liquid inlet of the first through hole U1a) is not higher than the surface of the carrier plate 200 around the first through hole U1a; the opening of the second through hole U2a relative to the stacking body 100 (i.e., the liquid outlet of the second through hole U2a) is not higher than the surface of the carrier plate 200 around the second through hole U2a. For example, in the embodiment shown in FIG. 11, the liquid inlet of the first through hole U1a and the liquid outlet of the second through hole U2a are substantially flush with the surface of the carrier plate 200 on the same side.

In the manufacturing method of the three-dimensional integrated element described in the above embodiment, a heat-conducting trench TR is formed on the surface of the stack 100, and a first through hole U1a connected to the first end TR1 of the heat-conducting trench TR and a second through hole U2a connected to the second end TR2 of the heat-conducting trench TR are formed in the carrier plate 200 keyed to the stack 100. When the three-dimensional integrated element is working, a heat dissipation liquid can be introduced into the heat-conducting trench TR from the first through hole U1a. The heat dissipation liquid is made to flow out of the second through hole U2a, so as to promptly take away the heat generated by the chips in the stack 100 when they are working, thereby achieving the purpose of cooling the device. In addition, the heat conduction efficiency is higher and the heat dissipation capacity is stronger. Compared with the heat dissipation method of attaching a metal heat sink adopted in the prior art, the risk of heat accumulation inside the three-dimensional integrated component can be reduced, which is helpful to improve the performance of the three-dimensional integrated component.

The present invention also relates to a three-dimensional integrated element. The three-dimensional integrated element can be manufactured by the manufacturing method of the three-dimensional integrated element described in the above embodiment.

Please refer to FIG. 11 , according to an embodiment of the present invention, the three-dimensional integrated component includes a stacking body 100 formed by stacking at least two layers of chips and a carrier plate 200. The stacking body 100 has a first surface 100a and a second surface 100b opposite to each other, wherein the first surface 100a is formed with a heat-conducting trench TR, and the length extension direction of the heat-conducting trench TR is parallel to the first surface 100a. The carrier plate 200 is bonded to the first surface 100a of the stacking body 100. The carrier plate 200 has a first through hole U1a and a second through hole U2a, wherein the first through hole U1a exposes the first end TR1 of the heat-conducting trench TR, and the second through hole U2a exposes the second end TR2 of the heat-conducting trench TR. The first through hole U1a is the inlet of the heat dissipation liquid, and the second through hole U2a is the outlet of the heat dissipation liquid.

In some embodiments, the opening of the first through hole U1a relative to the stack 100 (i.e., the liquid inlet of the first through hole U1a) is not higher than the surface of the carrier plate 200 around the first through hole U1a. In some embodiments, the opening of the second through hole U2a relative to the stack 100 (i.e., the liquid outlet of the second through hole U2a) is not higher than the surface of the carrier plate 200 around the second through hole U2a. For example, as shown in the embodiment of FIG. 11, the liquid inlet of the first through hole U1a and the liquid outlet of the second through hole U2a are substantially flush with the surface of the carrier plate 200 on the same side.

The thermally conductive trench TR is formed on the first surface 100 a of the stack 100 . The first surface 100 a is, for example, the surface of a semiconductor substrate in the stack 100 , but is not limited thereto. In another embodiment, the thermally conductive trench TR may also be formed on the surface of a dielectric layer in the stack 100 .

2 to 11 , the heat conducting trench TR may have one or more channel paths between the first end TR1 and the second end TR2 . The second surface 100 b of the stack 100 may be optionally provided with a solder bump 110 , and the solder bump 110 is electrically connected to the circuit inside the stack 100 .

In some embodiments, the three-dimensional integrated component further includes a circuit substrate 300 having pads, wherein the stacked body 100 is bonded to the circuit substrate 300 by soldering the solder bumps 110 to the corresponding pads.

Please continue to refer to Figure 11. In some embodiments, the stack 100 includes a first chip layer (for example, a logic wafer W1), the first chip layer includes a first substrate 101 and an electronic component formed on the front side of the first substrate 101, wherein the heat conductive trench TR is formed on the back side of the first substrate 101 opposite to the front side. The electronic component may include a logic component and/or a memory component. For example, the first chip layer may be a logic wafer, a logic chip, a memory wafer, or a memory chip. In some embodiments, the first chip layer is a wafer containing both a logic component and a memory component or a chip containing both a logic component and a memory component.

In the stack 100, each chip layer may include one or more chips. According to the embodiment, the stack 100 is formed by stacking a logic wafer W1 and a memory wafer W2. However, it is not limited thereto. According to the design of the three-dimensional integrated component, the stack 100 may include more than two chip layers, and each chip layer may have a wafer-level size or a chip-level size. Referring to FIG. 12 , in another embodiment, the stack 100 includes a logic wafer W1 and two or more memory wafers (e.g., the memory wafer W3 and the memory wafer W4 of the present embodiment), and the stack 100 is bonded to the circuit substrate 300 on one side of the logic wafer W1 and to the carrier plate 200 on one side of the memory wafer W3, and a thermal conductive trench TR is formed on the surface of the memory wafer W3.

The three-dimensional integrated component of the embodiment of the present invention includes a stacking body 100 formed by stacking at least two layers of chips and a supporting plate 200 bonded to the first surface 100a of the stacking body 100, wherein the first surface 100a of the stacking body 100 is formed with a heat-conducting groove TR, and the supporting plate 200 has a first through hole U1a and a second through hole U2a, the first through hole U1a exposes the first end TR1 of the heat-conducting groove TR, and the second through hole U2a exposes the second end TR2 of the heat-conducting groove TR, the first through hole U1a is the inlet of the heat dissipation liquid, and the second through hole U2a is the outlet of the heat dissipation liquid. Compared with the heat dissipation method of attaching a metal heat sink used in the prior art, the three-dimensional integrated component can use the flow of the heat dissipation liquid in the heat conductive groove TR to carry away the heat for heat dissipation, thereby achieving the purpose of cooling the device. It has higher thermal conductivity efficiency and stronger heat dissipation capacity, which can reduce the risk of heat accumulation inside the three-dimensional integrated component and help improve the performance of the three-dimensional integrated component.

It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the relevant points can be understood by reference.

The above description is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

100: stack body 101: first substrate 102: first interconnect structure 103: second substrate 104: second interconnect structure 105: first back dielectric layer 106: back interconnect layer 107: second back dielectric layer 108: solder pad 109: passivation layer 110: solder bump 200: carrier plate 300: circuit substrate 100a: first surface 110b: second surface S1: step S2: step S3: step S4: step S5: step TR: thermal conductive trench TR1: first end TR2: second end U1: first groove U1a: first through hole U2: second groove U2a: Second through hole W1: Logic wafer W2: Memory wafer W3: Memory wafer W4: Memory wafer

FIG. 1 is a schematic diagram of the process of the method for manufacturing a three-dimensional integrated element of an embodiment of the present invention. FIG. 2 is a schematic diagram of a cross-section of a stack in a method for manufacturing a three-dimensional integrated element of an embodiment of the present invention. FIG. 3 is a schematic diagram of a cross-section after a heat-conducting groove is formed on the first surface of the stack in a method for manufacturing a three-dimensional integrated element of an embodiment of the present invention. FIG. 4 is a simulated plan view of a heat-conducting groove formed on the first surface of the stack in a method for manufacturing a three-dimensional integrated element of an embodiment of the present invention. FIG. 5 is a schematic diagram of a cross-section after a first groove and a second groove are formed on the surface of a carrier plate in a method for manufacturing a three-dimensional integrated element of an embodiment of the present invention. FIG. 6 is a simulated plan view of a first groove and a second groove formed on the surface of a carrier plate in a method for manufacturing a three-dimensional integrated element of an embodiment of the present invention. FIG. 7 is a cross-sectional schematic diagram of a stacking body and a carrier plate after bonding in a method for manufacturing a three-dimensional integrated component of an embodiment of the present invention. FIG. 8 is a simulated cross-sectional diagram of a stacking body, a carrier plate and a heat-conducting groove after bonding in a method for manufacturing a three-dimensional integrated component of an embodiment of the present invention. FIG. 9 is a cross-sectional schematic diagram of a solder bump formed on the second surface of the stacking body in a method for manufacturing a three-dimensional integrated component of an embodiment of the present invention. FIG. 10 is a cross-sectional schematic diagram of a stacking body after bonding to a circuit substrate in a method for manufacturing a three-dimensional integrated component of an embodiment of the present invention. FIG. 11 is a cross-sectional schematic diagram of a method for manufacturing a three-dimensional integrated component of an embodiment of the present invention after removing the bottom of the first groove and the second groove. FIG. 12 is a cross-sectional schematic diagram of a three-dimensional integrated component of an embodiment of the present invention.

100: stack 101: first substrate 102: first interconnect structure 103: second substrate 104: second interconnect structure 105: first back dielectric layer 110: solder bump 200: carrier 300: circuit substrate 100a: first surface 110b: second surface TR: thermal conductive trench TR1: first end TR2: second end U1a: first through hole U2a: second through hole W1: logic wafer W2: memory wafer

Claims (11)

A three-dimensional integrated component, comprising: A stacked body, formed by stacking at least two layers of wafers, wherein each layer of wafers in the stacked body comprises a semiconductor substrate and electronic components, interconnection layers, and dielectric layers formed based on the semiconductor substrate, wherein the stacked body has a first surface and a second surface opposite to each other, the first surface is etched to form a heat-conducting groove, and the length extension direction of the heat-conducting groove is parallel to the first surface; and A carrier plate, bonded to the first surface of the stacked body, the carrier plate having a first through hole and a second through hole, the first through hole exposing a first end of the heat-conducting groove, and the second through hole exposing a second end of the heat-conducting groove, wherein the first through hole is an inlet of a heat-dissipating liquid, and the second through hole is an outlet of the heat-dissipating liquid. A three-dimensional integrated element as described in claim 1, wherein the opening of the first through hole relative to the stack is not higher than the surface of the supporting plate around the first through hole, and the opening of the second through hole relative to the stack is not higher than the surface of the supporting plate around the second through hole. In the three-dimensional integrated component as described in claim 1, a solder bump is formed on the second surface, and the solder bump is electrically connected to a circuit inside the stack. The three-dimensional integrated component as described in claim 3 further comprises: A circuit substrate having a solder pad, wherein the stack is joined to the circuit substrate by soldering the solder bumps to the corresponding solder pads. A three-dimensional integrated component as described in claim 1, wherein the stack includes a first chip layer, the first chip layer includes a first substrate and an electronic component formed on the front side of the first substrate, wherein the heat conductive trench is formed on the back side of the first substrate opposite to the front side. A three-dimensional integrated device as described in claim 5, wherein the electronic component includes a logic component and/or a memory component. A three-dimensional integrated component as described in any one of claims 1 to 6, wherein there is one or more channel paths between the first end and the second end of the heat conductive trench. A three-dimensional integrated device as described in any one of claims 1 to 6, wherein in the stack, each chip layer includes at least one chip. A method for manufacturing a three-dimensional integrated component as described in any one of claims 1 to 8, comprising: Stacking at least two chip layers to form a stack, the stack having a first surface and a second surface opposite to each other, wherein each chip layer in the stack includes a semiconductor substrate and electronic components, interconnection layers, and dielectric layers formed based on the semiconductor substrate; Etching a thermal conductive trench on the first surface, the thermal conductive trench having a length extension direction parallel to the first surface, and the thermal conductive trench having a first end and a second end in the length extension direction; Forming a first groove and a second groove on a surface of a carrier plate; Bonding the stack to the carrier plate, wherein the first groove is opposite to the first end of the thermal conductive trench, and the second groove is opposite to the second end of the thermal conductive trench; and The bottoms of the first groove and the second groove are removed, so that the first groove forms a first through hole, and the second groove forms a second through hole, the first through hole exposes the first end of the heat conductive groove, and the second through hole exposes the second end of the heat conductive groove, wherein the first through hole is an inlet of a heat dissipation liquid, and the second through hole is an outlet of the heat dissipation liquid. A manufacturing method as described in claim 9, wherein the bottoms of the first groove and the second groove are removed by thinning or etching the supporting plate. The manufacturing method as described in claim 9, wherein before removing the bottom of the first groove and the second groove, the method further comprises: forming a solder bump on the second surface, wherein the solder bump is electrically connected to a circuit inside the stack; and joining the stack to a circuit substrate, wherein the circuit substrate has a pad, wherein the solder bump is soldered to the corresponding pad.