TWI869242B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A method of forming a semiconductor device includes forming a trench in the substrate. The trench extends from an upper surface of the substrate, and the trench has a sidewall and a bottom surface. An angle between the sidewall and the bottom surface of the trench is not less than 90 degrees. A well region is formed at the upper surface of the substrate, the sidewall and the bottom surface of the trench. A source region is formed at the bottom of the trench. A body contact region is formed at the bottom of the trench, and the body contact region is adjacent to the source region. A gate structure is formed lining the upper surface of the substrate, the sidewall and the bottom surface of the trench. A source contact is formed in the trench and penetrates through the gate structure, and is electrically connected with the body contact region and the source region.

Description

Semiconductor device and method for manufacturing the same

Some embodiments of the present disclosure relate to semiconductor devices and methods of making the same.

Metal oxide semiconductor field effect transistors (MOS FETs) can be divided into horizontal channel MOSFETs and vertical channel MOSFETs according to their channel direction. Among them, vertical channel MOSFETs can provide the same current in a smaller area and obtain a smaller on-resistance (Rdson), which can greatly reduce production costs. How to further improve the efficiency of vertical channel MOSFETs has also become one of the important issues.

Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including forming a trench in a substrate, the trench extending downward from the top surface of the substrate, and the trench having side walls and a bottom surface, and the angle between the side walls and the bottom surface is greater than or equal to 90 degrees, forming a well region on the top surface of the substrate and the side walls and bottom surface of the trench, forming a source region on the bottom surface of the trench, forming a body contact region on the bottom surface of the trench, and the body contact region is adjacent to the source region, forming a gate structure along the top surface of the substrate and the side walls and bottom surface of the trench, and forming a source contact in the trench to penetrate the gate structure and electrically connect the source region and the body contact region.

In some implementations, the trench is an inverted trapezoidal trench.

In some embodiments, forming a trench in a substrate includes forming a plurality of stepped dielectric layer stacks on the substrate, and etching the substrate to form the trench using the stepped dielectric layer stacks as a mask.

In some embodiments, forming a step-shaped dielectric layer stack on a substrate includes forming a dielectric layer stack on the substrate, wherein the dielectric layer stack includes a plurality of first dielectric layers and a plurality of second dielectric layers that are cross-stacked, the first dielectric layer is made of a first material, and the second dielectric layer is made of a second material different from the first material, and the dielectric layer stack is patterned multiple times by a mask to form the step-shaped dielectric layer stack.

In some embodiments, when etching a substrate using the stepped dielectric layer stack as a mask, the stepped dielectric layer stack and the substrate are etched at the same etching rate.

In some embodiments, the angle between the side wall and the bottom surface is determined according to the lattice arrangement direction of the substrate.

Some embodiments of the present disclosure provide a semiconductor device including a substrate, a gate structure, a source contact, and a drain electrode. The substrate has a trench extending downward from the top surface of the substrate, the trench has side walls and a bottom surface, and the angle between the side walls and the bottom surface is greater than or equal to 90 degrees. The gate structure is on the substrate and along the top surface of the substrate, the side walls and the bottom surface of the trench. The source contact is in the trench of the substrate and penetrates the gate structure to electrically connect to the source region of the substrate. The drain electrode is under the substrate.

In some embodiments, the groove is an inverted trapezoidal groove.

In some embodiments, the source region is at the bottom of the trench, and the substrate further includes a well region and a body contact region. The well region is along the top surface of the substrate, the sidewalls and the bottom surface of the trench. The body contact region is at the bottom surface of the trench and adjacent to the source region.

In some embodiments, the extension direction of the sidewalls of the trench is the same as the lattice arrangement direction of the substrate.

Some embodiments of the present disclosure relate to forming a power semiconductor device with a vertical channel. The power semiconductor device with a vertical channel can provide a larger current under the same area, and thus can provide a smaller on-resistance.

FIG. 1 to FIG. 6 illustrate cross-sectional views of semiconductor devices formed in some embodiments of the present disclosure. Referring to FIG. 1, a substrate 110 is provided. The substrate 110 may be any suitable semiconductor substrate. For example, the substrate 110 may be a silicon substrate or a silicon carbide substrate. In some embodiments, the substrate 110 is a lightly doped region having a first conductivity type, for example, the substrate 110 may be an N-type lightly doped region and includes N-type dopants, such as arsenic, phosphorus, and nitrogen.

Next, a dielectric layer stack is formed on the substrate 110. The dielectric layer stack includes a plurality of cross-stacked first dielectric layers 210 and a plurality of second dielectric layers 220. The first dielectric layer 210 is made of a first material, and the second dielectric layer 220 is made of a second material different from the first material. In some embodiments, the first dielectric layer 210 may be made of silicon oxide, and the second dielectric layer 220 may be made of silicon nitride. In some embodiments, the thickness of the first dielectric layer 210 and the second dielectric layer 220 may be between 0.1 micrometers and 0.5 micrometers. In some embodiments, the dielectric layer stack may include 2 to 10 layers of the first dielectric layer 210 and the second dielectric layer 220, respectively. In the following description, the present disclosure takes the dielectric layer stack including three first dielectric layers 210A, 210B and 210C and three second dielectric layers 220A, 220B and 220C as an example.

Next, a first patterning process is performed by using a photomask to pattern the dielectric layer stack, and the dielectric layer stack has a first sidewall S1. Specifically, a first photoresist layer may be formed on the dielectric layer stack first, and the first photoresist layer may be patterned by using a photomask, and then all dielectric layers in the dielectric layer stack may be patterned by using the first photoresist layer. At this time, the photomask is located at a first position.

Then, the mask is moved in the first direction D1, and a second patterning process is performed by the mask to partially pattern the dielectric layer stack, so that the dielectric layer stack has a first sidewall S1 and a second sidewall S2 offset in the first direction D1, and the second sidewall S1 is on the first sidewall S1. Specifically, a second photoresist layer can be formed on the dielectric layer stack, and the mask is moved along the first direction D1 based on the first position, so that the mask is located at the second position, and the second photoresist layer is patterned by the mask. The second photoresist layer is offset by a distance along the first direction D1 compared to the first photoresist layer. Next, the second dielectric layer 220C is etched using the first gas with the second photoresist layer as a mask, and the first dielectric layer 210C is etched using the second gas with the second dielectric layer 220C as a mask. Since the second dielectric layer 220 and the first dielectric layer 210 are made of different materials, different etching gases can be selected to etch the first dielectric layer 210 and the second dielectric layer 220, respectively. In the present disclosure, the first gas can be defined as a gas whose etching rate for the second dielectric layer 220 is greater than the etching rate for the first dielectric layer 210. The second gas can be defined as a gas whose etching rate for the first dielectric layer 210 is greater than the etching rate for the second dielectric layer 220.

Then, the mask is moved in the first direction, and a third patterning process is performed by the mask to partially pattern the dielectric layer stack, so that the dielectric layer stack further has a third sidewall S3, and the third sidewall S3 is offset in the first direction D1 compared to the second sidewall S2, and the third sidewall S3 is on the second sidewall S2. Specifically, a third photoresist layer can be formed on the dielectric layer stack, and the mask is moved along the first direction D1 based on the second position, so that the mask is located at the third position, and the third photoresist layer is patterned by the mask. The third photoresist layer is offset by a distance along the first direction D1 compared to the second photoresist layer. Next, the photoresist layer and the first dielectric layer 210C are used as masks, and the first gas is used to etch the second dielectric layer 220C and the second dielectric layer 220B. Next, the second dielectric layer 220C and the second dielectric layer 220B are used as masks, and the second gas is used to etch the first dielectric layer 210C and the first dielectric layer 210B in the middle.

Then, the mask is moved in the first direction D1, and a fourth patterning process is performed by the mask to partially pattern the dielectric layer stack, so that the dielectric layer stack further has a fourth sidewall S4, and the fourth sidewall S4 is offset in the first direction compared to the third sidewall S3, and the fourth sidewall S4 is on the third sidewall S3. Specifically, a fourth photoresist layer can be formed on the dielectric layer stack, and the mask is moved along the first direction based on the third position, so that the mask is located at the fourth position, and the fourth photoresist layer is patterned by the mask. The fourth photoresist layer is offset by a distance along the first direction D1 compared to the third photoresist layer. Next, the fourth photoresist layer, the first dielectric layer 210C and the first dielectric layer 210B are used as masks, and the first gas is used to etch the second dielectric layer 220C, the second dielectric layer 220B and the second dielectric layer 220A, respectively. Thus, the sidewall of one side of the dielectric layer stack is formed into a step shape.

Then, in a similar manner as described above, the sidewall of the other side of the dielectric layer stack is also formed into a step shape (for example, the mask described above is moved from the first position to the second direction D2), so that a plurality of step-shaped dielectric layer stacks 200 can be formed on the substrate 110. In the present disclosure, the dielectric layer stack can be patterned by a mask PM to form a step-shaped dielectric layer stack 200. The shape of the sidewall of the step-shaped dielectric layer stack 200 can be determined by the amplitude of each movement of the mask PM. In addition, the offset distance of the second photoresist layer, the third photoresist layer, and the fourth photoresist layer corresponds to the amplitude of each movement of the mask. The step-shaped dielectric layer stack 200 includes sequentially contracted sidewalls S1, S2, S3, and S4. In some embodiments, the horizontal distance between two adjacent sidewalls (e.g., the horizontal distance between the sidewalls S1 and S2, the horizontal distance between the sidewalls S2 and S3, and the horizontal distance between the sidewalls S3 and S4) is approximately between 0.1 micrometers and 0.5 micrometers. The step-shaped dielectric layer stack 200 includes a plurality of cross-stacked first dielectric layers 210 and a plurality of second dielectric layers 220, wherein the first dielectric layers 210 are made of a first material, and the second dielectric layers 220 are made of a second material different from the first material. In some embodiments, the first dielectric layer 210 may be made of silicon oxide, and the second dielectric layer 220 may be made of silicon nitride. In some embodiments, the thickness of the first dielectric layer 210 and the second dielectric layer 220 may be between 0.1 micrometers and 0.5 micrometers. In some embodiments, the dielectric layer stack may include 2 to 10 layers of the first dielectric layer 210 and the second dielectric layer 220, respectively.

Referring to FIG. 2 , a trench T is formed in the substrate 110. Specifically, the substrate 110 can be etched using the stepped dielectric layer stack 200 as a mask to form the trench T. When the substrate 110 is etched using the stepped dielectric layer stack 200 as a mask, the stepped dielectric layer stack 200 and the substrate 110 are etched at the same etching rate until the stepped dielectric layer stack 200 is completely etched. Therefore, a stepped trench T can be formed in the substrate 110.

After forming the stepped trench T, the surface of the substrate 110 may be smoothed to make the surface of the trench T of the substrate 110 smooth. In some embodiments, referring to FIG. 3 , the substrate 110 may be first subjected to an oxidation process to form an oxide layer 111 on the surface of the substrate 110, and then referring to FIG. 4 , the oxide layer 111 is removed to make the surface of the trench T of the substrate 110 smooth. After the smoothing process, the trench T extends downward from the top surface 112 of the substrate 110, and the trench T has a side wall 114 and a bottom surface 116, and the angle between the side wall 114 and the bottom surface 116 is greater than 90 degrees. In other words, the trench T is an inverted trapezoidal trench.

5 , a first ion implantation process is performed on the substrate 110 to form a well region 122 on the top surface 112 of the substrate 110 and the sidewalls 114 and bottom surface 116 of the trench T. Specifically, when performing the first ion implantation process, dopants of the second conductive type may be implanted into the substrate 110 to form a well region 122 of the second conductive type on the top surface 112 of the substrate 110 and the sidewalls 114 and bottom surface 116 of the trench T. In some embodiments, the well region 122 may be a lightly doped region of the second conductive type, for example, the well region 122 may be a lightly doped region of a P type and include a P type dopant, such as boron, gallium, and aluminum. The remaining region not implanted with the second conductive type dopant still maintains the first conductive type doped region, and this first conductive type doped region can be referred to as the drift region 121. The doping concentration of the well region 122 is higher than that of the drift region 121.

Next, a second ion implantation process is performed on the substrate 110 to form a source region 124 at the bottom surface 116 of the trench T. Specifically, when performing the second ion implantation process, a first conductive type dopant may be implanted into the substrate 110 to form a source region 124 having the first conductive type at the bottom surface 116 of the trench T. In some embodiments, the source region 124 may be a heavily doped region of the first conductive type, and the doping concentration of the source region 124 is higher than the doping concentration of the well region 122. For example, the source region 124 may be an N-type heavily doped region and include N-type dopant, such as arsenic, phosphorus, and nitrogen.

After forming the source region 124, a junction field-effect transistor (JFET) region 126 may also be formed on the top surface 112 of the substrate 110, so that the JFET region 126 has the same conductivity type and doping concentration as the source region 124. In some embodiments, the JFET region 126 may be a heavily doped region of a first conductivity type, for example, the JFET region 126 may be an N-type heavily doped region and include N-type dopants, such as arsenic, phosphorus, and nitrogen.

Next, a third ion implantation process is performed on the substrate 110 to form a body contact region 128 on the bottom surface 116 of the trench T, and the body contact region 128 is adjacent to the source region 124. Specifically, when performing the third ion implantation process, dopants of the second conductive type may be implanted into the substrate 110 to form a body contact region 128 of the second conductive type on the bottom surface 116 of the trench T. In some embodiments, the body contact region 128 may be a heavily doped region of the second conductive type, and the doping concentration of the body contact region 128 is higher than the doping concentration of the well region 122. For example, the body contact region 128 may be a heavily doped region of P type and include P type dopants, such as boron, gallium and aluminum.

Next, a gate structure 130 is formed along the top surface 112 of the substrate 110 and the sidewalls 114 and bottom surface 116 of the trench T. In some embodiments, the gate structure 130 may have a first horizontal portion located on the top surface 112 of the substrate 110, an inclined portion located on the sidewalls 114 of the trench T, and a second horizontal portion located on the bottom surface 116 of the trench T. Specifically, a gate dielectric layer 132 may be first formed on the substrate 110 and along the top surface 112 of the substrate 110, the sidewalls 114 and bottom surface 116 of the trench T. Next, a gate layer 134 is formed on the gate dielectric layer 132. The gate dielectric layer 132 and the gate layer 134 may be collectively referred to as a gate structure 130. Next, an opening may be formed in the gate structure 130 to expose the body contact region 128 and a portion of the source region 124. In some embodiments, the gate dielectric layer 132 may be made of silicon oxide, and the gate layer 134 may be made of polysilicon.

6 , a dielectric layer 140 is formed on the substrate 110 and in the trench T. The dielectric layer 140 also fills the opening of the gate structure 130. Next, a source contact 150 is formed in the trench T to penetrate the gate structure 130 and contact the source region 124 and the body contact region 128. Specifically, an opening exposing the source region 124 and the body contact region 128 may be first formed in the dielectric layer 140, and then a contact material may be formed in the opening to form the source contact 150. Therefore, the source contact 150 penetrates the dielectric layer 140 and the gate structure 130 and contacts the source region 124 and the body contact region 128, and the dielectric layer 140 surrounds the source contact 150. Next, a drain electrode 160 is formed under the substrate 110.

In this way, a semiconductor device as shown in FIG. 6 can be obtained. The semiconductor device may include a substrate 110, a gate structure 130, a source contact 150, and a drain electrode 160. The substrate 110 has a trench T extending downward from the top surface 112 of the substrate 110, the trench T has a sidewall 114 and a bottom surface 116, and the angle between the sidewall 114 and the bottom surface 116 is greater than 90 degrees. The substrate 110 includes a drift region 121, a well region 122, a JFET region 126, a body contact region 128, and a source region 124. The well region 122 is on the drift region 121, and the well region 122 is along the top surface 112 of the substrate 110, the sidewall 114 of the trench T, and the bottom surface 116. The JFET region 126 is on the top surface 112 of the substrate 110. The source region 124 is on the bottom surface 116 of the trench T. The body contact region 128 is on the bottom surface 116 of the trench T and is adjacent to the source region 124. The gate structure 130 is on the substrate 110 and along the top surface 112 of the substrate 110, the sidewalls 114 and the bottom surface 116 of the trench T. The source contact 150 is in the trench T of the substrate 110, penetrates the gate structure 130 and electrically connects the source region 124 and the body contact region 128 to contact the substrate 110. The drain electrode 160 is under the substrate 110.

The semiconductor device disclosed in the present invention has a vertical channel, and the vertical channel is a well region 122 along the side wall 114 of the trench T. When the semiconductor device has a vertical channel, for example, when the angle between the side wall 114 and the bottom surface 116 of the trench T is greater than 90 degrees, a larger current can be provided under the same area, and thus a smaller on-resistance can be provided. In addition, the angle between the side wall 114 and the bottom surface 116 can be determined according to the lattice arrangement direction of the substrate 110. Specifically, the angle between the side wall 114 and the bottom surface 116 can determine the extension direction of the well region 122 along the side wall 114 of the trench, that is, the direction of the channel. When the direction of the channel is the same as the arrangement direction of the substrate 110, the carriers can have the maximum carrier mobility in the channel. In other words, the angle between the sidewall 114 and the bottom surface 116 can be determined according to the lattice arrangement direction of the substrate 110 to ensure that the carriers can have the maximum carrier mobility in the channel and have the maximum current (for example, when the extension direction of the sidewall 114 of the trench is the same as the lattice arrangement direction of the substrate 110). Since a portion of the gate structure 130 is formed along the sidewall 114 of the trench, when the extension direction of the sidewall 114 of the trench is the same as the lattice arrangement direction of the substrate 110, the extension direction of the gate structure 130 on the sidewall 114 of the trench is also the same as the lattice arrangement direction of the substrate 110.

FIG. 7 shows a cross-sectional view of a semiconductor device of another embodiment of the present disclosure. The semiconductor device of FIG. 7 is similar to the semiconductor device of FIG. 6, except that the angle between the sidewall 114 and the bottom surface 116 of the trench of the semiconductor device of FIG. 7 is 90 degrees. When manufacturing the semiconductor device of FIG. 7, the step-shaped dielectric layer stack can be directly replaced with a hard mask layer with vertical sidewalls in the step of FIG. 1, and the hard mask layer with vertical sidewalls is used to etch the substrate 110. Then, the steps of FIG. 2 to FIG. 6 are performed to form the semiconductor device of FIG. 7. When the angle between the sidewall 114 and the bottom surface 116 of the trench of the semiconductor device is 90 degrees, the semiconductor device can also provide a larger current under the same area, and thus can provide a smaller on-resistance.

The above is only a partial implementation of the present disclosure, not all implementations. Any equivalent changes made to the technical solution of the present disclosure by a person of ordinary skill in the art after reading the specification of the present disclosure are covered by the claims of the present disclosure.

110: substrate 111: oxide layer 112: top surface 114: sidewalls 116: bottom surface 121: drift region 122: well region 124: source region 126: junction field effect transistor region/JFET region 128: body contact region 130: gate structure 132: gate dielectric layer 134: gate layer 140: dielectric layer 150: source contact 160: drain electrode 210: first dielectric layer 220: second dielectric layer S1, S2, S3, S4: sidewalls T: trench

Figures 1 to 6 show cross-sectional views of semiconductor devices formed in some embodiments of the present disclosure.

FIG. 7 shows a cross-sectional view of a semiconductor device according to other embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

110: Substrate

112: Top

114: Side wall

116: Bottom

121: Drift Zone

122: Well area

124: Source region

126: Junction field effect transistor region/JFET region

128: Body contact area

130: Gate structure

132: Gate dielectric layer

134: Gate layer

140: Dielectric layer

150: Source contact point

160: Drain electrode

Claims (10)

A method for manufacturing a semiconductor device, comprising: Forming a trench in a substrate, the trench extending downward from a top surface of the substrate, and the trench having a side wall and a bottom surface, and an angle between the side wall and the bottom surface is greater than or equal to 90 degrees; Forming a well region on the top surface of the substrate and the side wall and the bottom surface of the trench; Forming a source region on the bottom surface of the trench; Forming a body contact region on the bottom surface of the trench, and the body contact region is adjacent to the source region; Forming a gate structure along the top surface of the substrate and the side wall and the bottom surface of the trench; A source contact is formed in the trench to penetrate the gate structure and electrically connect the source region and the body contact region. The method as described in claim 1, wherein the groove is an inverted trapezoidal groove. As described in claim 2, forming the trench in the substrate includes: forming a plurality of stepped dielectric layer stacks on the substrate; and etching the substrate to form the trench using the stepped dielectric layer stacks as masks. As described in claim 3, forming the step-shaped dielectric layer stacks on the substrate includes: forming a dielectric layer stack on the substrate, the dielectric layer stack including a plurality of first dielectric layers and a plurality of second dielectric layers stacked crosswise, the first dielectric layers being made of a first material, and the second dielectric layers being made of a second material different from the first material; and patterning the dielectric layer stack multiple times by a photomask to form the step-shaped dielectric layer stacks. A method as described in claim 3, wherein when the substrate is etched using the step-shaped dielectric layer stacks as masks, the step-shaped dielectric layer stacks and the substrate are etched at the same etching rate. A method as described in any one of claim 1 to claim 5, wherein an angle between the side wall and the bottom surface is determined based on a lattice arrangement direction of the substrate. A semiconductor device comprises: a substrate having a trench extending downward from a top surface of the substrate, the trench having a side wall and a bottom surface, and an angle between the side wall and the bottom surface is greater than or equal to 90 degrees; a gate structure on the substrate and along the top surface of the substrate, the side wall of the trench and the bottom surface; a source contact in the trench of the substrate and penetrating the gate structure to electrically connect to a source region of the substrate; and a drain electrode under the substrate. A semiconductor device as described in claim 7, wherein the trench is an inverted trapezoidal trench. A semiconductor device as described in any one of claim 7 to claim 8, wherein the source region is at the bottom surface of the trench, and the substrate further comprises: a well region along the top surface of the substrate, the sidewalls of the trench and the bottom surface; and an integral contact region at the bottom surface of the trench and adjacent to the source region. A semiconductor device as described in any one of claim 7 to claim 8, wherein the extension direction of the side wall of the trench is the same as a lattice arrangement direction of the substrate.

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