TWI869105B - Alignment detection pattern, alignment detection method and system - Google Patents

Abstract

A kind of alignment detection pattern is used to detect a process pattern unit of a substrate formed after a patterning process, the substrate has at least one circuit area, and the process pattern unit is located in the circuit area. The alignment detection pattern includes an alignment pattern unit formed on the outside of the circuit area, the alignment pattern unit includes a plurality of first alignment patterns located only on one side of two opposite sides of the circuit area along a first direction, and a plurality of second alignment patterns located only on one side of two opposite sides of the circuit area along a second direction. The alignment pattern unit is used as an alignment basis to obtain an alignment detection result of the process pattern unit. The design of the alignment pattern unit can reduce the capture range required for detecting the process pattern unit, thereby improving the detection efficiency. In addition, the present invention also provides an alignment detection method and system.

Description

Alignment detection pattern, alignment detection method and system

The present invention relates to an alignment detection pattern, an alignment detection method and a system, and in particular to an alignment detection pattern, an alignment detection method and a system for a patterning process.

With the development of semiconductor components or integrated circuit boards, the size of their process circuit patterns is getting smaller and the pattern design is getting more complex. As long as the formation position or critical dimension (CD) of the process circuit pattern does not meet expectations, it will affect the electrical connection of the component, and electrical connection failure or short circuit is likely to occur.

Therefore, how to monitor whether the process circuit patterns produced by the patterning process of semiconductor components or integrated circuit boards meet expectations, and use the detection results as a basis for judging whether the position of the process circuit patterns is offset or whether the key dimensions are deviated, so as to use this as a basis for adjusting the parameters of the next patterning process, thereby improving the accuracy of the patterning process, is an important topic in related fields.

In addition, the industry usually forms an alignment pattern in the patterning process that is located in the same or different layers as the process circuit pattern and frames the process circuit pattern, and uses this as a comparison basis to determine whether the process circuit pattern meets expectations. However, due to the instrument limitations of existing inspection equipment (e.g., electron microscopes), the number of circuit process patterns in the same inspection is limited by the field of view of the inspection equipment used to capture images, resulting in poor efficiency of alignment inspection.

Therefore, the purpose of the present invention is to provide an alignment detection pattern for detecting a process pattern unit formed on a substrate after a patterning process. The substrate has at least one square circuit area, and the process pattern unit is located in the at least one circuit area.

Therefore, the alignment detection pattern of the present invention includes an alignment pattern unit.

The alignment pattern unit is formed outside the at least one circuit area, including a plurality of first alignment patterns located only on one side of two opposite sides of the at least one circuit area along a first direction, and a plurality of second alignment patterns located only on one side of two opposite sides of the at least one circuit area along a second direction.

The first direction and the second direction are orthogonal to each other, the first pairs of bit patterns are arranged at intervals along the second direction and have the same pitch, and the second pairs of bit patterns are arranged at intervals along the first direction and have the same pitch.

Another object of the present invention is to provide a method for detecting a process pattern unit formed on a substrate after a patterning process, wherein the substrate has at least one square circuit area, and the process pattern unit and an alignment detection pattern corresponding to the process pattern unit and as described above are located in the at least one circuit area.

Therefore, the alignment detection method of the present invention includes a selection step, an alignment step, and a comparison step.

The selecting step is to extract a detection area from the substrate, wherein the detection area has the at least one circuit area, the process pattern unit, and the alignment detection pattern.

The alignment step is to align the alignment pattern unit of the alignment detection pattern in the detection area with a preset alignment information.

The comparison step is to compare the process pattern unit with a preset process information after the alignment step to obtain an alignment detection result.

The default alignment information is a default alignment pattern or a alignment reference value corresponding to the alignment pattern unit, and the default process information is a default process pattern or a default value corresponding to the process pattern unit.

Another object of the present invention is to provide an alignment detection system for detecting a process pattern unit formed on a substrate after a patterning process, wherein the substrate has at least one square circuit area, and the process pattern unit and an alignment detection pattern corresponding to the process pattern unit and as described above are located in the at least one circuit area.

Therefore, the alignment detection system of the present invention includes a selection unit, an alignment unit, and a comparison unit.

The selection unit is used to extract a detection area from the substrate, and the detection area has the at least one circuit area, the process pattern unit, and the alignment detection pattern.

The alignment unit is connected to the selection unit signal to align the alignment pattern unit of the alignment detection pattern with a preset alignment information.

The comparison unit is connected to the alignment unit signal to compare the process pattern unit with a preset process information to obtain an alignment detection result.

The default alignment information is a default alignment pattern or a alignment reference value corresponding to the alignment pattern unit, and the default process information is a default process pattern or a default value corresponding to the process pattern unit.

The effect of the present invention is that by utilizing a pattern design that allows the alignment pattern unit to be formed only on one of the two side edges of at least one circuit area spaced along the same direction, the process pattern unit can be inspected and the capture range required for monitoring the process pattern unit can be reduced. Therefore, in the same alignment inspection, a larger number of process pattern units or circuit areas can be captured within the field of view of the inspection equipment, thereby improving the inspection efficiency.

Before the present invention is described in detail, it should be noted that similar components are represented by the same number in the following description. In addition, it should be noted that the drawings of the present invention are only for representing the relative relationship between the structure and/or position of the components, and are not related to the actual size of each component.

Referring to FIG. 1 , an embodiment of the alignment detection pattern 200 of the present invention is formed on a substrate (not shown) through a patterning process, and is used to detect the process result of a process pattern unit 11 formed on the substrate through the patterning process. In this embodiment, the alignment detection pattern 200 and the process pattern unit 11 are obtained through the same patterning process and formed on the substrate (not shown).

The substrate has a circuit area 10 which is roughly square. The process pattern unit 11 has a plurality of process patterns 111 and is located in the circuit area 10. The alignment detection pattern 200 is used as an alignment reference to assist in alignment detection of the process patterns 111 within a capture range (i.e., the range of the circuit area 10). The substrate is selected from a semiconductor substrate, a circuit board, a glass substrate, a metal substrate, or an insulating substrate. The process patterns 111 can be selected from at least one of lithography patterns, circuits, trenches, or holes.

Specifically, the alignment detection pattern 200 includes an alignment pattern unit 2, a first auxiliary pattern 3, and a plurality of second auxiliary patterns 4.

The alignment pattern unit 2 is formed on the outer side of the circuit area 10, and includes a plurality of first alignment patterns 21 located only on one side of two opposite sides of the circuit area 10 along a first direction X, and a plurality of second alignment patterns 22 located only on one side of two opposite sides of the circuit area 10 along a second direction Y. The first direction X and the second direction Y are orthogonal to each other, and the center lines passing through the centers of the first alignment patterns 21 (such as the extended dotted lines in FIG. 1 ) are respectively orthogonal to the center lines passing through the centers of the second alignment patterns 22 (such as the extended dotted lines in FIG. 1 ), and a plurality of alignment intersections S arranged in an array are defined in the circuit area 10. Specifically, the center line of each first alignment pattern 21 passes through the center position of the two opposite sides of the first alignment pattern 21 along the second direction Y, and extends along the first direction X and toward the wiring area 10. The center line of each second alignment pattern 22 passes through the center position of the two opposite sides of the second alignment pattern 22 along the first direction X, and extends along the second direction Y and toward the wiring area 10, and the center lines of the first and second alignment patterns 21 and 22 respectively intersect in the wiring area 10 to define the alignment intersections S.

The first alignment patterns 21 and the second alignment patterns 22 are obtained through a patterning process, and are respectively selected from lithography patterns, circuits, trenches or holes, and can be the same or different from each other. In this embodiment, the alignment pattern unit 2 and the process pattern unit 11 are obtained by the same patterning process, and the first alignment patterns 21 and the second alignment patterns 22 are arranged at intervals along the second direction Y and the first direction X, respectively, and have the same pitch. However, in actual implementation, the first alignment patterns 21 and the second alignment patterns 22 can also have different pitches, and are not limited to this.

The first auxiliary pattern 3 and the alignment pattern unit 2 are obtained by the same patterning process, and may be formed correspondingly on at least one of the first alignment patterns 21 and the second alignment patterns 22, adjacent to or far from the bottom edge of the circuit area 10 and connected to the bottom edge thereof, so as to increase the attachment area of the alignment pattern unit 2 on the substrate and prevent the alignment pattern unit 2 from being peeled off from the substrate. In this embodiment, the first auxiliary pattern 3 extends along the first direction X and the second direction Y respectively and is connected to form an L shape, and is connected to the first alignment patterns 21 and the second alignment patterns 22 in the opposite direction to the bottom edge of the circuit area 10, and forms a comb-shaped pattern with the first alignment patterns 21 and the second alignment patterns 22.

In other embodiments, the first auxiliary pattern 3 may be a strip-shaped strip corresponding to only one of the first alignment patterns 21 and the second alignment patterns 22 and opposite to the circuit area 10, or the first auxiliary pattern 3 may be composed of two independently elongated strip-shaped auxiliary patterns (not shown) each formed on the bottom edge of the first alignment patterns 21 and the second alignment patterns 22 opposite to the circuit area 10.

The second auxiliary patterns 4 are located on a side of the circuit area 10 opposite to at least one of the first alignment patterns 21 and the second alignment patterns 22 and are arranged at intervals along the side corresponding to the circuit area 10 to demarcate the boundary of the circuit area 10 . In addition to enabling the image of the capture range to be detected to be more clearly identified when the process pattern unit 11 is subsequently detected, the second auxiliary patterns 4 can also be used to improve the uniformity of the circuit density of the semiconductor patterning process (such as etching, yellow light, thin film, diffusion, CMP, etc.), so that the circuit density of the process patterns 111 adjacent to the edge of the circuit area 10 remains consistent, thereby improving the uniformity of the circuit density of the entire process pattern unit 11 in the circuit area 10, which is beneficial to improving the loading effect or proximity effect of the patterning process.

In this embodiment, the second auxiliary patterns 4 are formed on the two sides of the circuit area 10 opposite to the first alignment patterns 21 and the second alignment patterns 22 (as shown in FIG. 1 ), and the second auxiliary patterns 4 are arranged in a staggered manner at equal distances, so that the bottom edges adjacent to and far from the circuit area 10 are not located on the same straight line.

However, in some embodiments, the shape, size and arrangement of the second auxiliary patterns 4 may vary according to different detection requirements. For example, the second auxiliary patterns 4 may be arranged at non-equidistant intervals, or may be located in the same straight line adjacent to or far from one of the bottom edges of the circuit area 10. In other embodiments, the second auxiliary patterns 4 may be arranged in several rows and aligned on the side of the circuit area 10, or the second auxiliary patterns 4 may be arranged in several rows and staggered with the second auxiliary patterns 4 in the adjacent rows.

In some embodiments, the alignment detection pattern 200 may also include only the alignment detection unit 2 as shown in FIG. 2 , without the first auxiliary pattern 3 and the second auxiliary patterns 4 being provided.

Referring to FIG. 3 , it should be noted that in other embodiments, the substrate may also have a plurality of circuit regions 10. FIG. 3 takes four circuit regions 10 as an example, and the process patterns 111 are distributed in the circuit regions 10. Specifically, in this embodiment, the first alignment patterns 21 and the second alignment patterns 22 formed on the substrate after the patterning process intersect in a cross, and four quadrant regions are defined on the substrate, and the four circuit regions 10 are respectively located in the four quadrant regions, and the process patterns 111 of the process pattern unit 11 are distributed in the circuit regions 10. Therefore, the first alignment patterns 21 and the second alignment patterns 22 can be used as alignment references for the process patterns 111 in the two adjacent circuit regions 10 at the same time.

Referring to FIG. 4 , in another embodiment, the process pattern unit 11 may be obtained by different (previous and next) patterning processes, and the alignment pattern unit 2 also has a plurality of patterns corresponding to the previous and next patterning processes simultaneously generated. The different patterning processes may be selected from the same or different types of processes, such as laser perforation, mask lithography, etching or deposition processes. Specifically, the process pattern unit 11 has a plurality of first process patterns 111a and a plurality of second process patterns 111b formed by different (previous and next) patterning processes. The first alignment patterns 21 and the second alignment patterns 22 of the alignment pattern unit 2 are respectively composed of a plurality of first patterns 211, 221 and a plurality of second patterns 212, 222. The first patterns 211, 221 and the first process patterns 111a are obtained through the same patterning process, and the second patterns 212, 222 and the second process patterns 111b are obtained through the same patterning process. The first patterns 211, 221 and the second patterns 212, 222 are alternately arranged and have the same pitch.

Compared to the existing alignment pattern that is framed around the process circuit pattern, the alignment pattern unit 2 of the alignment detection pattern 200 of the present invention is only formed on one of the two side edges of the circuit area 10 spaced in the same direction, so that the process patterns 111 can be detected, and the capture range required for monitoring the process patterns 111 can be reduced. Therefore, in the same alignment detection, a larger number of process patterns 111 or circuit areas 10 can be captured within the field of view of the detection equipment, thereby improving the detection efficiency.

1 , 6 and 7 , an alignment detection method for detecting a patterning process using the alignment detection pattern 200 is described below in accordance with an embodiment.

The alignment detection method is performed using an alignment detection system, and the alignment detection system includes a selection unit 61, an alignment unit 62, a comparison unit 63, and a feedback unit 64.

The selection unit 61 is used to extract a detection area 100 from the substrate. The detection area 100 includes at least one circuit area 10, the process pattern unit 11 formed in the at least one circuit area 10 after the patterning process, and the alignment detection pattern 200 corresponding to the process pattern unit 11 and as described above.

The alignment unit 62 is signal-connected to the selection unit 61 to align the alignment pattern unit 2 of the alignment detection pattern 200 with a preset alignment information of a preset data. The preset data has the preset alignment information corresponding to the alignment pattern unit 2 and the preset process information corresponding to the process pattern unit 11. The preset alignment information can be a preset alignment pattern corresponding to the alignment pattern unit 2 or a alignment reference value. The preset process information can be a preset process pattern or a preset value corresponding to the process pattern unit 11. The preset process pattern and the preset alignment pattern may be taken from image data system GDSII, OASIS, MEBES format image data, mask pattern, or hole array pattern according to different types of patterning processes. The alignment reference value may be the center value, coordinate value, or center intersection coordinate value of the alignment pattern unit 2, and the preset value may be at least one of the position, key size, area, curvature, and edge placement error (EPE) of the process pattern unit 11.

The comparison unit 63 is signal-connected to the alignment unit 62 for comparing the process pattern unit 11 with the preset process information to obtain an alignment detection result.

The feedback unit 64 is signal-connected to the comparison unit 63, and generates a warning signal, a pattern data correction parameter, or a process adjustment parameter for outputting feedback to the next patterning process according to the alignment detection result.

Specifically, the embodiment of the alignment detection method includes a selection step 71, an alignment step 72, a comparison step 73, and an adjustment parameter acquisition step 74.

Taking the alignment detection pattern 200 having the structure shown in FIG. 1 and being formed through the same patterning process as the process pattern unit 11 as an example, the selection step 71 is to utilize the selection unit 61 to extract the detection area 100 from the substrate, and the detection area 100 has a circuit area 10, the process pattern unit 11 located in the circuit area 10, and the alignment detection pattern 200 located outside the circuit area 10.

The alignment step 72 is to align the alignment pattern unit 2 with the preset alignment information of the preset data by using the alignment unit 62. In the present embodiment, the alignment step 72 is to align the alignment intersections S generated by the first alignment patterns 21 and the second alignment patterns 22 in the circuit area 10 with the preset alignment intersections of the corresponding preset alignment information, so as to synchronously move and adjust the first alignment patterns 21, the second alignment patterns 22 and the process pattern units 11 to align the alignment intersections S with the preset alignment intersections.

The comparison step 73 is performed after the alignment step 72 , using the comparison unit 63 to compare the process pattern unit 11 with the preset process information of the preset data to obtain the alignment detection result of the process pattern unit 11 .

In detail, the comparison step 73 uses the comparison unit 63 to compare the difference between the process pattern unit 11 and the preset process information to obtain a difference information. Afterwards, the comparison unit 63 compares the difference information with a standard value to obtain the alignment detection result. The difference information can be at least one of the position difference, key size difference, area difference, curvature difference, and edge placement difference between the process patterns 111 and the preset process information according to the type of the preset process information. The standard value is a process allowable parameter or is user-defined. In this embodiment, the process patterns 111 are moved and/or stretched and scaled until the process patterns 111 are consistent with the key dimensions of the preset process information, and adjustment parameters for moving and/or stretching the process patterns 111 are obtained as the difference information related to the key dimensions.

Next, the adjustment parameter acquisition step 74 is performed, and the feedback unit 64 is used to obtain the process adjustment parameters corresponding to the process pattern unit 11 according to the alignment detection result, so as to be used as the parameter adjustment basis for the next patterning process. In some embodiments, the adjustment parameter acquisition step 74 obtains the pattern data correction parameters corresponding to the process pattern unit 11 according to the alignment detection result as the correction basis for the pattern data, for example, as the correction basis for the mask pattern data or the laser parameter data, so that the next patterning process can generate the process pattern according to the corrected pattern data.

It should be noted that when the difference information obtained in the comparison step 73 meets the standard value, or the difference between the process pattern unit 11 and the preset data is not large, it can be regarded that the process pattern unit 11 meets expectations, and there is no need to execute the adjustment parameter acquisition step 74.

In addition, when the difference information obtained by the comparison unit 63 exceeds the standard value, or the alignment detection result does not meet expectations, the warning signal can be issued via the feedback unit 64.

In some embodiments, the default process information is the default process pattern, and the process patterns 111 and the default process pattern are hole array patterns suitable for a circuit board. The comparison step 73 is to compare the formation positions or key dimensions between the process patterns 111 and the default process pattern to obtain position differences or key dimension differences. Afterwards, the process adjustment parameters or the pattern data correction parameters are obtained in the adjustment parameter acquisition step 74. The process adjustment parameter may be an adjustment parameter related to the position or size of the hole array pattern, or a power adjustment parameter of a laser beam or an electron beam used to prepare the hole array pattern, and the pattern data correction parameter may be laser-related parameter data (such as laser power, laser position, etc.).

Referring to FIG. 4 , FIG. 6 and FIG. 7 , in another embodiment, when the process pattern unit 11 has a process pattern 111 (i.e., a first process pattern 111a and a second process pattern 111b) generated by different (previous and next) patterning processes as shown in FIG. 4 , the alignment detection pattern 200 has a plurality of first patterns 211 and 221 generated by the same patterning process as the first process patterns 111a, and a plurality of second patterns 212 and 222 generated by the same patterning process as the second process patterns 111b. And the first alignment patterns 21 and the second alignment patterns 22 are respectively composed of the first patterns 211 and 221 and the second patterns 212 and 222. The alignment step 72 of the alignment detection method is to adjust the alignment based on the pattern formed by one of the patterning processes and the corresponding preset alignment information, and compare the preset process information with the pattern formed by the other patterning process after alignment. Taking the first patterns 211 and 221 as a reference, the alignment step 72 is to synchronously move and/or stretch and scale the first patterns 211 and 221 and the first process patterns 111a to adjust the first patterns 211 and 221 to align with the corresponding preset alignment information. Afterwards, the process pattern 111 (ie, the second process patterns 111b) obtained by another patterning process can be compared with the corresponding preset process information through the comparison step 73 to obtain the alignment detection results of different patterning processes.

In addition, the aforementioned alignment step 72 may also be to first adjust the alignment based on the alignment pattern formed by the same patterning process and the corresponding preset alignment information, and then adjust the alignment for the second time with the alignment pattern formed by another same patterning process and the corresponding preset alignment information, and then perform the comparison step 73. In detail, using the first patterns 211, 221 as a reference, the alignment step 72 is to synchronously move and/or stretch and scale the first patterns 211, 221 and the first process patterns 111a until the first patterns 211, 221 are aligned with the corresponding preset alignment information, and then synchronously move and/or stretch and scale the second patterns 212, 222 and the second process patterns 111b to align with the corresponding preset alignment information of the second patterns 212, 222. Thereafter, the comparison step 73 is performed to compare the first process patterns 111a and/or the second process patterns 111b with the preset process information to obtain the alignment detection results of the two patterning processes.

Referring to FIG. 5 , FIG. 6 and FIG. 7 , in other embodiments, when the default alignment information and the default process information are image information, the default alignment information is a plurality of default alignment patterns 501 corresponding to the alignment pattern unit 2, and the default process information is a plurality of default process patterns 502 corresponding to the process pattern unit 11. The alignment step 72 can be performed by image overlay. The comparison step 73 can compare the image contour difference (key size difference) between the default process patterns 502 and the process patterns 111 to obtain the key size difference information. When the difference information exceeds the standard value, the process adjustment parameter or the pattern data correction parameter can be obtained through the adjustment parameter acquisition step 74, or the warning signal can be issued through the feedback unit 64 and/or the position where the image contour difference between the process patterns 111 and the preset process patterns 502 exceeds the standard value can be marked on the image.

In addition, when the alignment step 72 is performed by aligning the image of the alignment pattern unit 2 with the image of the preset alignment patterns 501, the comparison step 73 can use the measured pixel values (Pixel number) or the measured pitch values obtained by measuring the first alignment patterns 21 and the second alignment patterns 22 along different directions and perform a ratio operation with the corresponding pixel values (Pixel number) or pitch values of the preset alignment patterns 501 to obtain difference information related to the pixel value or the pitch value to obtain the alignment detection result.

In addition, the comparison step 73 may also be to compare the differences between the process patterns 111 and the preset process patterns 502 along the second direction Y to obtain the difference information along the second direction Y, and/or to compare the differences between the process patterns 111 and the preset process patterns 502 along the first direction X to obtain the difference information along the first direction X. Thereafter, in the adjustment parameter acquisition step 74, the images of the process patterns 111 may be adjusted along the first direction X and the second direction Y in the same or different proportions according to the difference information to obtain the process adjustment parameters related to the first and second directions X and Y, respectively.

In summary, the present invention utilizes the method of forming the alignment pattern unit 2 only on one of the two side edges of the circuit area 10 spaced apart in the same direction, so as to detect the process patterns 111 and reduce the capture range required for monitoring the process patterns 111. Therefore, in the same alignment detection, a larger number of process patterns 111 or circuit areas 10 can be captured within the field of view of the detection equipment, thereby improving the detection efficiency. By using the alignment pattern unit 2 as an alignment reference for the preset alignment information of the preset data, the difference between the process patterns 111 generated by the corresponding patterning process and the preset process information of the preset data can be obtained through comparison, thereby obtaining the alignment detection result of the patterning process, and the process adjustment parameters or the pattern data correction parameters can be obtained accordingly to optimize the next patterning process, so that the purpose of the present invention can be achieved.

However, the above is only an embodiment of the present invention and should not be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the present patent.

100: Detection area

10: Line area

11: Process pattern unit

111: Processing diagram

111a: First process pattern

111b: Second process pattern

200: Alignment detection pattern

2: Alignment pattern unit

21: The first alignment pattern

22: Second alignment pattern

211, 221: First pattern

212, 222: Second pattern

3: First auxiliary pattern

4: Second auxiliary pattern

501: Default alignment pattern

502: Default process pattern

61: Select unit

62: Alignment unit

63: Comparison unit

64: Feedback Unit

71:Select step

72: Alignment Step

73:Comparison step

74: Adjust parameter acquisition steps

X: First direction

Y: Second direction

S: Intersection point

Other features and effects of the present invention will be clearly presented in the implementation method with reference to the drawings, in which: FIG1 is a schematic diagram illustrating an implementation example of the alignment detection pattern of the present invention; FIG2 is a schematic diagram illustrating an implementation example in which the alignment detection pattern is not provided with the first auxiliary pattern and the second auxiliary pattern; FIG3 is a schematic diagram illustrating another implementation example of the alignment detection pattern; FIG4 is a schematic diagram illustrating an implementation example in which the alignment detection pattern is obtained by the previous and subsequent patterning processes; FIG5 is a schematic diagram illustrating the alignment relationship between the process pattern unit and the preset process pattern after the alignment detection pattern is aligned; FIG6 is a flow diagram illustrating an implementation example of the alignment detection method of the present invention; and FIG7 is a schematic diagram illustrating an alignment detection system used to execute the alignment detection method.

100: Detection area

10: Line area

11: Process pattern unit

111: Process diagram

200: Alignment detection pattern

2: Alignment pattern unit

21: The first alignment pattern

22: Second alignment pattern

3: The first auxiliary pattern

4: Second auxiliary pattern

X: First direction

Y: Second direction

S: Alignment intersection

Claims (13)

A positioning detection pattern is used to detect a process pattern unit formed on a substrate after a patterning process, the substrate having at least one circuit area and the at least one circuit area is in a square shape, the process pattern unit is located in the at least one circuit area, the positioning detection pattern comprises: a positioning pattern unit formed on the outer side of the at least one circuit area, including a plurality of first positioning patterns only located on one side of two opposite sides of the at least one circuit area along a first direction, and a plurality of first positioning patterns only located on one side of the at least one circuit area along a second direction. A second alignment pattern on one of the two opposite sides of the direction; and a first auxiliary pattern formed on one of the bottom sides of the first alignment patterns and/or the second alignment patterns, and connected to the bottom sides of the corresponding first alignment patterns and/or the second alignment patterns, wherein the first direction and the second direction are orthogonal to each other, the first alignment patterns are arranged at intervals along the second direction and have the same pitch, and the second alignment patterns are arranged at intervals along the first direction and have the same pitch. As described in claim 1, the alignment detection pattern, wherein the first alignment patterns and the second alignment patterns intersect in a cross shape, and four quadrant areas are defined on the substrate, the substrate has four circuit areas respectively located in the four quadrant areas, and the process pattern units are distributed in the circuit areas. The alignment detection pattern as described in claim 1 or 2 also includes a plurality of second auxiliary patterns, which are arranged at intervals and located on a side of any circuit area opposite to at least one of the first alignment patterns and the second alignment patterns. As described in claim 1 or 2, the alignment detection pattern, wherein the process pattern unit has a plurality of first process patterns and second process patterns respectively generated by the previous and subsequent patterning processes, the first alignment patterns and the second alignment patterns are respectively composed of a plurality of first patterns and a plurality of second patterns, and the first process patterns and the first patterns, and the second process patterns and the second patterns are each obtained through the same patterning process. The alignment detection pattern as described in claim 1 or 2, wherein the substrate is selected from a semiconductor substrate, a circuit board, a glass substrate, a metal substrate or an insulating substrate, and the first alignment patterns and the second alignment patterns are selected from lithography patterns, lines, trenches or holes, and may be the same or different. A method for detecting a position alignment is used to detect a process pattern unit formed on a substrate after a patterning process, the substrate having at least one circuit area and the at least one circuit area is square, the process pattern unit and a position alignment detection pattern corresponding to the process pattern unit and as described in claim 1 are located in the at least one circuit area, the method comprising: a selection step, extracting a detection area from the substrate, the detection area having the at least one circuit area, the process pattern unit, and the position alignment detection pattern ; a registration step, aligning the registration pattern unit of the registration detection pattern of the detection area with a preset registration information; and a comparison step, after the registration step, comparing the process pattern unit with a preset process information to obtain a registration detection result, wherein the preset registration information is a preset registration pattern or a registration reference value corresponding to the registration pattern unit, and the preset process information is a preset process pattern or a preset value corresponding to the process pattern unit. As described in claim 6, the alignment detection method, wherein the comparison step is to obtain a difference information by comparing the difference between the process pattern unit and the preset process information, and compare the difference information with a standard value to obtain the alignment detection result, wherein the standard value is a process allowable parameter or is user-defined. The alignment detection method as described in claim 6 further includes an adjustment parameter acquisition step performed after the comparison step, and a process adjustment parameter or a pattern data correction parameter corresponding to the process pattern unit is obtained according to the alignment detection result, for use as a parameter adjustment basis for the next patterning process. As described in claim 6, the alignment detection method, wherein the process pattern unit has a plurality of first process patterns and second process patterns respectively generated by the previous and subsequent patterning processes, the first alignment patterns and the second alignment patterns are respectively composed of a plurality of first patterns and a plurality of second patterns, the first process patterns and the first patterns, and the second process patterns and the second patterns are respectively generated by the same patterning process. The default alignment information corresponds to the first patterns and the second patterns respectively, the default process information corresponds to the first process patterns and the second process patterns respectively, the alignment step is to align the first patterns with the corresponding default alignment information based on the first patterns, and the comparison step is to compare the process pattern unit after the alignment step with the default process information to obtain the alignment detection result of the process pattern unit. As described in claim 9, the alignment detection method, wherein the alignment step is to align the first patterns with the corresponding preset alignment information based on the first patterns, and then further adjust the second patterns to align with the corresponding preset alignment information, and then perform the comparison step. As described in claim 7, the alignment detection method, wherein the preset value refers to at least one of the position, key size, area, curvature, and edge placement error of the process pattern unit, and the difference information refers to at least one of the position difference, key size difference, area difference, curvature difference, and edge placement error between the process pattern unit and the preset process information. A positioning detection system is used to detect a process pattern unit formed on a substrate after a patterning process, the substrate having at least one square circuit area, the process pattern unit and an alignment detection pattern corresponding to the process pattern unit and as described in claim 1 are located in the at least one circuit area, the positioning detection system comprises: a selection unit, used to extract a detection area from the substrate, the detection area having the at least one circuit area, the process pattern unit, and the alignment detection pattern; an alignment unit , connected to the selection unit signal, used to align the alignment pattern unit of the alignment detection pattern with a preset alignment information; and a comparison unit, connected to the alignment unit signal, used to compare the process pattern unit with a preset process information to obtain an alignment detection result, wherein the preset alignment information is a preset alignment pattern or an alignment reference value corresponding to the alignment pattern unit, and the preset process information is a preset process pattern or a preset value corresponding to the process pattern unit. The alignment detection system as described in claim 12 further includes a feedback unit connected to the comparison unit signal, which generates a process adjustment parameter, a pattern data correction parameter, or a warning signal for outputting a feedback to the next patterning process according to the alignment detection result.