TWI868931B - Pulse Width Modulation System - Google Patents

Abstract

The present invention discloses a pulse width modulation system, comprising: a direct current power source, a load powered by the direct current power source, a P-type metal oxide semiconductor field effect transistor (P-Metal-Oxide-Semiconductor Field-Effect Transistor, P-MOSFET) for controlling the voltage on the load, and a switch control unit for controlling the turning off and on of the P-MOSFET, wherein the switch control unit is connected to the gate of the P-MOSFET and is used to generate a pulse width modulation (Pulse Width Modulation, PWM) signal for controlling the turning off and on of the P-MOSFET to generate a constant target setting voltage on the load.

Description

Pulse Width Modulation System

The present invention relates to the field of circuits, and in particular to a pulse width modulation system.

In the field of consumer electronic products, there are many application scenarios where the input voltage is not fixed, but a fixed output voltage is required to achieve a constant load demand. For example, the electronic cigarette system is generally powered by batteries or charging equipment. As the battery is consumed, the voltage continues to decrease, but the output requires a fixed application voltage so that the electronic cigarette can maintain a consistent heating effect. The traditional approach is to use a closed-loop control system, which samples the output voltage and adjusts it through a loop to achieve precise control of the output voltage, but this system is often more complex and requires more external devices, and is not suitable for systems with small peripheral sizes.

According to an embodiment of the present invention, a pulse width modulation system is provided, comprising: a DC power supply, a load powered by the DC power supply, a P-type metal oxide semiconductor field effect transistor (P-MOSFET) for controlling the voltage on the load, and a switch control unit for controlling the turning off and on of the P-MOSFET, wherein the switch control unit is connected to the gate of the P-MOSFET and is used to generate a pulse width modulation PWM signal for controlling the turning off and on of the P-MOSFET to generate a constant target setting voltage on the load.

In one embodiment, the switch control unit includes a follower, a ramp signal generator, an oscillator, a reference signal generator and a comparator, wherein the input end of the follower is connected to the positive electrode of the DC power supply and the output end is connected to the first input end of the ramp signal generator, the output end of the oscillator is connected to the second input end of the ramp signal generator, the output end of the ramp signal generator is connected to the positive input end of the comparator, and the output end of the reference signal generator is connected to the positive input end of the comparator. The comparator is connected to the negative input terminal of the comparator, and the output terminal of the comparator is connected to the gate of the P-MOSFET, wherein the oscillator is used to generate a clock signal with a period of T and generate a ramp signal reset pulse signal with the same period at the rising edge of each clock, the ramp signal generator is used to output the ramp signal when the ramp signal reset pulse signal is at a low level, and the comparator is used to generate the PWM signal by comparing the ramp signal with the reference reference signal generated by the reference signal generator.

In one embodiment, at the beginning of each clock cycle T, the ramp signal generator reduces the output to 0 because the ramp signal reset pulse signal is at a high level, at which time the PWM signal turns to a low level and the P-MOSFET turns on; when the ramp signal reset pulse signal becomes a low level, the ramp signal generator generates the ramp signal, and when the ramp signal is equal to the reference signal, the PWM signal turns to a high level and the P-MOSFET turns off.

In one embodiment, the follower includes an operational amplifier, a resistor, the input P-MOSFET of a P-MOSFET current mirror formed by an input P-MOSFET and an output P-MOSFET, and an N-type metal oxide semiconductor field effect transistor (N-Metal-Oxide-Semiconductor Field-Effect Transistor, N-MOSFET) follower, wherein the positive input terminal of the operational amplifier is connected to the DC power supply and the negative input terminal is connected to the first end of the resistor, the second end of the resistor is grounded, the gate of the N-MOSFET follower is connected to the output terminal of the operational amplifier, the source is connected to the first end of the resistor, and the drain is connected to the input P-MOSFET of the P-MOSFET current mirror; the ramp signal generator includes the output P-MOSFET of the current mirror, a first capacitor, and In the embodiment, the first end of the first capacitor is connected to the output P-MOSFET and the second end of the first capacitor is grounded. The ramp signal generated by the ramp signal generator is the voltage on the first capacitor. The first capacitor is connected in parallel with the ramp signal reset pulse switch. When the ramp signal reset pulse signal is at a high level, the ramp signal reset pulse switch is closed to discharge the first capacitor. When the ramp signal reset pulse signal is at a low level, the ramp signal reset pulse switch is opened to charge the first capacitor through the current mirror.

In one embodiment, the reference signal generated by the reference signal generator is a fixed voltage.

In one embodiment, the reference signal generated by the reference signal generator is not a fixed voltage.

In one embodiment, the circuit of the reference signal generator periodically refreshes the base reference voltage by multiplexing the circuit of the ramp signal generator.

In one embodiment, the refresh period of the reference signal is (1+n)T.

In one embodiment, the reference signal generator includes a second capacitor, a first gate, and a reference signal reset pulse switch, wherein a first end of the second capacitor is connected to an output P-MOSFET of the current mirror through the first gate and a second end is grounded, and the second capacitor is connected in parallel with the reference signal reset pulse switch to realize charging and discharging of the second capacitor by controlling the opening and closing of the reference signal reset pulse switch by the reference signal reset pulse signal. The ramp signal generator further comprises a second gate, and the first capacitor of the ramp signal generator is connected to the output P-MOSFET of the current mirror through the second gate; and the target setting voltage for the load is input to the positive input terminal of the operational amplifier of the follower through the first gate, and the DC power supply is input to the positive input terminal of the operational amplifier of the follower through the second gate.

In one embodiment, the period of the reference signal reset pulse signal is (1+n)T, where n is a positive integer.

In one embodiment, at the beginning of the first clock cycle T, the reference signal reset pulse signal is at a high level, at which time the reference signal reset pulse switch is closed to discharge the second capacitor; when the reference signal reset pulse signal becomes a low level, the first gate is closed to gate the target setting voltage, at which time the first current I1 is generated on the resistor through the follower, and the The current mirror sends the first current I1 into the second capacitor to charge it. When the first clock cycle T ends, the first gate is disconnected, and the first reference voltage maintained on the second capacitor is generated at this time. At the beginning of the second clock cycle, the first gate is disconnected and the second gate is closed to select the voltage of the DC power supply, and then the second current I2 is generated on the resistor through the follower. The current mirror sends the second current I2 into the first capacitor to charge it. The ramp signal generator sends the ramp signal generated according to the voltage on the first capacitor to the comparator to compare with the first reference voltage, thereby generating the PWM signal. When the second clock cycle ends, the ramp signal resets the pulse signal to a high level. , at this time, the ramp signal reset pulse switch is closed to discharge the first capacitor, and then the second gate remains closed for n clock cycles T to continue charging and discharging the first capacitor for n clock cycles; at the beginning of the n+1th clock cycle, the second gate is disconnected and the first gate is closed at the same time to refresh the first reference voltage to the second reference voltage, and the above process is repeated.

In one embodiment, the power supply is a battery.

In one embodiment, the pulse modulation system is used in a discharge circuit of an electronic cigarette system.

According to the above-mentioned embodiment provided by the present invention, an open-loop pulse width adjustment circuit with a simple structure and good control of output accuracy is provided. It does not require a complex feedback loop and peripheral devices, greatly simplifying the entire application structure.

100: Discharge circuit

102,302: DC power supply

104: Control unit

106,206,306: Load

202,V _DC : DC voltage

204: Functional circuit

300: Simplified structure for generating high-precision output voltage

304: Switch control unit

308: P-type metal oxide semiconductor field effect transistor (P-MOSFET)

400: Internal structure diagram for generating high-precision output voltage

402: Follower

404: Ramp signal generator

406: Oscillator

408: Reference signal generator

410: Comparator

601: Operational amplifier

602: Input P-MOSFET

603: Output P-MOSFET

604: N-MOSFET follower

605:Resistance

606: First capacitor

607: Ramp signal resets pulse switch

701: First selector

702: Second selector

703: Second capacitor

704: Reference signal resets pulse switch

C: Capacitor

CLK: signal

GATE, Vtarget: voltage

I: Current

I1: first current

I2: Second current

L: Output inductance

pg: The power supply meets the requirements

PWM: Pulse Width Modulation

Reset Pulse: Ramp signal resets the pulse signal

T: First clock cycle

VR: output voltage

Vramp: Ramp signal (ramp voltage)

Vref Reset Pulse: Reference voltage reset pulse signal

Vref: reference signal voltage

The present invention can be better understood from the following description of the specific implementation of the present invention in conjunction with the drawings, wherein:

Figure 1 shows a simple schematic diagram of a typical DC power supply discharge circuit.

Figure 2 shows a schematic diagram of the discharge circuit of a DC power supply implemented with DC/DC (DC-DC).

FIG3 shows a schematic diagram of a discharge circuit of a DC power supply implemented with a transistor according to an embodiment of the present invention.

FIG4 shows a schematic diagram of an implementation of a switch control unit of the discharge circuit shown in FIG3 according to an embodiment of the present invention.

FIG5 shows a timing waveform diagram of multiple signals in the switch control unit shown in FIG4 according to an embodiment of the present invention.

FIG6 shows a circuit diagram of the switch control unit shown in FIG3 according to an embodiment of the present invention.

FIG7 shows another circuit diagram of the switch control unit shown in FIG4 according to an embodiment of the present invention.

FIG8 shows a timing diagram of the implementation of the switch control unit shown in FIG7 according to an embodiment of the present invention.

The features and exemplary embodiments of various aspects of the present invention are described in detail below. In the detailed description below, many specific details are set forth in order to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without some of these specific details. The following description of the embodiments is intended only to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is in no way limited to any specific configuration set forth below, but rather covers any modification, substitution, and improvement of elements, components, and algorithms without departing from the spirit of the present invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary ambiguity of the present invention. In addition, it should be noted that the term "A and B are connected" used here can mean "A and B are directly connected" or "A and B are indirectly connected via one or more other components."

Fig. 1 shows a simple schematic diagram of a typical discharge circuit 100 of a DC power source. As shown in Fig. 1, the discharge circuit 100 includes a DC power source 102 providing a DC voltage V _DC , a control unit 104, and a load 106, wherein VR represents an output voltage.

In one embodiment, the DC power source 102 may be any device that provides a DC voltage. For example, the DC power source 102 may be a battery, which is not limited in this article.

In one embodiment, the load 106 may be any device that can be powered by a DC power source. For example, the load 106 may be a heating wire, which is not limited in this article.

The discharge circuit 100 works in such a way that, under the condition of being powered by a DC power source 102, a constant average set voltage is generated on the load through a control unit 104. As an example, the discharge circuit 100 can be used in an electronic cigarette system.

Traditionally, a DC-DC structure can be used to achieve output constant voltage, as shown in FIG2, which shows a schematic diagram of a discharge circuit of a DC power supply implemented by DC-DC. In the structure shown in FIG2, the circuit structure is complex, the chip area is large, and the periphery also requires inductors and capacitors, which occupies a large area of the application board and is not suitable for system applications with small peripheral dimensions. Therefore, the present invention proposes a new structure to solve the problem of complex circuit structure and/or low precision of the existing circuit.

FIG3 shows a schematic diagram of a discharge circuit of a DC power supply implemented with a transistor according to an embodiment of the present invention. As shown in FIG3 , the discharge circuit includes a DC power supply 302 providing a DC voltage V _DC , a switch control unit 304, a load 306, and a P-type metal oxide semiconductor field effect transistor (P-MOSFET) 308, wherein VR represents an output voltage. The switch control unit 304 can be used to control the turning off and on of the P-MOSFET 308, thereby controlling the voltage applied to the load.

In one embodiment, the DC power source 302 may be any device that provides a DC voltage, for example, the DC power source 302 may be a battery, which is not limited herein.

In one embodiment, the load 306 may be any device that can be powered by a DC power source. For example, the load 306 may be a heating wire, which is not limited in this document.

In one embodiment, the switch control unit 304 is used to control the GATE voltage of the P-MOSFET 308, thereby generating a square wave pulse on the load, and the average value of this pulse is a set value, thereby achieving a fixed voltage output.

In one embodiment, the switch control unit 304 is implemented as a square wave generating circuit, and the implemented structure is shown in FIG4 , wherein the switch control unit 304 may include: a follower 402, a ramp signal generator 404, an oscillator 406, a reference signal generator 408, and a comparator 410. The DC power supply, load, and P-MOSFET 308 shown in FIG4 have similar structures and functions to the DC power supply, load, and P-MOSFET 308 shown in FIG3 , and are labeled with the same reference numerals, which will not be described in detail here.

In one embodiment, the input terminal of the follower 402 is connected to the positive terminal of the DC power source 302 and the output terminal is connected to the first input terminal of the ramp signal generator 404, the output terminal of the oscillator 406 is connected to the second input terminal of the ramp signal generator 404, the output terminal of the ramp signal generator 404 is connected to the positive input terminal of the comparator 410, the output terminal of the reference signal generator 408 is connected to the negative input terminal of the comparator 410, and the output terminal of the comparator 410 is connected to the gate terminal of the P-MOSFET 308.

The oscillator 406 can be used to generate a clock signal (CLK) with a period of T and generate a ramp signal reset pulse signal with the same period at the rising edge of each clock; the ramp signal generator 404 can be used to discharge the ramp signal to 0 when the ramp signal reset pulse signal is at a high level, and generate a ramp signal Vramp when the ramp signal reset pulse signal is at a low level and directly transmit the generated ramp signal Vramp to the comparator 410; the comparator 410 can be used to generate a PWM signal by comparing the received ramp signal Vramp with the reference signal Vref generated by the reference signal generator 408 to control the P-MOSFET 308.

FIG5 shows a timing waveform diagram of multiple signals in the switch control unit shown in FIG4 according to an embodiment of the present invention, wherein CLK is a square wave signal with a period of T, Reset Pulse is a ramp signal reset pulse signal with the same period generated by CLK, Vramp is a fixed ramp signal, Vref is a reference signal, and PWM is a square wave signal generated to control the P-MOSFET 308 GATE. As can be seen from FIG5, a fixed square wave PWM can be generated by comparing Vramp and Vref.

Specifically, at the beginning of each clock cycle T, the ramp signal generator 404 reduces the output to 0 because the ramp signal reset pulse signal is at a high level, at which time the PWM signal turns to a low level and the P-MOSFET is turned on; when the ramp signal reset pulse signal becomes a low level, the ramp signal generator 404 starts to generate the ramp signal Vramp, and when the ramp signal Vramp is equal to the reference signal Vref, the PWM signal turns to a high level and the P-MOSFET 308 is turned off.

FIG6 shows a circuit diagram of the switch control unit 304 according to an embodiment of the present invention. As shown in FIG6 , the follower 402 may include: an operational amplifier 601, an input P-MOSFET 602 in a P-MOSFET current mirror formed by an input P-MOSFET 602 and an output P-MOSFET 603, an N-type metal oxide semiconductor field effect transistor (N-MOSFET) follower 604, and a resistor 605, wherein the positive input terminal of the operational amplifier 601 is connected to the DC power supply 302 and the negative input terminal is connected to the first end of the resistor 605, the second end of the resistor 605 is grounded, and the gate of the N-MOSFET follower 604 is connected to the output terminal of the operational amplifier 601, the source is connected to the first end of the resistor 605, and the drain is connected to the input P-MOSFET 602 of the P-MOSFET current mirror.

The ramp signal generator 404 includes an output P-MOSFET 603 of a current mirror and a first capacitor 606, wherein a first end of the first capacitor 606 is connected to the output P-MOSFET 603 and a second end of the first capacitor 606 is grounded, and a ramp voltage Vramp generated by the ramp signal generator 404 is a voltage on the first capacitor 606, and the first capacitor 606 is connected in parallel with a ramp signal reset pulse switch 607. When the ramp signal reset pulse signal is at a high level, the ramp signal reset pulse switch is closed to discharge the first capacitor 606, and when the ramp signal reset pulse signal is at a low level, the ramp signal reset pulse switch is opened to charge the first capacitor 606 through the current mirror.

Specifically, when a clock cycle of the oscillator starts, the ramp signal reset pulse signal is at a high level. At this time, the ramp signal reset pulse switch 607 is closed so that all the charges on the first capacitor 606 are discharged. At the same time, the PWM is flipped to a low level, turning on the P-MOSFET 308, and then starting to generate a current I through the resistor 605. The current I charges the first capacitor 606 through the input P-MOSFET 602 and the output P-MOSFET 603 of the image current mirror. The ramp voltage Vramp is the voltage on the first capacitor 606. When the ramp voltage Vramp reaches the reference voltage Vref, the PWM signal output by the comparator 410 is flipped to turn off the P-MOSFET. 308, and then repeat the previous cycle process (see FIG5). The comparator 410 generates a square wave PWM signal with an average value equal to the target value by comparing Vramp and Vref generated by the DC voltage V _DC . The accuracy of the PWM duty cycle determines the accuracy of Vtarget.

Let the output target average voltage be Vtarget, given that:

According to formulas (1) and (2), the desired target average voltage Vtarget can be obtained by properly setting the first capacitor, clock cycle T, reference voltage Vref and resistor.

In one embodiment, the reference voltage Vref generated by the reference signal generator has a fixed voltage value.

However, since the generation of the ramp signal Vramp is affected by the error of the follower 402, the error of the input P-MOSFET 602 and the output P-MOSFET 603 of the current mirror, and the absolute value deviation of the resistor 605 and the first capacitor 606, its variation range is very wide, with a variation of more than +/-50%. If the reference voltage Vref is a fixed voltage, then the large variation range of the ramp signal Vramp will cause the duty cycle of the PWM signal output by the comparator 410 to have the same variation range, thereby resulting in poor accuracy of the PWM output signal. In order to obtain a high-precision PWM output signal and to improve output accuracy, in one embodiment, the reference voltage Vref may not be a fixed voltage. In one embodiment, the circuit of the reference signal generator 408 can reuse the circuit of the ramp signal generator 404 so that the deviations of the two completely follow and are consistent. In one embodiment, the reference signal generator 408 can periodically refresh the reference voltage.

FIG7 shows another circuit diagram of the switch control unit shown in FIG4 according to an embodiment of the present invention, wherein the circuit of the reference signal generator 408 reuses part of the circuit and components of the ramp signal generator 404. The DC power supply, load, and P-MOSFET 308 shown in FIG7 have similar structures and functions to the DC power supply, load, and P-MOSFET 308 shown in FIG3 or FIG4, and are labeled with the same reference numerals, which will not be described again. In addition, the operational amplifier, input P-MOSFET 602 and output P-MOSFET 603 of the current mirror, N-MOSFET follower 604, resistor 605, and first capacitor 606 shown in FIG7 have similar structures and functions as the operational amplifier, input P-MOSFET 602 and output P-MOSFET 603 of the current mirror, N-MOSFET follower 604, resistor 605, and first capacitor 606 shown in FIG6 , and are marked with the same reference numerals, which will not be described in detail here.

As shown in FIG7 , the reference signal generator 408 includes a first gate 701, a second capacitor 703, and a reference signal reset pulse switch 704. The first end of the second capacitor 703 is connected to the output P-MOSFET 603 of the current mirror through the first gate 701 and the second end is grounded, and the second capacitor 703 is connected in parallel with the reference signal reset pulse switch 704 to realize the charging and discharging of the second capacitor 703 by controlling the opening and closing of the reference signal reset pulse switch 704 by the reference voltage reset pulse signal (Vref Reset Pulse).

In one embodiment, the discharge signal of the second capacitor 703 is a reference voltage reset pulse signal at a high level. Specifically, when the reference signal reset pulse signal is at a high level, the reference signal reset pulse switch 704 is closed to discharge the second capacitor 703, and when the reference signal reset pulse signal is at a low level, the reference signal reset pulse switch 704 is opened to charge the second capacitor 703 through the current mirror.

As shown in FIG7 , the ramp signal generator further includes a second gate 702, and the first capacitor 606 of the ramp signal generator is connected to the output P-MOSFET 603 of the current mirror through the second gate 702. The target setting voltage Vtarget for the load is input to the positive input terminal of the operational amplifier 601 of the follower through the first gate 701, and the DC voltage V _DC is input to the positive input terminal of the operational amplifier 601 of the follower through the second gate 702.

The working principle of the circuit structure shown in FIG7 is as follows: first, at the beginning of the first clock cycle T, a discharge signal is generated, that is, the reference voltage reset pulse signal (Vref Reset Pulse) becomes high level, and the charge on the second capacitor 703 is discharged. Then the first gate 701 is closed, and the Vtarget voltage is selected. After the Vtarget voltage is gated, a first current I1 is generated on the resistor 605 through the follower. The current mirror sends the first current I1 to the second capacitor 703 to charge the second capacitor 703. When the clock cycle ends, the charging current is turned off, and the first gate 701 is opened. At this time, the voltage Vref is generated on the second capacitor 703, and then Vref is maintained on the second capacitor 703. In one embodiment, at the beginning of the first clock cycle T, the ramp signal reset pulse signal also becomes a high level to discharge the first capacitor 606.

The first gate 701 is turned on and the second gate 702 is closed (a new clock cycle T is entered at this time), selecting the DC power supply voltage V _DC , V The _DC voltage is selected to generate a second current I2 on the resistor 605 through the follower. The current mirror sends the second current I2 to the first capacitor 606 to charge the first capacitor 606 to generate a ramp signal Vramp. The generated ramp signal Vramp and the reference voltage signal Vref are sent to the comparator together to generate a PWM square wave, thereby controlling the GATE voltage of the P-MOSFET. When the clock cycle T expires, the charge on the first capacitor 606 is discharged by the ramp signal reset pulse signal, and then continues to time the next clock cycle T to repeat the charging process to generate the next square wave.

After the first capacitor 606 is charged and discharged for n clock cycles T, the second gate 702 is closed and the first gate 701 is opened. At the same time, the charge on the second capacitor 703 is discharged by the reference signal reset pulse signal, and then the second capacitor 703 is charged again to generate a new Vref, and then the previous process is repeated to charge and discharge the first capacitor 606 in a new clock cycle. In other words, the refresh cycle of the reference signal Vref is (1+n)T, where n is a positive integer. The value of n may depend on the process level, and this article does not limit this.

FIG8 shows a timing diagram of the implementation of the switch control unit shown in FIG7 according to an embodiment of the present invention.

As shown in FIG8 , when the power supply voltage reaches a certain requirement, that is, the Power Good (pg) signal is at a high level, the first clock cycle T starts. At the beginning of the first clock cycle T, the reference signal reset pulse signal is at a high level. At this time, the reference signal reset pulse switch 704 is closed to discharge the second capacitor 703, and the first gate 701 is closed; when the reference signal reset pulse signal becomes a low level, the reference signal reset pulse switch 704 is disconnected to start charging the second capacitor 703. When the first clock cycle T ends, the first gate 701 is disconnected, and the first reference voltage maintained on the second capacitor 703 is generated.

When the first gate 701 is turned off (i.e., when the second clock cycle starts), the second gate 702 is closed to gate the DC power supply voltage V _DC , and the ramp voltage reset pulse signal becomes a high level at the same time. At this time, the ramp signal reset pulse switch 607 is closed to discharge the first capacitor 606. Then, when the ramp signal reset pulse signal becomes a low level, the first capacitor 606 is charged. The ramp signal generator sends the ramp signal Vramp generated according to the voltage on the first capacitor 606 to the comparator to compare with the first reference voltage, thereby generating a PWM square wave signal. Then, the second selector 702 remains closed for n clock cycles T to continue charging and discharging the first capacitor 606 for n clock cycles, that is, generating a square wave PWM signal of n cycles.

At the beginning of the n+1th clock cycle, the second gate 702 is disconnected and the first gate 701 is closed to repeat the above process to refresh the first reference voltage to the second reference voltage, and repeat the above square wave PWM signal generation process.

The duty cycle of the square wave PWM signal generated according to the above embodiment is calculated as follows:

When Vramp=Vref:

It can be seen that through the architecture implemented by the embodiments shown in Figures 7 and 8, the PWM duty cycle ton/T is not affected by the resistor R and the capacitor C, so the accuracy is higher. In this way, this architecture realizes the generation of high-precision Vtarget voltage.

According to the above embodiment provided by the present invention, an open-loop pulse width adjustment circuit with a simple structure and good control of output accuracy is provided. It does not require a complex feedback loop and peripheral devices, greatly simplifying the entire application structure. It can be understood that the above embodiment of the present invention can be implemented in any PWM system for converting a DC high voltage into a low voltage.

The above mentioned "one embodiment", "another embodiment", and "yet another embodiment", but it should be understood that the features mentioned in each embodiment are not necessarily applicable only to that embodiment, but may be used in other embodiments. The features in one embodiment may be applied to another embodiment, or may be included in another embodiment.

It should be understood that the numerical subscripts of the devices and circuits mentioned above are for the convenience of description and reference, and there is no order of precedence.

The present invention is described above with reference to specific embodiments of the present invention, but those skilled in the art should understand that the above embodiments are exemplary rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on studying the drawings, instructions and the scope of the patent application, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. Any diagrammatic mark in the claim should not be construed as a limitation on the scope of protection. The functions of multiple parts appearing in the claim can be implemented by a single hardware or software module. The appearance of certain technical features in different subordinate claims does not mean that these technical features cannot be combined to achieve beneficial effects.

302: DC power supply

306: Load

308: P-type metal oxide semiconductor field effect transistor (P-MOSFET)

400: Internal structure diagram for generating high-precision output voltage

402: Follower

404: Ramp signal generator

406: Oscillator

408: Reference signal generator

410: Comparator

PWM: Pulse Width Modulation

V _DC : DC voltage

VR: output voltage

Vramp: Ramp signal (ramp voltage)

Vref: reference signal voltage

Claims (13)

A pulse width modulation system includes: a DC power source, a load powered by the DC power source, a P-type metal oxide semiconductor field effect transistor (P-MOSFET) for controlling the voltage on the load, and a switch control unit for controlling the turning off and on of the P-MOSFET, wherein the switch control unit is connected to the gate of the P-MOSFET and is used to generate a pulse width for controlling the turning off and on of the P-MOSFET. Modulate the PWM signal to generate a constant target setting voltage on the load; the switch control unit includes a follower, a ramp signal generator, an oscillator, a reference signal generator and a comparator, wherein the input end of the follower is connected to the positive pole of the DC power supply and the output end is connected to the first input end of the ramp signal generator, the output end of the oscillator is connected to the second input end of the ramp signal generator, and the output end of the ramp signal generator is connected to the positive pole of the DC power supply and the output end is connected to the first input end of the ramp signal generator. The reference signal generator is connected to the positive input terminal of the comparator, the output terminal of the reference signal generator is connected to the negative input terminal of the comparator, and the output terminal of the comparator is connected to the gate of the P-MOSFET; the follower includes an operational amplifier, a resistor, the input P-MOSFET transistor of the P-MOSFET current mirror formed by the input P-MOSFET transistor and the output P-MOSFET transistor, an N-type metal oxide semiconductor Field effect transistor N-MOSFET follower, wherein the positive input terminal of the operational amplifier is connected to the DC power supply and the negative input terminal is connected to the first end of the resistor, the second end of the resistor is grounded, the gate of the N-MOSFET follower is connected to the output terminal of the operational amplifier, the source is connected to the first end of the resistor, and the drain is connected to the input P-MOSFET transistor of the P-MOSFET current mirror. A pulse width modulation system as described in claim 1, wherein the oscillator is used to generate a clock signal with a period of T and generate a ramp signal reset pulse signal with the same period at the rising edge of each clock, the ramp signal generator is used to output a ramp signal when the ramp signal reset pulse signal is at a low level, and the comparator is used to generate the PWM signal by comparing the ramp signal with a reference reference signal generated by the reference signal generator. A pulse width modulation system as described in claim 2, wherein at the beginning of each clock cycle T, the ramp signal generator reduces the output to 0 because the ramp signal reset pulse signal is at a high level, at which time the PWM signal turns to a low level and the P-MOSFET turns on; when the ramp signal reset pulse signal becomes a low level, the ramp signal generator generates the ramp signal, and when the ramp signal is equal to the reference signal, the PWM signal turns to a high level and the P-MOSFET turns off. A pulse width modulation system as described in claim 1 or 2, wherein the ramp signal generator includes the output P-MOSFET transistor of the current mirror and a first capacitor, wherein the first end of the first capacitor is connected to the output P-MOSFET transistor and the second end of the first capacitor is grounded, the ramp signal generated by the ramp signal generator is the voltage on the first capacitor, the first capacitor is connected in parallel with a ramp signal reset pulse switch, when the ramp signal reset pulse signal is at a high level, the ramp signal reset pulse switch is closed to discharge the first capacitor, and when the ramp signal reset pulse signal is at a low level, the ramp signal reset pulse switch is opened to charge the first capacitor through the current mirror. A pulse width modulation system as described in claim 4, wherein the reference signal generated by the reference signal generator is a fixed voltage. A pulse width modulation system as described in claim 4, wherein the reference signal generated by the reference signal generator is not a fixed voltage. A pulse width modulation system as described in claim 6, wherein the circuit of the reference signal generator periodically refreshes the base reference voltage by multiplexing the circuit of the ramp signal generator. A pulse width modulation system as described in claim 7, wherein the refresh period of the reference signal is (1+n)T. A pulse width modulation system as described in claim 7 or 8, wherein the reference signal generator includes a second capacitor, a first gate and a reference signal reset pulse switch, a first end of the second capacitor is connected to the output P-MOSFET transistor of the current mirror through the first gate and a second end is grounded, and the second capacitor is connected in parallel with the reference signal reset pulse switch to realize the second capacitor by controlling the opening and closing of the reference signal reset pulse switch by the reference signal reset pulse signal. The ramp signal generator further comprises a second gate, through which the first capacitor of the ramp signal generator is connected to the output P-MOSFET transistor of the current mirror; and wherein the target setting voltage for the load is input to the positive input terminal of the operational amplifier of the follower through the first gate, and the DC power supply is input to the positive input terminal of the operational amplifier of the follower through the second gate. A pulse width modulation system as described in claim 9, wherein the period of the reference signal resetting pulse signal is (1+n)T, where n is a positive integer. A pulse width modulation system as described in claim 10, wherein, at the beginning of a first clock cycle, the reference signal reset pulse signal is at a high level, at which time the reference signal reset pulse switch is closed to discharge the second capacitor; when the reference signal reset pulse signal becomes a low level, the first gate is closed to gate the target setting voltage, at which time the resistor is connected to the resistor through the follower. The first current is generated on the resistor, and the current mirror sends the first current to the second capacitor to charge it. When the first clock cycle ends, the first gate is disconnected, and the first reference voltage maintained on the second capacitor is generated at this time; when the second clock cycle starts, the first gate is disconnected and the second gate is closed to gate the voltage of the DC power supply, and then a second current is generated on the resistor through the follower, and the current mirror sends the second current to the first capacitor to charge it. The ramp signal generator sends the ramp signal generated according to the voltage on the first capacitor to the comparator to compare with the first reference voltage, thereby generating the PWM signal. When the second clock cycle ends, the ramp signal resets the pulse signal. becomes high level, at which time the ramp signal resets the pulse switch to close to discharge the capacitor, and then the second gate remains closed for n clock cycles to continue charging and discharging the capacitor for n clock cycles; at the beginning of the n+1th clock cycle, the second gate is disconnected and the first gate is closed to refresh the first reference voltage to the second reference voltage, and the above process is repeated. A pulse width modulation system as described in claim 1, wherein the DC power supply is a battery. A pulse width modulation system as described in claim 1, wherein the pulse width modulation system is used in a discharge circuit of an electronic cigarette system.

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