TWI868942B - Memory device - Google Patents

Abstract

A memory device includes a stop structure, a stack structure, and a slit. The stop structure is disposed above a substrate. The stack structure is disposed on the stop structure. The stack structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked. The slit extends through the stack structure and a portion of the stop structure. The stop structure includes a top layer, and the top layer includes a plurality of anti-oxidation atoms therein. The memory device may be a 3D NAND flash memory with high capacity and high performance.

Description

Memory device

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a memory device and a manufacturing method thereof.

Non-volatile memory devices (such as flash memory) have the advantage that the stored data will not disappear even after power failure. Therefore, they have become a type of memory device widely used in personal computers and other electronic devices.

The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each memory cell in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in many electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory. For example, there may be gaps in the gate conductor layer formed by gate replacement, causing electrical problems.

The present invention provides a memory device that can avoid or reduce cracks in a formed gate conductor layer.

The present invention provides a memory element, including a stop structure, a stacking structure and a separation wall (SLT). The stop structure is located above a substrate. The stacking structure is located on the stop structure, wherein the stacking structure includes a plurality of insulating layers and a plurality of conductive layers alternating with each other. The separation wall (SLT) extends in the stacking structure and a portion of the stop structure. The stop structure includes a top layer, wherein the top layer has a plurality of anti-oxidation atoms.

Based on the above, the embodiment of the present invention forms anti-oxidation atoms on the surface of the first stacked structure, which can reduce or prevent the conductor layer of the first stacked structure from being oxidized, thereby avoiding the horizontal trench width from being too narrow during the gate replacement process, so that the gate conductor layer can be smoothly filled into the horizontal trench. Therefore, the gap in the formed gate conductor layer can be avoided or reduced.

1A to 1L are cross-sectional schematic diagrams showing a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention.

Referring to FIG. 1A , a substrate 10 is provided. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. A component layer 20 is formed on the substrate 10. The component layer 20 may include active components or passive components. The active components are, for example, transistors, diodes, etc. The passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor (CMOS) component.

A metal interconnect structure 30 is formed on the device layer 20. The metal interconnect structure 30 may include multiple dielectric layers, multiple plugs, and multiple wires. The dielectric layer separates adjacent wires. The wires may be connected by plugs, and the wires may be connected to the device layer 20 by plugs.

A stacked structure SK1 is formed on the metal interconnect structure 30. The stacked structure SK1 includes a plurality of insulating layers 92 and a plurality of conductive layers 94 that are alternately stacked. In FIG. 1A , the stacked structure SK1 includes insulating layers 92a, 92b, 92c and conductive layers 94a, 94b, 94c. In one embodiment, the material of the insulating layer 92 includes silicon oxide, and the material of the conductive layer 94 includes doped polysilicon. The number of insulating layers 92 and conductive layers 94 is not limited to that shown in the figure. Since the memory array will be formed above the stacked structure SK1, and the device layer 20, such as a complementary metal oxide semiconductor device (CMOS), is formed below the memory array, this structure can also be called a complementary metal oxide semiconductor device below the memory array (CMOS-Under-Array, CUA) structure. For simplicity, some layers below the conductive layer 94a are omitted in Figures 1B to 1L.

Referring to FIG. 1B , the stacked structure SK1 of the embodiment of the present invention has a top layer TL. The top layer TL has a plurality of anti-oxidation atoms 96. The anti-oxidation atoms 96 include inert atoms, such as nitrogen atoms. In some embodiments, the top layer TL is a conductive layer 94c. The anti-oxidation atoms 96 can be formed on the surface of the conductive layer 94c by a surface treatment process 98. The surface treatment process 98 includes a plasma treatment process. The gas used in the plasma treatment process includes ammonia, nitrogen, or a combination thereof.

Referring to FIG. 1C , a stacked structure SK2 is then formed on the substrate 10. The stacked structure SK2 includes a plurality of alternately stacked insulating layers 102 and a plurality of intermediate layers 104. In one embodiment, the insulating layer 102 is made of silicon oxide, and the intermediate layer 104 is made of silicon nitride. The intermediate layer 104 may be used as a sacrificial layer, which will be partially or completely removed in a subsequent process.

Referring to FIG. 1D , the middle layer 104 and the insulating layer 102 of the stacked structure SK2 are patterned to form a stair structure (not shown). In some embodiments, the stair structure (not shown) can be formed by a multi-stage patterning process, but the present invention is not limited thereto. The patterning process may include processes such as lithography, etching, and trimming. Thereafter, a dielectric layer (not shown) is formed on the substrate 10 to cover the stair structure.

Referring to FIG. 1D , a patterning process is performed to remove a portion of the stacked structure SK2 and a portion of the stacked structure SK1 to form one or more openings 106 passing through the stacked structure SK2 and the stacked structure SK1. In one embodiment, the opening 106 may have sidewalls that are substantially vertical, as shown in FIG. 1D . The opening 106 is also referred to as a vertical channel (VC) hole. In another embodiment, the opening 106 may have a slight tilt (not shown). In one embodiment, the opening 106 may be formed by a single-stage lithography and etching process. In another embodiment, the opening 106 is formed by a multi-stage lithography and etching process. The profile of the sidewall of the opening 106 formed by multiple stages of lithography and etching processes is, for example, a bamboo-node shape. Then, a vertical channel column CP is formed in the opening 106. The vertical channel column CP can be formed by the following method.

First, please continue to refer to FIG. 1D , and form a charge storage structure 108 on the sidewall of the opening 106. The charge storage structure 108 contacts the insulating layer 102, the middle layer 104, the plurality of conductive layers 94, and the plurality of insulating layers 92. In one embodiment, the charge storage structure 108 is an oxide/nitride/oxide (ONO) composite layer. In some embodiments, the charge storage structure 108 can be formed in a U-shaped form on the sidewall and bottom surface of the opening 106. In other embodiments, the charge storage structure 108 is formed on the sidewall of the opening 106 in the form of a spacer, and the bottom surface of the opening 106 is exposed (not shown).

Then, please continue to refer to Figure 1D, a channel layer 110 is formed on the charge storage structure 108. In one embodiment, the material of the channel layer 110 includes polysilicon. In one embodiment, the channel layer 110 covers the charge storage structure 108 on the sidewalls of the opening 106, and also covers the charge storage structure 108 on the bottom surface of the opening 106. Next, an insulating column 112 is formed at the bottom of the opening 106. In one embodiment, the material of the insulating column 112 includes silicon oxide. Thereafter, a conductive plug 114 is formed at the top of the opening 106, and the conductive plug 114 contacts the channel layer 110. In one embodiment, the material of the conductive plug 114 includes polysilicon. The channel layer 110, the insulating pillar 112, and the conductive plug 114 may be collectively referred to as a vertical channel pillar CP. The charge storage structure 108 surrounds the vertical outer surface of the vertical channel pillar CP.

Please continue to refer to FIG. 1E , and the stacked structure SK2 is subjected to a patterning process. The patterning process includes a first stage etching process. The first stage etching process forms a plurality of trenches 116. The trenches 116 pass through the stacked structure SK2 and extend into the conductive layer 94c of the stacked structure SK1. The trenches 116 expose the intermediate layer 104, the insulating layer 102, and the conductive layer 94c.

1F , the second stage etching process is performed with the insulating layer 92 c as a stop layer, so that the trench 116 extends downward, thereby exposing the insulating layer 92 c.

Referring to FIG. 1G , a protective layer 118 is formed on the sidewall of the conductive layer 94c exposed in the trench 116. The material of the protective layer 118 includes silicon oxide. The protective layer 118 can be formed by a thermal oxidation process. During the thermal oxidation process, since the top layer TL has anti-oxidation atoms 96, the diffusion of oxygen in the thermal oxidation process into the conductive layer 94c can be suppressed, and in particular, the reaction of oxygen with the surface 94s of the conductive layer 94c in contact with the bottom surface of the stacked structure SK2 can be suppressed. Therefore, the anti-oxidation atoms 96 of the embodiment of the present invention can prevent the surface 94s of the conductive layer 94c from being oxidized and squeezing the stacked structure SK2 upward, thereby preventing the bottom layer or layers of the intermediate layer 104 from being squeezed and deformed.

1H, an etching process is then performed to remove the insulating layer 92c, the conductive layer 94b and the insulating layer 92c, and to remove a portion of the charge storage structure 108 to form a horizontal opening 97. The horizontal opening 97 exposes the channel layer 110. During the etching process, the protective layer 118 can protect the conductive layer 94c from being damaged by the etching.

1I, a conductor layer 93 is formed in the horizontal opening 97. The conductor layer 93 includes a semiconductor layer, such as a polysilicon layer or a doped polysilicon layer. The conductor layer 93 and the conductor layers 94a and 94c together form a source line 95. The source line 95 can also be referred to as a common source conductor layer 95. In some embodiments, the conductor layer 93 and the conductor layers 94a and 94c can also be referred to as a stop structure 95.

Afterwards, a protective layer 120 is formed in the trench 116 to cover the sidewalls of the conductive layer 94c and the surface of the conductive layer 93. The protective layer 118 may be removed or retained to form a part of the protective layer 120. The material of the protective layer 120 is different from that of the conductive layers 94c, 93 and the intermediate layer 104. The material of the protective layer 120 is, for example, silicon oxide. The protective layer 120 may be formed by a thermal oxidation process. Similarly, during the thermal oxidation process, since the top layer TL contains anti-oxidation atoms 96, it is possible to inhibit the oxygen in the thermal oxidation process from diffusing into the conductive layer 94c, especially inhibiting the oxygen from reacting with the surface 94s of the conductive layer 94c in contact with the bottom surface of the stacked structure SK2, thereby preventing the bottom layer or layers of the intermediate layer 104 from being squeezed and deformed.

Referring to Figures 1I to 1K, the middle layer 104 is replaced by the conductive layer 126. First, a selective etching process is performed so that the etchant contacts the stacked structure SK2 on both sides through the trench 116. Thereby, the middle layer 104 is removed to form a plurality of horizontal openings 121, as shown in Figure 1J. The horizontal openings 121 expose part of the charge storage structure 108 and the upper and lower surface sidewalls of the insulating layer 102. The selective etching process can be an isotropic etching, such as a wet etching process. The etchant used in the wet etching process is, for example, hot phosphoric acid.

Then, referring to FIG. 1K , a conductive layer 126 is formed in the trench 116 and the horizontal opening 121. The conductive layer 126 can be used as a gate layer or a word (WL). The conductive layer 126 includes, for example, a barrier layer 122 and a metal layer 124. In one embodiment, the material of the barrier layer 122 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the metal layer 124 includes tungsten (W). Since the bottom one or several intermediate layers 104 are not squeezed and deformed, the horizontal opening ₁₂₁₁ formed after removing the intermediate layer 104 has a sufficient width _W1 , and is equal to or close to the width _W2 of the horizontal openings 121 formed at other locations. Therefore, the conductive layer 126 can be smoothly filled into each horizontal opening 121, especially, can be smoothly filled into the bottom one or several horizontal openings ₁₂₁₁ without gaps.

Referring to FIG. 1L , a filling layer 134 is then formed in the trench 116. The protection layer 120 is located between the filling layer 134 and the stop structure 95. The filling layer 134 may include a liner 128, a conductive layer 130, and a conductive pad 132. The liner 128 is, for example, silicon oxide. The conductive layer 130 includes a semiconductor material, such as polysilicon. The conductive pad 132 is, for example, tungsten. The conductive pad 132 and the conductive layer 130 together form a source line conductive wall (source line slit) 136 for conducting current from the source line 95. The source line conductor wall 136 is isolated by the liner layer 128 to avoid contact with the conductor layer 126. The filling layer 134 and the protection layer 120 form a separation wall SLT. The separation wall SLT extends from the stacking structure SK1 to a portion of the stop structure 95.

Afterwards, subsequent related processes are carried out to complete the production of memory devices.

Referring to Figure 1L, in this embodiment, the stop structure 95 includes a bottom layer BL, a middle layer ML and a top layer TL. The middle layer ML is located below the top layer TL and the separation wall SLT, and is electrically connected to the conductor layer 130 of the separation wall SLT. The bottom layer BL is located below the middle layer ML. The bottom layer BL, the middle layer ML and the top layer TL are conductor layers 94a, 93, and 94c, respectively. The conductor layers 94a, 93, and 94c can be semiconductor layers, such as polycrystalline silicon layers or doped polycrystalline silicon layers. The conductor layer 94c has a plurality of anti-oxidation atoms 96. The anti-oxidation atoms are different from the constituent elements of the protective layer 120 of the separation wall SLT. The anti-oxidation atoms 96 include nitrogen atoms. The concentration of nitrogen atoms ranges from 15 atomic % to 25 atomic %. The distribution range of the anti-oxidation atoms 96 is higher than the bottom surface of the partition wall SLT. The anti-oxidation atoms 96 are distributed in the upper part of the conductor layer (e.g., semiconductor layer) 94c. In other words, the concentration of the anti-oxidation atoms 96 in the upper part of the conductor layer (e.g., semiconductor layer) 94c is higher than that in the lower part of the conductor layer (e.g., semiconductor layer) 94c, and is higher than the conductor layer 93 and the conductor layer 94a. In some embodiments, the conductor layer 93 and the conductor layer 94a do not have the plurality of anti-oxidation atoms 96.

2A to 2D are cross-sectional schematic diagrams showing a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

2A, the top layer TL includes top layers TL1 and TL2. The top layer TL1 is a conductor layer 94c, and the top layer TL2 is a barrier layer, such as a silicon nitride layer. The silicon nitride layer is formed above the conductor layer 94c. The silicon nitride layer can be formed by chemical vapor deposition after the conductor layer 94c is formed.

2B , the stacked structure SK2, trench 116 and protective layer 118 are formed according to the above method. Similarly, in the thermal oxidation process of forming the protective layer 118, the top layer TL2 can prevent or reduce the oxidation of the surface 94s of the conductive layer 94c and squeeze the stacked structure SK2 upward, thereby preventing the bottom one or more intermediate layers 104 from being squeezed and deformed.

2C , the conductive layer 93 and the protective layer 120 are formed according to the above method. Similarly, in the thermal oxidation process of forming the protective layer 120, the top layer TL2 can prevent or reduce the oxidation of the surface 94s of the conductive layer 94c and squeeze the stacked structure SK2 upward, thereby preventing the bottom one or more intermediate layers 104 from being squeezed and deformed.

2D, a conductive layer 126 and a separation wall SLT are formed according to the above method.

In this embodiment, the stop structure 95 includes a bottom layer BL, a middle layer ML and a top layer TL. The middle layer ML is located below the top layer TL and the separation wall SLT, and is electrically connected to the conductor layer 130 of the separation wall SLT. The bottom layer BL is located below the middle layer ML. The bottom layer BL and the middle layer ML are conductor layers 94a and 93, respectively. The top layer TL includes top layers TL1 and TL2. The top layer TL1 is a conductor layer 94c. The top layer TL2 is a silicon nitride layer. The thickness of the top layer TL2 ranges from 20 angstroms to 100 angstroms, for example. The conductor layers 94a, 93, and 94c can be semiconductor layers, such as polycrystalline silicon layers or doped polycrystalline silicon layers. The top layer TL2 is, for example, silicon nitride. The anti-oxidation atoms 96 include nitrogen atoms. The top layer TL2 is higher than the bottom surface of the separation wall SLT. The top layer TL2 is located on the upper part of the conductor layer (such as a semiconductor layer) 94c. In other words, the nitrogen atom concentration of the top layer TL2 is higher than that of the conductor layer 94c, the conductor layer 93, and the conductor layer 94a. The conductor layer 94c, the conductor layer 93, and the conductor layer 94a do not have the multiple anti-oxidation atoms 96.

The embodiment of the present invention can reduce or prevent the top conductor layer of the first stacked structure from being oxidized and pushing the upper middle layer by forming anti-oxidation atoms, so that the middle layer maintains a sufficient width, and the gate conductor layer can be smoothly filled into the formed horizontal trench (the middle layer is removed) during the gate replacement process, thereby avoiding or reducing the formation of cracks in the gate conductor layer.

10: substrate 20: device layer 30: metal interconnect structure 92, 92a, 92b, 92c, 102: insulating layer 93, 93b, 94, 94a, 94b, 94c: conductor layer 94s: surface 95: source line, common source conductor layer, stop structure 96: anti-oxidation atoms 97, 121: horizontal trench 104: intermediate layer 106: opening 108: charge storage structure 110: channel layer 112: insulating pillar 114: conductor plug 116: trench 118, 120: protective layer 121, 121 ₁ : horizontal opening 122: barrier layer 124: metal layer 126: conductor layer 128: liner 130: conductor layer 132: conductor pad 134: source line conductor wall CP: vertical channel pillar SK1, SK2: stacking structure SLT: separation wall WL: word line TL, TL1, TL2: top layer ML: middle layer ML: bottom layer _W1 , _W2 : width

Figures 1A to 1L are schematic cross-sectional views of a method for manufacturing a three-dimensional memory element according to some embodiments of the present invention. Figures 2A to 2D are schematic cross-sectional views of another method for manufacturing a three-dimensional memory element according to another embodiment of the present invention.

10: Base

92, 92b, 92c: Insulating layer

94, 94a, 94b, 94c: Conductor layer

96: Antioxidant Atoms

98: Surface treatment process

SK1: Stacked structure

TL: Top layer

Claims (9)

A memory device comprises: a stop structure located above a substrate; a stacking structure located on the stop structure, wherein the stacking structure comprises a plurality of insulating layers and a plurality of conductive layers alternating with each other; a separation wall extending in the stacking structure and a portion of the stop structure, wherein the stop structure comprises a top layer, a bottom layer, and a middle layer located below the top layer and above the bottom layer. The top layer has a plurality of anti-oxidation atoms, and the top layer directly contacts the bottommost insulating layer of the stacked structure, wherein the top layer, the bottom layer and the middle layer include a polysilicon layer, wherein the partition wall includes a protective layer located on the side wall of the top layer; and a channel column extending through the stacked structure and the stop structure and electrically connected to the middle layer. A memory device as described in claim 1, wherein the partition wall includes a filling layer, and the protective layer is located between the top layer of the stop structure and the filling layer. A memory device as described in claim 1, wherein the plurality of anti-oxidation atoms include nitrogen atoms and the protective layer includes silicon oxide. A memory device as described in claim 3, wherein the concentration of the nitrogen atoms ranges from 15 atomic % to 25 atomic %. A memory device as described in claim 4, wherein the top layer includes a first polysilicon layer, and the plurality of anti-oxidation atoms are distributed on the upper portion of the first polysilicon layer. A memory device as described in claim 5, wherein the middle layer is located below the top layer and the partition wall, and the middle layer includes a second polysilicon layer electrically connected to the partition wall. A memory element as described in claim 6, wherein the sidewalls of the first polysilicon layer and the top surface of the second polysilicon layer are covered by the protective layer. A memory device as described in claim 7, wherein the concentration of the plurality of anti-oxidation atoms in the first polysilicon layer is greater than the concentration of the plurality of anti-oxidation atoms in the second polysilicon layer. A memory device as described in claim 7, wherein the bottom layer includes a third polysilicon layer, and the third polysilicon layer does not contain the plurality of anti-oxidation atoms.