TWI868805B - Controller, segment lcd device, and method for detecting the status of display module - Google Patents

Abstract

A controller, a segment LCD device, and a method for detecting the status of a display module are provided. The controller is adapted to drive a display module having a plurality of pixels and includes a signal generation circuit and an anomaly detection circuit. The signal generation circuit is configured to couple to the display module and generate a plurality of control signals for driving the pixels based on a power source signal, in which the signal generation circuit outputs the control signal having a test waveform under a test mode. The anomaly detection circuit is configured to receive the power source signal and detect a variation, caused by the test waveform, in the power source signal, so as to generate a detection value corresponding to a pixel to be tested..

Description

Controller, segmented liquid crystal display device, and display module status detection method

The present invention relates to a detection technology for a display device, and in particular to a state detection method for a controller, a segmented liquid crystal display device, and a display module.

Segmented liquid crystal display (Segmented LCD) is a patterned liquid crystal display, which is commonly used in the display interface of electronic devices such as air-conditioning remote controls, electronic blood pressure meters and electronic computers. The display mechanism of the segmented liquid crystal display is mainly to drive the pixels/fields in the display module through the control of the common signal (COM signal) and the segment signal (SEG signal) to display different patterns and numbers.

The connection interface of the display module of the segment LCD is usually composed of pins for receiving SEG signals and COM signals, wherein the controller connects to the display module through the connection interface and sends a control signal to drive the display module to display images.

This type of display module has a common abnormality, that is, a short circuit may occur between its pins, or the pins may short-circuit to other external circuits, causing the segment LCD to display abnormally. Therefore, in the production process, it is necessary to detect whether the display image/number of each pixel/field is abnormal. The common method of detection is to use manual visual inspection or use I/O to control the pin to be tested to a high/low level to confirm whether each pin has a short circuit through the signal status.

Although manual inspection can more intuitively confirm whether each pixel/field can be displayed normally, this method is very time-consuming, and manual inspection may fail to detect abnormal conditions due to distraction or fatigue, making it difficult to improve overall efficiency and detection accuracy.

On the other hand, in the detection method that uses I/O to control the pin to be tested to a high/low level, the main method is to determine whether the pin to be tested is short-circuited by confirming whether other pins have the same high/low level. If the same high/low level as the pin to be tested is detected on other pins, it means that a short circuit has occurred. Although this method can detect basic short circuit conditions, it cannot know the severity of the short circuit condition. Sometimes, although a short circuit occurs between pins, the equivalent impedance between the two ends is large enough to show that no abnormality has occurred. This situation does not need to be classified as an abnormal state that needs to be screened out in some applications. However, through the above-mentioned I/O control detection method, no matter what the short circuit condition is, it will be screened as an abnormality, which results in an unnecessary increase in manufacturing costs.

This disclosure proposes a controller, a segmented liquid crystal display device, and a state detection method for a display module, which can detect the degree of short circuit between pins to avoid filtering out pixels that can be displayed normally.

The present disclosure provides a controller suitable for driving a display module having a plurality of pixels, wherein the controller includes a signal generating circuit and an abnormality detecting circuit. The signal generating circuit is used to couple the display module and generate a plurality of control signals for driving the plurality of pixels based on a power signal, wherein the signal generating circuit outputs a control signal having a test waveform in a test mode. The abnormality detecting circuit receives the power signal and is used to detect the power signal in response to the change of the test waveform in the test mode, thereby generating a detection value corresponding to the pixel to be tested among the plurality of pixels.

The present disclosure provides a segmented liquid crystal display device, including a segmented liquid crystal display module and a controller. The segmented liquid crystal display module has a plurality of display fields, wherein each display field has two pins. The controller is coupled to the plurality of pins to generate a plurality of control signals based on a power signal and output them to the plurality of pins to drive the segmented liquid crystal display module. The controller outputs a control signal having a test waveform in a test mode, and detects the power signal in response to the change of the test waveform, thereby generating a detection value indicating the degree of short circuit of the corresponding display field.

The present disclosure provides a state detection method for a display module, comprising the following steps: sending a first control signal having a first test waveform to one of the multiple pins of the display module, and sending a second control signal having a second test waveform to another of the multiple pins of the display module, wherein the one of the pins and the other of the pins correspond to pixels to be tested of the display module; detecting a power signal used to generate the control signal; and generating a detection value corresponding to the pixel to be tested according to the change of the power signal.

Based on the above, the controller, segmented liquid crystal display device and display module state detection method disclosed in the present invention can more accurately detect the actual short circuit degree and abnormal conditions of the pins corresponding to each pixel of the display module, so that the availability of the display module can be more accurately evaluated according to the required application scenario in the back-end application, thereby avoiding excessive screening of modules with slight short circuit conditions but no effect on the display, resulting in unnecessary increase in manufacturing costs; or avoiding the unanticipated product reliability risk caused by the failure to screen out mild short circuit conditions in some applications requiring high reliability. In addition, some embodiments disclosed in the present invention can set the functions and operations of the test mode on the existing LCD driver without any additional output setting modification or additional circuit addition, effectively reducing the manufacturing cost of designing and modifying the circuit.

10: Display device

100: Controller

110:Signal generating circuit

120: Abnormal detection circuit

122: Voltage detection unit

124: Counting unit

130: Power supply circuit

CTV: test value

LCM: Display Module

Pab: Pixel

P_COM0~P_COMn, P_SEG0~P_SEGm: pins

S110~S130, S210~S290: Steps of the status detection method of the display module

Sc_0~Sc_x, Sc_a, Sc_b: control signal

St1, St2: trigger signal

TM:Test mode

Tff, Tfn: Discharge period

Trf, Trn: During charging

Tf, Tn: charging and discharging period

VLCD, VLCDn, VLCDf: power signal

VDD, VSS, VH, VL, V0~V4, VP: voltage level

Vt1: first voltage

Vt2: Second voltage

VSEGab: voltage difference

WF1, WF2: test waveform

FIG. 1 is a schematic diagram of a display device of an embodiment of the present disclosure; FIG. 2 is a schematic diagram of a controller of an embodiment of the present disclosure; FIG. 3 is a schematic diagram of a signal timing of a controller of an embodiment of the present disclosure in a test mode; and FIG. 4 is a schematic diagram of a signal timing of a controller of another embodiment of the present disclosure in a test mode; FIG. 5 is a step flow chart of a state detection method of a display module of an embodiment of the present disclosure; and FIG. 6 is a step flow chart of a state detection method of a display module of another embodiment of the present disclosure.

The present disclosure proposes a new controller, a segmented liquid crystal display device, and a state detection method for a display module to solve the problems mentioned in the background art. In order to make the features and advantages of the present disclosure more clear and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the attached figures. The following description contains specific information related to the exemplary embodiments in the present disclosure. The attached figures and the detailed descriptions attached thereto in the present disclosure are only exemplary embodiments. However, the present disclosure is not limited to these exemplary embodiments. Other variations and embodiments of the present disclosure will occur to those skilled in the art. Unless otherwise specified, the same or corresponding elements in the attached figures may be indicated by the same or corresponding figure numbers. In addition, the attached figures and illustrations in the present disclosure are generally not drawn to scale and are not intended to correspond to actual relative sizes.

All descriptions related to specific numerical values in this disclosure, although not directly described, all contain the meaning of "approximately" or "substantially", that is, these specific numerical values will cover the possible numerical error range, so as to express the possible unexpected effects and deviations in the process or material selection. The numerical error range may include numerical changes that do not significantly change the material structure, characteristics, and effects, such as a range of 0%~10% deviation. This error range is clear to those with ordinary knowledge in this field.

FIG1 is a schematic diagram of a display device of an embodiment of the present disclosure. Referring to FIG1 , the display device 10 includes a display module LCM and a controller 100 for driving the display module LCM. The present disclosure does not limit the category/type to which the display device 10 and its display module LCM are applied. In some embodiments, the display device 10 may be an electronic device with a display function, such as an electronic watch, an electronic clock, or a display interface of a remote control. In some embodiments, the display module LCM may be a liquid crystal display (LCD) module or a segment LCD module. When the display module LCM is an LCD module, the display device 10 may also be referred to as a liquid crystal display device; similarly, when the display module LCM is a segment LCD module, the display device 10 may be referred to as a segment LCD display device.

In this embodiment, the display module LCM is a segment LCD module with multiple pins. The multiple pins may be, for example, n+1 pins P_COM0~P_COMn for receiving COM signals, and m+1 pins P_SEG1~P_SEGm for receiving SEG signals, where m and n are natural numbers and may be selected according to actual design.

Specifically, the display module LCM includes a plurality of pixels, each pixel receives a COM signal and a SEG signal through two corresponding pins, wherein because some or all of the plurality of pixels can share the COM signal, the number of pins used to receive the COM signal can be less than the number of pixels. On the other hand, each pixel receives a corresponding SEG signal, so the number of pins used to receive the SEG signal can correspond one-to-one to the number of pixels, but the present disclosure is not limited thereto. In the application of the segment code liquid crystal display device, each pixel can refer to a corresponding display field.

The controller 100 is coupled to the pins P_COM0~P_COMn and P_SEG0~P_SEGm of the display module LCM, and is used to generate a plurality of control signals Sc_0~Sc_x as LCD driving signals (i.e., the COM signal and the SEG signal) based on a power signal, and respectively provide them to the pixels in the display module LCM through the corresponding pins P_COM0~P_COMn and P_SEG0~P_SEGm to drive the display module LCM. In this embodiment, the control signals Sc_0~Sc_x can be in a one-to-one correspondence with the pins P_COM0~P_COMn and P_SEG0~P_SEGm, that is, when driving the display module LCM, the control signal Sc_0 is the COM0 signal provided to the pin P_COM0, the control signal Sc_1 is the COM1 signal provided to the pin P_COM1, and so on; therefore, the number x of control signals will be less than or equal to m+n+2. However, the present disclosure is not limited to this.

Taking a segmented liquid crystal display device that displays "8" as an example, it may include 7 display fields, so the display module LCM may include 1 pin P_COM0 (i.e. n=0) for receiving COM signals and 7 pins P_SEG0~P_SEG6 (i.e. m=6) for receiving SEG signals, so that each SEG signal pin P_SEG0~P_SEG6 is matched with the COM signal pin P_COM0 to form two corresponding pins of a display field to receive the control signals Sc_0~Sc_7 issued by the controller 100, wherein the control signal Sc_0 is the COM signal provided to the pin P_COM0, the control signal Sc_1 is the SEG signal provided to the pin P_SEG0, and the control signal Sc_2 is the SEG signal provided to the pin P_SEG1, and the others can be deduced in the same way.

An exemplary configuration of the controller 100 may be shown in FIG. 2, where FIG. 2 is a schematic diagram of a controller of an embodiment of the present disclosure. Please refer to FIG. 1 and FIG. 2 simultaneously. In addition to being used to drive the display module LCM, the controller 100 of the present embodiment may also output a control signal having a corresponding test waveform to each pin P_COM0~P_SEGm of the display module LCM in the test mode TM to detect each pixel/display field in the display module LCM, and may output a detection value indicating the short circuit degree/type of each pixel/display field.

Specifically, the controller 100 may include a signal generating circuit 110, an abnormality detecting circuit 120, and a power supply circuit 130. In addition to generating control signals Sc_0~Sc_x as LCD driving signals when driving the display module LCM, the signal generating circuit 110 may also be used to generate control signals Sc_0~Sc_x having test waveforms WF1 and WF2 based on the power signal VLCD in the test mode TM, and output the control signals Sc_0~Sc_x to the corresponding pins, thereby sequentially testing the short circuit degree of each pixel.

For example, FIG2 shows the signal output state of the pixel Pab for testing. The signal generating circuit 110 outputs the first control signal Sc_a having the test waveform WF1 and the second control signal Sc_b having the test waveform WF2 to the corresponding two pins of the pixel Pab, so that the pixel Pab is enabled in response to the first control signal Sc_a and the second control signal Sc_b, and the pixels corresponding to the other pins are disabled in response to the received control signals. The detection value obtained at this time will reflect the short circuit degree of the pixel Pab. After completing the detection of the pixel Pab, the signal generating circuit 110 can select the two pins corresponding to the next pixel to output the control signal with the test waveforms WF1 and WF2 to continue to detect the next pixel, and the first control signal Sc_a/second control signal Sc_b with the test waveforms WF1/WF2 is now switched to a control signal that disables the corresponding pixel Pab. The test of other pixels can be deduced in the same way.

For example, if the two corresponding pins of the pixel Pab are pins P_COM0 and pin P_SEG0, the signal generating circuit 110 will output a control signal Sc_0 having a test waveform WF1 to pin P_COM0, and output a control signal having a test waveform WF2 to pin P_SEG0; the other pins P_COM1~P_COMn and P_SEG1~P_SEGm will receive control signals that will not enable the pixels corresponding to the pins P_COM1~P_COMn and P_SEG1~P_SEGm. When the pixel Pab completes the test, the signal generating circuit 110 will change to output a control signal with a test waveform WF2 to the pin P_SEG1, so that the pixels corresponding to the pins P_COM0 and P_SEG1 can be tested, and the pin P_SEG0 will receive a control signal to disable the pixel Pab.

In other words, the signal generating circuit 110 outputs a first control signal (such as Sc_a) having a test waveform WF1 and a second control signal (such as Sc_b) having a test waveform WF2 to two corresponding pins of a pixel to be tested (such as Pab) in the display module LCM in the test mode TM, so that the abnormality detection circuit 120 generates a detection value CTV corresponding to the pixel to be tested.

It should be noted here that the short circuit refers to the unexpected electrical connection of the line/pin associated with the pixel to the surrounding line/component/pin, so that the line/pin of the pixel can be regarded as electrically connected to the surrounding line/component/pin through a short-circuit resistor, and cause leakage current through the short-circuit resistor, wherein the short-circuit degree/situation refers to the size of the short-circuit impedance and/or leakage current. The more severe the short circuit, the greater the leakage current/the smaller the short-circuit impedance, while the milder the short circuit, the smaller the leakage current/the larger the short-circuit impedance.

In some embodiments, the test waveforms WF1 and WF2 may be square waves with opposite phases to each other, so as to form an AC signal to enable the corresponding pixel to be tested.

In some embodiments, the test waveforms WF1 and WF2 may be waveforms that conform to the LCD drive signal format; that is, the LCD drive signal may be directly used as the test signal for testing. Specifically, the waveform that conforms to the LCD drive signal format may be a step signal waveform having multiple levels (e.g., at least three levels) of different voltage levels in one cycle, and each level of the voltage level conforms to the output voltage under the LCD drive signal format. In other words, the voltage difference between the test waveforms WF1 and WF2 can constitute a periodic multi-level AC square wave that can drive LCD pixels. Specific examples of the controller 100 performing detection under different test waveforms WF1 and WF2 will be further described in subsequent embodiments.

Since the controller 100 can use the test waveforms WF1 and WF2 that conform to the LCD drive signal format for detection, the hardware of the signal generation circuit 110 can be implemented using a general LCD driver architecture without the need for additional hardware configuration.

The abnormal detection circuit 120 can receive the power signal VLCD and detect the power signal VLCD in response to the changes of the test waveforms WF1 and WF2 in the test mode TM, thereby generating the detection value CTV corresponding to each pin P_COM0~P_SEGm.

Specifically, when the controller 100 sends the first control signal Sc_a and the second control signal Sc_b with the test waveforms WF1 and WF2 to the corresponding pins to enable the pixel Pab to be tested, the state of the pixel Pab to be tested is similar to that in the driving mode, so the power signal VLCD will respond to the working current of the pixel Pab to be tested and have a charging and discharging waveform similar to that in the driving mode.

When there is no short circuit in the line/pin of the pixel Pab to be tested, the load current caused by the basic power consumption is very small, and the voltage level of the power signal VLCD will be relatively gentle when pulled down (i.e., the slope is small), and it will also recover to the steady-state voltage relatively quickly when charging. On the contrary, when a short circuit occurs in the line/pin of the pixel Pab to be tested, the short circuit path will cause additional leakage current, causing the voltage level of the power signal VLCD to be pulled down quickly (i.e., the slope is large), wherein the larger the leakage current, the faster the voltage level of the power signal VLCD will be pulled down. In addition, the short-circuit resistance will also cause the power supply circuit 130 to take longer to recharge the voltage level of the power signal VLCD to a steady-state voltage.

In other words, the variation of the power signal VLCD is related to the size of the leakage current/short-circuit resistance, which is related to the degree of short-circuit of the pin to be tested.

The controller 100 of this embodiment uses the above-mentioned voltage level variation characteristics to obtain the detection value CTV that reflects the short-circuit degree of the pins P_COM0~P_SEGm and/or the wiring related to the detection pixel. In other words, the controller 100 of this embodiment can output the control signals Sc_0~Sc_x with the test waveforms WF1 and WF2 in the test mode TM, and the detection power signal VLCD responds to the changes of the test waveforms WF1 and WF2, so as to generate the detection value CTV indicating the short-circuit degree of the pixel Pab to be tested.

The detection value CTV can be a value that indicates the degree of short circuit of the test pin in a proportional relationship. It can be, for example, a count value, a voltage value, or other types of values, depending on the actual implementation of the abnormal detection circuit.

It should be noted that the short circuit described in this disclosure does not limit the short-circuited two-terminal pins/components/lines to have no impedance or only negligible impedance on their short-circuit paths. As long as the two-terminal pins/components can be equivalently connected through impedance, and the leakage current caused by the impedance path is identifiably greater than the load current caused by the basic power consumption, it may belong to the short circuit described in this disclosure. For example, if there is a short-circuit impedance of 5 ohms, 50 ohms, 500 ohms or 5000 ohms between the two pins, it can be regarded as a short circuit in this disclosure, and the difference lies only in the degree of short circuit.

In some embodiments, the abnormality detection circuit 120 may include a voltage detection unit 122 and a counting unit 124. The voltage detection unit 122 is used to detect the voltage level of the power signal VLCD in the test mode TM to generate trigger signals St1 and St2. The counting unit 124 is coupled to the voltage detection unit 122 and is used to count in response to the trigger signals St1 and St2 and generate a detection value CTV accordingly.

More specifically, the voltage detection unit 122 can generate a first trigger signal St1 to trigger the counting unit 124 to start counting when the voltage level of the power signal VLCD exceeds the first voltage Vt1 (which can be from a high voltage to less than the first voltage Vt1, or increased from a low voltage to greater than the first voltage Vt1), and generate a second trigger signal St2 to trigger the counting unit 124 to stop counting when the voltage level of the power signal VLCD exceeds the second voltage Vt2 (which can be from a high voltage to less than the second voltage Vt2, or increased from a low voltage to greater than the second voltage Vt2). In other words, the counting unit 124 starts counting in response to the first trigger signal St1, and stops counting in response to the second trigger signal St2. The voltage detection unit 122 may generate the first trigger signal St1 when the voltage level of the power signal VLCD starts to drop from the steady-state voltage, or generate the first trigger signal St1 when the voltage level of the power signal VLCD reaches the valley voltage; in addition, the voltage detection unit 122 may generate the second trigger signal St2 when the voltage level of the power signal VLCD reaches the valley voltage, or generate the second trigger signal St2 when the voltage level of the power signal VLCD returns to the steady-state voltage.

In other words, the detection value CTV generated by the counting unit 124 can be a count value of the time required for the voltage level of the counting power supply signal VLCD to drop from the steady-state voltage to the valley voltage, a count value of the time required for the voltage level of the counting power supply signal VLCD to rise from the valley voltage to the steady-state voltage, or a count value of the time required for the voltage level of the counting power supply signal VLCD to drop from the steady-state voltage to the valley voltage and then rise to the steady-state voltage. The present disclosure is not limited to this.

Similar to the above, the time required for the voltage level of the power signal VLCD to drop from the steady-state voltage to the valley voltage and then rise back to the steady-state voltage is related to the leakage current/short-circuit impedance of the pixel to be tested, and the leakage current/short-circuit impedance is related to the degree of short circuit, so the count value obtained by the counting unit 124 can be used as the detection value CTV indicating the degree of short circuit. In other words, in this embodiment, the abnormal detection circuit 120 reflects the change amplitude of the power signal VLCD by counting the time when the voltage level of the power signal VLCD changes, and uses this as the detection value CTV indicating the degree of short circuit.

The power supply circuit 130 is coupled to the signal generating circuit 110 and the abnormal detection circuit 120, and is used to generate a power signal VLCD to provide to the signal generating circuit 110 and the abnormal detection circuit 120. In actual applications, the power supply circuit 130 can be implemented using a charge pump, an internal analog voltage source, or an external voltage source, depending on the driving voltage required by the display module LCM, but the present disclosure is not limited thereto.

Through the above method, the controller 100 disclosed in the present invention can more accurately detect the actual short circuit degree of the pins P_COM0~P_SEGm corresponding to each pixel of the display module LCM, so that the availability of the display module LCM can be more accurately evaluated according to the required application scenario in the back-end application, avoiding excessive screening of modules with slight short circuit conditions but no display impact in some applications, resulting in unnecessary increase in manufacturing costs; or avoiding the situation of slight short circuit conditions not being screened out in some applications requiring high reliability, resulting in unexpected product reliability risks.

In addition, compared to the traditional detection method, the controller 100 disclosed in the present invention does not need to use an input/output port (I/O port) for detection, but can use a signal output that conforms to the LCD drive signal format and detect power supply signal changes to determine the short circuit situation, so that the detection mechanism can be directly integrated into the LCD drive control circuit without the need for additional hardware development costs.

It should be noted that the test mode TM can be a mode different from the normal driving mode that is activated by user operation. As long as any controller has the function and/or operation of enabling the above-mentioned detection of the short circuit degree of the pin of the display module LCM through control, it can be regarded as including the test mode or including all operations in the test mode. In other words, even if the features of the controller 100 described in the present disclosure cannot be directly observed in the appearance of a display device in operation, it does not necessarily mean that the controller included in the display device does not fall within the scope of the rights claimed by the present disclosure. In fact, as long as it can be discovered/verified through any testing method or reverse engineering means (including conventional usage methods not indicated by the display device) that the controller included in the display device has the test mode, or operates in a test mode that complies with the scope of rights claimed by this disclosure, the controller can be considered to fall within the scope of rights claimed by this disclosure.

The operation of the controller in the test mode is further explained below with the signal timings of Figures 3 and 4, wherein Figure 3 is a schematic diagram of the signal timing of the controller in the test mode according to one embodiment of Figure 2; and Figure 4 is a schematic diagram of the signal timing of the controller in the test mode according to another embodiment of Figure 2.

Please refer to FIG. 2 and FIG. 3, where FIG. 3 shows the signal timing when the controller 100 tests the pixel Pab of the display module LCM as an example. In this embodiment, the signal generating circuit 110 sends a first control signal Sc_a having a periodic square wave waveform and a second control signal Sc_b having a waveform opposite to the first control signal Sc_a (i.e., the phase difference between the two signals is 180 degrees) to the pixel Pab to be tested, wherein the first control signal Sc_a may be, for example, a signal sent to the COM pin of the pixel Pab, and the second control signal Sc_b may be, for example, a signal sent to the SEG pin of the pixel Pab, but the present disclosure is not limited thereto.

In addition, the signal generating circuit 110 can send a control signal having the same/in-phase waveform as one of the first control signal Sc_a and the second control signal Sc_b to other pins (or at least part of other pins) of the display module LCM, so that non-test pixels are not enabled. For example, when the first control signal Sc_a and the second control signal Sc_b are respectively given to the COM pin and the SEG pin of the pixel Pab, the signal generating circuit 110 can send a control signal having the same waveform as the first control signal Sc_a to other SEG pins that share the COM signal with the pixel Pab, so that other non-test pixels are not enabled.

During the period when the pixel Pab is enabled in response to the first control signal Sc_a and the second control signal Sc_b, the power signal VLCD will repeatedly charge and discharge in a certain voltage range (such as the range between the voltage levels VL and VH) in response to the working load of the pixel Pab to maintain a roughly stable power supply.

In a normal state where the associated pins/lines of the pixel Pab are not short-circuited, the time for the power signal VLCDn to discharge from the voltage level VH to the voltage level VL is Tfn, and the time for the power signal VLCDn to recharge from the voltage level VL to the voltage level VH is Trn, so a complete charge-discharge period Tn is the discharge period Tfn plus the charge period Trn. In some embodiments, in the case of a short circuit in the associated pins/lines of the pixel Pab, the additional leakage current will cause the power signal VLCDf to be quickly pulled down from the voltage level VH to the voltage level VL, so that the discharge period Tff will be shorter than the discharge period Tfn in the normal state. On the other hand, since a short circuit may cause an unexpected impedance to be connected in series, the series impedance caused by the short circuit will prolong the charging time of the power supply VLCDf from the voltage level VL to the voltage level VH. Therefore, the charging period Trf in the case of a short circuit will be greater than the charging period Trn in the normal state. In this way, when the related pins/lines of the pixel Pab are short-circuited, a complete charging and discharging period Tf of the power supply signal VLCDf will be greater than the charging and discharging period Tn in the normal state.

Therefore, counting the discharge period Tfn/Tff, the charge period Trn/Trf, or the charge and discharge period Tn/Tf can be used to identify whether a short circuit occurs. Furthermore, according to the difference in specifications of the product to be tested, the above-mentioned different identification conditions can be selected for detection to improve the accuracy of the detection. For example, in the case of a small load detection application, it is more suitable to detect by counting the discharge period Tfn/Tff; while in the case of a large load or short circuit impedance detection application, it is more suitable to detect by counting the charge period Trn/Trf, but the present disclosure is not limited to this.

Please refer to FIG. 2 and FIG. 4, where FIG. 4 also shows the signal timing when the controller 100 tests the pixel Pab of the display module LCM. In this embodiment, the signal generating circuit 110 sends a first control signal Sc_a and a second control signal Sc_b with waveforms similar to/same as conventional LCD driving signals to the pixel Pab to be tested, wherein the conventional LCD driving signal can be similar to a periodic multi-level square wave with multiple levels such as voltage levels V0 to V4 as shown in the figure.

The first control signal Sc_a of the present embodiment may be, for example, a signal sent to the COM pin of the pixel Pab, and the second control signal Sc_b may be, for example, a signal sent to the SEG pin of the pixel Pab, but the present disclosure is not limited thereto. The first control signal Sc_a and the second control signal Sc_b will form an alternating voltage difference VSEGab on the pixel Pab to enable the pixel Pab, wherein the maximum value of the voltage difference VSEGab is the voltage level VP, which may be, for example, twice the difference between the voltage levels V4 and V1.

In addition, in some embodiments, the signal generating circuit 110 can send a control signal having a fixed voltage level (e.g., a ground level) to other pins (or at least part of other pins) of the display module LCM, so that non-tested pixels are not enabled.

In other embodiments, the signal generating circuit 110 may also send a third control signal having the same/in-phase waveform as one of the first control signal Sc_a and the second control signal Sc_b to other pins (or at least part of other pins) of the display module LCM similarly to the embodiment of FIG. 3, so that the non-tested pixels are not enabled. In other words, for the non-tested pixels, the control signals received by the corresponding pins may have different forms, as long as the voltage difference formed by the corresponding pins is not sufficient to enable the non-tested pixels.

During the period when the pixel Pab is enabled in response to the first control signal Sc_a and the second control signal Sc_b, the changes of the power signal VLCDn in the normal state and the power signal VLCDf in the abnormal state (i.e., the state where a short circuit occurs) are similar to the embodiment of Figure 3 above, that is, the discharge period Tff in the abnormal state will be shorter than the discharge period Tfn in the normal state, the charge period Trf in the abnormal state will be longer than the charge period Trn in the normal state, and the complete charge and discharge period Tf in the abnormal state will be longer than the complete charge and discharge period Tn in the normal state. Therefore, a counting method similar to the above can be used to determine whether the pins and lines associated with the pixel Pab currently being tested are abnormal.

Compared with the embodiment of FIG. 3 , since the present embodiment directly uses the waveform of the LCD driving signal as the test waveform for testing, the signal generating circuit 110 does not need to make any additional output setting modification or add any additional circuit. The test can be realized by only sending the corresponding test waveform to the pixel Pab to be tested in sequence according to the test sequence, so that the function and operation of the test mode can be easily implemented on the existing LCD driver, effectively reducing the manufacturing cost of designing and modifying the circuit.

FIG5 is a flow chart of the state detection method of the display module of an embodiment of the present disclosure. Referring to FIG5, the state detection method of the present embodiment can be applied to the display device and its controller described in the embodiments of FIG1 to FIG4, and the state detection method includes: in a test mode (such as TM), a first control signal (such as Sc_a) having a first test waveform (such as WF1) is sent to one of the pins of the display module (such as LCM), and a second control signal (such as Sc_b) having a second test waveform (such as WF2) is sent to another pin of the display module (step S110), wherein the one of the pins and the other of the pins are two pins corresponding to a pixel to be tested (such as Pab) in the display module.

Next, the power signal (such as VLCD) used to generate the control signal is detected (step S120), and the detection value (such as CTV) corresponding to the pixel to be tested is generated according to the change of the power signal (step S130), wherein the change of the power signal can be at least one of the charging period, the discharging period and the charging and discharging period of the power signal. The detection value can represent whether the related pins/lines of the pixel to be tested have a short circuit and whether the short circuit is serious.

More specifically, the step flow of the state detection method in some specific test scenarios can be shown in FIG6, where FIG6 is a step flow chart of the state detection method of the display module of another embodiment of the present disclosure.

Please refer to Figure 6. In this embodiment, before conducting actual testing, engineers can first test the display modules of the same batch that are confirmed to be in normal condition, obtain the test value of the display modules that are tested normally as the screening value (step S210), and use this screening value as the judgment standard for subsequent testing.

After obtaining the screening value, the controller can send a first control signal having a first test waveform and a second control signal having a second test waveform to a group of pins defined as detection pins in the display module (step S220) to enable the pixel to be tested. Step S220 is similar to step S110 of the aforementioned embodiment, and can be performed with reference to the relevant description of the above-mentioned embodiments of Figures 1 to 5, which will not be repeated here.

In addition, the controller may also send a third control signal having a third test waveform to some or all of the remaining pins (step S230) to disable other non-test pixels. Depending on the test waveform used in step S220, the third test waveform may be the same waveform as one of the first test waveform and the second test waveform, or a fixed voltage level, but the present disclosure is not limited thereto. Step S230 may also be performed with reference to the relevant description of the above-mentioned embodiments of Figures 1 to 5, and will not be repeated here.

Next, the controller detects the power signal used to generate the control signal (step S240), and counts the change time of the power signal to generate a detection value (step S250), and then compares the detection value with the screening value to determine whether the pixel currently detected is abnormal (step S260). The change time of the power signal can be at least one of the charging period, the discharging period, and the charging and discharging period of the power signal, and the present disclosure is not limited to this.

If the currently detected pixel is judged to be abnormal in step S260, the controller can further output the detection result and the related detection value (step S270); on the contrary, if the currently detected pixel is judged to be normal in step S260, the controller can further judge whether the corresponding pins of all pixels have completed the test (step S280).

If there are still pixels that have not completed the test, the controller selects a set of pins corresponding to an untested pixel as the detection pins (step S290), and returns to step S220 to test and obtain the detection value. On the other hand, if it is determined in step S280 that all pixels have completed the test, the controller will end the test process and leave the test mode.

It should be noted that the step flow of FIG. 6 is only an illustrative example of the present disclosure. A person with ordinary knowledge in the field can change the above step flow without affecting the purpose of the test after referring to the above description. For example, in some embodiments, the controller can omit step S260, and output the test result to the engineer for judgment regardless of whether the test value exceeds the screening value. In other words, as long as a specific test waveform is output to enable a certain pixel to be tested of the display module, and other non-test pixels are disabled, and then the test method is generated by detecting the change of the power signal to indicate the abnormality of the related pins/lines of the pixel to be tested, it belongs to the scope disclosed and protected by this application.

This disclosure is not limited to the above-mentioned implementation methods, and various changes can be made within the scope indicated in the claim. The implementation methods obtained by appropriately combining the technical means disclosed in different implementation methods are also included in the technical scope of this disclosure. Furthermore, by combining the technical means disclosed in each implementation method, new technical features can be formed.

In summary, the controller, segmented LCD device, and display module state detection method disclosed herein can more accurately detect the actual short circuit degree and abnormal conditions of the pins corresponding to each pixel of the display module, so that the availability of the display module can be more accurately evaluated according to the required application scenario in the back-end application, thereby avoiding excessive screening of modules with slight short circuit conditions but no effect on the display, resulting in unnecessary increase in manufacturing costs; or avoiding the unpredictable product reliability risk caused by the failure to screen out mild short circuit conditions in some applications requiring high reliability. In addition, some embodiments disclosed herein can set the function and operation of the test mode on the existing LCD driver without any additional output setting modification or additional circuit addition, effectively reducing the manufacturing cost of designing and modifying the circuit.

100: Controller

110:Signal generating circuit

120: Abnormal detection circuit

122: Voltage detection unit

124: Counting unit

130: Power supply circuit

CTV: test value

Pab: Pixel

Sc_a, Sc_b: control signal

St1, St2: trigger signal

TM: Test mode

VLCD: power signal

Vt1: first voltage

Vt2: Second voltage

WF1, WF2: test waveform

Claims (10)

A controller is suitable for driving a display module having a plurality of pixels, wherein the controller comprises: a signal generating circuit, coupled to the display module, and generating a plurality of control signals for driving the pixels based on a power signal, wherein the signal generating circuit outputs a control signal having a test waveform in a test mode; and an abnormality detecting circuit, receiving the power signal, and detecting the power signal in response to a change of the test waveform in the test mode, thereby detecting an abnormality. To generate a detection value corresponding to a pixel to be tested among the pixels; wherein each pixel has two pins to receive the control signals, the control signals include a first control signal with a first test waveform and a second control signal with a second test waveform; the signal generating circuit is used to output the first control signal and the second control signal to the two pins of the pixel to be tested in the test mode, so that the abnormal detection circuit generates the detection value corresponding to the pixel to be tested. A controller as described in claim 1, wherein the control signals further include a third control signal having a third test waveform; the signal generating circuit is used to output the third control signal to the pins of at least part of the pixels other than the pixel to be tested in the test mode, wherein the third test waveform is different from at least one of the first test waveform and the second test waveform. A controller as described in claim 1, wherein the detection value indicates the degree of short circuit of the pin of the pixel to be tested in a proportional relationship. A controller as described in claim 1, wherein the voltage difference between the first test waveform and the second test waveform constitutes a periodic multi-stage AC square wave. A controller as described in claim 1, wherein the first test waveform and the second test waveform are periodic square waves that are inverted from each other. A controller as described in claim 1, wherein the abnormality detection circuit comprises: a voltage detection unit for detecting the voltage level of the power signal in the test mode to generate a trigger signal; and a counting unit coupled to the voltage detection unit for counting in response to the trigger signal and generating the detection value accordingly, wherein the counting unit counts at least one of a falling period and a rising period of the voltage level of the power signal as the detection value. A segment code liquid crystal display device comprises: a segment code liquid crystal display module having a plurality of display segments, wherein each of the display segments has two pins; and a controller coupled to the pins for generating a plurality of control signals based on a power signal and outputting them to the pins respectively to drive the segment code liquid crystal display module, wherein the controller outputs a control signal having a test waveform in a test mode, and detects the power signal in response to the change of the test waveform, thereby generating a detection value indicating the degree of short circuit of one of the display segments. A segmented liquid crystal display device as described in claim 7, wherein the controller comprises: a signal generating circuit for receiving the power signal to generate the control signals; a voltage detection unit for detecting the voltage level of the power signal in the test mode to generate a trigger signal; and a counting unit coupled to the voltage detection unit for counting in response to the trigger signal and generating the detection value accordingly. A segment code liquid crystal display device as described in claim 8, wherein: when the voltage level of the power signal drops below a first voltage, the voltage detection unit generates a first trigger signal, and the counting unit starts counting in response to the first trigger signal; and when the voltage level of the power signal rises to a level higher than a second voltage, the voltage detection unit generates a second trigger signal, and the counting unit stops counting in response to the second trigger signal. A state detection method for a display module includes: sending a first control signal having a first test waveform to one of a plurality of pins of a display module, and sending a second control signal having a second test waveform to another of the pins of the display module, wherein the one of the pins and the other of the pins correspond to a pixel to be tested of the display module; detecting a power signal used to generate the control signal; and generating a detection value corresponding to the pixel to be tested according to the change of the power signal.