TWI868733B - A detection system for a dram memory module - Google Patents

Abstract

A detection system for a DRAM memory module, used to verify the function of writing and reading information in an EEPROM memory, that is contained in a DRAM memory module. The detection system includes at least one memory module slot, and the processing unit. The memory module slot is used to insert the DRAM memory module, and the DRAM memory module has EEPROM memory. After using the operating system to control the processing unit, the I²C operation register in the processing unit can access the DRAM memory module through the I²C BUS. And can write and read test data in the EEPROM memory. When the test data does not have the sample data, it can be replaced by SPD data.

Description

Dynamic random access memory module detection system

The present invention relates to the technical field of a detection system for a dynamic random access memory module of an AMD system, and in particular to a detection system for verifying the information write and read functions of an electronically erasable rewritable read-only memory contained in the dynamic random access memory module.

Generally speaking, server or computer assemblers only perform read and write stress tests on memory during production, that is, testing the stability of the memory and its ability to store and retrieve data. However, the serial presence test (SPD) recorded in the electronically erasable programmable read-only memory (EEPROM) on the memory is also a test method. Detect; SPD) information is not detected, but the serial presence detection information usually records some important information about the memory module, such as the type of memory particles, serial number, capacity, speed, required voltage, and manufacturer, etc. If the serial presence detection information can be detected and the relevant information can be obtained, the access timing of the memory module used can be set to the best state when using the memory, which can ensure that the system can operate normally and stably.

For example, application number CN201010186093.3 is designed to avoid communication address duplication conflicts caused by multiple blade systems sharing the same Inter-Integrated Circuit (I ² C) bus, and adopts a method of automatically allocating different I ² C communication addresses to the electronically erasable rewritable read-only memory in the electronic device to improve this situation.

However, when used with AMD systems, the serial presence detection information is not detected. When users use AMD systems, although they may find that the price-performance ratio is ideal in the early stage, after long-term use, they will find that it is not stable, the performance drops quickly, and many other shortcomings.

Therefore, in order to solve the problem of poor use of some AMD systems, the main purpose of this invention is to provide a detection system for the dynamic random-access memory (DRAM) module of the AMD system, so as to develop an ideal technical method to solve the above problems.

In view of the fact that the prior art does not detect the information writing and reading functions in the electronically erasable rewritable read-only memory, the main purpose of the present invention is to provide a detection system for the dynamic random access memory module of the AMD system.

In order to solve the problems of the previous technology, the necessary technical means adopted by this invention is to provide a detection system for the dynamic random access memory module of the AMD system, and it can be verified in two ways.

The present invention provides a detection system for a dynamic random access memory module of an AMD system, which is used to verify the information writing and reading functions of the electronically erasable rewritable read-only memory contained in the dynamic random access memory module. The detection system includes at least one memory module slot and a processing unit.

The memory module slot is used to insert the dynamic random access memory module, and the dynamic random access memory module has an electronically erasable rewritable read-only memory.

The processing unit includes an I ² C operation register, and the I ² C operation register can be electrically coupled to the memory module slot via an I ² C bus.

The I ² C operation register in the processing unit can access the dynamic random access memory module through the I ² C bus, and can write and read test data in the electronically erasable rewritable read-only memory.

In the detection system described above, the information includes serial presence detection information and temperature sensor on DIMMs (TSOD) information. The memory controller can access the DRAM module through the I ² C bus by reading the I ² C slave address in the DRAM module, thereby accessing and reading the serial presence detection information and temperature sensor information.

In the detection system described above, the memory module slot is suitable for use in places with complex structures and where component contents can be reused, that is, space can be reserved in the memory module slot of the present invention, and when the ^I2C operation register can access the dynamic random access memory module through the ^I2C bus, the access content can be stored in the electronically erasable rewritable read-only memory on the dynamic random access memory module.

Next, in the detection system described above, the processing unit is an AMD central processing unit (CPU), which has the advantages of high-performance computing capabilities and can improve processor efficiency. In addition, because the yield of AMD central processors is improved, the production cost can be greatly reduced.

In addition, when the detection system described above is in operation, the AMD central processor will be controlled through the operating system.

In the detection system as described above, a PCA9546A chip is further included. The PCA9546A chip has a plurality of mapping addresses, and the plurality of mapping addresses further include at least one mapping address belonging to a dynamic random access memory module. When the I ² C operation register in the processing unit accesses the mapping address belonging to the dynamic random access memory module through the PCA9546A chip, all dynamic random access memory modules are accessed through the I ² C bus, and then the specific dynamic random access memory module can be accessed through the access address to which the specific dynamic random access memory module belongs among all the dynamic random access memory modules.

As in the detection system described above, the test data can be one of the sample data and the serial presence detection information. When the detection system does not yet have the original sample data, in addition to writing the sample data into the EEPROM and then reading it out, the serial presence detection information can also be written first and then transmitted to the EEPROM of the DRAM module through the I ² C slave address. Afterwards, the I ² C bus can be used to read the serial presence detection information previously written in the EEPROM of the DRAM module.

In addition, since the number of write and read operations of the electronically erasable rewritable read-only memory is limited, the test data in the detection system is verified by writing and reading a small amount, which can reduce the time required for each verification.

The present invention can also be a detection system for a dynamic random access memory module of an AMD processor system, used to verify the information writing and reading functions of the electronically erasable rewritable read-only memory contained in the dynamic random access memory module. The detection system includes at least one memory module slot and a baseboard management controller (Board Management Controller; BMC).

The memory module slot can be used to insert a dynamic random access memory module, and the dynamic random access memory module has an electronically erasable rewritable read-only memory.

The baseboard management controller can be electrically coupled to the memory module socket via an I ² C bus.

The baseboard management controller accesses the dynamic random access memory module through the I ² C bus and writes and reads test data in the electronically erasable rewritable read-only memory.

The detection system as described above further includes a PCA9546A chip, the PCA9546A chip has a plurality of mapping addresses, and the plurality of mapping addresses include at least one mapping address belonging to a dynamic random access memory module. When the baseboard management controller accesses the mapping address belonging to the dynamic random access memory module through the PCA9546A chip, it accesses all the dynamic random access memory modules through the I ² C bus, and then accesses the specific dynamic random access memory module through the access address of the specific dynamic random access memory module in all the dynamic random access memory modules.

Therefore, the present invention provides a detection system for a dynamic random access memory module of an AMD system, which can access the electronically erasable rewritable read-only memory of the dynamic random access memory module through an I ² C bus through a processing unit with a central processor or a baseboard management controller, and can also write and read test data in the electronically erasable rewritable read-only memory. When the test data does not have sample data, a serial presence detection information method of first writing and then reading can be used for verification.

The specific embodiments adopted by the present invention will be further described through the following embodiments and drawings.

1: Detection system

2: Memory module slot

3: Operating system

10: Dynamic random access memory module

20: Processing unit

201: AMD CPU

202: Baseboard management controller

22:I ² C Operation Register

24:I ² C bus

30: PCA9546A chip

40: Electronically erasable rewritable read-only memory

The first figure is a functional relationship diagram of the detection system when the processing unit of the present invention is a central processing unit.

The second figure is a flow chart showing the method of the detection system of the present invention to process unit detection sample data.

The third figure is a flow chart showing the method of the detection system of the present invention to detect serial existence detection information by processing unit detection.

The fourth figure is a functional relationship diagram showing another embodiment of the detection system of the present invention.

The fifth figure is a flow chart showing the method of detecting sample data with a baseboard management controller according to the present invention.

The sixth figure is a schematic diagram showing the method of detecting sample data when using a baseboard management controller according to the present invention.

The purpose of the present invention is to provide a detection system for a dynamic random access memory module of an AMD system, which is used to verify the information writing and reading functions of the electronically erasable rewritable read-only memory contained in the dynamic random access memory module, and includes a first embodiment and a second embodiment. According to the specification of the JEDEC Solid State Technology Association, the electronically erasable rewritable read-only memory contains 512 bytes, which are distributed in two storage pages, each storage page has 256 bytes, each storage page has 2 quadrants, and each quadrant has 128 bytes, so the electronically erasable rewritable read-only memory contains a total of 512 bytes.

Please refer to the first figure, which is a functional association diagram of the detection system 1 when the processing unit 20 of the present invention is a central processor. In the first embodiment, it can be seen that the detection system 1 includes sixteen memory module slots 2 and a processing unit 20 which is an AMD central processor 201.

The memory module slot 2 is used to insert the dynamic random access memory module 10, so the sixteen memory module slots 2 can be inserted with sixteen dynamic random access memory modules 10, and each dynamic random access memory module 10 has an electronically erasable rewritable read-only memory 40, and the electronically erasable rewritable read-only memory 40 can write serial presence detection information, so the electronically erasable rewritable read-only memory 40 is the place where the information writing and reading function is to be detected.

The processing unit 20 includes an I ² C operation register 22 . The I ² C operation register 22 can be electrically coupled to each memory module slot 2 via an I ² C bus 24 . As shown in the ^figure , there is an I 2 C bus 24 on each side. The I ² C operation register 22 is electrically coupled to a total of sixteen memory module slots 2 on the left and right sides via the two I ² C buses 24 .

The I ² C operation register 22 in the processing unit 20 can access the DRAM module 10 inserted in the memory module slot 2 through the I ² C bus 24 and can write and read test data in the EEPROM 40 on the DRAM module 10 .

In the detection system 1 described above, the information includes serial presence detection information and temperature sensing information. A memory controller (not shown) can access the dynamic random access memory module 10 through the I ² C bus 24 by reading the I ² C slave address corresponding to the dynamic random access memory module 10, so as to access and read the serial presence detection information and temperature sensing information.

As mentioned above, the memory module slot 2 in the detection system 1 is suitable for use in a computer device with a complex structure and reusable components. The memory module slot 2 of the present invention can reserve more expandable space. When the ^I2C operation register 22 accesses the dynamic random access memory module 10 through the ^I2C bus 24, the sample data or the serial storage detection information and other test data can be written and stored in the electronically erasable rewritable read-only memory 40 on the dynamic random access memory module 10 as the content that can be accessed later.

It is to be noted that when the detection system 1 described above is in operation, the operating system 3 will be used to control the processing unit 20 to start operation. The processing unit 20 in the detection system 1 is an AMD central processor 201, which has the advantages of high-performance computing capabilities and can improve processor efficiency. In addition, because the yield of the AMD central processor 201 is improved, the cost can be greatly reduced when producing and assembling servers or laptops. The above-mentioned detection system 1 will control the central processor through the operating system 3 to start operation at the beginning.

In addition, the detection system 1 as described above further includes a PCA9546A chip 30, which has a plurality of mapping addresses, including at least one mapping address belonging to the dynamic random access memory module 10. When the ^I2C operation register 22 in the processing unit 20 accesses the mapping address belonging to the dynamic random access memory module 10 through the PCA9546A chip 30 and accesses all the dynamic random access memory modules 10 through the ^I2C bus 24, the specific dynamic random access memory module 10 is accessed through the access address belonging to the specific dynamic random access memory module 10 in all the dynamic random access memory modules 10. That is, the PCA9546A chip 30 has at least one mapping address belonging to the DRAM module 10. When the ^I2C operation register 22 passes through the PCA9546A chip 30, all DRAM modules 10 are accessed through the ^I2C bus 24. The specific DRAM module 10 can be accessed through the access address of the specific DRAM module 10 in the DRAM module 10.

As in the detection system 1 described above, the test data can be sample data or serial presence detection information. When the detection system 1 does not have the original sample data, in addition to writing the sample data into the EEPROM 40 and then reading it out, the serial presence detection information can also be written first. The process is the same, accessing the EEPROM 40 of the DRAM module 10 through the I ² C slave address, and then using the I ² C bus 24 to read the previously written serial presence detection information in the EEPROM 40 of the DRAM module 10 to detect the write-read function.

In addition, since the number of write and read times of the EEPROM 40 is limited, the test data in the detection system 1 is verified by writing and reading a small amount, which can reduce the time and energy required for each verification. For example, only 3 bytes of sample data are written in each quadrant of the EEPROM as a write and read test, which can effectively save test time and meet the hardware limitations of the EEPROM.

Please refer to the second figure, which is a flow chart of the method of the detection system 1 of the present invention detecting sample data with the processing unit 20, and the third figure, which is a flow chart of the method of the detection system 1 of the present invention detecting serial existence detection information with the processing unit 20. In the aforementioned first embodiment, the detection method can be further described by using the detection of the horsea model. The detection method can be divided into a state where there is sample data originally and a state where there is no sample data originally and then reads and writes sample data or serial existence detection information.

The method shown in the second figure, which is the state with original sample data, includes the following steps:

Step S01: The detection system 1 controls the AMD central processor 201 through the operating system 3 to start operation.

Step S02: The I ² C operation register 22 in the AMD CPU 201 is coupled to the memory module slot 2 via the I ² C bus 24 through the PCA9546A chip 30, and accesses the I ² C slave address corresponding to the specific dynamic random access memory module 10 according to the mapping address of the dynamic random access memory module 10 on the PCA9546A chip 30, so as to access the specific dynamic random access memory module 10.

Step S03: In the electronically erasable rewritable read-only memory 40 of the dynamic random access memory module 10, read the original sample data in the electronically erasable rewritable read-only memory 40 as test data.

The method for detecting sample data or serial existence detection information in the third figure includes the following steps:

Step S11: The detection system 1 controls the AMD central processor 201 through the operating system 3 to start operation.

Step S12: The I ² C operation register 22 in the AMD CPU 201 is coupled to the memory module slot 2 via the I ² C bus 24 through the PCA9546A chip 30, and accesses the I ² C slave address corresponding to the specific dynamic random access memory module 10 according to the mapping address of the dynamic random access memory module 10 on the PCA9546A chip 30, so as to access the specific dynamic random access memory module 10.

Step S13: Write sample data or serial presence detection information into the electronically erasable rewritable read-only memory 40 of the dynamic random access memory module 10 as test data.

Step S14: Read the test data from the electronically erasable rewritable read-only memory 40.

Please refer to the fourth figure, which is a functional association diagram of another embodiment of the detection system 1 of the present invention. In the second embodiment, the present invention is also a detection system 1 of a dynamic random access memory module 10 of an AMD processor system, which is used to verify the information writing and reading functions of the electronically erasable rewritable read-only memory 40 included in the dynamic random access memory module 10. The visible detection system 1 in the figure includes sixteen memory module slots 2 and a baseboard management controller 202.

The memory module slot 2 can be used to insert the dynamic random access memory module 10, so the sixteen memory module slots 2 can be inserted with sixteen dynamic random access memory modules 10, and each dynamic random access memory module 10 has an electronically erasable rewritable read-only memory 40, and the electronically erasable rewritable read-only memory 40 can write serial presence detection information, so the electronically erasable rewritable read-only memory 40 is the place where the information writing and reading function is to be detected. .

The baseboard management controller 202 can be electrically coupled to each memory module slot 2 via an I ² C bus 24 . As shown in the figure, there is an I ² C bus 24 on each side. The baseboard management controller 202 is electrically coupled to a total of sixteen memory module slots 2 on the left and right sides via the two I ² C buses 24 .

The baseboard management controller 202 accesses the DRAM module 10 inserted in the memory module slot 2 via the I ² C bus 24 , and can write and read test data in the EEPROM 40 on the DRAM module 10 .

As described above, the detection system 1 further includes a PCA9546A chip 30, which has a plurality of mapping addresses, including at least one mapping address belonging to the dynamic random access memory module 10. When the baseboard management controller 202 accesses the mapping address belonging to the dynamic random access memory module 10 through the PCA9546A chip 30 and accesses all the dynamic random access memory modules 10 through the I ² C bus 24, the specific dynamic random access memory module 10 can be accessed through the access address of the specific dynamic random access memory module 10 in all the dynamic random access memory modules 10.

As in the detection system 1 described above, the test data may also be sample data or serial presence detection information. When the detection system 1 does not have the original sample data yet, in addition to writing the sample data into the EEPROM 40 and then reading it out, the serial presence detection information may also be written first. The process is the same, accessing the EEPROM 40 of the DRAM module 10 through the I ² C slave address, and then using the I ² C bus 24 to read the previously written serial presence detection information in the EEPROM 40 of the DRAM module 10 to detect the write-read function.

In addition, since the number of write and read operations of the EEPROM 40 is limited, the test data in the detection system 1 is verified by writing and reading a small amount of data, which can reduce the time and energy required for each verification. For example, only 3 bytes of sample data are written in each quadrant of the EEPROM as a write and read test, which can effectively save test time and meet the hardware limitations of the EEPROM. In the same time, multiple averages can be used for verification to obtain the most accurate result, that is, the number of samples can be increased to obtain the average value of the test to confirm whether the information writing and reading function in the EEPROM 40 is normal.

Please refer to the fifth figure, which is a flow chart showing the method of detecting sample data by the baseboard management controller 202 of the present invention, and the sixth figure, which is a schematic diagram of the method of detecting sample data by the baseboard management controller 202 of the present invention. The method is also divided into a state where there is sample data originally and a state where there is no sample data originally and then the sample data is read and written or the detection information exists serially.

The method in the state where the original sample data is available includes the following steps:

Step S21: The detection system 1 controls the sensor of the baseboard management controller 202 to be turned off through the operating system 3 to reduce the influence of the baseboard management controller 202 on the electronically erasable rewritable read-only memory 40.

Step S22: Switch the PCA9546A chip 30 to channels 0, 1, 2, and 3 in sequence. The baseboard management controller 202 will communicate with the memory module slot 2 through the PCA9546A chip 30 via the I ² C bus 24, and access the I ² C slave address corresponding to the specific dynamic random access memory module 10 according to the mapping address of the dynamic random access memory module 10 on the PCA9546A chip 30, so as to access the specific dynamic random access memory module 10.

Step S23: In the electronically erasable rewritable read-only memory 40 of the dynamic random access memory module 10, read the original sample data in the electronically erasable rewritable read-only memory 40 as test data.

Step S24: After the test, turn on the sensor of the baseboard management controller 202.

The method of using read and write sample data or serial presence detection information as test data includes the following steps:

Step S31: The detection system 1 controls the sensor of the baseboard management controller 202 to be turned off through the operating system 3 to reduce the influence of the baseboard management controller 202 on the electronically erasable rewritable read-only memory 40.

Step S32: Switch the PCA9546A chip 30 to channels 0, 1, 2, and 3 in sequence. The baseboard management controller 202 will communicate with the memory module slot 2 through the PCA9546A chip 30 via the I ² C bus 24, and access the I ² C slave address corresponding to the specific dynamic random access memory module 10 according to the mapping address of the dynamic random access memory module 10 on the PCA9546A chip 30, so as to access the specific dynamic random access memory module 10.

Step S33: Write sample data or serial presence detection information into the electronically erasable rewritable read-only memory 40 of the dynamic random access memory module 10 as test data.

Step S34: Read the test data from the electronically erasable rewritable read-only memory 40.

Step S35: After the test, turn on the sensor of the baseboard management controller 202.

Therefore, the present invention provides a detection system 1 for a dynamic random access memory module 10 of an AMD system, which can access the dynamic random access memory module 10 through an I ² C bus 24 via a processing unit 20 of an AMD central processor or a baseboard management controller 202, and further can write and read test data in an electronically erasable rewritable read-only memory 40. When the test data does not have sample data, the sample data can be written first and then read, or the serial presence detection information method can be adopted for verification.

The above detailed description of the preferred specific embodiments is intended to more clearly describe the features and spirit of the present invention, but is not intended to limit the scope of the present invention by the preferred specific embodiments disclosed above. On the contrary, the purpose is to cover various changes and arrangements with equivalents within the scope of the patent that the present invention intends to apply for.

1: Detection system

2: Memory module slot

3: Operating system

10: Dynamic random access memory module

20: Processing unit

201: AMD CPU

22:I ² C Operation Register

24:I ² C bus

30: PCA9546A chip

40: Electronically erasable rewritable read-only memory

Claims (2)

A detection system for a dynamic random access memory module is used to verify the information writing and reading function of an electronically erasable rewritable read-only memory contained in the dynamic random access memory module. The detection system comprises: at least one memory module slot, the memory module slot is used to insert the dynamic random access memory module, and the dynamic random access memory module has the electronically erasable rewritable read-only memory; a baseboard management controller, the baseboard management controller is electrically coupled to the memory module slot through an I ² C bus; wherein an operating system controls to close the sensor of the baseboard management controller, and the baseboard management controller controls to close the sensor through the I ² The DRAM module is accessed through a C bus, and a test data is written into and read from the DRAM. A detection system as described in claim 2, wherein the detection system further includes a PCA9546A chip, the PCA9546A chip has a plurality of mapping addresses, and the plurality of mapping addresses include at least one mapping address belonging to the dynamic random access memory module. When the baseboard management controller accesses the mapping address belonging to the dynamic random access memory module through the PCA9546A chip, the dynamic random access memory module is accessed through the ^I2C bus, and the specific dynamic random access memory module can be accessed through the access address belonging to the specific dynamic random access memory module in the dynamic random access memory module.