TWI867883B - Light-emitting signal generation circuit and display device - Google Patents

Abstract

A light-emitting signal generation circuit and a display device are provided. The light-emitting signal generation circuit includes a first signal generating circuit, a second signal generating circuit, an RS latch circuit and an output selection circuit. The first signal generating circuit provides a first light-emitting timing signal. The second signal generating circuit provides a second light-emitting timing signal. The RS latch circuit generates a light-emitting modulation signal based on the first light-emitting timing signal and the second light-emitting timing signal, wherein the pulse width of the light-emitting modulation signal is related to the phase difference of the first light-emitting timing signal and the second light-emitting timing signal. The output selection circuit provides a first light-emitting timing signal or a light-emitting modulation signal to a display module as a light-emitting signal based on a voltage switch signal.

Description

Luminescent signal generating circuit and display device

The present invention relates to a signal generating circuit, and in particular to a light emitting signal generating circuit and a display device.

In recent years, due to its advantages of low power consumption, thinner display modules, bright colors, more obvious contrast, and overcoming the problem of motion blur, self-luminous display technology has become the mainstream of display devices. Self-luminous display devices are mainly divided into organic light-emitting diode (OLED) displays and micro-light-emitting diode (μLED) displays, and in the micro-light-emitting diode pixel circuit, pulse amplitude modulation (PAM) is used to drive the micro-light-emitting diode. However, in order to improve the display brightness of micro-light-emitting diode displays, multiple emitting technology has been proposed. Since multi-luminescence technology mainly determines its total luminescence time (that is, its luminescence brightness) through the number of pulses, but too many pulses will cause excessive power consumption, how to increase the brightness of the display while reducing the impact of power consumption has become a problem that needs to be solved urgently.

The present invention provides a luminous signal generating circuit and a display device, which can adjust the pulse width of the luminous signal driving the micro-light-emitting diode pixel circuit to reduce the pulse number of the luminous signal, thereby reducing the overall power consumption.

The light-emitting signal generating circuit of the present invention comprises a first signal generating circuit, a second signal generating circuit, an RS latch circuit and an output selection circuit. The first signal generating circuit receives a first trigger signal, a first clock signal and a second clock signal to provide a first light-emitting timing signal. The second signal generating circuit receives a second trigger signal, a third clock signal and a fourth clock signal to provide a second light-emitting timing signal. The RS latch circuit couples the first signal generating circuit and the second signal generating circuit to generate a light-emitting modulation signal based on the first light-emitting timing signal and the second light-emitting timing signal, wherein the pulse width of the light-emitting modulation signal is related to the phase difference between the first light-emitting timing signal and the second light-emitting timing signal. The output selection circuit is coupled to the RS latch circuit and the first signal generating circuit, and receives the voltage switch signal to provide a first light emitting timing signal or a light emitting modulation signal to the display module as a light emitting signal based on the voltage switch signal.

The display device of the present invention includes a display module, a timing controller and a light driver. The display module has a plurality of pixel circuits. The timing controller is used to provide a first start signal, a second start signal, a first clock signal, a second clock signal, a third clock signal and a fourth clock signal. The light driver includes a plurality of light signal generating circuits as described above, and is coupled to the display module and the timing controller to receive the first start signal, the second start signal, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal, wherein the light driver provides a plurality of light signals based on the first start signal, the second start signal, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal.

Based on the above, in the luminous signal generating circuit and the display device of the embodiment of the present invention, the pulse width of the luminous modulation signal is adjusted corresponding to the phase difference between the first luminous timing signal and the second luminous timing signal, so the pulse width of the luminous signal can adopt the pulse width of the luminous modulation signal or the pulse width of the first luminous timing signal as needed. Thus, through the luminous modulation signal with adjustable pulse width, the number of pulses can be reduced to reduce the overall power consumption of the display device.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless expressly defined as such in this document.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". " or "means" and/or". As used herein, the terms "and/or" include any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and/or "include" specify the presence and/or parts of the features, regions, entireties, steps, operations, elements, components and/or parts, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and/or combinations thereof.

FIG1 is a system schematic diagram of a luminous signal generating circuit according to an embodiment of the present invention. Referring to FIG1 , in the present embodiment, the luminous signal generating circuit 100 is used to generate a luminous signal EM[n] for driving a self-luminous pixel circuit (such as the pixel circuit PX shown in FIG10 ), and includes a first signal generating circuit 110, a second signal generating circuit 120, an RS latch circuit 130, and an output selection circuit 140, wherein n is, for example, a positive integer, and the self-luminous pixel circuit is, for example, a micro-light emitting diode pixel, but the present embodiment is not limited thereto.

The first signal generating circuit 110 receives the first trigger signal R_out[n-1], the first clock signal CK1 and the second clock signal CK2 to provide the first light emission timing signal Out_R. The second signal generating circuit 120 receives the second trigger signal S_out[n-1], the third clock signal CK3 and the fourth clock signal CK4 to provide the second light emission timing signal Out_S. The RS latch circuit 130 couples the first signal generating circuit 110 and the second signal generating circuit 120 to generate a light emission modulation signal Out_Q based on the first light emission timing signal Out_R and the second light emission timing signal Out_S, wherein the pulse width of the light emission modulation signal Out_Q is related to the phase difference between the first light emission timing signal Out_R and the second light emission timing signal Out_S. The output selection circuit 140 is coupled to the RS latch circuit 130 and the first signal generating circuit 110, and receives the voltage switch signal V_switch to provide the first light timing signal Out_R or the light modulation signal Out_Q to the display module (such as the display module 1030 shown in FIG. 10 ) as the light signal EM[n] based on the voltage switch signal V_switch.

According to the above, when the enabling time of the first trigger signal and the second trigger signal has a phase difference (or time difference), the phase difference between the first light-emitting timing signal and the second light-emitting timing signal will be adjusted accordingly, so that the pulse width of the light-emitting modulation signal can be adjusted accordingly. Therefore, the pulse width of the light-emitting signal can adopt the pulse width of the light-emitting modulation signal or the pulse width of the first light-emitting timing signal as needed, and through the light-emitting modulation signal with adjustable pulse width, the number of pulses (i.e., the number of rising edges) driving the pixel circuit (such as the pixel circuit PX shown in FIG. 10) can be reduced to reduce the overall power consumption of the display device (such as the display device 1000 shown in FIG. 10).

In this embodiment, the first light emitting timing signal Out_R and the second light emitting timing signal Out_S are output to the next stage to serve as the first trigger signal R_out[n] and the second trigger signal S_out[n] of the next stage, but the embodiment of the present invention is not limited thereto.

In an embodiment of the present invention, the pulse widths of the first light emitting timing signal Out_R and the second light emitting timing signal Out_S may be smaller than or larger than the time length of a single horizontal scanning period, but the present invention is not limited thereto.

FIG2A is a circuit diagram of a light-emitting signal generating circuit according to an embodiment of the present invention. Referring to FIG1 and FIG2A, in this embodiment, the light-emitting signal generating circuit 100a assumes that a plurality of pixel circuits (e.g., the pixel circuit PX shown in FIG10) configured in a display module (e.g., the display module 1030 shown in FIG10) are composed of a plurality of P-type pixel circuits (e.g., composed of a plurality of P-type transistors), and the RS latch circuit 130a can be composed of at least a pair of NAND logic gates Nand1 and Nand2 to correspond to the control logic of the P-type pixel circuit (i.e., a low voltage level is enabled, and a high voltage level is disabled).

Specifically, when the set terminal S=1 (i.e., receiving a high voltage level) and the reset terminal R=0 (i.e., receiving a low voltage level) of the RS latch circuit 130a, the voltage level of the output terminal Q will be a low voltage level, and the voltage level of the inverting output terminal Ǭ will be a high voltage level; when the set terminal S=0 and the reset terminal R=1 of the RS latch circuit 130a, the voltage level of the output terminal Q will be a high voltage level. voltage level, and the voltage level of the inverting output terminal Ǭ will be a low voltage level; when the setting terminal S=1 and the reset terminal R=1 of the RS latch circuit 130a, the voltage level of the output terminal Q and the inverting output terminal Ǭ will maintain the previous state; and, when the setting terminal S=0 and the reset terminal R=0 of the RS latch circuit 130a, the voltage level of the output terminal Q and the inverting output terminal Ǭ will be a high voltage level at the same time.

In this embodiment, the output selection circuit 140a includes a first selection transistor TS1 and a second selection transistor TS2, wherein the first selection transistor TS1 is an N-type transistor, and the second selection transistor TS2 is a P-type transistor. The first selection transistor TS1 has a first end receiving the light modulation signal Out_Q, a control end receiving the voltage switch signal V_switch, and a second end providing the light signal EM[n]. The second selection transistor TS2 has a first end receiving the first light timing signal Out_R, a control end receiving the voltage switch signal V_switch, and a second end coupled to the second end of the first selection transistor TS1.

FIG2B to FIG2E are driving waveform diagrams of the light-emitting signal generating circuit according to an embodiment of the present invention. Please refer to FIG1 and FIG2A to FIG2E. In this embodiment, the driving is performed based on the control logic of the P-type pixel circuit, that is, the first signal generating circuit 110 and the second signal generating circuit 120 will preset the output disable level (i.e., high voltage level) of the first light-emitting timing signal Out_R and the second light-emitting timing signal Out_S, and the light-emitting signal EM[n] is also preset to a high voltage level. Next, when the first signal generating circuit 110 is triggered by the first trigger signal R_out[n-1], the first signal generating circuit 110 outputs the first clock signal CK1 as the first light emitting timing signal Out_R, and when the second clock signal CK2 is at an enable level (ie, a low voltage level), the first light emitting timing signal Out_R is pulled back to a high voltage level.

Similarly, when the second signal generating circuit 120 is triggered by the second trigger signal S_out[n-1], the second signal generating circuit 120 will output the third clock signal CK3 as the second light emitting timing signal Out_S, and when the fourth clock signal CK4 is at the enable level, the second light emitting timing signal Out_S will be pulled back to the high voltage level. In addition, when the first light emitting timing signal Out_R is enabled, the light emitting modulation signal Out_Q will be at a low voltage level, and when the second light emitting timing signal Out_S is enabled, the light emitting modulation signal Out_Q will be pulled back to the high voltage level.

In the embodiment of the present invention, when the pulse width of the luminous signal EM[n] is the same as the pulse width of the first luminous timing signal Out_R, the first selection transistor TS1 can be turned off and the second selection transistor TS2 can be turned on by the voltage switch signal V_switch, so that the first luminous timing signal Out_R is provided to the display module (such as the display module 1030 shown in FIG. 10 ) as the luminous signal EM[n]. B; when the pulse width of the luminous signal EM[n] is different from the pulse width of the first luminous timing signal Out_R, the first selection transistor TS1 can be turned on and the second selection transistor TS2 can be turned off through the voltage switch signal V_switch, so that the luminous modulation signal Out_Q is provided as the luminous signal EM[n] to the display module (such as the display module 1030 shown in Figure 10), as shown in Figures 2C~2E.

Furthermore, in the embodiment of the present invention, by shortening the phase difference (or time difference) between the first trigger signal R_out[n-1] and the second trigger signal S_out[n-1], the phase difference (or time difference) between the first light-emitting timing signal Out_R and the second light-emitting timing signal Out_S is shortened, thereby shortening the pulse width of the light-emitting signal EM[n], and even shortening it to be smaller than the pulse width of the first light-emitting timing signal Out_R, as shown in FIG. 2C. As shown; and, by increasing the phase difference (or time difference) between the first trigger signal R_out[n-1] and the second trigger signal S_out[n-1], the phase difference (or time difference) between the first light-emitting timing signal Out_R and the second light-emitting timing signal Out_S will be increased, thereby lengthening the pulse width of the light-emitting signal EM[n], and even making it several times longer than the pulse width of the first light-emitting timing signal Out_R, as shown in Figures 2D and 2E. The phase difference (or time difference) between the first trigger signal R_out[n-1] and the second trigger signal S_out[n-1] can roughly determine the pulse width of the luminous signal EM[n], while the phase difference (or time difference) between the first clock signal CK1 and the third clock signal CK3 can accurately determine the pulse width of the luminous signal EM[n]. In other words, the pulse width of the luminous signal EM[n] can be coarsely adjusted through the timing setting of the first trigger signal R_out[n-1] and the second trigger signal S_out[n-1], and the pulse width of the luminous signal EM[n] can be finely adjusted through the timing setting of the first clock signal CK1 and the third clock signal CK3. This depends on the circuit design and the embodiments of the present invention are not limited thereto.

FIG3 is a circuit diagram of an RS latch circuit according to an embodiment of the present invention. Referring to FIG1, FIG2A and FIG3, in this embodiment, the NAND logic gate Nand1 includes transistors T11 to T14, and the NAND logic gate Nand2 includes transistors T15 to T18, wherein the transistors T11, T12, T15, and T16 are, for example, P-type transistors, and the transistors T13, T14, T17, and T18 are, for example, N-type transistors. In this embodiment, transistors T11 and T12 are connected in parallel between the system high voltage VDD and the output terminal Q, and transistors T13 and T14 are connected in series between the output terminal Q and the system low voltage VSS; transistors T15 and T16 are connected in parallel between the system high voltage VDD and the inverting output terminal Ǭ, and transistors T17 and T18 are connected in series between the inverting output terminal Ǭ and the system low voltage VSS.

Furthermore, transistors T11 and T14 are controlled by the voltage level of the set terminal S, transistors T12 and T13 are controlled by the voltage level of the inverting output terminal Ǭ, transistors T15 and T17 are controlled by the voltage level of the output terminal Q, and transistors T16 and T18 are controlled by the voltage level of the reset terminal R.

FIG4 is a schematic circuit diagram of a first signal generating circuit and a second signal generating circuit according to an embodiment of the present invention. Referring to FIG1, FIG2A and FIG4, in this embodiment, the first signal generating circuit 110 and the second signal generating circuit 120 can be implemented by a signal generating circuit 400, and the signal generating circuit 400 includes transistors T21-T28 (corresponding to the first transistor to the eighth transistor) and a capacitor C21 (corresponding to the first capacitor), wherein the transistors T21-T28 are P-type transistors as an example.

The transistor T21 has a first end for receiving the first trigger signal R_out[n-1] or the second trigger signal S_out[n-1], a control end for receiving the first trigger signal R_out[n-1] or the second trigger signal S_out[n-1], and a second end. The transistor T22 has a first end for receiving the first clock signal CK1 or the third clock signal CK3, a control end coupled to the second end of the transistor T21, and a second end for providing the first light-emitting timing signal Out_R or the second light-emitting timing signal Out_S. The first capacitor C21 is coupled between the control end of the transistor T22 and the second end of the transistor T22.

The transistor T23 has a first end receiving the second clock signal CK2 or the fourth clock signal CK4, a control end receiving the second clock signal CK2 or the fourth clock signal CK4, and a second end. The transistor T24 has a first end coupled to the second end of the transistor T23, a control end coupled to the second end of the transistor T21, and a second end. The transistor T25 has a first end coupled to the second end of the transistor T24, a control end coupled to the second end of the transistor T21, and a second end receiving the gate high voltage VGH.

The transistor T26 has a first end coupled to the second end of the transistor T21, a control end coupled to the second end of the transistor T23, and a second end. The transistor T27 has a first end coupled to the second end of the transistor T26, a control end coupled to the second end of the transistor T23, and a second end receiving the gate high voltage VGH. The transistor T28 has a first end coupled to the second end of the transistor T22, a control end coupled to the second end of the transistor T23, and a second end receiving the gate high voltage VGH.

FIG5 is a circuit diagram of a first signal generating circuit and a second signal generating circuit according to another embodiment of the present invention. Referring to FIG1, FIG2A and FIG5, in this embodiment, the first signal generating circuit 110 and the second signal generating circuit 120 can be implemented by a signal generating circuit 500, and the signal generating circuit 500 includes transistors T31-T42 (corresponding to the ninth transistor to the twentieth transistor) and capacitors C31 and C32 (corresponding to the second capacitor and the third capacitor), wherein the transistors T31-T42 are P-type transistors as an example.

The transistor T31 has a first end receiving the first trigger signal R_out[n-1] or the second trigger signal S_out[n-1], a control end receiving the second clock signal CK2 or the fourth clock signal CK4, and a second end. The transistor T32 has a first end coupled to the second end of the transistor T31, a control end receiving the second clock signal CK2 or the fourth clock signal CK4, and a second end. The capacitor C31 is coupled between one of the first clock signal CK1 and the third clock signal CK3 and the second end of the transistor T32.

The transistor T33 has a first end receiving the gate low voltage VGL, a control end coupled to the second end of the transistor T32, and a second end providing the first light-emitting timing signal Out_R or the second light-emitting timing signal Out_S. The transistor T34 has a first end, a control end receiving the first trigger signal R_out[n-1] or the second trigger signal S_out[n-1], and a second end. The capacitor C32 is coupled between one of the second clock signal CK2 and the fourth clock signal CK4 and the first end of the transistor T34.

The transistor T35 has a first end coupled to the second end of the transistor T34, a control end receiving the first trigger signal R_out[n-1] or the second trigger signal S_out[n-1], and a second end receiving the gate high voltage VGH. The transistor T36 has a first end receiving the gate low voltage VGL, a control end coupled to the first end of the transistor T34, and a second end. The transistor T37 has a first end coupled to the second end of the transistor T36, a control end coupled to the second end of the transistor T32, and a second end.

The transistor T38 has a first end coupled to the second end of the transistor T37, a control end coupled to the second end of the tenth transistor T32, and a second end receiving the gate high voltage VGH. The transistor T39 has a first end coupled to the second end of the transistor T32, a control end coupled to the second end of the transistor T36, and a second end. The transistor T40 has a first end coupled to the second end of the transistor T39, a control end coupled to the second end of the transistor T36, and a second end receiving the gate high voltage VGH.

The transistor T41 has a first end coupled to the second end of the transistor T33, a control end coupled to the second end of the transistor T36, and a second end. The transistor T42 has a first end coupled to the second end of the transistor T41, a control end coupled to the second end of the transistor T36, and a second end receiving the gate high voltage VGH.

FIG6 is a circuit diagram of a light-emitting signal generating circuit according to another embodiment of the present invention. Referring to FIG1, FIG2A and FIG6, in this embodiment, the light-emitting signal generating circuit 100b assumes that a plurality of pixel circuits (e.g., the pixel circuit PX shown in FIG10) configured in the display module (e.g., the display module 1030 shown in FIG10) are composed of a plurality of N-type pixel circuits (e.g., composed of a plurality of N-type transistors), wherein the output selection circuit 140a can refer to FIG2A, and will not be described in detail here. At this time, the RS latch circuit 130b can be composed of at least a pair of NOR logic gates Nor1 and Nor2 to correspond to the control logic of the N-type pixel circuit (i.e., a high voltage level is enabled, and a low voltage level is disabled).

Specifically, when the set terminal S=1 and the reset terminal R=0 of the RS latch circuit 130b, the voltage level of the output terminal Q will be a high voltage level, and the voltage level of the inverting output terminal Ǭ will be a low voltage level; when the set terminal S=0 and the reset terminal R=1 of the RS latch circuit 130b, the voltage level of the output terminal Q will be a low voltage level, and the inverting output terminal Ǭ will be a high voltage level. The voltage level will be a high voltage level; when the setting terminal S=1 and the reset terminal R=1 of the RS latch circuit 130b, the voltage levels of the output terminal Q and the inverting output terminal Ǭ will be high voltage levels at the same time; and, when the setting terminal S=0 and the reset terminal R=0 of the RS latch circuit 130b, the voltage level of the output terminal Q and the inverting output terminal Ǭ will maintain the previous state.

FIG7 is a circuit diagram of an RS latch circuit according to an embodiment of the present invention. Referring to FIG1, FIG6 and FIG7, in this embodiment, the NOR logic gate Nor1 includes transistors T51 to T54, and the NOR logic gate Nor2 includes transistors T55 to T58, wherein the transistors T51, T52, T55 and T56 are P-type transistors, and the transistors T53, T54, T57 and T58 are N-type transistors. In this embodiment, transistors T51 and T52 are connected in series between the system high voltage VDD and the output terminal Q, and transistors T53 and T54 are connected in parallel between the output terminal Q and the system low voltage VSS; transistors T55 and T56 are connected in series between the system high voltage VDD and the inverting output terminal Ǭ, and transistors T57 and T58 are connected in parallel between the inverting output terminal Ǭ and the system low voltage VSS.

Furthermore, transistors T51 and T53 are controlled by the voltage level of the set terminal S, transistors T52 and T54 are controlled by the voltage level of the inverting output terminal Ǭ, transistors T56 and T57 are controlled by the voltage level of the output terminal Q, and transistors T55 and T58 are controlled by the voltage level of the reset terminal R.

FIG8 is a circuit diagram of a first signal generating circuit and a second signal generating circuit according to another embodiment of the present invention. Referring to FIG1 , FIG6 and FIG8 , in this embodiment, the first signal generating circuit 110 and the second signal generating circuit 120 can be implemented by a signal generating circuit 800, and the signal generating circuit 800 includes transistors T61-T71 (corresponding to the 21st transistor to the 31st transistor) and a resistor R61 (corresponding to the first resistor), wherein the transistors T61-T71 are N-type transistors as an example.

The transistor T61 has a first end for receiving the first direction scanning signal U2D, a control end for receiving the first trigger signal R_out[n-1] or the second trigger signal S_out[n-1], and a second end. The transistor T62 has a first end coupled to the second end of the transistor T61, a control end for receiving the third trigger signal R_out[n+1] (equivalent to the first trigger signal R_out[n-1] propagating in the reverse direction) or the fourth trigger signal S_out[n+1] (equivalent to the second trigger signal S_out[n-1] propagating in the reverse direction), and a second end for receiving the second direction scanning signal D2U. The transistor T63 has a first end coupled to the second end of the transistor T61, a control end for receiving the gate high voltage VGH, and a second end.

The transistor T64 has a first end receiving the first clock signal CK1 or the third clock signal CK3, a control end coupled to the second end of the transistor T63, and a second end. The transistor T65 has a first end coupled to the second end of the transistor T64, a control end coupled to the second end of the transistor T63, and a second end coupled to the second end of the transistor T64. The transistor T66 has a first end receiving the gate high voltage VGH, a control end receiving the second clock signal CK2 or the fourth clock signal CK4, and a second end.

The transistor T67 has a first end, a control end coupled to the second end of the transistor T61, and a second end receiving the ground reference voltage XDONB. The resistor R61 is coupled between the second end of the transistor T66 and the first end of the transistor T67. The transistor T68 has a first end receiving the reset signal RST, a control end receiving the reset signal RST, and a second end coupled to the first end of the transistor T67.

The transistor T69 has a first end coupled to the second end of the transistor T61, a control end coupled to the first end of the transistor T67, and a second end receiving the ground reference voltage XDONB. The transistor T70 has a first end coupled to the second end of the transistor T61, a control end coupled to the second end of the transistor T64, and a second end coupled to the second end of the transistor T64. The transistor T71 has a first end coupled to the second end of the transistor T64, a control end coupled to the first end of the transistor T67, and a second end receiving the ground reference voltage XDONB.

FIG9 is a circuit diagram of a first signal generating circuit and a second signal generating circuit according to another embodiment of the present invention. Referring to FIG1 , FIG6 and FIG9 , in this embodiment, the first signal generating circuit 110 and the second signal generating circuit 120 can be implemented by a signal generating circuit 900, and the signal generating circuit 900 includes transistors T81 to T90 (corresponding to the 32nd transistor to the 41st transistor) and capacitors C81 and C82 (corresponding to the 4th capacitor and the 5th capacitor), wherein the transistors T81 to T90 are N-type transistors as an example.

The transistor T81 has a first end receiving the first trigger signal R_out[n-1] or the second trigger signal S_out[n-1], a control end receiving the second clock signal CK2 or the fourth clock signal CK4, and a second end. The capacitor C81 is coupled between one of the first clock signal CK1 and the third clock signal CK3 and the second end of the transistor T81. The transistor T82 has a first end receiving the gate high voltage VGH, a control end coupled to the second end of the transistor T81, and a second end providing the first light-emitting timing signal Out_R or the second light-emitting timing signal Out_S.

The transistor T83 has a first end, a control end receiving the first trigger signal R_out[n-1] or the second trigger signal S_out[n-1], and a second end. The capacitor C82 is coupled between the first end of the thirty-fourth transistor T83 and one of the second clock signal CK2 and the fourth clock signal CK4. The transistor T84 has a first end coupled to the second end of the transistor T83, a control end receiving the first trigger signal R_out[n-1] or the second trigger signal S_out[n-1], and a second end receiving the gate low voltage VGL.

The transistor T85 has a first end receiving the gate high voltage VGH, a control end coupled to the first end of the transistor T83, and a second end. The transistor T86 has a first end coupled to the second end of the transistor T85, a control end coupled to the second end of the transistor T81, and a second end. The transistor T87 has a first end coupled to the second end of the transistor T86, a control end coupled to the second end of the transistor T81, and a second end receiving the gate low voltage VGL.

The transistor T88 has a first end coupled to the second end of the transistor T81, a control end coupled to the second end of the transistor T85, and a second end. The transistor T89 has a first end coupled to the second end of the transistor T88, a control end coupled to the second end of the transistor T85, and a second end receiving the gate low voltage VGL. The transistor T90 has a first end coupled to the second end of the transistor T82, a control end coupled to the second end of the transistor T85, and a second end receiving the gate low voltage VGL.

FIG10 is a system schematic diagram of a display device according to an embodiment of the present invention. Referring to FIG1 and FIG10 , in this embodiment, the display device 1000 at least includes a timing controller 1010, a light-emitting driver 1020, and a display module 1030, wherein the display module 1030 has a plurality of pixel circuits PX arranged in an array. The timing controller 1010 is used to provide a first start signal R_stv, a second start signal S_stv, a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4. The light-emitting driver 1020 includes a plurality of light-emitting signal generating circuits 1021-1023, and is coupled to the display module 1030 and the timing controller 1010 to receive a first start signal R_stv, a second start signal S_stv, a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4, wherein the light-emitting driver 1020 provides a plurality of light-emitting signals EM[1]-EM[3] to the display module 1030 based on the first start signal R_stv, the second start signal S_stv, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4.

In the embodiment of the present invention, the light signal generating circuits 1021-1023 can refer to the light signal generating circuit 100, wherein the first light signal generating circuit 1021 receives the first start signal R_stv as the first trigger signal, and receives the second start signal S_stv as the second trigger signal. Then, the first light signal generating circuit 1021 provides the first trigger signal R_out[1] to the second light signal generating circuit 1022, and provides the second trigger signal S_out[1] to the second light signal generating circuit 1022. Similarly, the second light emitting signal generating circuit 1022 provides the first trigger signal R_out[2] and the second trigger signal S_out[2] to the third light emitting signal generating circuit 1023, and the rest is analogous, which will not be elaborated here.

In summary, in the luminous signal generating circuit and the display device of the embodiment of the present invention, the pulse width of the luminous modulation signal is adjusted corresponding to the phase difference between the first luminous timing signal and the second luminous timing signal, so the pulse width of the luminous signal can adopt the pulse width of the luminous modulation signal or the pulse width of the first luminous timing signal as needed. Thus, by using the luminous modulation signal with adjustable pulse width, the number of pulses can be reduced to reduce the overall power consumption of the display device.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

100, 100a, 100b, 1021~1023: light-emitting signal generating circuit 110: first signal generating circuit 120: second signal generating circuit 130, 130a, 130b: RS latch circuit 140, 140a: output selection circuit 400, 500, 800, 900: signal generating circuit 1000: display device 1010: timing controller 1020: light-emitting driver 1030: display module C21, C31, C32, C81, C82: capacitor CK1: first clock signal CK2: second clock signal CK3: third clock signal CK4: fourth clock signal D2U: second direction scanning signal EM[n], EM[1]~EM[3]: luminous signal Nand1, Nand2: NAND logic gate Nor1, Nor2: NOR logic gate Ǭ: inverting output terminal Out_Q: luminous modulation signal Out_R: first luminous timing signal Out_S: second luminous timing signal PX: pixel circuit Q: output terminal R: reset terminal R_out[n+1]: third trigger signal R_out[n-1], R_out[n], R_out[1]~R_out[3]: first trigger signal R_stv: first start signal R61: resistor RST: reset signal S: set terminal S_out[n+1]: fourth trigger signal S_out[n-1], S_out[n], S_out[1]~S_out[3]: second trigger signal S_stv: second start signal T11~T18, T21~T28, T31~T42, T51~T58, T61~T71, T81~T90: transistors TS1: first selection transistor TS2: second selection transistor U2D: first direction scan signal V_switch: voltage switch signal VDD: system high voltage VGH: gate high voltage VGL: gate low voltage VSS: system low voltage XDONB: ground reference voltage

FIG. 1 is a system schematic diagram of a luminous signal generating circuit according to an embodiment of the present invention. FIG. 2A is a circuit schematic diagram of a luminous signal generating circuit according to an embodiment of the present invention. FIG. 2B to FIG. 2E are driving waveform schematic diagrams of a luminous signal generating circuit according to an embodiment of the present invention. FIG. 3 is a circuit schematic diagram of an RS latch circuit according to an embodiment of the present invention. FIG. 4 is a circuit schematic diagram of a first signal generating circuit and a second signal generating circuit according to an embodiment of the present invention. FIG. 5 is a circuit schematic diagram of a first signal generating circuit and a second signal generating circuit according to another embodiment of the present invention. FIG. 6 is a circuit schematic diagram of a luminous signal generating circuit according to another embodiment of the present invention. FIG7 is a circuit diagram of an RS latch circuit according to an embodiment of the present invention. FIG8 is a circuit diagram of a first signal generating circuit and a second signal generating circuit according to another embodiment of the present invention. FIG9 is a circuit diagram of a first signal generating circuit and a second signal generating circuit according to another embodiment of the present invention. FIG10 is a system diagram of a display device according to an embodiment of the present invention.

100: Luminous signal generating circuit

110: First signal generating circuit

120: Second signal generating circuit

130: RS latch circuit

140: Output selection circuit

CK1: First clock signal

CK2: Second clock signal

CK3: Third clock signal

CK4: Fourth clock signal

EM[n]: luminous signal

Out_Q: Luminescence modulation signal

Out_R: First light emission timing signal

Out_S: Second light-emitting timing signal

R_out[n-1], R_out[n]: first trigger signal

S_out[n-1], S_out[n]: second trigger signal

V_switch: voltage switch signal

Claims (9)

A light-emitting signal generating circuit includes: a first signal generating circuit, receiving a first trigger signal, a first clock signal and a second clock signal to provide a first light-emitting timing signal; a second signal generating circuit, receiving a second trigger signal, a third clock signal and a fourth clock signal to provide a second light-emitting timing signal; an RS latch circuit, coupling the first signal generating circuit and the second signal generating circuit to generate a first light-emitting timing signal based on the first light-emitting timing signal; The first light-emitting timing signal and the second light-emitting timing signal generate a light-emitting modulation signal, wherein a pulse width of the light-emitting modulation signal is related to the phase difference between the first light-emitting timing signal and the second light-emitting timing signal; and an output selection circuit, coupled to the RS latch circuit and the first signal generating circuit, and receiving a voltage switch signal, to provide the first light-emitting timing signal or the light-emitting modulation signal to a display module as a light-emitting signal based on the voltage switch signal. The light-emitting signal generating circuit as described in claim 1, wherein the first signal generating circuit and the second signal generating circuit respectively include: a first transistor having a first end receiving the first trigger signal or the second trigger signal, a control end receiving the first trigger signal or the second trigger signal, and a second end; a second transistor having a first end receiving the first clock signal or the third clock signal, a control end coupled to the first transistor a control terminal of the second terminal of the second transistor, and a second terminal providing the first light-emitting timing signal or the second light-emitting timing signal; a first capacitor coupled between the control terminal of the second transistor and the second terminal of the second transistor; a third transistor having a first terminal receiving the second clock signal or the fourth clock signal, a control terminal receiving the second clock signal or the fourth clock signal, and a second terminal; a fourth transistor having a first end coupled to the second end of the third transistor, a control end coupled to the second end of the first transistor, and a second end; a fifth transistor having a first end coupled to the second end of the fourth transistor, a control end coupled to the second end of the first transistor, and a second end receiving a gate high voltage; a sixth transistor having a first end coupled to the second end of the first transistor, a control end coupled to the second end of the third transistor, and a second end receiving a gate high voltage; a control terminal coupled to the second end of the sixth transistor, and a second end; a seventh transistor having a first end coupled to the second end of the sixth transistor, a control terminal coupled to the second end of the third transistor, and a second end receiving the gate high voltage; and an eighth transistor having a first end coupled to the second end of the second transistor, a control terminal coupled to the second end of the third transistor, and a second end receiving the gate high voltage. The light-emitting signal generating circuit as described in claim 1, wherein the first signal generating circuit and the second signal generating circuit respectively include: a ninth transistor having a first end for receiving the first trigger signal or the second trigger signal, a control end for receiving the second clock signal or the fourth clock signal, and a second end; a tenth transistor having a first end coupled to the second end of the ninth transistor, a control end for receiving the second clock signal or the fourth clock signal, and a second end; a second capacitor coupled between the second end of the tenth transistor and one of the first clock signal and the third clock signal; an eleventh transistor , having a first end receiving a gate low voltage, a control end coupled to the second end of the tenth transistor, and a second end providing the first light-emitting timing signal or the second light-emitting timing signal; a twelfth transistor, having a first end, a control end receiving the first trigger signal or the second trigger signal, and a second end; a third capacitor coupled between the first end of the twelfth transistor and one of the second clock signal and the fourth clock signal; a thirteenth transistor, having a first end coupled to the second end of the twelfth transistor, a control end receiving the first trigger signal or the second trigger signal, and a second end receiving a gate high voltage. a second end receiving the gate voltage; a fourteenth transistor having a first end receiving the gate low voltage, a control end coupled to the first end of the twelfth transistor, and a second end; a fifteenth transistor having a first end coupled to the second end of the fourteenth transistor, a control end coupled to the second end of the tenth transistor, and a second end; a sixteenth transistor having a first end coupled to the second end of the fifteenth transistor, a control end coupled to the second end of the tenth transistor, and a second end receiving the gate high voltage; a seventeenth transistor having a first end coupled to the second end of the tenth transistor, a control end coupled to the second end of the tenth transistor, and a second end receiving the gate high voltage; a control terminal coupled to the second end of the fourteenth transistor, and a second end; an eighteenth transistor having a first end coupled to the second end of the seventeenth transistor, a control terminal coupled to the second end of the fourteenth transistor, and a second end receiving the gate high voltage; a nineteenth transistor having a first end coupled to the second end of the eleventh transistor, a control terminal coupled to the second end of the fourteenth transistor, and a second end; and a twentieth transistor having a first end coupled to the second end of the nineteenth transistor, a control terminal coupled to the second end of the fourteenth transistor, and a second end receiving the gate high voltage. The light-emitting signal generating circuit as described in claim 1, wherein the first signal generating circuit and the second signal generating circuit respectively include: a twenty-first transistor having a first end for receiving a first direction scanning signal, a control end for receiving the first trigger signal or the second trigger signal, and a second end; a twenty-second transistor having a first end coupled to the second end of the twenty-first transistor, a control end for receiving a third trigger signal or a fourth trigger signal, and a second end for receiving a second direction scanning signal; a twenty-third transistor having a first end coupled to the second end of the twenty-first transistor, a control end for receiving a third trigger signal or a fourth trigger signal, and a second end for receiving a second direction scanning signal; a first end coupled to the second end of the twenty-fourth transistor, a control end receiving a gate high voltage, and a second end; a twenty-fourth transistor having a first end receiving the first clock signal or the third clock signal, a control end coupled to the second end of the twenty-third transistor, and a second end; a twenty-fifth transistor having a first end coupled to the second end of the twenty-fourth transistor, a control end coupled to the second end of the twenty-third transistor, and a second end coupled to the second end of the twenty-fourth transistor; a twenty-sixth transistor having a first end receiving the gate high voltage, a control end receiving the first a control terminal for receiving the second clock signal or the fourth clock signal, and a second terminal; a twenty-seventh transistor having a first terminal, a control terminal coupled to the second terminal of the twenty-first transistor, and a second terminal receiving a ground reference voltage; a first resistor coupled between the second terminal of the twenty-sixth transistor and the first terminal of the twenty-seventh transistor; a twenty-eighth transistor having a first terminal for receiving a reset signal, a control terminal for receiving the reset signal, and a second terminal coupled to the first terminal of the twenty-seventh transistor; a twenty-ninth transistor having a first terminal coupled to the twenty-first transistor a first end coupled to the second end of the 24th transistor, a control end coupled to the first end of the 27th transistor, and a second end receiving the ground reference voltage; a 30th transistor having a first end coupled to the second end of the 21st transistor, a control end coupled to the second end of the 24th transistor, and a second end coupled to the second end of the 24th transistor; a 31st transistor having a first end coupled to the second end of the 24th transistor, a control end coupled to the first end of the 27th transistor, and a second end receiving the ground reference voltage. The light-emitting signal generating circuit as described in claim 1, wherein the first signal generating circuit and the second signal generating circuit respectively include: a thirty-second transistor having a first end receiving the first trigger signal or the second trigger signal, a control end receiving the second clock signal or the fourth clock signal, and a second end; a fourth capacitor coupled between the second end of the thirty-second transistor and one of the first clock signal and the third clock signal; a thirty-third transistor having a first end receiving a gate high voltage, a control end coupled to the second end of the thirty-second transistor, and a fourth capacitor coupled between the second end of the thirty-second transistor and the first end of the thirty-third transistor. a control terminal, and a second terminal providing the first light-emitting timing signal or the second light-emitting timing signal; a thirty-fourth transistor having a first terminal, a control terminal receiving the first trigger signal or the second trigger signal, and a second terminal; a fifth capacitor coupled between the first terminal of the thirty-fourth transistor and one of the second clock signal and the fourth clock signal; a thirty-fifth transistor having a first terminal coupled to the second terminal of the thirty-fourth transistor, a control terminal receiving the first trigger signal or the second trigger signal, and a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a gate low voltage receiving a control terminal and a control terminal providing the first light-emitting timing signal and a control terminal providing the first light-emitting timing signal and the second trigger signal; a thirty-fourth transistor having a first terminal coupled to the second terminal of the thirty-fourth transistor, a control terminal receiving the first trigger signal or the second trigger signal, and a second terminal receiving the first trigger signal a second end; a thirty-sixth transistor having a first end receiving the gate high voltage, a control end coupled to the first end of the thirty-fourth transistor, and a second end; a thirty-seventh transistor having a first end coupled to the second end of the thirty-sixth transistor, a control end coupled to the second end of the thirty-second transistor, and a second end; a thirty-eighth transistor having a first end coupled to the second end of the thirty-seventh transistor, a control end coupled to the second end of the thirty-second transistor, and a second end receiving the gate low voltage; a thirty-ninth transistor a transistor having a first end coupled to the second end of the thirty-second transistor, a control end coupled to the second end of the thirty-sixth transistor, and a second end; a fortieth transistor having a first end coupled to the second end of the thirty-ninth transistor, a control end coupled to the second end of the thirty-sixth transistor, and a second end receiving the gate low voltage; and a forty-first transistor having a first end coupled to the second end of the thirty-third transistor, a control end coupled to the second end of the thirty-sixth transistor, and a second end receiving the gate low voltage. The light-emitting signal generating circuit as described in claim 1, wherein when the plurality of pixel circuits configured in the display module are a plurality of P-type pixel circuits, the RS latch circuit is composed of at least a pair of NAND logic gates, and when the pixel circuits are a plurality of N-type pixel circuits, the RS latch circuit is composed of at least a pair of NOR logic gates. A light-emitting signal generating circuit as described in claim 1, wherein the output selection circuit comprises: a first selection transistor having a first end receiving the light-emitting modulation signal, a control end receiving the voltage switch signal, and a second end providing the light-emitting signal; and a second selection transistor having a first end receiving the first light-emitting timing signal, a control end receiving the voltage switch signal, and a second end coupled to the second end of the first selection transistor. A light-emitting signal generating circuit as described in claim 1, wherein the pulse width of the first light-emitting timing signal and the second light-emitting timing signal is less than or greater than the time length of a single horizontal scanning period. A display device comprises: a display module having a plurality of pixel circuits; a timing controller for providing a first start signal, a second start signal, a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; and a light driver comprising a plurality of light signal generating circuits as described in claim 1, and coupled to the display module and the timing controller to receive the first start signal, the second start signal, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal. The light driver provides a plurality of light signals based on the first start signal, the second start signal, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal, wherein the first start signal and the second start signal are used as the first trigger signal and the second trigger signal of a first light signal generating circuit among the light signal generating circuits, and each of the light signal generating circuits sequentially provides the first trigger signal and the second trigger signal to the next level light signal generating circuit.

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