TWI867877B - Semiconductor decive and method of forming the same - Google Patents

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor includes: a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a burrier layer disposed on the channel layer; a first compound semiconductor layer disposed on the barrier layer; a second compound semiconductor layer disposed on the first compound layer; a gate metal disposed on the second compound semiconductor layer; a first passivation layer disposed on the first compound semiconductor layer, the second compound semiconductor layer and the gate metal; and a second passivation layer disposed on the first passivation layer.

Description

Semiconductor device and method for forming the same

The present invention relates to a semiconductor device and a method for forming the same, and in particular to a high electron mobility transistor device and a method for forming the same.

Gallium nitride (GaN) materials have various excellent properties and are therefore widely used. For example, GaN has a wide band-gap, high heat resistance, and high electron saturation rate. In addition, GaN materials also have a very strong polarization effect. In addition to the spontaneous polarization effect formed by the lattice structure, the lattice squeezing caused by lattice mismatch will also cause additional piezoelectric polarization. Due to the simultaneous presence of these two polarization effects, GaN materials will generate extremely large polarized charges at heterojunctions.

In view of the above-mentioned excellent properties of gallium nitride materials, gallium nitride-based semiconductors have been widely used in high electron mobility transistors (HEMT) including heterojunction structures.

During the manufacturing process, high electron mobility transistors may be affected by the process (e.g., etching process, high temperature environment), resulting in poor electrical performance or uniformity. Although existing high electron mobility transistors have generally met the requirements, they are not satisfactory in all aspects.

The present invention provides a semiconductor device, comprising: a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer; a first compound semiconductor layer disposed on the barrier layer; a second compound semiconductor layer disposed on the first compound semiconductor layer; a gate metal disposed on the second compound semiconductor layer; a first passivation layer disposed on the first compound semiconductor layer, the second compound semiconductor layer and the gate metal; and a second passivation layer disposed on the first passivation layer.

The present invention also provides a method for forming a semiconductor device, comprising: providing a substrate, on which a buffer layer, a channel layer, and a barrier layer are sequentially formed; forming a first compound semiconductor layer on the barrier layer; forming a second compound semiconductor material layer on the first compound semiconductor layer; etching the second compound semiconductor material layer to form a second compound semiconductor layer; forming a gate metal on the second compound semiconductor layer; forming a first passivation layer on the first compound semiconductor layer, the second compound semiconductor layer, and the gate metal; and forming a second passivation layer on the first passivation layer.

The following disclosure provides many different embodiments or examples for implementing different components of the provided semiconductor device. Specific examples of each component and its configuration are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, if the description refers to a first component formed on a second component, it may include an embodiment in which the first and second components are directly in contact, and it may also include an embodiment in which additional components are formed between the first and second components so that they are not in direct contact. In addition, the embodiments of the present invention may repeatedly reference numbers and/or letters in different examples. Such repetition is for the sake of simplicity and clarity, and is not intended to indicate the relationship between the different embodiments and/or forms discussed.

Furthermore, spatially relative terms such as "upper", "lower", "above", "below" and similar terms include not only the orientation shown in the drawings, but also different orientations of the device in use or operation. When the device is turned to other orientations (rotated 90 degrees or other orientations), the spatially relative descriptions used herein can also be interpreted according to the rotated orientation.

Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied.

Some embodiments of the present invention are described below, and additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages described may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor devices of the embodiments of the present invention. Some of the components described may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

FIG. 1 to FIG. 9 are schematic cross-sectional views of a semiconductor device 10 at various stages according to some embodiments of the present invention.

1 , a substrate 100 is provided, on which a buffer layer 200, a channel layer 300, and a barrier layer 400 are formed. The buffer layer 200 may be disposed on the substrate 100. The channel layer 300 may be disposed on the buffer layer 200 and the substrate 100, that is, the buffer layer 200 may be disposed between the substrate 100 and the channel layer 300. The barrier layer 400 may be disposed on the channel layer 300.

In some embodiments, the substrate 100 may be a semiconductor on insulator substrate, such as silicon on insulator or silicon germanium on insulator (SGOI). In other embodiments, the substrate 100 may be a silicon (Si) substrate or a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al ₂ O ₃ ) substrate (or sapphire substrate), a glass substrate, or other similar substrates. In some embodiments, the substrate 100 may include a ceramic substrate and a pair of barrier layers disposed on the upper and lower surfaces of the ceramic substrate, respectively, wherein the ceramic substrate may include a ceramic material, and the ceramic material includes a metal inorganic material. For example, the ceramic substrate may include silicon carbide, aluminum nitride, sapphire substrate, or other suitable materials. The sapphire substrate may be aluminum oxide.

The lattice or thermal expansion coefficient of the substrate 100 may be different from that of the upper component (e.g., the channel layer 300), so strain may be generated at or near the interface between the substrate 100 and the upper component, which may easily form defects such as cracks or warps. Therefore, as shown in FIG. 1, a buffer layer 200 may be formed on the substrate 100 to reduce the strain of the component (e.g., the channel layer 300) formed above the buffer layer 200 to prevent defects from being formed in the upper component.

In some embodiments, the material of the buffer layer 200 may include a III-V compound semiconductor material, such as a III-nitride. For example, the material of the buffer layer 200 may be or include gallium nitride, aluminum nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), any other suitable material, or a combination thereof. In some embodiments, the buffer layer 200 may be a multi-layer structure (not shown). For example, the buffer layer 200 may include a superlattice buffer layer and/or a gradient buffer layer, wherein the superlattice buffer layer is disposed on the substrate 100, and the gradient buffer layer is disposed on the superlattice buffer layer, which can effectively prevent the dislocation in the substrate 100 from entering the upper component, and further improve the crystal quality of other films and/or layers above. In some embodiments, the thickness of the buffer layer 200 may be, for example, 0.5 microns to 10 microns, for example, about 3 microns.

In some embodiments, the buffer layer 200 may be formed by an epitaxial growth process, such as chemical vapor deposition, physical vapor deposition, and more specifically, metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), atomic layer deposition (ALD), liquid phase epitaxy (LPE), other suitable methods, or a combination thereof.

In some embodiments, a seed layer (not shown) may be formed between the substrate 100 and the buffer layer 200 as required. In these embodiments, the seed layer may alleviate the lattice difference between the substrate 100 and the film and/or layer grown thereon to improve the crystal quality. The material of the seed layer may include: AlN, Al ₂ O ₃ , AlGaN, SiC, Al, a combination thereof, or similar materials. The seed layer of a single layer or multi-layer structure can be formed by a suitable process, such as chemical vapor deposition, physical vapor deposition, etc., more specifically, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), atomic layer deposition (ALD), liquid phase epitaxy (ILPE), other suitable methods, or a combination thereof. In some embodiments, the material of the buffer layer 200 depends on the material of the seed layer and the gas introduced during the epitaxial process.

The channel layer 300 is formed on the buffer layer 200. In some embodiments, the material of the channel layer 300 includes a III-V compound semiconductor material, such as a III-nitride. In some embodiments, the material of the channel layer 300 may be gallium nitride (GaN), AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, any other suitable material, or a combination thereof. In some embodiments, the channel layer 300 may be undoped. In some embodiments, the channel layer 300 may be doped by an n-type dopant or a p-type dopant. The channel layer 300 may include a single layer or a multi-layer structure. In some embodiments, the thickness of the channel layer 300 may range from about 0.01 μm to about 10 μm. The channel layer 300 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, atomic layer deposition, liquid phase epitaxy, combinations thereof, or the like.

The barrier layer 400 is formed on the channel layer 300. In some embodiments, the material of the barrier layer 400 may include a III-V compound semiconductor, such as a III-nitride. In some embodiments, the material of the barrier layer 400 may be GaN, AlGaN, AlN, GaAs, GaInP, AlInN, AlGaAs, InP, InAlAs, InGaAs, other appropriate materials, or a combination thereof, but is not limited thereto. In some embodiments, the barrier layer 400 may be undoped. In some embodiments, the barrier layer 400 may be doped by an n-type dopant or a p-type dopant. The barrier layer 400 may include a single layer or a multi-layer structure. In some embodiments, the barrier layer 400 may have a thickness ranging from about 1 nm to about 100 nm, for example.

In some embodiments, the barrier layer 400 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, atomic layer deposition, liquid phase epitaxy, a combination thereof, or the like. In some embodiments of the present invention, the channel layer 300 and the barrier layer 400 are made of different materials, and the interface is a heterojunction structure. Due to the lattice mismatch between the channel layer 300 and the barrier layer 400, stress may be generated to cause a piezoelectric polarization effect, and the ionicity of the bonding between the group III metal (such as Al, Ga, or In) and nitrogen is stronger, resulting in spontaneous polarization. Due to the different energy gaps between the channel layer 300 and the barrier layer 400 and the aforementioned piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas (2DEG) is formed on the heterogeneous interface between the channel layer 300 and the barrier layer 400, as shown by the dotted line in FIG. 1. In some embodiments, the two-dimensional electron gas channel is used to provide conductive carriers for a subsequently formed high electron mobility transistor, so it can serve as a current path.

Next, referring to FIG. 2 , a first compound semiconductor layer 500 may be formed on the barrier layer 400, wherein the first compound semiconductor layer 500 has a surface 500s. In some embodiments, the first compound semiconductor layer 500 may be undoped gallium nitride (uGaN). In some embodiments, the first compound semiconductor layer 500 may include undoped AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other appropriate III-V group materials, or a combination thereof. The first compound semiconductor layer 500 may serve as an etch stop layer to protect the barrier layer 400 from being affected by etching in a subsequent etching process. In some embodiments, the thickness of the first compound semiconductor layer 500 is, for example, 3 nm to 30 nm, for example, 5 nm to 28 nm, 8 nm to 25 nm, 10 nm to 23 nm, 13 nm to 20 nm, or 15 to 18 nm.

In some embodiments, the first compound semiconductor layer 500 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, atomic layer deposition, liquid phase epitaxy, a combination thereof, or the like. In some embodiments, the first compound semiconductor layer 500 can be formed by high temperature chemical vapor deposition at a temperature of 400°C to 1500°C, such as 500°C to 1400°C, 600°C to 1300°C, 700°C to 1200°C, 800°C to 1100°C, 900°C to 1000°C.

Next, referring to FIG. 3 , a second compound semiconductor material layer 510 a is formed on the first compound semiconductor layer 500. In some embodiments, the second compound semiconductor material layer 510 a may be gallium nitride. In some other embodiments, the second compound semiconductor material layer 510 a may include AlGaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other appropriate III-V group materials, or a combination thereof. In some embodiments, the thickness of the second compound semiconductor material layer 510 a may be, for example, 20 nm to 80 nm, for example, 25 nm to 75 nm, 30 nm to 70 nm, 35 nm to 65 nm, 40 nm to 60 nm, 45 nm to 55 nm, etc. In some embodiments, the second compound semiconductor material layer 510a may be formed by a deposition process such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, atomic layer deposition, liquid phase epitaxy, a combination thereof, or the like.

Next, as shown in FIG. 4 , the second compound semiconductor material layer 510a is patterned and doped to form a second compound semiconductor layer 510. The second compound semiconductor material layer 510a may be doped before or after patterning. In some embodiments, the second compound semiconductor layer 510 may be p-type doped or n-type doped, and the doping concentration may be 1e15/cm ³ to 1e20/cm ³ , such as 5e15/cm ³ to 5e19/cm ³ , 1e16/cm ³ to 1e19/cm ³ , 5e16/cm ³ to 5e18/cm ³ , 1e17/cm ³ to 1e18/cm ³ .

For example, the patterning process may include a lithography process (e.g., photoresist coating, soft baking, mask aligning, exposure, post-exposure baking, photoresist development, other appropriate processes, or a combination thereof), an etching process (e.g., a wet etching process, a dry etching process, other appropriate processes, or a combination thereof), other appropriate processes, or a combination thereof. According to some embodiments, a patterned mask layer (not shown) is formed on the second compound semiconductor material layer 510a, and then the second compound semiconductor material layer 510a is etched to remove the portion of the second compound semiconductor material layer 510a not covered by the patterned mask layer, thereby forming the second compound semiconductor layer 510. The position of the second compound semiconductor layer 510 is adjusted according to the predetermined position of the gate. In some embodiments, the second compound semiconductor layer 510 can suppress the two-dimensional electron gas channel thereunder, thereby overcoming the safety concerns of the conventional normally-on state and achieving a normally-off state for the semiconductor device 10 formed subsequently.

In some embodiments, the patterned mask layer can be a photoresist, such as a positive photoresist or a negative photoresist. In other embodiments, the patterned mask layer can be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, similar materials, or combinations thereof. In some embodiments, the patterned mask layer can be formed by spin coating, physical vapor deposition, chemical vapor deposition, similar processes, or combinations thereof.

In some embodiments, the etching of the second compound semiconductor material layer 510a can use a dry etching process, a wet etching process, or a combination thereof. For example, the etching of the second compound semiconductor material layer 510a includes reactive ion etching (RIE), inductively-coupled plasma (ICP) etching, neutron beam etching (NBE), electron cyclotron resonance (ERC) etching, similar etching processes, or a combination thereof. In addition, although the second compound semiconductor layer 510 in the figure has substantially vertical sidewalls and a flat upper surface, the present invention is not limited thereto, and the second compound semiconductor layer 510 may also be in other shapes, such as inclined sidewalls and/or an uneven upper surface. In some embodiments, the etching of the second compound semiconductor material layer 510a stops at the surface 500s of the first compound semiconductor layer 500, that is, the etching step of the second compound semiconductor material layer 510a uses the first compound semiconductor layer 500 as an etching stop layer.

Next, as shown in FIG. 5 , a gate metal 520 is formed on the second compound semiconductor layer 510 . In some embodiments, the material of the gate metal 520 includes a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantulum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), metal oxides, metal alloys, other suitable conductive materials, or combinations thereof.

In some embodiments, the formation of the gate metal 520 includes depositing a conductive material on the second compound semiconductor layer 510, and then performing a patterning process on the deposited conductive material to form the gate metal 520. The conductive material may be deposited by, for example, chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), electroplating, atomic layer deposition, other appropriate methods, or a combination thereof, and the patterning process may include a lithography process, an etching process, other appropriate processes, or a combination thereof, and specific reference may be made to the patterning of the second compound semiconductor material layer 510a, which will not be described in detail here.

In some embodiments, the second compound semiconductor layer 510 and the gate metal 520 may be formed by depositing a second compound semiconductor material layer and a gate metal material layer and then performing appropriate etching.

Due to the easy oxidation of gate metal, it is difficult to maintain the gate leakage current (Ig) and 2DEG sheet resistance (R _SH ) of semiconductor devices within the target range through the previous process. Therefore, in this case, a thinner passivation layer is set on the gate metal at a lower temperature to prevent the gate metal from oxidizing in the subsequent high-temperature process environment and prevent the gate resistance from increasing.

Continuing with FIG. 6 , a first passivation layer 530 is disposed on the semiconductor device 10. The first passivation layer 530 may be formed on the first compound semiconductor layer 500, the second compound semiconductor layer 510, and the gate metal 520. In other words, the first passivation layer 530 may be disposed between the first compound semiconductor layer 500, the second compound semiconductor layer 510, the gate metal 520, and the second passivation layer to be formed subsequently. The _first passivation layer 530 may include, for example, _silicon oxide ( _SiOx ), silicon nitride ( _SixNy ), silicon oxynitride ( _SiOxNy ), aluminum oxide ( _AlOx ), aluminum nitride (AlN), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), other insulating materials, or a combination thereof. The first passivation layer 530 may be a single layer or a multi-layer film. The first passivation layer 530 may have a thickness of 3Å to 200Å, for example, 5Å to 180Å, 10Å to 160Å, 15Å to 140Å, 20Å to 120Å, 25Å to 100Å, 30Å to 80Å, 35Å to 75Å, 40Å to 70Å, 45Å to 65Å, 50Å to 60Å, etc.

In some embodiments, the first passivation layer 530 may have a flat surface. In some embodiments, the first passivation layer 530 may have a step surface. The shape of the step surface corresponds to the shapes of the first compound semiconductor layer 500, the second compound semiconductor layer 510, and the gate metal 520, that is, conformally, or conformally, formed on the surfaces of the first compound semiconductor layer 500, the second compound semiconductor layer 510, and the gate metal 520. It should be noted that the step surface of the first passivation layer 530 shown in FIG. 6 is only an example and not a limitation, that is, the shape of the first passivation layer 530 is not limited to FIG. 6. In some embodiments, the corners of the stepped surface of the first passivation layer 530 may be sharp angles, right angles, rounded corners, blunt corners, or any suitable shapes. In some embodiments, the first passivation layer 530 may be any shape having a height difference corresponding to the surface of the first compound semiconductor layer 500, the second compound semiconductor layer 510, and the gate metal 520, that is, the first passivation layer 530 may have a shape corresponding to the step difference.

In some embodiments, the first passivation layer 530 may be formed by a deposition process, such as plasma-enhanced CVD (PECVD), atomic layer deposition, high-density plasma CVD (HDPCVD), other suitable processes, or a combination thereof. In some embodiments, the first passivation layer 530 may be deposited at a temperature of 40°C to 400°C, such as 50°C to 390°C, 60°C to 380°C, 70°C to 370°C, 80°C to 360°C, 90°C to 350°C, 100°C to 340°C, 110°C to 330°C, 120°C to 3 20°C, 130°C to 310°C, 140°C to 300°C, 150°C to 290°C, 160°C to 280°C, 170°C to 270°C, 180°C to 260°C, 190°C to 250°C, 200°C to 240°C, 210°C to 230°C, 220°C to 225°C. By forming the first passivation layer 530 at a relatively low temperature, the gate metal 520 can be prevented from being oxidized by the subsequent high temperature process, so that the gate leakage current (Ig) and the 2DEG sheet resistance (R _SH ) of the semiconductor device can be maintained within the target range, thereby obtaining a suitable on-resistance (R _on ) of the semiconductor device.

Next, as shown in FIG. 7 , a second passivation layer 540 may be formed on the first passivation layer 530. The second passivation layer 540 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, einsteinium oxide, aluminum nitride, polyimide, benzocyclobutene, polybenzoxazole, tetraethoxysilane oxide, phosphosilicate glass, borophosphosilicate glass, other insulating materials, or a combination thereof. The second passivation layer 540 may be a single layer or a multi-layer film. The second passivation layer 540 may have a thickness of 100Å to 2000Å, for example, 150Å to 1900Å, 200Å to 1800Å, 250Å to 1700Å, 300Å to 1600Å, 350Å to 1500Å, 400Å to 1400Å, 450Å to 1300Å, 500Å to 1200Å, 550Å to 1100Å, 600Å to 1000Å, 650Å to 900Å, 700Å to 850Å, 750Å to 800Å, etc.

In some embodiments, the second passivation layer 540 may have a flat surface. In some embodiments, the second passivation layer 540 may have a stepped surface. The shape of the stepped surface corresponds to the shape of the first passivation layer 530, that is, it is conformally formed on the surface of the first passivation layer 530. It should be noted that the stepped surface of the second passivation layer 540 shown in FIG. 7 is only an example and not a limitation, that is, the shape of the second passivation layer 540 is not limited to FIG. 7. In some embodiments, the corners of the stepped surface of the second passivation layer 540 may be sharp angles, right angles, rounded corners, blunt corners, or any suitable shape. In some embodiments, the second passivation layer 540 may have any shape having a height difference corresponding to the surface of the first passivation layer 530, that is, the second passivation layer 540 may have a shape corresponding to the step.

In some embodiments, the second passivation layer 540 may be formed by a deposition process, such as low-pressure CVD (LPCVD), atomic layer deposition, molecular beam epitaxy (MBE), other suitable processes, or a combination thereof. In some embodiments, the second passivation layer 530 may be deposited at a temperature of 350°C to 1200°C, such as 400°C to 1000°C, 450°C to 950°C, 500°C to 900°C, 550°C to 850°C, 600°C to 800°C, 650°C to 750°C, 680°C to 720°C, 690°C to 700°C, etc. Even if the second passivation layer 540 is formed at a higher temperature, the gate metal 520 will not be oxidized and affect the electrical properties of the semiconductor device 10 due to the formation of the first passivation layer 530 .

Next, referring to FIG. 8 , an opening OP penetrating the second passivation layer 540, the first passivation layer 530, the first compound semiconductor layer 500, and the barrier layer 400 may be formed by a patterning process. The opening OP may be formed on both sides of the gate metal 520. In some embodiments, the contact opening OP may extend into the channel layer 300. The contact opening OP is used to form a source/drain electrode. For example, the patterning process may include a lithography process, an etching process, other appropriate processes, or a combination thereof, and specific reference may be made to the patterning of the second compound semiconductor material layer 510a, which will not be described in detail here.

Referring to FIG. 9 , source/drain electrodes 610 are formed in two contact openings OP respectively. The material of the source/drain electrodes 610 includes a conductive material, such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tantalum carbide, tantalum silicon nitride, tantalum carbonitride, titanium aluminum, titanium aluminum nitride, metal oxide, metal alloy, other suitable conductive materials or a combination thereof. In addition, the shape of the source/drain electrodes 610 is not limited to the vertical sidewalls in the figure, and may also be a tapered sidewall or have other profiles. The material of the source/drain electrodes 610 may be the same as or different from the material of the gate metal 520 .

In some embodiments, a conductive material may be deposited in the contact opening OP by chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), electroplating, atomic layer deposition, other appropriate methods, or a combination thereof, and the deposited conductive material may be patterned to form a source/drain electrode 610 disposed on both sides of the gate metal 520 and in contact with the channel layer 300.

Next, gate metal 520 and source/drain electrode 610 contacts may be further formed as required. For example, in accordance with FIG. 9 , a dielectric layer is formed on the semiconductor device 10, and then the dielectric layer is patterned to form contact openings corresponding to the gate metal 520 and source/drain electrode 610, and finally a metal material is deposited in the contact openings to form contacts.

In other embodiments, a third passivation layer 550 may be further formed on the second passivation layer 540. Referring to FIG. 10, which is a continuation of FIG. 7, by patterning the second passivation layer 540, a portion of the surface of the first passivation layer 530 is exposed on one or both sides of the gate metal 520. In some embodiments, the surface of the first passivation layer 530 is exposed closer to the drain electrode to be formed subsequently, and in some embodiments, the surface of the first passivation layer 530 is exposed closer to the source electrode to be formed subsequently. The ratio of the exposed and unexposed first passivation layer 530 on one side of the gate metal 520 can be adjusted as required. Next, a third passivation layer 550 is formed on the first passivation layer 530 and the second passivation layer 540 , wherein the third passivation layer 550 is in direct contact with the exposed first passivation layer 530 , and the first passivation layer 530 can serve as a nucleation layer for the third passivation layer 550 .

The _third passivation layer 550 _may include, for example, silicon oxide ( _SiOx ), silicon nitride ( _SixNy ), silicon oxynitride ( _SiOxNy ), aluminum oxide ( _AlOx ), aluminum nitride (AlN), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), gallium nitride, other insulating materials, or a combination thereof. The third passivation layer 550 may have a thickness of 3Å to 200Å, for example, 5Å to 180Å, 10Å to 160Å, 15Å to 140Å, 20Å to 120Å, 25Å to 100Å, 30Å to 80Å, 35Å to 75Å, 40Å to 70Å, 45Å to 65Å, 50Å to 60Å, etc.

In some embodiments, the third passivation layer 550 may have a flat surface. In some embodiments, the third passivation layer 550 may have a step surface. The shape of the step surface corresponds to the shape of the first passivation layer 530 and the second passivation layer 540, and the step surface of the third passivation layer 550 shown in FIG. 10 is only an example and not a limitation. By forming the third passivation layer 550 directly contacting a portion of the first passivation layer 530, the 2DEG characteristics (e.g., density, mobility, etc.) between the source and the drain can be enhanced, thereby further reducing the sheet resistance (R _SH ). In some embodiments, better current improvement can be obtained by arranging the contact position between the first passivation layer 530 and the third passivation layer 550 closer to the drain relative to the source.

In some embodiments, the third passivation layer 550 may be formed by a deposition process, such as plasma enhanced chemical vapor deposition, low vacuum chemical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, molecular beam epitaxy (MBE), other suitable processes, or a combination thereof. In some embodiments, the third passivation layer 550 may be deposited at a temperature of 40°C to 1200°C, for example, 50°C to 1000°C, 100°C to 950°C, 150°C to 900°C, 200°C to 850°C, 250°C to 800°C, 250°C to 750°C, 300°C to 700°C, 350°C to 650°C, 400°C to 600°C, 450°C to 550°C, 500°C to 525°C, etc.

Then, source/drain electrodes 610 are formed on both sides of the gate metal 520. In some embodiments, the opening for forming the source passes through the third passivation layer 550, the second passivation layer 540, the first passivation layer 530, the first compound semiconductor layer 500 and the barrier layer 400, while the opening for forming the drain passes through the third passivation layer 550, the first passivation layer 530, the first compound semiconductor layer 500 and the barrier layer 400, that is, the opening for forming the drain passes through the position where the first passivation layer 530 contacts the third passivation layer 550, and does not pass through the second passivation layer 540. In some embodiments, the opening for forming the source does not penetrate the second passivation layer 540. In some embodiments, the source/drain electrode 610 extends into the channel layer 300. In some embodiments, the source is closer to the gate metal 520 than the drain. The process and materials of the source/drain electrode 610 can refer to the embodiments described in Figures 8-9, and will not be repeated here.

The above summarizes the components of several embodiments so that those with ordinary knowledge in the art to which the present invention belongs can more easily understand the perspectives of the embodiments of the present invention. Those with ordinary knowledge in the art to which the present invention belongs should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present invention belongs should also understand that such equivalent processes and structures do not violate the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

10: Semiconductor devices

100: Substrate

200: Buffer layer

300: Channel layer

400: Barrier

500: first compound semiconductor layer

510a: second compound semiconductor material layer

510: Second compound semiconductor layer

520: Gate Metal

530: First passivation layer

540: Second passivation layer

550: The third passivation layer

OP: Open mouth

610: Source/Drain Electrode

The following will be described in detail with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention. Figures 1 to 9 show cross-sectional views of semiconductor devices at various formation stages according to some embodiments of the present invention. Figure 10 shows a cross-sectional view of a semiconductor device according to other embodiments of the present invention.

10: Semiconductor devices

100: Substrate

200: Buffer layer

300: Channel layer

400: Barrier layer

500: First compound semiconductor layer

510: Second compound semiconductor layer

520: Gate metal

530: First passivation layer

540: Second passivation layer

610: Source/drain electrode

Claims (21)

A semiconductor device includes: a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer; a first compound semiconductor layer disposed on the barrier layer; a second compound semiconductor layer disposed on the first compound semiconductor layer; and a gate metal disposed on the second compound semiconductor layer. a first passivation layer disposed on the first compound semiconductor layer, the second compound semiconductor layer and the gate metal; a second passivation layer disposed on the first passivation layer; and a source/drain electrode located on both sides of the gate metal, and the source/drain electrode passes through the second passivation layer, the first passivation layer, the first compound semiconductor layer and the barrier layer. A semiconductor device as described in claim 1, wherein the first passivation layer comprises aluminum oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. A semiconductor device as described in claim 1 or 2, wherein the thickness of the first passivation layer is 3Å to 200Å. A semiconductor device as described in claim 1, wherein the second passivation layer comprises aluminum oxide, aluminum oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. A semiconductor device as described in claim 1 or 4, wherein the thickness of the second passivation layer is 100Å to 2000Å. A semiconductor device as described in claim 1, wherein the first compound semiconductor layer comprises undoped gallium nitride. A semiconductor device as described in claim 1, wherein the second compound semiconductor layer includes p-type gallium nitride. A semiconductor device as described in claim 1, wherein the gate metal comprises titanium nitride. The semiconductor device as described in claim 1 further includes a third passivation layer, which is disposed on the first passivation layer and the second passivation layer, wherein the third passivation layer is in direct contact with the first passivation layer on one side of the gate metal. A semiconductor device as described in claim 9, wherein the third passivation layer comprises aluminum oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, gallium nitride, or a combination thereof. A method for forming a semiconductor device includes: providing a substrate, on which a buffer layer, a channel layer, and a barrier layer are sequentially formed; forming a first compound semiconductor layer on the barrier layer; forming a second compound semiconductor material layer on the first compound semiconductor layer; etching the second compound semiconductor material layer to form a second compound semiconductor layer; forming a gate metal on the first compound semiconductor layer; On the second compound semiconductor layer; forming a first passivation layer on the first compound semiconductor layer, the second compound semiconductor layer and the gate metal; forming a second passivation layer on the first passivation layer; and forming a source/drain electrode on both sides of the gate metal, wherein the source/drain electrode passes through the second passivation layer, the first passivation layer, the first compound semiconductor layer and the barrier layer. A method for forming a semiconductor device as described in claim 11, wherein the etching of the second compound semiconductor material layer stops at the surface of the first compound semiconductor layer. A method for forming a semiconductor device as described in claim 11, wherein the first passivation layer is conformally formed on the surfaces of the first compound semiconductor layer, the second compound semiconductor layer, and the gate metal. A method for forming a semiconductor device as described in claim 11, wherein the first passivation layer is formed at a temperature below 400°C. A method for forming a semiconductor device as described in claim 11 or 14, wherein the first passivation layer comprises aluminum oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. A method for forming a semiconductor device as described in claim 11 or 14, wherein the thickness of the first passivation layer is 3Å to 200Å. A method for forming a semiconductor device as described in claim 11, wherein the second passivation layer is conformally formed on the surface of the first passivation layer. A method for forming a semiconductor device as described in claim 11, wherein the second passivation layer is formed at a temperature above 350°C. A method for forming a semiconductor device as described in claim 11 or 18, wherein the second passivation layer comprises aluminum oxide, aluminum oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. A method for forming a semiconductor device as described in claim 11 or 18, wherein the thickness of the second passivation layer is 100Å to 2000Å. The method for forming a semiconductor device as claimed in claim 11 further includes: performing a patterning process on the second passivation layer to expose a portion of the surface of the first passivation layer on one side of the gate metal; and forming a third passivation layer on the second passivation layer and the first passivation layer, wherein the third passivation layer is in direct contact with the first passivation layer on one side of the gate metal.

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