TWI867779B - Micro light-emitting diode display apparatus - Google Patents

Abstract

A micro light-emitting diode (uLED) display apparatus including a display panel and uLED driving circuits is disclosed. The display panel includes pixels. Each uLED driving circuit is coupled to at least one pixel of the display panel. The uLED driving circuits include a first uLED driving circuit and a second uLED driving circuit coupled in series. The first uLED driving circuit receives a zeroth data signal, a zeroth enabling signal and a zeroth clock signal and outputs a first data signal, a first enabling signal and a first clock signal to the second uLED driving circuit. The zeroth clock signal and the first clock signal have opposite phases to each other and a phase difference between the zeroth data signal and the first data signal is less than one clock signal period.

Description

Micro-luminescent diode display device

The present invention relates to a display device, and in particular to a micro-light emitting diode (uLED) display device.

Please refer to FIG1 , in a conventional micro-LED display device 1, a column input signal COL inputted to a display panel PL in a vertical direction is a data signal, and a row input signal ROW inputted to a display panel PL in a horizontal direction is a clock signal. When the column input signal COL and the row input signal ROW are transmitted to a display panel PL having a high resistance value (such as a glass substrate), their waveforms are distorted by parasitic resistance and capacitance, causing the conventional uLED display system 1 to be unable to operate smoothly at high frequencies, thereby limiting the resolution and size of the display panel PL.

Therefore, the present invention proposes a micro-luminescent diode display device to effectively solve the above problems encountered in the prior art.

A preferred specific embodiment of the present invention is a micro-luminescent diode display device. In this embodiment, the micro-luminescent diode display device includes a display panel and a plurality of micro-luminescent diode driving circuits. The display panel includes a plurality of pixels. Each micro-luminescent diode driving circuit is coupled to at least one pixel of the display panel. The plurality of micro-luminescent diode driving circuits include a first micro-luminescent diode driving circuit and a second micro-luminescent diode driving circuit connected in series with each other. The first micro-LED driving circuit receives the zeroth data signal, the zeroth enable signal and the zeroth clock signal and outputs the first data signal, the first enable signal and the first clock signal to the second micro-LED driving circuit. The zeroth clock signal and the first clock signal are inverted and the phase difference between the zeroth data signal and the first data signal is less than one clock signal cycle.

In one embodiment, the micro-luminescent diode display device further includes: a data driver coupled to the first micro-luminescent diode driving circuit and providing a zeroth data signal, a zeroth enable signal and a zeroth clock signal to the first micro-luminescent diode driving circuit.

In one embodiment, the first micro-luminescent diode driving circuit includes: a D-type flip-flop for generating a first data signal according to a zeroth data signal and a zeroth clock signal; and a gate for generating a first clock signal according to the zeroth clock signal.

In one embodiment, the phase difference between the positive edge or negative edge of the zeroth clock signal and the zeroth data signal is between 0.3 and 0.7 cycles of the clock signal.

In one embodiment, the phase difference between the zeroth data signal and the first data signal is 0.5 clock signal period.

In one embodiment, the waveform of the zeroth clock signal changes from a low level to a high level and the waveform of the first clock signal changes from a high level to a low level.

In one embodiment, the waveform of the zeroth clock signal changes from a high level to a low level and the waveform of the first clock signal changes from a low level to a high level.

In one embodiment, the start time of the zeroth enable signal corresponds to the start time of the zeroth data cycle of the zeroth data signal, and the start time of the first enable signal corresponds to the start time of the first data cycle of the first data signal.

In one embodiment, the second micro-luminescent diode driving circuit receives a first data signal, a first enable signal and a first clock signal and outputs a second data signal, a second enable signal and a second clock signal, the first clock signal and the second clock signal are inverted and the phase difference between the first data signal and the second data signal is less than one clock signal cycle.

In one embodiment, the second micro-luminescent diode driving circuit includes: a D-type flip-flop for generating a second data signal according to a first data signal and a first clock signal; and a gate for generating a second clock signal according to the first clock signal.

In one embodiment, the phase difference between the positive edge or negative edge of the first clock signal and the first data signal is between 0.3 and 0.7 cycles of the clock signal.

In one embodiment, the phase difference between the first data signal and the second data signal is 0.5 clock signal period.

In one embodiment, the waveform of the first clock signal changes from a low level to a high level and the waveform of the second clock signal changes from a high level to a low level.

In one embodiment, the waveform of the first clock signal changes from a high level to a low level and the waveform of the second clock signal changes from a low level to a high level.

In one embodiment, the start time of the second enable signal corresponds to the start time of the second data cycle of the second data signal.

Compared with the prior art, the micro-luminescent diode display device of the present invention divides the traditional row input signal (ROW) into an enable signal (EN) and a clock signal (CLK). When the enable signal (EN), the clock signal (CLK) and the data signal (DATA) are input to a display panel PL (such as a glass substrate) having a high resistance value, the enable signal (EN), the clock signal (CLK) and the data signal (DATA) are sequentially transmitted to a plurality of micro-luminescent diodes connected in series. The electrode driving circuit, and the enable signal (EN) and the data signal (DATA) are re-timed in each micro-LED driving circuit to have the same delay and the clock signal (CLK) is transmitted in reverse to the next micro-LED driving circuit to avoid the signal being distorted by parasitic resistance and capacitance, so that the micro-LED display device of the present invention can operate smoothly at high frequency and the resolution and size of its display panel are not limited.

A preferred embodiment of the present invention is a micro-luminescent diode display device. Please refer to FIG2 , which is a schematic diagram of the micro-luminescent diode display device in this embodiment.

As shown in FIG2 , the micro-LED display device 2 includes a data driver DD, a display panel PL, and a plurality of micro-LED driving circuits uIC00 to uIC77. The display panel PL includes a plurality of pixels (not shown). The plurality of micro-LED driving circuits uIC00 to uIC77 are arranged in a (8*8) matrix form, but not limited thereto. Each micro-LED driving circuit uIC00 to uIC77 is respectively coupled to at least one pixel of the display panel PL and is used to drive the at least one pixel (for example, 16 pixels, but not limited thereto).

In this embodiment, the plurality of micro-LED driving circuits uIC00-uIC77 include a plurality of rows of micro-LED driving circuits uIC00-uIC70, uIC01-uIC71, uIC02-uIC72, uIC03-uIC73, ..., uIC06-uIC76, uIC07-uIC77 connected in series.

The data driver DD is respectively coupled to the micro-LED driving circuits uIC00, uIC01, uIC02, uIC03, ..., uIC06, uIC07 in the plurality of micro-LED driving circuits uIC00~uIC77, that is, the data driver DD is respectively coupled to the first micro-LED driving circuit uIC00, uIC01, uIC02, uIC03, ..., uIC06, uIC07 in each row of micro-LED driving circuits uIC00~uIC70, uIC01~uIC71, uIC02~uIC72, uIC03~uIC73, ..., uIC06~uIC76, uIC07~uIC77, but is not limited to this.

As shown in FIG. 3 , if the first row of micro-LED driving circuits uIC00~uIC70 is taken as an example for explanation, the data driver DD is coupled to the data signal input terminal DATAI, the enable signal input terminal ENI and the clock signal input terminal CLKI of the micro-LED driving circuit uIC00 and provides the zeroth data signal DATA0, the zeroth enable signal EN0 and the zeroth clock signal CLK0 to the data signal input terminal DATAI, the enable signal input terminal ENI and the clock signal input terminal CLKI of the first micro-LED driving circuit uIC00 respectively.

When the data signal input terminal DATAI, the enable signal input terminal ENI and the clock signal input terminal CLKI of the first micro-light-emitting diode driving circuit uIC00 respectively receive the zeroth data signal DATA0, the zeroth enable signal EN0 and the zeroth clock signal CLK0, the data signal output terminal DATAO, the enable signal output terminal ENO and the clock signal output terminal CLKO of the first micro-light-emitting diode driving circuit uIC00 respectively output the first data signal DATA1, the first enable signal EN1 and the first clock signal CLK1 to the data signal input terminal DATAI, the enable signal input terminal ENI and the clock signal input terminal CLKI of the second micro-light-emitting diode driving circuit uIC10.

It should be noted that the zeroth clock signal CLK0 output by the data driver DD and the first clock signal CLK1 output by the first micro-LED driving circuit uIC00 are in opposite phases, and the phase difference between the zeroth data signal DATA0 output by the data driver DD and the first data signal DATA1 output by the first micro-LED driving circuit uIC00 is less than one clock signal cycle.

Similarly, when the data signal input terminal DATAI, the enable signal input terminal ENI and the clock signal input terminal CLKI of the second micro-LED driving circuit uIC10 receive the first data signal DATA1, the first enable signal EN1 and the first clock signal CLK1 respectively, the data signal output terminal DATAO, the enable signal output terminal ENO and the clock signal output terminal CLKO of the second micro-LED driving circuit uIC10 respectively output the second data signal DATA2, the second enable signal EN2 and the second clock signal CLK2 to the next micro-LED driving circuit (the third micro-LED driving circuit uIC20. The rest can be deduced accordingly.

It should be noted that the first clock signal CLK1 output by the first micro-LED driving circuit uIC00 and the second clock signal CLK2 output by the second micro-LED driving circuit uIC10 are in opposite phases to each other, and the phase difference between the first data signal DATA1 output by the first micro-LED driving circuit uIC00 and the second data signal DATA2 output by the second micro-LED driving circuit uIC10 is less than one clock signal cycle.

Please refer to FIG. 4 and FIG. 5 , which respectively illustrate timing diagrams of the zeroth data signal DATA0 , the zeroth clock signal CLK0 , the first data signal DATA1 , and the first clock signal CLK1 in different embodiments.

As shown in FIG. 4 , assuming that a clock signal cycle is from time t0 to t2, the phase difference between the positive edge or negative edge of the zeroth clock signal CLK0 and the zeroth data signal DATA0 may be between 0.3 and 0.7 clock signal cycles; the phase difference between the zeroth data signal DATA0 and the first data signal DATA1 is 0.5 clock signal cycles, i.e., from time t0 to t1 or from time t1 to t2.

The zeroth clock signal CLK0 and the first clock signal CLK1 are in opposite phases. For example, during the period from t0 to t2, the waveform of the zeroth clock signal CLK0 changes from a low level to a high level and the waveform of the first clock signal CLK1 changes from a high level to a low level; during the period from t1 to t3, the waveform of the zeroth clock signal CLK0 changes from a high level to a low level and the waveform of the first clock signal CLK1 changes from a low level to a high level.

As for FIG. 5 , although the zeroth clock signal CLK0 is also in phase opposite to the first clock signal CLK1, FIG. 5 is different from FIG. 4 in that: during the time period t0 to t2, the waveform of the zeroth clock signal CLK0 changes from a high level to a low level and the waveform of the first clock signal CLK1 changes from a low level to a high level; during the time period t1 to t3, the waveform of the zeroth clock signal CLK0 changes from a low level to a high level and the waveform of the first clock signal CLK1 changes from a high level to a low level.

FIG. 6 and FIG. 7 are schematic diagrams of the first micro-LED driving circuit uIC00 and the second micro-LED driving circuit uIC10 respectively.

As shown in FIG6 , the first micro-LED driving circuit uIC00 includes a D-type flip-flop DFF and a gate NOT. The D-type flip-flop DFF is used to generate a first data signal DATA1 according to the zeroth data signal DATA0 and the zeroth clock signal CLK0 and then output it. The phase difference between the zeroth data signal DATA0 and the first data signal DATA1 is less than one clock signal cycle. The gate NOT is used to generate a first clock signal CLK1 that is inverted with the zeroth clock signal CLK0 according to the zeroth clock signal CLK0 and then output it.

As shown in FIG7 , the second micro-LED driving circuit uIC10 includes a D-type flip-flop DFF and a gate NOT. The D-type flip-flop DFF is used to generate a second data signal DATA2 according to the first data signal DATA1 and the first clock signal CLK1 from the first micro-LED driving circuit uIC00 and then output it. The phase difference between the first data signal DATA1 and the second data signal DATA2 is less than one clock signal cycle. The gate NOT is used to generate a second clock signal CLK2 that is inverted with the first clock signal CLK1 according to the first clock signal CLK1 from the first micro-LED driving circuit uIC00 and then output it. The rest can be deduced accordingly.

Please refer to FIG8 and FIG9, which respectively illustrate timing diagrams of the zeroth data signal DATA0, the zeroth enable signal EN0, the zeroth clock signal CLK0, the row input signal ROW, the first data signal DATA1, the first enable signal EN1, the first clock signal CLK1, the second data signal DATA2, the second enable signal EN2, and the second clock signal CLK2 in different embodiments. Among them, the row input signal ROW is an internal row input signal generated according to the enable signal and the clock signal.

As shown in FIG8 , the zeroth data signal DATA0 output by the data driver DD is the zeroth data signal DATA0 received by the first micro-LED driving circuit uIC00. The first data signal DATA1 output by the first micro-LED driving circuit uIC00 is the first data signal DATA1 received by the second micro-LED driving circuit uIC10. The second data signal DATA2 output by the second micro-LED driving circuit uIC10 is the second data signal DATA2 received by the third micro-LED driving circuit uIC20. The rest can be deduced in the same way.

Similarly, the zeroth clock signal CLK0 output by the data driver DD is the zeroth clock signal CLK0 received by the first micro-LED driver circuit uIC00. The first clock signal CLK1 output by the first micro-LED driver circuit uIC00 is the first clock signal CLK1 received by the second micro-LED driver circuit uIC10. The second clock signal CLK2 output by the second micro-LED driver circuit uIC10 is the second clock signal CLK2 received by the third micro-LED driver circuit uIC20. The rest can be deduced in this way.

The zeroth data signal DATA0, the first data signal DATA1, and the second data signal DATA2 may sequentially include the zeroth data line data DL0, the zeroth pixel data PX0, the first data line data DL1, the first pixel data PX1, the second data line data DL2, the second pixel data PX2, the third data line data DL3, and the third pixel data PX3.

The zeroth data signal DATA0, the first data signal DATA1, and the second data signal DATA2 may all be five-bit data. The first data line data DL1, the second data line data DL2, and the third data line data DL3 may all be two-bit data, for example, the first data line data DL1, the second data line data DL2, and the third data line data DL3 may include a first data bit I (L) and a second data bit I (M).

The zeroth pixel data PX0, the first pixel data PX1, and the second pixel data PX2 may be three-bit data, for example, the zeroth pixel data PX0 may include the zeroth red sub-pixel data R0, the zeroth green sub-pixel data G0, and the zeroth blue sub-pixel data B0; the first pixel data PX1 may include the first red sub-pixel data R1, the first green sub-pixel data G1, and the first blue sub-pixel data B1; the second pixel data PX2 may include the second red sub-pixel data R0, the second green sub-pixel data G2, and the second blue sub-pixel data B2; the third pixel data PX3 may include the third red sub-pixel data R3, the third green sub-pixel data G3, and the third blue sub-pixel data B3. The rest may be deduced in the same manner.

The start time (positive edge) of the zeroth enable signal EN0 corresponds to the start time of the zeroth data line data DL0 of the zeroth data signal DATA0, both of which are time t0. The period during which the zeroth enable signal EN0 changes from a low level to a high level at time t0 and the zeroth enable signal EN0 remains at a high level is the period during which the first micro-LED driving circuit uIC00 is actuated.

After the first enable signal EN1 is re-timed, the start time (positive edge) of the first enable signal EN1 corresponds to the start time of the first data cycle D1 of the first data signal DATA1, which is time t3. The period during which the first enable signal EN1 changes from a low level to a high level at time t3 and the first enable signal EN1 remains at a high level is the period during which the second micro-LED driving circuit uIC10 is actuated.

Similarly, after the second enable signal EN2 is re-timed, the start time (positive edge) of the second enable signal EN2 corresponds to the start time of the second data cycle D2 of the second data signal DATA2, which is time t5. The period during which the second enable signal EN2 changes from a low level to a high level at time t5 and the second enable signal EN2 remains at a high level is the period during which the third micro-LED driving circuit uIC20 is actuated. The rest can be deduced in this way.

Assuming that time t0 to t2 is one clock signal cycle, the phase difference between the positive edge or negative edge of the zeroth clock signal CLK0 and the zeroth data signal DATA0 may be between 0.3 and 0.7 clock signal cycles, but not limited thereto; the phase difference between the zeroth data signal DATA0 and the first data signal DATA1 may be 0.5 clock signal cycles, for example, the start time of the zeroth data signal DATA0 corresponds to time t0 and the start time of the first data signal DATA1 corresponds to time t1 and the period from time t0 to t1 is 0.5 clock signal cycles, but not limited thereto.

The zeroth clock signal CLK0 and the first clock signal CLK1 are in opposite phases. When the waveform of the zeroth clock signal CLK0 changes from low level to high level, the waveform of the first clock signal CLK1 changes from high level to low level; when the waveform of the zeroth clock signal CLK0 changes from high level to low level, the waveform of the first clock signal CLK1 changes from low level to high level.

Similarly, the phase difference between the positive edge or negative edge of the first clock signal CLK1 and the first data signal DATA1 may be between 0.3 and 0.7 clock signal cycles, but not limited thereto; the phase difference between the first data signal DATA1 and the second data signal DATA2 may be 0.5 clock signal cycles, for example, the start time of the first data signal DATA1 corresponds to time t1 and the start time of the second data signal DATA2 corresponds to time t2 and the period from time t1 to t2 is 0.5 clock signal cycles, but not limited thereto.

The first clock signal CLK1 and the second clock signal CLK2 are in opposite phases. When the waveform of the first clock signal CLK1 changes from low level to high level, the waveform of the second clock signal CLK2 changes from high level to low level; when the waveform of the first clock signal CLK1 changes from high level to low level, the waveform of the second clock signal CLK2 changes from low level to high level. The same can be said for the rest.

As shown in FIG9 , the zeroth data signal DATA0 output by the data driver DD is the zeroth data signal DATA0 received by the first micro-LED driving circuit uIC00. The first data signal DATA1 output by the first micro-LED driving circuit uIC00 is the first data signal DATA1 received by the second micro-LED driving circuit uIC10. The second data signal DATA2 output by the second micro-LED driving circuit uIC10 is the second data signal DATA2 received by the third micro-LED driving circuit uIC20. The rest can be deduced in the same way.

Similarly, the zeroth clock signal CLK0 output by the data driver DD is the zeroth clock signal CLK0 received by the first micro-LED driver circuit uIC00. The first clock signal CLK1 output by the first micro-LED driver circuit uIC00 is the first clock signal CLK1 received by the second micro-LED driver circuit uIC10. The second clock signal CLK2 output by the second micro-LED driver circuit uIC10 is the second clock signal CLK2 received by the third micro-LED driver circuit uIC20. The rest can be deduced in this way.

The zeroth data signal DATA0, the first data signal DATA1, and the second data signal DATA2 may include the zeroth pixel data PX0, the first pixel data PX1, the second pixel data PX2, and the third pixel data PX3 in sequence.

The zeroth pixel data PX0, the first pixel data PX1, and the second pixel data PX2 may all be (n+1)-bit data. For example, the zeroth pixel data PX0 may include (n+1) data bits D0[0]~D0[n], the first pixel data PX1 may include (n+1) data bits D1[0]~D1[n], the second pixel data PX2 may include (n+1) data bits D2[0]~D2[n], and the third pixel data PX3 may include (n+1) data bits D3[0]~D3[n]. The rest may be deduced in the same manner.

The start time (positive edge) of the zeroth enable signal EN0 corresponds to the start time of the data bit D0[0] of the zeroth data signal DATA0, which is time t0. The period during which the zeroth enable signal EN0 changes from a low level to a high level at time t0 and the zeroth enable signal EN0 remains at a high level is the period during which the first micro-LED driving circuit uIC00 is actuated.

After the first enable signal EN1 is re-timed, the start time (positive edge) of the first enable signal EN1 corresponds to the start time of the data bit D1[0] of the first data signal DATA1, which is time t3. The period during which the first enable signal EN1 changes from a low level to a high level at time t3 and the first enable signal EN1 remains at a high level is the period during which the second micro-LED driving circuit uIC10 is actuated.

Similarly, after the second enable signal EN2 is re-timed, the start time (positive edge) of the second enable signal EN2 corresponds to the start time of the data bit D2[0] of the second data signal DATA2, which is time t5. The period during which the second enable signal EN2 changes from a low level to a high level at time t5 and the second enable signal EN2 remains at a high level is the period during which the third micro-LED driving circuit uIC20 is actuated. The rest can be deduced in this way.

Assuming that time t0 to t2 is one clock signal cycle, the phase difference between the positive edge or negative edge of the zeroth clock signal CLK0 and the zeroth data signal DATA0 may be between 0.3 and 0.7 clock signal cycles, but not limited thereto; the phase difference between the zeroth data signal DATA0 and the first data signal DATA1 may be 0.5 clock signal cycles, for example, the start time of the zeroth data signal DATA0 corresponds to time t0 and the start time of the first data signal DATA1 corresponds to time t1 and the period from time t0 to t1 is 0.5 clock signal cycles, but not limited thereto.

The zeroth clock signal CLK0 and the first clock signal CLK1 are in opposite phases. When the waveform of the zeroth clock signal CLK0 changes from low level to high level, the waveform of the first clock signal CLK1 changes from high level to low level; when the waveform of the zeroth clock signal CLK0 changes from high level to low level, the waveform of the first clock signal CLK1 changes from low level to high level.

Similarly, the phase difference between the positive edge or negative edge of the first clock signal CLK1 and the first data signal DATA1 may be between 0.3 and 0.7 clock signal cycles, but not limited thereto; the phase difference between the first data signal DATA1 and the second data signal DATA2 may be 0.5 clock signal cycles, for example, the start time of the first data signal DATA1 corresponds to time t1 and the start time of the second data signal DATA2 corresponds to time t2 and the period from time t1 to t2 is 0.5 clock signal cycles, but not limited thereto.

The first clock signal CLK1 and the second clock signal CLK2 are in opposite phases. When the waveform of the first clock signal CLK1 changes from low level to high level, the waveform of the second clock signal CLK2 changes from high level to low level; when the waveform of the first clock signal CLK1 changes from high level to low level, the waveform of the second clock signal CLK2 changes from low level to high level. The same can be said for the rest.

Compared with the prior art, the micro-luminescent diode display device of the present invention divides the traditional row input signal (ROW) into an enable signal (EN) and a clock signal (CLK). When the enable signal (EN), the clock signal (CLK) and the data signal (DATA) are input to a display panel PL (such as a glass substrate) having a high resistance value, the enable signal (EN), the clock signal (CLK) and the data signal (DATA) are sequentially transmitted to a plurality of micro-luminescent diodes connected in series. The electrode driving circuit, and the enable signal (EN) and the data signal (DATA) are re-timed in each micro-LED driving circuit to have the same delay and the clock signal (CLK) is transmitted in reverse to the next micro-LED driving circuit to avoid the signal being distorted by parasitic resistance and capacitance, so that the micro-LED display device of the present invention can operate smoothly at high frequency and the resolution and size of its display panel are not limited.

uIC00~uICmn: micro-luminescent diode driver circuit uIC00~uIC77: micro-luminescent diode driver circuit COL: column input signal ROW: row input signal DATA0: zeroth data signal EN0: zeroth enable signal CLK0: zeroth clock signal DATA1: first data signal EN1: first enable signal CLK1: first clock signal DATA2: second data signal EN2: second enable signal CLK2: second clock signal DATAI: data signal input terminal ENI: enable signal input terminal CLKI: clock signal input terminal DATAO: data signal output terminal ENO: enable signal output terminal CLKO: clock signal output terminal D0: zeroth data cycle D1: first data cycle D2: second data cycle t0~t6: time DFF: D-type flip-flop CLK: clock port NOT: gate DL0: zeroth data line data DL1: first data line data DL2: second data line data DL3: third data line data PX0: zeroth pixel data PX1: first pixel data PX2: second pixel data PX3: third pixel data I(L): first data bit I(M): second data bit R0: zeroth red sub-pixel data G0: zeroth green sub-pixel data B0: zeroth blue sub-pixel data R1: first red sub-pixel data G1: first green sub-pixel data B1: first blue sub-pixel data R2: Second red sub-pixel data G2: Second green sub-pixel data B2: Second blue sub-pixel data R3: Third red sub-pixel data G3: Third green sub-pixel data B3: Third blue sub-pixel data D0[0]~D0[n], D1[0]~D1[n], D2[0]~D2[n], D3[0]~D3[n]: Data bits

FIG. 1 is a schematic diagram of a conventional micro-luminescent diode display device.

FIG. 2 is a schematic diagram of a micro-luminescent diode display device in a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram showing signal transmission between a data driver and a micro-LED driving circuit connected in series with each other.

FIG. 4 and FIG. 5 respectively illustrate timing diagrams of the zeroth data signal, the zeroth clock signal, the first data signal, and the first clock signal in different embodiments.

FIG. 6 and FIG. 7 are schematic diagrams of a first micro-LED driving circuit and a second micro-LED driving circuit, respectively.

8 and 9 respectively illustrate timing diagrams of a zeroth data signal, a zeroth enable signal, a zeroth clock signal, a row input signal, a first data signal, a first enable signal, a first clock signal, a second data signal, a second enable signal, and a second clock signal in different embodiments.

uIC00: First micro-LED driving circuit

uIC10: Second micro-LED driving circuit

DATA0: zeroth data signal

EN0: Zeroth enable signal

CLK0: zeroth clock signal

DATA1: first data signal

EN1: First enable signal

CLK1: first clock signal

DATA2: Second data signal

EN2: Second enable signal

CLK2: Second clock signal

DATAI: Data signal input terminal

ENI: Enable signal input terminal

CLKI: Clock signal input terminal

DATAO: data signal output terminal

ENO: Enable signal output terminal

CLKO: Clock signal output terminal

Claims (14)

A micro-luminescent diode display device includes: a display panel including a plurality of pixels; and a plurality of micro-luminescent diode driving circuits, each of which is coupled to at least one pixel of the display panel, and the plurality of micro-luminescent diode driving circuits include a first micro-luminescent diode driving circuit and a second micro-luminescent diode driving circuit connected in series with each other, the first micro-luminescent diode driving circuit receiving a zero data signal, a zero enable signal, and a second micro-luminescent diode driving circuit. The circuit outputs a first data signal, a first enabling signal and a first clock signal to the second micro-luminescent diode driving circuit; wherein the first clock signal and the first clock signal are inverted and the phase difference between the first data signal and the zero data signal is less than one clock signal cycle, and the phase difference between the positive edge or negative edge of the zero clock signal and the zero data signal is between 0.3 and 0.7 clock signal cycles. The micro-luminescent diode display device as described in claim 1 further includes: a data driver coupled to the first micro-luminescent diode driving circuit and providing the zeroth data signal, the zeroth enable signal and the zeroth clock signal to the first micro-luminescent diode driving circuit. The micro-luminescent diode display device as described in claim 1, wherein the first micro-luminescent diode driving circuit includes: a D-type flip-flop for generating the first data signal according to the zeroth data signal and the zeroth clock signal; and a gate for generating the first clock signal according to the zeroth clock signal. A micro-luminescent diode display device as described in claim 1, wherein the phase difference between the zeroth data signal and the first data signal is 0.5 clock signal cycle. A micro-luminescent diode display device as described in claim 1, wherein the waveform of the zeroth clock signal changes from a low level to a high level and the waveform of the first clock signal changes from a high level to a low level. A micro-luminescent diode display device as described in claim 1, wherein the waveform of the zeroth clock signal changes from a high level to a low level and the waveform of the first clock signal changes from a low level to a high level. A micro-luminescent diode display device as described in claim 1, wherein the start time of the zeroth enable signal corresponds to the start time of the zeroth data cycle of the zeroth data signal, and the start time of the first enable signal corresponds to the start time of the first data cycle of the first data signal. A micro-luminescent diode display device includes: a display panel including a plurality of pixels; and a plurality of micro-luminescent diode driving circuits, each of which is coupled to at least one pixel of the display panel, and the plurality of micro-luminescent diode driving circuits include a first micro-luminescent diode driving circuit and a second micro-luminescent diode driving circuit connected in series with each other, the first micro-luminescent diode driving circuit receives a zero data signal, a zero enable signal and a zero clock signal and outputs a first data signal, a first enable signal and a first clock signal to the display panel. A second micro-luminescent diode driving circuit; wherein the zeroth clock signal and the first clock signal are inverted and the phase difference between the zeroth data signal and the first data signal is less than one clock signal cycle, wherein the second micro-luminescent diode driving circuit receives the first data signal, the first enable signal and the first clock signal and outputs a second data signal, a second enable signal and a second clock signal, wherein the first clock signal and the second clock signal are inverted and the phase difference between the first data signal and the second data signal is less than one clock signal cycle. The micro-luminescent diode display device as described in claim 8, wherein the second micro-luminescent diode driving circuit includes: a D-type flip-flop for generating the second data signal according to the first data signal and the first clock signal; and a gate for generating the second clock signal according to the first clock signal. A micro-luminescent diode display device as described in claim 8, wherein the phase difference between the positive edge or negative edge of the first clock signal and the first data signal is between 0.3 and 0.7 clock signal cycles. A micro-luminescent diode display device as described in claim 8, wherein the phase difference between the first data signal and the second data signal is 0.5 clock signal cycle. A micro-luminescent diode display device as described in claim 8, wherein the waveform of the first clock signal changes from a low level to a high level and the waveform of the second clock signal changes from a high level to a low level. A micro-luminescent diode display device as described in claim 8, wherein the waveform of the first clock signal changes from a high level to a low level and the waveform of the second clock signal changes from a low level to a high level. A micro-luminescent diode display device as described in claim 8, wherein the start time of the second enable signal corresponds to the start time of the second data cycle of the second data signal.