TWI866935B - Back-illuminated solid-state imaging device, method for manufacturing back-illuminated solid-state imaging device, imaging device and electronic device - Google Patents

Abstract

The present invention relates to a back-illuminated solid-state imaging device capable of reducing manufacturing costs, a manufacturing method of the back-illuminated solid-state imaging device, an imaging device, and an electronic device. The memory circuit and logic circuit that have been monolithicized are arranged in the horizontal direction, flattened by embedding an oxide film, and then laminated under the solid-state imaging element in a manner of encapsulating in the plane direction. The present invention can be applied to imaging devices.

Description

Back-illuminated solid-state imaging device, method for manufacturing back-illuminated solid-state imaging device, imaging device and electronic device

The present invention relates to a back-illuminated solid-state imaging device, a manufacturing method of the back-illuminated solid-state imaging device, an imaging device and an electronic device, and more particularly to a back-illuminated solid-state imaging device, a manufacturing method of the back-illuminated solid-state imaging device, an imaging device and an electronic device capable of reducing manufacturing costs.

Solid-state cameras are achieving high image quality in the form of high-fidelity, 4k×2k ultra-high-fidelity, and even super-slow motion functions. As the number of pixels increases, the frame rate becomes higher and the pitch becomes higher.

The transfer rate is the number of pixels × frame rate × step size. For example, when the number of pixels is 4 k × 2 k = 8 M, the frame rate is 240 f/s, and the step size is 14 bit, the transfer rate is 8 M × 240 f/s × 14 bit = 26 Gbps.

After the signal processing in the back-end of the solid-state imaging device, the output of the color-coordinated RGB needs to be transmitted at a higher speed of 26 G×3=78 Gbps.

If high-speed transmission is performed through a smaller number of connection terminals, the signal rate of each connection terminal becomes higher, and the difficulty of impedance matching for obtaining a high-speed transmission path becomes higher. In addition, the higher the clock frequency, the greater the loss, so the power consumption increases.

In order to avoid the above situation, the number of connection terminals can be increased to divide the transmission and slow down the signal rate. However, increasing the number of connection terminals will increase the number of terminals required for connecting the solid-state imaging device with the subsequent signal processing circuit or memory circuit, so the package of each circuit becomes larger.

In addition, the substrate for electrical wiring required for the signal processing circuit or memory circuit at the later stage also needs to have a finer wiring density due to multilayer wiring, and the wiring path length becomes longer, which in turn increases the power consumption.

If the package of each circuit becomes larger, the mounting substrate itself will also become larger, which will eventually cause the imaging device equipped with the solid-state imaging element to become larger in structure itself.

Therefore, as a technology for miniaturizing the structure of an imaging device, a technology for stacking solid-state imaging elements and circuits such as signal processing circuits or memory circuits by bonding them in a wafer state has been proposed (see Patent Document 1).

By using the stacking technology that utilizes WoW, semiconductors can be connected through more fine wiring, so the transmission speed of each line becomes lower, thereby suppressing power consumption. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Publication No. 2014-099582

[The problem the invention is trying to solve]

However, in the case of WoW, the chips of the stacked wafer only need to be the same size, but if the sizes of the chips formed in the wafer are different, the size must be consistent with the largest chip size, which reduces the theoretical yield of each circuit and increases costs.

Furthermore, the yield of each wafer in the stack is that a defective chip on each wafer will also cause the chips of other stacked wafers to become defective. Since the yield of the entire stacked wafer is the product of the yields of each wafer, the yield deteriorates and the cost increases.

In addition, a technique has been proposed to connect chips of different sizes by forming small bumps. In this case, the chips of different sizes that have been selected as good products are connected through bumps, so the theoretical yield difference of each wafer or the yield of each chip is less affected.

However, it is difficult to form small bumps and the connection pitch is limited, so it is not possible to obtain more connection terminals than WoW. In addition, since the connection is made during the installation process, if the number of connection terminals increases, the yield will decrease due to the connection, resulting in an increase in cost. In addition, the connection in the installation process is also performed separately, so the time spent on the connection becomes longer, and thus the process cost increases.

The present invention was completed in view of this situation, and can especially reduce the manufacturing cost of solid-state imaging devices. [Technical means to solve the problem]

The first aspect of the present invention is a back-illuminated solid-state imaging device, an imaging device, and an electronic machine, comprising: a first semiconductor element, which is an imaging element that generates a pixel signal in pixel units; a second semiconductor element and a third semiconductor element, which are smaller than the first semiconductor element, and in which signal processing circuits required for signal processing of the pixel signals are embedded in an embedded component; and interconnecting wiring that electrically connects the second semiconductor element and the third semiconductor element.

In the first aspect of the present invention, it includes: a first semiconductor element, which has an imaging element that generates pixel signals in pixel units; a second semiconductor element and a third semiconductor element, which are smaller than the first semiconductor element, and the signal processing circuits required for signal processing of the pixel signals are embedded in the embedded components; and interconnection wiring, which electrically connects the second semiconductor element and the third semiconductor element.

The manufacturing method of the back-illuminated solid-state imaging device of the second aspect of the present invention is the following manufacturing method of the back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprises: a first semiconductor element, which has an imaging element that generates a pixel signal in a pixel unit; a second semiconductor element and a third semiconductor element, which are smaller than the first semiconductor element, and the signal processing circuits required for the signal processing of the pixel signal are embedded in the embedded component; and interconnection wiring, which electrically connects the second semiconductor element and the third semiconductor element; and the manufacturing method of the back-illuminated solid-state imaging device is in a state where the second semiconductor element and the third semiconductor element are electrically connected to each other. The wafer of the imaging element formed by a semiconductor process is further configured with the signal processing circuit including the second semiconductor element and the third semiconductor element formed by a semiconductor process. The second semiconductor element and the third semiconductor element judged as good products by electrical inspection are embedded by the embedded component to form interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element. The oxide film is bonded and layered in a manner that electrically connects the wiring between the first semiconductor element and the second semiconductor element and the third semiconductor element, and then the wafer is singulated.

In the second aspect of the present invention, a method for manufacturing a back-illuminated solid-state imaging device is the following method for manufacturing a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising: a first semiconductor element having an imaging element that generates a pixel signal in pixel units; a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, and in which a signal processing circuit required for signal processing of the pixel signal is embedded in an embedded component; and interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element; and the back-illuminated solid-state imaging device is manufactured by semiconductors. The wafer of the imaging element formed by the semiconductor process is further configured with the signal processing circuit including the second semiconductor element and the third semiconductor element formed by the semiconductor process, the second semiconductor element and the third semiconductor element judged as good products by electrical inspection, and are embedded by the embedded component to form interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element, and oxide film bonding is performed in a manner that the wiring between the first semiconductor element and the second semiconductor element and the third semiconductor element is electrically connected. After lamination, they are singulated to manufacture a back-illuminated solid-state imaging device.

The back-illuminated solid-state imaging device of the third aspect of the present invention comprises: a first semiconductor element layer, which has an imaging element that generates pixel signals in pixel units; a second semiconductor element layer, which has a second semiconductor element and a third semiconductor element, wherein the second semiconductor element and the third semiconductor element are smaller than the first semiconductor element, and signal processing circuits required for signal processing of the pixel signals are embedded in an embedded component; and a supporting substrate; the second semiconductor element layer is arranged between the first semiconductor element layer and the supporting substrate, and the first semiconductor element layer and the second semiconductor element layer are bonded by direct bonding.

In the third aspect of the present invention, there are provided: a first semiconductor element layer having an imaging element that generates pixel signals in pixel units; a second semiconductor element layer having a second semiconductor element and a third semiconductor element, wherein the second semiconductor element and the third semiconductor element are smaller than the first semiconductor element, and signal processing circuits required for signal processing of the pixel signals are embedded in an embedded component; and a supporting substrate; the second semiconductor element layer is disposed between the first semiconductor element layer and the supporting substrate, and the first semiconductor element layer and the second semiconductor element layer are bonded by direct bonding.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in this specification and drawings, components having substantially the same functional configuration are labeled with the same symbols to omit repeated descriptions.

Furthermore, the following order is used for explanation. 1. Overview of the present invention 2. First embodiment 3. Second embodiment 4. Application example of the second embodiment 5. Third embodiment 6. Fourth embodiment 7. Fifth embodiment 8. Sixth embodiment 9. Seventh embodiment 10. Eighth embodiment 11. Ninth embodiment 12. Application example of the ninth embodiment 13. Tenth embodiment 14. First application example of the tenth embodiment 15. Second application example of the tenth embodiment 16. Application example for electronic equipment 17. Use example of solid-state imaging device 18. Application example for endoscopic surgical system 19. Application example for moving object

＜＜1. Summary of the invention＞＞ The present invention is to reduce the manufacturing cost of a solid-state imaging device.

Here, when describing the present invention, WoW (Wafer on Wafer) disclosed in Patent Document 1 is described.

For example, as shown in FIG1 , WoW is a technology that combines and stacks a solid-state imaging device and a signal processing circuit or an IC (intergrated circuit) including a memory circuit in a wafer state.

FIG. 1 schematically shows a WoW in which a wafer W1 having a plurality of solid-state imaging devices 11 formed thereon, a wafer W2 having a plurality of memory circuits 12 formed thereon, and a wafer W3 having a plurality of logic circuits 13 formed thereon are bonded and stacked in a state of being precisely aligned.

By integrating the structure stacked in this manner into single chips, a solid-state imaging device such as shown in FIG. 2 is formed.

In the solid-state imaging device 1 of FIG. 2 , a chip-mounted lens and a chip-mounted color filter 10, a solid-state imaging element 11, a memory circuit 12, a logic circuit 13, and a supporting substrate 14 are sequentially stacked from the top.

Here, by applying the WoW technology, the wiring 21-1 that electrically connects the solid-state imaging element 11 and the memory circuit 12, and the wiring 21-2 that electrically connects the memory circuit 12 and the logic circuit 13 can be connected at a fine pitch.

As a result, the number of wiring lines can be increased, so the transmission speed in each signal line can be reduced, thereby achieving power saving.

However, the stacked solid-state imaging device 11, memory circuit 12, and logic circuit 13 each require different areas, so a space Z1 where neither a circuit nor a wiring is formed is generated on the left and right of the memory circuit 12 in the figure, which is smaller in area than the largest solid-state imaging device 11. Also, a space Z2 where neither a circuit nor a wiring is formed is generated on the left and right of the logic circuit 13 in the figure, which is smaller in area than the memory circuit 12.

That is, the spaces Z1 and Z2 are generated due to the different areas required by the solid-state imaging element 11, the memory circuit 12, and the logic circuit 13. In FIG. 2 , the solid-state imaging element 11 requiring the largest area is used as the reference area.

As a result, the theoretical yield associated with the manufacture of the solid-state imaging device 1 is reduced, resulting in an increase in the cost associated with the manufacture.

1, the defective structures in the solid-state imaging device 11, the memory circuit 12, and the logic circuit 13 formed on the wafers W1 to W3 are filled with a grid to express them. That is, FIG1 shows that two defects are generated in each of the wafers W1 to W3.

As shown in Fig. 1, the defects generated in the solid-state imaging element 11, the memory circuit 12, and the logic circuit 13 formed on the wafers W1 to W3 are not necessarily generated at the same position. Therefore, as shown in Fig. 1, the solid-state imaging device 1 formed as a stacked structure has six defects marked with crosses on the wafer W1 of the solid-state imaging element 11.

Therefore, for the six defective solid-state imaging devices 1, although at least two of the three components of the solid-state imaging element 11, the memory circuit 12, and the logic circuit 13 are not defective, they are processed as six defects respectively. Therefore, for each component, there could have been two defects, but they become six defects accumulated by the number of wafers.

As a result, the yield rate of the solid-state imaging device 1 is reduced, thereby increasing the manufacturing cost.

Furthermore, consider that as shown in FIG. 3, after the solid-state imaging device 11, the memory circuit 12, and the logic circuit 13 of different chip sizes are monolithicized, only good products are selectively arranged, and small bumps are formed for connection.

In the solid-state imaging device 1 of FIG. 3 , a chip-mounted lens and a chip-mounted color filter 10 and a solid-state imaging element 11 are stacked from the top, and a memory circuit 12 and a logic circuit 13 are stacked on the same layer below, and a supporting substrate 14 is arranged and stacked below the layer. Furthermore, the solid-state imaging element 11 is electrically connected to the memory circuit 12 and the logic circuit 13 arranged on the same layer via small bumps 31.

In the solid-state imaging device 1 of FIG. 3 , chips of different sizes that have been screened as good products are connected via bumps 31 , and the theoretical yield difference of each wafer or the impact of the yield of each chip can be reduced.

However, it is difficult to form a small bump 31, as shown in FIG. 3, and the reduction of the connection pitch d2 is limited, so it cannot be smaller than the connection pitch d1 of FIG. 2 when WoW is used.

Therefore, the solid-state imaging device 1 of FIG. 3 using bump lamination cannot obtain a larger number of connection terminals than the solid-state imaging device 1 of FIG. 2 using WoW lamination. In addition, in the case of using bump connection as in the solid-state imaging device 1 of FIG. 3 , if the number of connection terminals increases, the yield associated with the bonding is reduced due to the bonding during the mounting process, thereby increasing the cost. Furthermore, the connection of the bumps during the mounting process also becomes a separate operation, so the time of each process is longer, thereby increasing the process cost.

Based on the above, the imaging element of the present invention reduces the costs associated with manufacturing from the perspectives of theoretical yield, installation cost, and process cost.

＜＜2. First Implementation Form＞＞ Figure 4 is a diagram illustrating a structure obtained by laminating a plurality of wafers by combining the CoW (Chip on Wafer) technology and the WoW technology used in manufacturing the solid-state imaging device of the present invention.

When manufacturing the solid-state imaging device of the present invention, two wafers are stacked in a state where wiring has been precisely performed and aligned. The two wafers include a wafer 101 on which a plurality of solid-state imaging elements (CMOS (Complementary Metal Oxide Semiconductor) image sensors or CCD (Charge Coupled Device)) 120 are formed, and a wafer 102 on which a memory circuit 121 and a logic circuit 122 are further configured. In addition, the solid-state imaging element 120 is described as a CMOS image sensor (CMOS Image Sensor) in the figure below, and is also simply referred to as CIS120.

In the wafer 101, a plurality of solid-state imaging devices 120 are formed by a semiconductor process.

A plurality of memory circuits 121 are disposed in the wafer 102. The plurality of memory circuits 121 are formed on the wafer 103 by a semiconductor process and are singulated and then individually electrically inspected to be confirmed as good quality chips.

Furthermore, a plurality of logic circuits 122 are disposed in the wafer 102. The plurality of logic circuits 122 are formed on the wafer 104 by a semiconductor process and are singulated and then individually electrically inspected to be confirmed as good quality chips.

<Example of a solid-state imaging device formed by stacking wafers using the WoW technology shown in FIG. 4> A plurality of wafers are stacked using the WoW technology shown in FIG. 4 and then singulated to form the solid-state imaging device 111 (FIG. 5) of the present invention.

The solid-state imaging device of the present invention is configured as shown in Fig. 5, for example. The upper portion of Fig. 5 is a side cross-sectional view, and the lower portion is a diagram showing the horizontal arrangement relationship of the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122 as viewed from the upper surface.

The solid-state imaging device 111 in the upper part of FIG. 5 is formed by stacking a color filter and a wafer-carrying lens 131, and a solid-state imaging element 120 from the upper part of the figure, and below it, a memory circuit 121 and a logic circuit 122 are stacked on the same layer on the left and right, and a supporting substrate 132 is formed below the layer. That is, as shown in the upper part of FIG. 5 , the solid-state imaging device 111 in FIG. 5 includes a semiconductor element layer E1 and a semiconductor element layer E2, the semiconductor element layer E1 includes the solid-state imaging element 120 formed by the wafer 101, and the semiconductor element layer E2 includes the memory circuit 121 and the logic circuit 122 formed on the wafer 102.

The wiring 120a on the memory circuit 121 in the wiring 120a of the solid-state imaging element 120 and the wiring 121a of the memory circuit 121 are electrically connected via the wiring 134, and the wiring 134 is connected via CuCu connection.

Furthermore, the wiring 120a on the logic circuit 122 in the wiring 120a of the solid-state imaging element 120 and the wiring 122a of the logic circuit 122 are electrically connected via the wiring 134, and the wiring 134 is connected via CuCu connection.

The space around the memory circuit 121 and the logic circuit 122 in the semiconductor device layer E2 where the memory circuit 121 and the logic circuit 122 are formed is filled with the oxide film 133. Thus, the memory circuit 121 and the logic circuit 122 are buried in the oxide film 133 in the semiconductor device layer E2.

If the oxide film 133 is an inorganic film, it is preferably a Si-based oxide film such as SiO ₂ , SiO, or SRO in terms of heat resistance and the warp after film formation. The oxide film 133 may also be replaced by an organic film. In this case, the organic film is preferably a polyimide-based film (PI (polyimide), PBO (polybenzoxazole), etc.) or a polyamide-based film that can easily ensure high heat resistance.

Furthermore, the boundary between the semiconductor element layer E1 formed with the solid-state imaging element 120 and the semiconductor element layer E2 formed with the memory circuit 121 and the logic circuit 122 is bonded by oxide film bonding to form an oxide film bonding layer 135. Furthermore, the semiconductor element layer E2 of the memory circuit 121 and the logic circuit 122 is bonded to the supporting substrate 132 by oxide film bonding to form an oxide film bonding layer 135.

5, the memory circuit 121 and the logic circuit 122 are arranged so as to be contained within the range of the solid-state imaging element 120 on the top layer when viewed from the top surface. With this arrangement, the empty space other than the memory circuit 121 and the logic circuit 122 in the layers of the memory circuit 121 and the logic circuit 122 is reduced, thereby improving the theoretical yield.

When each solid-state imaging device 111 is singulated on the wafer 102 of FIG. 4 , the memory circuit 121 and the logic circuit 122 are finely adjusted and rearranged in such a manner that they are arranged within the range of the solid-state imaging element 120 as viewed from their respective upper surfaces.

<Manufacturing method of the solid-state imaging device of FIG. 5> Next, referring to FIG. 6 to FIG. 9 , the manufacturing method of the solid-state imaging device 111 of FIG. 5 is described. Furthermore, the side sectional views 6A to 6L of FIG. 6 to FIG. 9 show the side sectional views of the solid-state imaging device 111.

In the first process, as shown in the side cross-sectional view 6A of FIG6 , the memory circuit 121 and the logic circuit 122 that are confirmed as good products after electrical inspection are re-arranged on the re-arrangement substrate 151 in a manner as shown in the lower section of FIG5 . An adhesive 152 is applied on the re-arrangement substrate 151, and the memory circuit 121 and the logic circuit 122 are re-arranged and fixed on the re-arrangement substrate 151 by the adhesive 152.

In the second step, as shown in the side cross-sectional view 6B of Figure 6, an oxide film is formed by inverting the upper surface of the memory circuit 121 and the logic circuit 122 shown in the side cross-sectional view 6A to become the lower surface, and an oxide film bonding layer 135 is formed on the planarized supporting substrate 161 to perform oxide film bonding.

In the third step, as shown in the side cross-sectional view 6C of FIG. 6 , the reconfiguration substrate 151 is debonded and peeled off together with the adhesive 152 to be removed.

In the fourth step, as shown in the side cross-sectional view 6D of FIG. 7 , the silicon layer of the upper surface portion of the memory circuit 121 and the logic circuit 122 is thinned to a height A that does not affect the characteristics of the device.

In the fifth step, as shown in the side cross-sectional view 6E of FIG7 , an oxide film 133 is formed to function as an insulating film, and the chip including the reconfigured memory circuit 121 and the logic circuit 122 is buried. At this time, the surface of the oxide film 133 is flattened to a height corresponding to the memory circuit 121 and the logic circuit 122.

In the sixth step, as shown in the side cross-sectional view 6F of FIG. 7 , an oxide film bonding layer 135 is formed on the planarized oxide film 133 by oxide film bonding to bond the support substrate 171 .

In the seventh step, as shown in the side cross-sectional view 6G of FIG8 , the support substrate 171 is removed by stripping or etching. Through the processing of the first step to the seventh step, the memory circuit 121 and the logic circuit 122 are rearranged in the layout shown in the lower part of FIG5 , and are embedded with an insulating film including an oxide film 133, thereby completing the wafer 102 in a state where an oxide film bonding layer 135 is formed on the planarized uppermost surface.

In the eighth step, as shown in the side cross-sectional view 6H of FIG. 8 , the wiring 134 is formed for the wiring 121a of the memory circuit 121 and the wiring 122a of the logic circuit 122 for electrical connection with the solid-state imaging element 120.

In the ninth step, as shown in the side cross-sectional view 6I of FIG8 , the wiring 121a of the memory circuit 121 and the wiring 122a of the logic circuit 122 in the wafer 102 are appropriately aligned with the wiring 134 of the wiring 120a of the solid-state imaging device (CIS) 120 in the wafer 101 so as to be in opposing positions.

In the tenth process, as shown in the side cross-sectional view 6J of FIG. 9 , the wiring 121a of the memory circuit 121 and the wiring 122a of the logic circuit 122 in the wafer 102 are connected to the wiring 134 of the wiring 120a of the solid-state imaging device 120 in the wafer 101 by CuCu bonding, and in this way, the wafers 101 and 102 are bonded by WoW. Through this process, the memory circuits 121 and the logic circuits 122 of the wafer 102 are electrically connected to the solid-state imaging devices 120 of the wafer 101.

In the eleventh step, as shown in the side cross-sectional view 6K of FIG. 9 , the upper layer of the solid-state imaging element 120 in the figure, that is, the silicon layer, is thinned.

In the twelfth process, as shown in the side cross-sectional view 6L of FIG. 9 , the color filter and the chip-mounted lens 131 are disposed on the solid-state imaging element 120 and singulated, thereby completing the solid-state imaging device 111 .

Through the above steps, the solid-state imaging device 111 including the first layer on which the solid-state imaging element 120 is formed and the second layer on which the memory circuit 121 and the logic circuit 122 are formed is manufactured.

With this structure, the connection between the solid-state imaging element 120 and the memory circuit 121 and the logic circuit 122 can be formed by terminals with a fine wiring density through semiconductor lithography technology in the same way as WoW, thereby increasing the number of connection terminals and reducing the signal processing speed in each wiring, thereby reducing power consumption.

Furthermore, since the memory circuit 121 and the logic circuit 122 are connected only to good chips, the defective wafers which are the disadvantages of WoW are reduced, thereby reducing the yield loss.

Furthermore, unlike WoW, the connected memory circuit 121 and the logic circuit 122 can be set to the smallest possible size regardless of the chip size of the solid-state imaging element 120, and can be configured as independent island shapes as shown in the lower part of Figure 5, thereby improving the theoretical yield of the connected memory circuit 121 and the logic circuit 122.

In the above situation, since the solid-state imaging device 120 needs to have the minimum pixel size necessary for reacting to optical light, there is no need for a fine wiring process in the manufacturing process of the solid-state imaging device 120, so the manufacturing cost can be reduced. In addition, the manufacturing process of the logic circuit 122 can reduce power consumption by using the most advanced fine wiring process. Furthermore, the theoretical yield of the memory circuit 121 and the logic circuit 122 can be increased. As a result, the cost associated with the manufacturing of the solid-state imaging device 111 can be reduced.

Furthermore, since the chips can be rearranged and bonded to the wafer, even if there are different types of processes that are difficult to manufacture in the same wafer, such as power ICs, clock analog circuits, and logic circuits 122, which are constructed by completely different processes, or the wafer sizes are different, they can be stacked on one chip.

In addition, the above description uses the memory circuit 121 and the logic circuit 122 as an example of a circuit connected to the solid-state imaging device 120, but as long as it is a signal processing circuit required for the operation of the solid-state imaging device 120, such as a circuit related to the control of the solid-state imaging device 120 and a circuit related to the processing of the captured pixel signal, a circuit other than the memory circuit 121 and the logic circuit 122 may be used. As the signal processing circuit required for the operation of the solid-state imaging device 120, for example, it may be a power supply circuit, an image signal compression circuit, a clock circuit, and an optical communication conversion circuit.

<<3. Second embodiment>> The above describes the solid-state imaging device 111 having a two-layer structure, which is a layer in which the solid-state imaging element 120 is stacked, and a layer in which the memory circuit 121 and the logic circuit 122 are further arranged.

However, in a CoC (Chip On Chip) in which a plurality of chips are mounted on one chip in the above-described manner (a CoC in which two chips including a memory circuit 121 and a logic circuit 122 are mounted on a chip of a solid-state imaging device 120), as shown in FIG. 10, wiring (hereinafter also referred to as interconnect wiring) for connecting the two chips including the memory circuit 121 and the logic circuit 122 arranged on a plane must be formed on the surface of a semiconductor device (solid-state imaging device 120) of a larger size.

Fig. 10 is a side cross-sectional view of the solid-state imaging device 111 showing in more detail the internal terminals or wirings of the solid-state imaging element (CIS) 120, the memory circuit 121, and the logic circuit 122 constituting the solid-state imaging device 111 shown in Fig. 5. In the following, the oxide film bonding layer 135 may be omitted for convenience of explanation.

As shown in FIG10 , at the joint surface F1 facing the solid-state imaging device 120 and the memory circuit 121, the pads 120b and 121b electrically connected to the wirings 120a and 121a are mutually CuCu-jointed. Similarly, at the joint surface F1 facing the solid-state imaging device 120 and the logic circuit 122, the pads 120b and 122b electrically connected to the wirings 120a and 122a are mutually CuCu-jointed.

Furthermore, each pad 120b of the solid-state imaging device 120 is connected to various circuits, wiring 120a, or other pads 120b via wiring 120c. Furthermore, pads 121b of the memory circuit 121 are connected to wiring 121a via wiring 121c. Furthermore, pads 122b of the logic circuit 122 are connected to wiring 122a via wiring 122c.

Furthermore, the wiring 134 in FIG. 5 is a structure in which the wiring 120c, the pads 120b and 121b, and the wiring 121c are integrated.

In addition, for the structures that need to be specially distinguished for each of the wirings 120a, 121a, 122a, the pads 120b, 121b, 122b, and the wirings 120c, 121c, 122c, "-" is added to the end of each symbol and a separate symbol is added.

That is, the pads 122b-1 and 122b-2 of the logic circuit 122 and the pads 120b-1 and 120b-2 of the solid-state imaging element 120 are CuCu-bonded, and the pads 121b-2 and 121b-1 of the memory circuit 121 and the pads 120b-3 and 120b-4 of the solid-state imaging element 120 are CuCu-bonded.

Furthermore, the pad 120b-1 of the solid-state imaging device 120 is connected to the wiring 120c-1. Furthermore, the pads 120b-2 and 120b-3 are connected to each other via the wiring 120c-2. Furthermore, the pad 120c-4 is connected to the wiring 120c-3.

With this configuration, the solid-state imaging device 120 and the memory circuit 121 are electrically connected via the wiring 120c-2.

The memory circuit 121 and the logic circuit 122 are connected via the wiring 120c-2 in the solid-state imaging device 120 having the largest chip area.

That is, in FIG. 10 , the wiring 120 c - 2 functions as an interconnection wiring between the memory circuit 121 and the logic circuit 122 .

Here, referring to FIG. 11 , the wiring structure is described with reference to the configuration of the pads 120b-1 to 120b-4 of the solid-state imaging element 120, wirings 120c-1 to 120c-3, wirings 121a-1, 121a-2, pads 121b-1, 121b-2, and wirings 121c-1, 121c-2 of the memory circuit 121, and wirings 122a-1, 122a-2, pads 122b-1, 122b-2, and wirings 122c-1, 122c-2 of the logic circuit 122, with the wirings 120c-2 selected as the interconnect wiring.

As shown in FIG. 11 , when the wiring 120c-2 functions as an interconnection wiring of the memory circuit 121 and the logic circuit 122, the memory circuit 121 and the logic circuit 122 are electrically connected via the wiring (solder pad) 121a-2, the wiring 121c-2, the solder pads 121b-2 and 120b-3, the wiring 120c-2, the solder pads 120b-2 and 122b-2, the wiring 122c-2, and the wiring (solder pad) 122a-2.

If such a wiring structure is adopted, the number of steps for forming interconnecting wiring increases in the manufacturing process of the solid-state imaging device 120, resulting in a yield loss corresponding to the increase in steps. In addition, since the memory circuit 121 and the logic circuit 122 pass through the wiring 120c-2 of the solid-state imaging device 120, the signal line distance increases due to layout restrictions, or becomes a collective wiring, thereby increasing power consumption.

Therefore, in the solid-state imaging device 111 in the configuration example of the second embodiment of the present invention, as shown in FIG. 12, interconnection wiring connecting the memory circuit 121 and the logic circuit 122 is formed in the semiconductor element layer E2 in which the memory circuit 121 and the logic circuit 122 are formed, and the pads 121b and 122b are electrically connected to each other.

That is, the solid-state imaging device 111 of FIG. 12 is different from the solid-state imaging device 111 of FIG. 10 in the following aspects: the structure of the semiconductor element layer E2 is different.

Among them, the pads 120b-11 to 120b-14 and the wirings 120c-11 and 120c-14 of the solid-state imaging element 120 in FIG. 12 correspond to the pads 120b-1 to 120b-4 and the wirings 120c-1 and 120c-3 of the solid-state imaging element 120 in FIG. 10 , respectively.

10 . In addition, the wirings 121a-11, 121a-12, the pads 121b-11, 121b-12, and the wirings 121c-11, 121c-12 of the memory circuit 121 of FIG. 12 correspond to the wirings 121a-1, 121a-2, the pads 121b-1, 121b-2, and the wirings 121c-1, 121c-2 of the memory circuit 121 of FIG. 10 , respectively.

Furthermore, the wirings 122a-11, 122a-12, pads 122b-11, 122b-12, and wirings 122c-11, 122c-12 of the logic circuit 122 of FIG. 12 correspond to the wirings 122a-1, 122a-2, pads 122b-1, 122b-2, and wirings 122c-1, 122c-2 of the logic circuit 122 of FIG. 10 , respectively.

That is, in the semiconductor device layer E2 of FIG. 12 , a wiring layer is formed between the memory circuit 121 and the logic circuit 122 and the pads 121b and 122b, and wirings 121c′-1 and 122c′-1 obtained by expanding the wirings 121c and 122c are formed.

Furthermore, in the same wiring layer where the wirings 121c'-1 and 122c'-1 are formed, an interconnection wiring T is formed to connect the wiring 121c-12 of the memory circuit 121 and the wiring 122c-12 of the logic circuit 122.

Furthermore, as shown in FIG. 13 , the memory circuit 121 and the logic circuit 122 may be directly electrically connected via the interconnection wiring T without passing through the wiring 120 c of the solid-state imaging device 120 .

That is, as shown in the dotted line range Z1 of FIG. 13 , there is no need to form interconnection wirings or other wiring sets for forming interconnection wirings in the solid-state imaging device 120 , so that the increase in the process of the solid-state imaging device 120 can be suppressed, thereby improving the yield.

In addition, the increase in the distance of the wiring path can be suppressed, thereby suppressing the increase in power consumption.

Furthermore, since the total area of the memory circuit 121 and the logic circuit 122 is smaller than that of the solid-state imaging device 120, by utilizing the empty space, for example, as shown in FIG. 12 , the wiring spacing of 121c′-1 and 122c′-1 can be expanded to correspond to the area of the solid-state imaging device 120.

As a result, the wiring spacing within the dotted line range Z2 of FIG. 13 is enlarged, thereby reducing the impact of defects, thereby improving the yield and reducing power consumption.

<Manufacturing method of the solid-state imaging device of FIG. 12> Next, referring to the flow chart of FIG. 14 and the side cross-sectional views of FIG. 15 to FIG. 22, the manufacturing method of the solid-state imaging device 111 of FIG. 12 is described.

First, a method for manufacturing the logic circuit 122 will be described.

In the process (Logic_FEOL) of step S11, for example, in the wafer 104 of FIG. 4, a wiring pattern is formed on the substrate of each logic circuit 122 by FEOL (Front-End-Of-Line: substrate process).

In the process (Logic_BEOL) of step S12, wiring is formed along the wiring pattern on the substrate of the logic circuit 122 by using a metal including Al or Cu, etc., through BEOL (Back-End-Of-Line: wiring process).

In the process of step S13 (Logic_Inspection (KGD (Known Good Die))), as shown in the side cross-sectional view 15A of Figure 15, the wiring (pad) 122c of the logic circuit 122 is inspected using the measuring terminal C, and the logic circuit 122 is screened as a good product based on the inspection result.

In the process of step S14 (pad embedding), as shown in the side cross-sectional view 15B of FIG. 15 , the wiring (pad) 122c of the logic circuit 122 is embedded with an oxide Si film 122L by plasma CVD (Chemical Vapor Deposition).

In the process of step S15 (buried planarization), as shown in the side cross-sectional view 15C of FIG. 15 , the buried step LD (see the side cross-sectional view 15B ) formed of the Si oxide film 122L of the logic circuit 122 is polished and planarized by CMP (Chemical Mechanical Polishing).

In the process (Logic Dicing) of step S16, the logic circuit 122 in the wafer 104 is singulated by dicing, and good products are selected.

In the above manner, the logic circuit 122 is manufactured through the process of steps S11 to S16.

Next, a method for manufacturing the memory circuit 121 will be described.

In the process (Memory_FEOL) of step S21, for example, in the wafer 103 of FIG. 4, a wiring pattern is formed on the substrate of each memory circuit 121 by FEOL (Front-End-Of-Line: substrate process).

In the process (memory_BEOL) of step S22, wiring is formed along the wiring pattern on the substrate of the memory circuit 121 by using a metal including Al or Cu, etc., through BEOL (Back-End-Of-Line: wiring process).

In the process of step S23 (memory_inspection (KGD: Known Good Die)), as shown in the side sectional view 16A of FIG. 16, the wiring (pad) 121c of the memory circuit 121 is inspected using the measuring terminal C, and the memory circuit 121 is screened as a good product based on the inspection result.

In the process (bonding pad embedding) of step S24, as shown in the side cross-sectional view 16B of FIG. 16, the wiring (bonding pad) 121c of the memory circuit 121 is embedded with an oxide Si film 121M by plasma CVD (Chemical Vapor Deposition).

In the process (buried planarization) of step S25, as shown in the side cross-sectional view 16C of FIG. 16, the buried step MD (see the side cross-sectional view 16B) of the memory circuit 121 formed of the Si oxide film 121M is polished and planarized by CMP (Chemical Mechanical Polishing).

In the process (memory_dividing) of step S26, the memory circuit 121 in the wafer 103 is singulated by dicing, and good products are selected.

In the above manner, the memory circuit 121 is manufactured through the process of steps S21 to S26.

Next, the process of re-arranging the manufactured memory circuit 121 and logic circuit 122 on the re-arrangement substrate 151 will be described.

In the process of step S31 (memory_die CoW), as shown in the side cross-sectional view 17A of FIG. 17 , a Si oxide film for bonding is formed on the reconfiguration substrate 151 by the CVD method, and the memory circuit 121 is temporarily connected to the reconfiguration substrate 151 in such a manner that the surface provided with the wiring (pad) 121c abuts against the reconfiguration substrate 151 (face down). The connection method for the temporary connection is oxide film bonding such as plasma bonding, etc.

In addition, the temporary connection may be a method other than oxide film bonding such as plasma bonding, for example, a commercially available temporary bonding tape may be used. Furthermore, by pre-forming a CoW alignment mark on the reconfiguration substrate 151 side, the connection quality can be improved.

In the process of step S32 (Logic_Chip CoW), as shown in the side cross-sectional view 17B of Figure 17, the logic circuit 122 is temporarily connected to the reconfiguration substrate 151 in a manner (face down) in which the surface provided with the wiring (pad) 122c is abutted against the reconfiguration substrate 151.

In the process of step S33 (grain embedding), as shown in the side cross-sectional view 17C of Figure 17, the gaps (part) between the memory circuit 121 and the logic circuit 122 are filled with an oxide film 133 by plasma CVD method and singulated, so that the obtained memory circuit 121 and logic circuit 122 are fixed to the reconfiguration substrate 151.

In the process of step S34 (crystal thinning), as shown in the side cross-sectional view 18A of Fig. 18, the Si substrate of the singulated memory circuit 121 and the logic circuit 122 is thinned. More specifically, CMP is performed to improve the surface quality by grinding at high speed using a grinder.

In the process of step S35 (grain embedding), as shown in the side cross-sectional view 18B of Figure 18, in order to fill the gap between the thinned memory circuit 121 and the logic circuit 122, an oxide film 133 is formed again by plasma CVD method or the like until the step is embedded.

In the process of step S36 (buried surface CMP), as shown in the side cross-sectional view 18C of FIG18, the step KD formed on the surface of the memory circuit 121 and the logic circuit 122 is flattened by the CMP method. At this time, the Si film thickness of the memory circuit 121 and the logic circuit 122 is controlled to be about 1 μm to 10 μm for finishing.

Through the processing up to this point, the memory circuit 121 and the logic circuit 122 are reconfigured on the reconfiguration substrate 151 and are buried by the oxide film 133.

Next, the process of forming the memory circuit 121 and the logic circuit 122 reconfigured on the reconfiguration substrate 151 on the support substrate 132 will be described.

In the process of step S41 (permanent bonding WoW), as shown in the side cross-sectional view 19A of Figure 19, the support substrate 132 formed with an oxide Si film is permanently bonded to the memory circuit 121 and the logic circuit 122 reconfigured on the reconfiguration substrate 151 by plasma bonding.

In the process of step S42 (relocation substrate debonding), as shown in the side cross-sectional view 19B of FIG. 19 , the relocation substrate 151 is debonded and peeled off.

In the process of step S43 (interconnection wiring formation), as shown in the side cross-sectional view 20B of Fig. 20, an oxide film 133 is further laminated. Then, as shown in the side cross-sectional view 20C of Fig. 20, an interconnection wiring T connecting the memory circuit 121 and the logic circuit 122 is formed.

In the process of step S44 (Cu-Cu connecting wiring (etc.) formation), as shown in the side cross-sectional view 20C of FIG. 20 , pads 121 b and 122 b for electrical connection with the solid-state imaging element 120 are formed.

Furthermore, regarding the interconnection wiring T, a plurality of interconnections T1 to T5 may be formed corresponding to the spacing between the pads 121b and 122b as shown in Fig. 21. Also, interconnections T3 to T5 may be formed beyond the arrangement area of the memory circuit 121 and the logic circuit 122.

Furthermore, the pads 121b and 122b may also be formed on the grid in the area of the solid-state imaging device 120 to be laminated later. Also, the interconnection wiring may be connected to other circuits other than the memory circuit 121 and the logic circuit 122 as indicated by the interconnection wiring T6, so that the memory circuit 121 or the logic circuit 122 is connected to other circuits respectively.

21 is a top view of the support substrate 132, and the bottom view is a side view. In addition, the dotted line range in the top view of FIG. 21 is the range of the solid-state imaging element 120 for the deposition layer.

After the wafer on which the memory circuit 121 and the logic circuit 122 are reconfigured is formed through the above steps, the memory circuit 121 and the logic circuit 122 are connected by interconnection wiring T, and further, pads 121 b and 122 b for connecting to the solid-state imaging device 120 are formed.

Next, the manufacturing of the solid-state imaging device 120 is described.

In the process (CIS_FEOL) of step S51, for example, in the wafer 101 of FIG. 4, a wiring pattern is formed on the substrate of each solid-state imaging element 120 by FEOL (Front-End-Of-Line: substrate process).

In the process (CIS_BEOL) of step S52, wiring is formed along the wiring pattern on the substrate of the solid-state imaging device 120 by means of a metal including Al or Cu, etc., through BEOL (Back-End-Of-Line: wiring process).

In the process of step S53 (embedded planarization), although not shown in the figure, the pad 120b of the solid-state imaging element 120 is embedded with an oxide Si film by plasma CVD (Chemical Vapor Deposition), and the embedded step formed by the oxide Si film is polished and planarized by CMP (Chemical Mechanical Polishing).

In the process of step S54 (Cu-Cu connecting wiring (etc.) formation), as shown in the side cross-sectional view 22A of FIG. 22 , a pad 120 b for electrical connection to the solid-state imaging element 120 is formed, thereby completing the wafer 101 of the solid-state imaging element 120 .

In the above manner, the solid-state imaging device 120 is manufactured through the process of steps S51 to S54.

Next, a process of manufacturing the solid-state imaging device 111 by bonding the wafer 102 on which the memory circuit 121 and the logic circuit 122 are reconfigured and on which interconnection wirings T are formed to the wafer 101 on which the solid-state imaging element 120 is formed will be described.

In the process of step S61 (permanent (Cu-Cu bonding WoW)), as shown in the side cross-sectional view 22B of Figure 22, the pad 120b of the solid-state imaging element 120 is CuCu bonded (directly bonded) to the pad 121b of the memory circuit and the pad 122b of the logic circuit 122.

In the process of step S62 (back CIS process), as shown in the side cross-sectional view 22C of Figure 22, after the solid-state imaging element 120 is thinned and a protective film is formed, as shown in the side cross-sectional view 22D of Figure 22, a color filter and a crystal-carrying lens 131 are formed.

Through the above series of steps, the solid-state imaging device 111 of FIG. 12 is manufactured, in which the interconnection wiring of the memory circuit 121 and the logic circuit 122 is formed without using the solid-state imaging element 120.

As a result, there is no need to form interconnection wiring passing through the solid-state imaging device 120, so the increase in the number of steps in the manufacture of the solid-state imaging device 120 can be suppressed, and the yield can be improved.

Furthermore, since the degree of freedom in routing the wiring is improved, the wiring length can be shortened or the wiring can be increased, thereby achieving power stabilization or low power consumption.

Furthermore, the degree of freedom in forming a light-shielding film for coping with hot carriers is improved.

Furthermore, since interconnection wiring can be routed within a range larger than the area of the solid-state imaging device 120, the wiring pitch can be increased, thereby suppressing a decrease in yield.

Furthermore, since there is no need to aggregate wiring, the wiring density can be reduced, thereby reducing resistance and thus reducing power consumption.

＜＜4. Application examples of the second embodiment＞＞ The above describes an example in which the interconnection wiring T of the memory circuit 121 and the logic circuit 122 is formed on the boundary side with the solid-state imaging device 120 in the semiconductor device layer E2, but other ranges are also possible as long as the memory circuit 121 and the logic circuit 122 can be connected.

For example, interconnection wiring may also be disposed on the interface between the semiconductor device layer E2 and the supporting substrate 132.

FIG. 23 shows a solid-state imaging device 111 having interconnection wiring T' formed on the boundary side with the support substrate 132 in the semiconductor element layer E2.

In the case of the solid-state imaging device 111 of FIG. 23, the same effect as that of the solid-state imaging device 111 of FIG. 12 in which the interconnection wiring T is formed can be obtained.

23, the interconnection wiring T' is formed at the boundary side of the memory circuit 121 and the logic circuit 122 with the support substrate 132. Other than this, it is the same as the solid-state imaging device 111 in FIG. 12, so the description of the manufacturing method is omitted.

<<5. Third Implementation Form>> As described above, the connection between the solid-state imaging element 120 and the memory circuit 121 and the logic circuit 122 is performed between the wirings where the pad 120b to be connected is CuCu-bonded with the pads 121b and 122b on the bonding surface F2.

However, the solid-state imaging device 120, the memory circuit 121, and the logic circuit 122 only need to be electrically connected, and thus they may be connected by other methods.

The electrical connection between the solid-state imaging device 120 and the memory circuit 121 and the logic circuit 122 may be achieved through, for example, a through chip via (TCV).

That is, in the solid-state imaging device 111 of Fig. 24, the solid-state imaging element 120 and the memory circuit 121 are connected via the through electrode TCV1, and the solid-state imaging element 120 and the logic circuit 122 are connected via the through electrode TCV2. The through electrodes TCV1 and TCV2 contain Cu, and an insulating film is formed on the surface thereof.

More specifically, a pad 121b connected to the through electrode TCV1 is provided on the memory circuit 121, and a pad 122b connected to the through electrode TCV2 is provided on the logic circuit 122.

Furthermore, the pads 121b of the memory circuit 121 and the pads 122b of the logic circuit 122 are formed when the interconnection wiring T is formed.

By adopting such a structure, the steps of forming the pads 120b in the solid-state imaging element 120, the pads 121b in the memory circuit 121, and the pads 122b in the logic circuit 122 can be omitted, thereby improving the yield.

Furthermore, wiring can be arranged in the space provided for the pad 120b of the solid-state imaging element 120, the pad 121b of the memory circuit 121, and the pad 122b of the logic circuit 122, thereby reducing the impedance caused by wiring and reducing power consumption.

<Manufacturing method of the solid-state imaging device of FIG. 24> Next, referring to the flow chart of FIG. 25, the manufacturing method of the solid-state imaging device 111 of FIG. 24 is described.

25, the manufacturing processes for the memory circuit 121, the logic circuit 122, and the reconfiguration substrate 151 in the flowchart of FIG. 14 are the same and thus omitted.

In addition, regarding the steps S71, S72, S81 to S83, S91, and S93 of Figure 25, since they are the same as the steps S41, S42, S51 to S53, S61, and S62 described with reference to Figure 14, their description is omitted.

That is, in the flowchart of Fig. 25, in the process of step S73 (interconnection wiring (etc.) formation), the interconnection wiring T is formed. At this time, the pad 121b of the memory circuit 121 and the pad 122b of the logic circuit 122 for connecting to the through electrodes TCV1 and TCV2 are formed at positions corresponding to the through electrodes TCV1 and TCV2.

Furthermore, in the process of step S92 (upper and lower die connection (TCV)), through holes are formed in the Si substrate of the solid-state imaging device 120 at the positions of the through electrodes TCV1 and TCV2 in FIG. 24 and then filled with Cu to form electrodes.

Through this process, the solid-state imaging device 111 of Figure 24 is manufactured.

Furthermore, since wiring can be arranged in the space provided for the pads 120b of the solid-state imaging element 120, the pads 121b of the memory circuit 121, and the pads 122b of the logic circuit 122, the impedance caused by wiring can be reduced, thereby reducing power consumption.

＜＜6. Fourth Implementation Form＞＞ The above describes an example in which the bonding surface F2 is formed in a state where the wiring layer side of the memory circuit 121 and the logic circuit 122 is opposite to the wiring layer side of the solid-state imaging device 120. However, it is also possible to form a through electrode on the surface of the memory circuit 121 and the logic circuit 122 opposite to the wiring layer (the surface on the Si substrate side) and bond to the solid-state imaging device 120.

FIG. 26 shows a solid-state imaging device 111. In the solid-state imaging device 111, through-silicon vias (TSVs) are formed on the surfaces of the memory circuit 121 and the logic circuit 122 opposite to the wiring layer to connect the memory circuit 121 and the logic circuit 122 to the solid-state imaging element 120.

That is, in the solid-state imaging device 111 of FIG. 26 , the differences from the solid-state imaging device 111 of FIG. 12 are as follows: the memory circuit 121 and the logic circuit 122 are formed into a structure in which the top and bottom in the figure are reversed, through electrodes 121d and 122d are respectively formed on the back side (the Si substrate side which becomes the upper surface of FIG. 26 ), and the wirings 121c' and 122c' are connected to the pads 121b and 122b via the through electrodes (TSV).

With this structure, the same effect as the solid-state imaging device 111 in the first embodiment can be achieved.

<Manufacturing method of the solid-state imaging device of FIG. 26> Next, referring to the flow chart of FIG. 27 and the side cross-sectional views of FIG. 28 to FIG. 32, the manufacturing method of the solid-state imaging device 111 of FIG. 26 is described.

Furthermore, in the flowchart of FIG. 27 , the manufacturing process of the memory circuit 121 and the logic circuit 122 is the same as steps S11 to S16 and steps S21 to S26 in the flowchart of FIG. 14 , and thus the description thereof is omitted.

In addition, since the manufacturing process of the solid-state imaging device 120, i.e., the process from step S111 to step S114, is the same as the process from step S51 to step S54 in FIG. 14, the description thereof is omitted.

Furthermore, since the redistribution substrate 151 is not used as described below, there are no steps in the redistribution substrate 151.

That is, in the process of step S101 (memory_grain CoW), as shown in the side cross-sectional view 28A of FIG28, a Si oxide film for bonding is formed on the support substrate 132 by the CVD method, and the memory circuit 121 is connected to the support substrate 132 in such a manner that the surface provided with the wiring (pad) 121c abuts against the support substrate 132 (face down). The connection method is oxide film bonding such as plasma bonding, etc.

Furthermore, the connection may be made by a method other than oxide film bonding such as plasma bonding, for example, a commercially available temporary bonding tape may be used. Furthermore, by forming a CoW alignment mark in advance on the supporting substrate 132 side, the connection quality may be improved.

In the process of step S102 (Logic_Chip CoW), as shown in the side cross-sectional view 28B of Figure 28, the logic circuit 122 is connected to the supporting substrate 132 in a manner such that the surface provided with the wiring 122c abuts against the supporting substrate 132 (face down).

In the process of step S103 (grain thinning), as shown in the side cross-sectional view 28C of Figure 28, the gaps (part) between the memory circuit 121 and the logic circuit 122 are filled with an oxide film 133 by the plasma CVD method and singulated, so that the obtained memory circuit 121 and logic circuit 122 are fixed to the supporting substrate 132.

29A, the wall thickness of the Si substrate of the singulated memory circuit 121 and the logic circuit 122 is thinned. More specifically, CMP is performed to improve the surface quality by grinding at high speed using a grinder.

In the process of step S104 (grain embedding), as shown in the side cross-sectional view 29B of Figure 29, in order to fill the gap between the thinned memory circuit 121 and the logic circuit 122, an oxide film 133 is formed again by plasma CVD method or the like until the step is embedded.

Furthermore, as shown in the side cross-sectional view 29C of Fig. 29, the step KD formed on the surface of the memory circuit 121 and the logic circuit 122 is flattened by the CMP method. At this time, the Si film thickness of the memory circuit 121 and the logic circuit 122 is controlled to be about 1 μm to 10 μm for finishing.

Through the processing up to this point, the memory circuit 121 and the logic circuit 122 are re-arranged on the supporting substrate 132 and are buried by the oxide film 133.

In the process of step S105 (rewiring & pad formation), plasma SiO ₂ is formed to a thickness of about 100 nm to 1500 nm in order to insulate the Si film of the memory circuit 121 and the logic circuit 122 after CMP.

Next, as shown in the side cross-sectional view 30A of FIG. 30 , grooves 121e, 122e, Te corresponding to the wirings connecting the memory circuit 121 and the logic circuit 122 are formed by resist patterning and oxide film dry etching.

At this time, the grooves 121e, 122e, and Te are formed to a depth that does not reach Si of the memory circuit 121 and the logic circuit 122.

Furthermore, as shown in the side cross-sectional view 30A of FIG. 30 , the grooves 121e and 122e formed above are opened to a depth just before reaching the copper wiring at the bottom layer of the multi-layer wiring layer, or to a depth just before reaching the Al pad at the top layer, thereby forming through holes 121f and 122f. The diameter of the through holes 121f and 122f is, for example, about 1 μm to 5 μm.

Furthermore, the side walls of Si exposed by the above processing are etched back after forming an insulating film including SiO ₂ , thereby removing the SiO ₂ formed as a protective film at the bottom of the through holes 121f and 122f, and exposing the wiring layers of the memory circuit 121 and the logic circuit 122.

Next, as shown in the side cross-sectional view 30B of FIG. 30 , after the barrier metal is formed, a metal such as Cu is embedded into the through holes 121f and 122f, and the surface is polished by CMP (Chemical Mechanical Polishing) method, leaving only the grooves 121e, 122e, Te and the conductive material of the through holes 121f and 122f.

Thus, in the region within the insulating spacer layer, an interconnection wiring T connecting the memory circuit 121 and the logic circuit 122 and lead wirings 121c' and 122c' from the through electrodes 121d and 122d of the memory circuit 121 and the logic circuit 122 are formed.

Furthermore, as shown in the side cross-sectional view 30C of FIG. 30 , pads 121 b and 122 b for CuCu (hybrid) bonding with the solid-state imaging element 120 are formed.

Furthermore, regarding the interconnection wiring T, a plurality of interconnections T may be formed corresponding to the spacing between the pads 121b and 122b, as shown by the interconnection wirings T1 to T5 in FIG. 31. Also, as shown by the interconnection wirings T3 to T5, they may be formed within the arrangement area of the solid-state imaging element 120 and beyond the arrangement area of the memory circuit 121 and the logic circuit 122.

Furthermore, the pads 121b and 122b may also be formed on the grid in the area of the solid-state imaging device 120 to be laminated later. Also, the interconnection wiring may be connected to other circuits other than the memory circuit 121 and the logic circuit 122 as indicated by the interconnection wiring T6, so that the memory circuit 121 or the logic circuit 122 is connected to other circuits respectively.

31 is a top view of the support substrate 132, and the bottom view is a side view. In addition, the dotted line range in the top view of FIG31 is the range of the solid-state imaging element 120 for the deposition layer.

After the wafer on which the memory circuit 121 and the logic circuit 122 are reconfigured is formed through the above steps, the memory circuit 121 and the logic circuit 122 are connected by interconnection wiring T, and further, pads 121 b and 122 b for connecting to the solid-state imaging device 120 are formed.

Furthermore, in the process from step S111 to step S114 (formation of Cu-Cu connecting wiring (etc.)), as shown in the side cross-sectional view 32A of Figure 32, a pad 120b is formed for electrical connection with the pads 121b and 122b of the memory circuit 121 and the logic circuit 122, thereby completing the wafer 101 of the solid-state imaging element 120.

Next, in the process of step S115 (permanent (Cu-Cu bonding WoW)), as shown in the side cross-sectional view 32B of Figure 32, the pad 120b of the solid-state imaging element 120 is CuCu bonded (directly bonded) with the pad 121b of the memory circuit and the pad 122b of the logic circuit 122.

In the process of step S116 (back CIS process), as shown in the side cross-sectional view 32C of Figure 32, after the solid-state imaging element 120 is thinned and a protective film is formed, as shown in the side cross-sectional view 32D of Figure 32, a color filter and a crystal-mounted lens 130 are formed.

Through the above series of steps, the solid-state imaging device 111 of FIG. 26 is manufactured, in which the interconnection wiring of the memory circuit 121 and the logic circuit 122 is formed without using the solid-state imaging element 120.

As a result, there is no need to form interconnection wiring passing through the solid-state imaging device 120, so the increase in the number of steps in the manufacture of the solid-state imaging device 120 can be suppressed and the occurrence of defects can be reduced.

Furthermore, since the degree of freedom in routing the wiring is improved, the wiring length can be shortened or the wiring can be increased, thereby achieving stabilization of the power supply or reduction of power consumption.

Furthermore, the degree of freedom in forming a light-shielding film for coping with hot carriers is improved.

Furthermore, since interconnection wiring can be routed within a range larger than the area of the solid-state imaging device 120, the wiring pitch can be increased, thereby suppressing a decrease in yield.

Furthermore, since there is no need to aggregate wiring, the wiring density is reduced, thereby reducing resistance and thus reducing power consumption.

＜＜7. Fifth Implementation Form＞＞ The above describes an example in which wiring layers are formed on the memory circuit 121, the logic circuit 122, and the solid-state imaging element 120, respectively, and the bonding surface F2 is formed in a state in which they are respectively opposed to each other. However, a wiring layer may also be formed on the supporting substrate 132, and interconnection wiring between the memory circuit 121 and the logic circuit 122 may be formed on the wiring layer on the supporting substrate 132.

FIG33 shows an example of the configuration of a solid-state imaging device 111. In the solid-state imaging device 111, a wiring layer is also formed on a supporting substrate 132, and interconnections between a memory circuit 121 and a logic circuit 122 are formed via the wiring layer on the supporting substrate 132.

That is, in the solid-state imaging device 111 of FIG. 33 , the structure that is different from the solid-state imaging device 111 of FIG. 26 is as follows: the solid-state imaging element 120 is electrically connected to the memory circuit 121 and the logic circuit 122 at the joint surface F4-1, and the memory circuit 121 and the logic circuit 122 are electrically connected to the supporting substrate at the joint surface F4-2.

In the memory circuit 121 and the logic circuit 122, pads 121b' and 122b' on the surface facing the support substrate 132 are formed at positions corresponding to pads 132b forming a wiring layer of the support substrate 132.

In addition, in the supporting substrate 132, a pad 132b is formed at a position opposite to the memory circuit 121 and the logic circuit 122, and further, a wiring 132a and an interconnection wiring T'' between the memory circuit 121 and the logic circuit 122 are formed at the lower portion in FIG. 33.

The wiring 132a can also be used for electrical connection and can also be used for positioning by serving as an alignment mark.

The pad 132 b of the support substrate 132 is CuCu-connected to the pad 121 b ′ of the memory circuit 121 and the pad 122 b ′ of the logic circuit 122 .

In the solid-state imaging device 111 of FIG. 33 , an example is shown in which the interconnection wirings of the memory circuit 121 and the logic circuit 122 include two interconnection wirings T and T″, but only one of them may be provided.

With the above configuration, there is no need to form interconnection wiring through the solid-state imaging device 120, thereby suppressing the increase in process steps, and there is no need to integrate the wiring within the solid-state imaging device 120, so the wiring density is reduced, thereby reducing the occurrence of defects. In addition, for the same reason, the resistance can be reduced, thereby reducing power consumption.

<Manufacturing method of the solid-state imaging device of FIG. 33> Next, referring to the flow chart of FIG. 34 and the side cross-sectional views of FIG. 35 to FIG. 38, the manufacturing method of the solid-state imaging device 111 of FIG. 33 is described.

Furthermore, in the flowchart of FIG. 34 , the manufacturing process of the memory circuit 121 and the logic circuit 122 is the same as steps S11 to S16 and steps S21 to S26 in the flowchart of FIG. 14 except for steps S126 and S136, so their description is omitted.

In addition, since the process of supporting the substrate 132, i.e., the process of steps S142 to S147, is the same as the process of steps S101 to S106 in Figure 27, its description is omitted.

Furthermore, the manufacturing process of the solid-state imaging device 120, i.e., steps S151 to S154, is the same as the steps S51 to S54 in FIG. 14, and thus the description thereof is omitted.

That is, in the process of step S126 (Cu-Cu connection pad formation), for the logic circuit 122 manufactured on the wafer 104 as shown in the side cross-sectional view 35A of Figure 35, a pad 122b' for CuCu bonding with the pad 132b of the supporting substrate 132 is formed as shown in the side cross-sectional view 35B of Figure 35.

The pad 122b' is formed by the same method as the through electrode 122d, wiring 122c', and pad 122b' in the solid-state imaging device 111 of FIG26 in the process of step S106 described with reference to the flowchart of FIG27. After the pad 121b' is formed, the logic circuit 122 on the wafer 104 is cut and good products are selected.

Furthermore, in step S136, the same method is used to form the bonding pad 121b' in the memory circuit 121, and then the wafer is cut and good products are selected.

Furthermore, in the process of step S141 (interconnection wiring (etc.) formation), as shown in FIG. 36 , wiring 132a, interconnection wiring T″, and pad 132b are formed on supporting substrate 132.

More specifically, a thermal oxide film or LP-SiN is formed on a supporting substrate (bare Si) 132 having no device structure to insulate it from Si.

Next, plasma _SiO2 is formed to a thickness of about 100 nm to 1500 nm, and corresponding to the layout of the pads 121b' and 122b' of the memory circuit 121 and the logic circuit 122, an anti-etching pattern is formed for the wiring pattern with a line spacing width of 0.5 μm to 5 μm for connecting between chips, and a groove with a depth of 100 nm to 1000 nm is formed by dry etching.

After forming a barrier metal of Ta or Ti in the groove portion, copper is embedded by electroplating, and the remaining copper in the field portion is removed by CMP, thereby forming inter-chip connections and wiring 132a from each chip.

Next, by the same method as in the case of forming the through electrode 122d, the wiring 122c', and the pad 122b, the pad 132b for CuCu connection is formed.

Furthermore, at this time, the wiring 132a is used to simultaneously form an alignment mark for chip connection, thereby improving the alignment accuracy when forming the interconnection wiring T'' on the supporting substrate 132.

In the processes of steps S142 and S143 (memory_die CoW, logic_die CoW), as shown in the side cross-sectional view 37A of Figure 37, the pads 121b' and 122b' of the memory circuit 121 and the logic circuit 122 are CuCu-bonded (directly bonded) in a manner that they correspond to the pad 132b and are electrically connected to a supporting substrate 132 formed with interconnect wiring T'', a pad 132b, and wiring 132a serving as an alignment mark.

In the process of step S144 (grain thinning), the gaps (part) between the memory circuit 121 and the logic circuit 122 are filled with an oxide film 133 by plasma CVD method and singulated, so that the obtained memory circuit 121 and logic circuit 122 are fixed to the supporting substrate 132.

Furthermore, the wall thickness of the Si substrate of the singulated memory circuit 121 and the logic circuit 122 is reduced. More specifically, the surface is ground at high speed by a grinder to perform CMP in order to improve the surface quality.

In the process of step S145 (grain embedding), as shown in the side cross-sectional view 37B of Figure 37, in order to fill the gap between the thinned memory circuit 121 and the logic circuit 122, the oxide film 133 is formed again by plasma CVD method etc. until the step is embedded.

Furthermore, the CMP method is used to flatten the step difference formed on the surface of the memory circuit 121 and the logic circuit 122. At this time, the memory circuit 121 and the logic circuit 122 are finished so that the Si film thickness is controlled to be about 1 μm to 10 μm.

In the process (TSV formation) of step S146, plasma SiO ₂ is formed to a thickness of about 100 nm to 1500 nm in order to insulate the Si films of the memory circuit 121 and the logic circuit 122 after CMP.

Next, as shown in the side cross-sectional view 37C of FIG. 37 , grooves 121e, 122e, Te corresponding to the wirings connecting the memory circuit 121 and the logic circuit 122 are formed by resist patterning and oxide film dry etching.

At this time, the grooves 121e, 122e, and Te are formed to a depth that does not reach Si of the memory circuit 121 and the logic circuit 122.

Furthermore, the through holes 121f and 122f are formed by opening from the regions of the grooves 121e and 122e formed above to a depth just before reaching the copper wiring at the bottom of the multi-layer wiring layer, or just before reaching the Al pad at the top layer, so as to penetrate the Si of the memory circuit 121 and the logic circuit 122. The diameter of the through holes 121f and 122f is, for example, about 1 μm to 5 μm.

In the process of step S147 (rewiring & pad formation), as shown in the side cross-sectional view 37D of Figure 37, the side wall of Si exposed by the above processing is etched back after forming an insulating film containing _SiO2 , thereby removing the _SiO2 formed as the protective film at the bottom of the through holes 121f and 122f, and exposing the wiring layers of the memory circuit 121 and the logic circuit 122.

Next, after forming the barrier metal, a metal such as Cu is embedded into the through holes 121f and 122f, and the surface is polished by CMP (Chemical Mechanical Polishing) so that only the grooves 121e and 122e, Te and the conductive material of the through holes 121f and 122f remain.

Thus, in the region within the insulating spacer layer, an interconnection wiring T connecting the memory circuit 121 and the logic circuit 122 and lead wirings 121c' and 122c' from the through electrodes 121d and 122d of the memory circuit 121 and the logic circuit 122 are formed.

Furthermore, pads 121b and 122b for hybrid (Cu-Cu) connection with the solid-state imaging element 120 are formed.

After the wafer on which the memory circuit 121 and the logic circuit 122 are reconfigured is formed through the above steps, the memory circuit 121 and the logic circuit 122 are connected by interconnection wirings T and T″, and further, pads 121b and 122b for connecting to the solid-state imaging element 120 are formed.

Furthermore, in the process from step S151 to step S154 (Cu-Cu connecting wiring (etc.) formation), the bonding pad 120b is formed to complete the wafer 101 of the solid-state imaging element 120.

Next, in the process of step S155 (permanent (Cu-Cu bonding WoW)), as shown in the side cross-sectional view 38A of Figure 38, the pad 120b of the solid-state imaging element 120 is CuCu bonded to the pad 121b of the memory circuit and the pad 122b of the logic circuit 122.

In the process of step S156 (back CIS process), as shown in the side cross-sectional view 32B of Figure 38, after the solid-state imaging element 120 is thinned and a protective film is formed, as shown in the side cross-sectional view 38C of Figure 38, a color filter and a crystal-mounted lens 130 are formed.

Through the above series of steps, the solid-state imaging device 111 of FIG. 33 is manufactured, in which the interconnection wirings T and T″ of the memory circuit 121 and the logic circuit 122 are formed without using the solid-state imaging element 120.

As a result, there is no need to form interconnection wiring passing through the solid-state imaging device 120, so the increase in the number of steps in the manufacture of the solid-state imaging device 120 can be suppressed, and the yield can be improved.

Furthermore, since the degree of freedom in routing the wiring is improved, the wiring length can be shortened or the wiring can be increased, thereby achieving stabilization of the power supply or reduction of power consumption.

Furthermore, the degree of freedom in forming a light-shielding film for coping with hot carriers is improved.

Furthermore, since interconnection wiring can be routed within a range larger than the area of the solid-state imaging device 120, the wiring pitch can be increased, thereby suppressing a decrease in yield.

Furthermore, since there is no need to aggregate wiring, the wiring density is reduced, thereby reducing resistance and thus reducing power consumption.

＜＜8. Sixth Implementation Form＞＞ The above describes a solid-state imaging device 111 in which a memory circuit 121 and a logic circuit 122 are arranged on a supporting substrate 132 having interconnection wiring and a solid-state imaging element 120 is stacked. However, the following configuration may be adopted: a memory element substrate having the function of a memory circuit 121 is replaced with a supporting substrate 132, a logic circuit 122 is stacked thereon, and a solid-state imaging element 120 is stacked on the logic circuit 122.

FIG39 shows a configuration example of a solid-state imaging device 111 in which a memory element substrate having the function of a memory circuit 121 is used instead of a support substrate 132, a logic circuit 122 is stacked thereon, and a solid-state imaging element 120 is stacked on the logic circuit 122.

The structure of the solid-state imaging device 111 of Figure 39 is set as follows: a memory element substrate 201 having the function of a memory circuit 121 is provided instead of the supporting substrate 132, a logic circuit 122 is stacked on the memory element substrate 201 in a manner of being buried by an oxide film 133, and then a solid-state imaging element 120 is stacked on the logic circuit 122.

Furthermore, the solid-state imaging device 120, the logic circuit 122, and the memory device substrate 201 are electrically connected by CuCu bonding of the pad 120b, the pads 201b', and the pads 122b on the bonding surface F5-1.

More specifically, in the oxide film 133 in which the logic circuit 122 is embedded, the pad 201b', the wiring 201c, and the through electrode 201d are formed in a connected state, and the pad 201b and the through electrode 201d of the memory element substrate 201 are connected in the bonding surface F5-2.

Thereby, the memory element 201 and the solid-state imaging element 120 are electrically connected via the pad 201b', the wiring 201c, the through electrode 201d, and the pad 201b.

Furthermore, the logic circuit 122 and the memory device substrate 201 are electrically connected by CuCu bonding of the pads 201b and 122b in the bonding surface F5-2. In other words, the CuCu bonding pads 201b and 122b substantially function as interconnect wiring.

With this structure, the memory device substrate 201 and the logic circuit 122 do not need interconnection wiring by stacking, so it is not necessary to form interconnection wiring via the solid-state imaging device 120, thereby suppressing the increase in process steps.

Furthermore, since there is no need to integrate the wiring in the solid-state imaging device 120, the wiring density is reduced, thereby improving the yield, and the resistance can be reduced, thereby reducing power consumption.

Furthermore, in the solid-state imaging device 111 of FIG. 39 , a configuration example is shown in which a memory element substrate 201 having the function of the memory circuit 121 is provided in place of the support substrate 132, and is laminated in such a manner that the logic circuit 122 is sandwiched between the solid-state imaging element 120. However, a configuration in which a logic element substrate having the function of the logic circuit 122 is provided in place of the support substrate 132, and is laminated in such a manner that the memory circuit 121 is sandwiched between the solid-state imaging element 120 may be used.

<Manufacturing method of the solid-state imaging device of FIG. 39> Next, referring to the flow chart of FIG. 40 and the side cross-sectional views of FIG. 41 to FIG. 43, the manufacturing method of the solid-state imaging device 111 of FIG. 39 is described.

Furthermore, in the flowchart of FIG40, the manufacturing process of the logic circuit 122 is the same as steps S121 to S127 in the flowchart of FIG34, so the description thereof is omitted. Also, the manufacturing process of the solid-state imaging device 120, i.e., steps S191 to S194, is the same as steps S51 to S54 in the flowchart of FIG14, so the description thereof is omitted.

In the processes of steps S171 and S172 (memory_FEOL, memory_BEOL), similarly to the processes of steps S21 and S22 in FIG. 14 , a wiring pattern for realizing the function of the memory circuit 121 is formed in the memory element substrate 201, and the wiring is formed by a metal including Al or Cu.

Furthermore, after the process (memory_BEOL) of step S172, an inspection may be performed to identify good dies and bad dies in advance.

In the process of step S173 (rewiring & Cu-Cu connection pad formation), wiring 201a and pad 201b are formed. Here, alignment marks for connection are also formed.

In the process of step S174 (logic_chip CoW), as shown in the side cross-sectional view 41A of FIG41, the pad 201b of the memory element substrate 201 is CuCu bonded to the pad 122b' of the logic circuit 122. Furthermore, in FIG41, an example of connecting only the logic circuit 122 is described, but a plurality of circuit chips may be connected in accordance with the function.

In the process (crystal thinning) of step S175, the logic circuit 122 is thinned after being fixed on the memory device substrate 201 by filling the oxide film 133 around the logic circuit 122 on the memory device substrate 201.

In the process of step S176 (grain embedding), as shown in the side cross-sectional view 41B of FIG. 41 , the process of step S175 is repeated, thereby embedding the logic circuit 122 into the oxide film 133 .

In the processes of steps S177 and S178 (TSV formation, memory connection through hole formation), as shown in the side cross-sectional views 42A to 42C of Figure 42, a Si through electrode 122d that penetrates the logic circuit 122 and a through electrode 201d for connecting to the memory element substrate 201 are formed.

In more detail, as shown in the side cross-sectional view 42A of FIG. 42, in order to insulate Si after CMP, an insulating film 221 including plasma _SiO2 is formed to be 100 nm to 1500 nm. Then, by resist patterning and oxide film dry etching, a pad 201b', a wiring 201c, and a region formed by a through electrode 201d for connecting the memory element substrate 201 to the solid-state imaging element 120, and a groove 222 corresponding to a pad wiring used when connecting the solid-state imaging element 120 to the logic circuit 122 are formed. At this time, the groove 222 is formed to a depth that does not reach the Si of the logic circuit 122 or the memory element 201.

Next, the anti-etching agent used for processing the groove portion 222 is removed, and then as shown in the side cross-sectional view 42B of Figure 42, the through hole 223 used to connect to the memory element substrate 201 and the through hole 224 used to connect to the logic circuit 122 are patterned, and dry etching of the oxide film 133 is started.

Since the oxide film 133 on the logic circuit 122 is relatively thin, the through hole 224 reaches Si in the middle of forming the through hole 223 of the memory element substrate 201. However, since the selectivity of _SiO2 to Si is relatively high, Si will not be processed, thereby forming through holes 223 and 224 of different depths.

Furthermore, at this time, before the through hole 223 reaches the pad 201b on the memory device substrate 201, the _SiO2 processing of the through hole 224 is terminated.

Thereafter, the etching conditions are changed to process the through holes 223 and 224. That is, after removing the processing resist, an insulating film 221 containing plasma _SiO2 is formed to insulate Si, and then etching back is performed, thereby forming through holes 223' and 254' at the same time as shown in the side cross-sectional view 42C of FIG. 42.

In the process of step S179 (rewiring & pad formation), as shown in the side cross-sectional view 43A of FIG. 43, after the barrier metal is formed, a metal such as Cu is embedded in the through holes 223', 224', and the surface is polished by CMP (Chemical Mechanical Polishing).

Through this process, only the conductive material of the wirings 122c', 201c and the through electrodes 122d, 201d remains. In this way, the wirings 122c', 201c and the through electrodes 122d, 201d, which are lead wirings from the memory device substrate 201 and the logic circuit 122, are formed.

Furthermore, pads 201b and 122b are formed for CuCu connection with the solid-state imaging element 120.

In the process of step S195 (permanent (Cu-Cu) bonding WoW), as shown in the side cross-sectional view 43B of FIG. 43 , the pad 120b of the solid-state imaging element 120 is CuCu bonded to the pads 201b and 122b′ of the memory element substrate 201 and the logic circuit 122 .

In the process of step S196 (back CIS process), as shown in the side cross-sectional view 43C of Figure 43, after the wall of the solid imaging element 120 is thinned and a protective film is formed, as shown in the side cross-sectional view 43D of Figure 43, a color filter and a crystal-carrying lens 131 are formed.

The solid-state imaging device 111 manufactured by the above process can reduce the number of processes before the larger solid-state imaging element 120 is joined, thereby improving the yield corresponding to the reduction in the number of processes.

Furthermore, since the wiring of the memory device substrate 201 and the logic circuit 122 can be formed without utilizing the wiring of the solid-state imaging device 120, the degree of freedom in routing the wiring can be increased.

As a result, the wiring length can be shortened or the wiring can be increased, thereby stabilizing the power supply or reducing power consumption. In addition, the degree of freedom in forming the light shielding film for dealing with hot carriers can be increased.

Furthermore, since at least one of the memory circuit 121 and the logic circuit 122 can be joined after inspection, the yield of the final back-illuminated solid-state imaging device 111 can be improved.

＜＜9. Seventh embodiment＞＞ ＜Method for manufacturing a solid-state imaging device by laminating a memory circuit and a logic circuit on the solid-state imaging device＞ The above describes an example in which a memory circuit 121 and a logic circuit 122 are laminated on a reconfiguration substrate 151 or a support substrate 132 and embedded in an oxide film 133, and a solid-state imaging device 120 is laminated on the memory circuit 121 and the logic circuit 122, thereby manufacturing a solid-state imaging device 111.

However, the memory circuit 121 and the logic circuit 122 may be stacked on the solid-state imaging device 120 and embedded in the oxide film 133, and the support substrate 132 may be stacked on the memory circuit 121 and the logic circuit 122.

The structure of the completed solid-state imaging device 111 is basically the same as that of FIG10. Therefore, the manufacturing method of the solid-state imaging device 111 is described here with reference to the side cross-sectional views of FIG44 to FIG46. The manufacturing method of the solid-state imaging device 111 is to stack the memory circuit 121 and the logic circuit 122 on the solid-state imaging element 120 and bury them in the oxide film 133, and stack the support substrate 132 on the memory circuit 121 and the logic circuit 122.

Furthermore, it is assumed that the solid-state imaging device 120, the memory circuit 121, and the logic circuit 122 are manufactured, the memory circuit 121 and the logic circuit 122 are cut into pieces, and good products are selected by inspection.

In the first process, as shown in the side cross-sectional view 44A of FIG. 44 , the wiring 120 a and the pad 120 b are formed in the solid-state imaging element 120 .

In the second process, as shown in the side cross-sectional view 44B of FIG. 44, the memory circuit 121 and the logic circuit 122 are stacked on the solid-state imaging device 120, and the pad 120b is CuCu-bonded with the pads 121b and 122b. At this time, since the oxide film connection is performed after the hydrophilization treatment, the connection can be performed at room temperature during the CuCu connection, and the solid-state imaging device 120 and the memory circuit 121 and the logic circuit 122 can be aligned with higher accuracy.

For example, the alignment accuracy can meet the level of 1 μm < 3σ. In addition, as shown in the side cross-sectional view 44B of FIG. 44, after alignment, the memory circuit 121 is tilted so that a portion of it abuts against the solid-state imaging device 120, and then the entire device is joined. By mounting in this way, the interlayer gap can be suppressed, thereby improving the operational reliability of the solid-state imaging device 120, the memory circuit 121, and the logic circuit 122. Furthermore, it is also easy to cope with the situation where the heights of the mounted memory circuit 121 and the logic circuit 122 are different. Furthermore, in the side sectional view 44B of FIG. 44, a state is shown in which only the memory circuit 121 is tilted so that a portion of it abuts against the solid-state imaging element 120, and the logic circuit 122 is also installed by the same method.

In the third step, as shown in the side cross-sectional view 44C of FIG. 44, the Si of the memory circuit 121 and the logic circuit 122 is thinned. Considering the embedding property of the oxide film 133, the memory circuit 121 and the logic circuit 122 are preferably made as thin as possible before the embedding process of the oxide film 133. From the perspective of ensuring the embedding flatness of the oxide film 133 and increasing the warp amount, it is preferable to set the thickness of the memory circuit 121 and the logic circuit 122 to, for example, about 20 μm or less.

In the fourth step, as shown in the side cross-sectional view 45A of FIG. 45 , the memory circuit 121 and the logic circuit 122 are buried by the oxide film 133. If the oxide film 133 is an inorganic film, it is preferably a Si-based oxide film such as SiO ₂ , SiO, or SRO in terms of heat resistance and warp angle after film formation. In addition, if the oxide film 133 is an organic film, it is preferably a polyimide-based oxide film (PI, PBO, etc.) or a polyamide-based oxide film that is easy to ensure high heat resistance.

In the fifth step, as shown in the side cross-sectional view 45B of FIG. 45, grooves 121e', 122e', Te' corresponding to the wirings connecting the memory circuit 121 and the logic circuit 122 are formed by resist patterning and oxide film dry etching.

At this time, the grooves 121e', 122e', Te' are formed to a depth that does not reach Si of the memory circuit 121 and the logic circuit 122.

Furthermore, the grooves 121e' and 122e' formed above are opened to a depth just before reaching the copper wiring at the bottom of the multi-layer wiring layer, or just before reaching the Al pad at the top layer, so as to form through holes 121f' and 122f'. The diameter of the through holes 121f' and 122f' is, for example, about 1 μm to 5 μm.

In the sixth step, as shown in the side cross-sectional view 45C of Figure 45, the side wall of Si exposed by the above processing is etched back after forming an insulating film containing _SiO2 , thereby removing the _SiO2 of the protective film formed at the bottom of the through holes 121f' and 122f', and exposing the wiring layers of the memory circuit 121 and the logic circuit 122.

Next, after forming the barrier metal, a metal such as Cu is embedded into the through holes 121f' and 122f', and the surface is polished by CMP (Chemical Mechanical Polishing) method, so that only the grooves 121e', 122e', Te' and the conductive material of the through holes 121f' and 122f' remain.

Thus, in the region within the insulating spacer layer, an interconnection wiring T''' connecting the memory circuit 121 and the logic circuit 122, and through electrodes 121d' and 122d' of the memory circuit 121 and the logic circuit 122 are formed.

In the seventh step, as shown in the side sectional view 46A of FIG. 46 , the state in the side sectional view 45C of FIG. 45 is reversed upside down and then connected to the supporting substrate 132 .

Next, in the eighth step, as shown in the side cross-sectional view 46B of FIG. 46 , after the Si substrate wall of the solid-state imaging element 120 is thinned, a color filter and a wafer-mounted lens 131 are formed.

Through the above processing, the theoretical yield can be increased, thereby reducing costs.

Furthermore, when an organic photoelectric conversion film is used as the structure of the solid-state imaging element 120, in the eighth step, in addition to forming a crystal-based lens (color filter is not included in FIG. 46 ) 131, an organic photoelectric conversion film 241 may be formed between the crystal-based lens 131 and the solid-state imaging element 120, as shown in the side cross-sectional view 46C of FIG. 46 .

When the solid-state imaging device 120 is an imaging device using an organic photoelectric conversion film 241 proposed in recent years to improve pixel characteristics, the heat-resistant temperature of the organic photoelectric conversion film 241 is relatively low and cannot withstand the soldering temperature that requires heating above 200°C.

However, in the seventh embodiment of the present invention, an organic photoelectric conversion film 241 with lower heat resistance can be formed after chip lamination, and fine CuCu bonding technology can be applied, so that a solid-state imaging device 111 having a solid-state imaging element 120 can be realized, and the solid-state imaging element 120 maintains a higher external quantum efficiency and has a lower dark current characteristic.

＜＜10. 8th Implementation Form＞＞ ＜Manufacturing Method of Laminated Memory Circuit and Logic Circuit on Solid-State Imaging Device＞ The above describes the following example: Memory circuit 121 and logic circuit 122 are arranged and laminated on solid-state imaging device 120 and embedded in oxide film 133, and support substrate 132 is laminated on memory circuit 121 and logic circuit 122, thereby manufacturing solid-state imaging device 111.

However, the memory circuit 121 and the logic circuit 122 may be stacked on the solid-state imaging element 120 and embedded in the oxide film 133, and the support substrate 132 may be stacked on the stacked memory circuit 121 and the logic circuit 122, thereby manufacturing the solid-state imaging device 111.

FIG47 shows a configuration example of a solid-state imaging device 111, which is manufactured by stacking a memory circuit 121 and a logic circuit 122 on a solid-state imaging element 120 and embedding them in an oxide film 133, and stacking a support substrate 132 on the memory circuit 121 and the logic circuit 122.

That is, the logic circuit 122 is stacked on the support substrate 132, and two memory circuits 121-1 and 121-2 are stacked in the horizontal direction on the logic circuit 122, and the solid-state imaging device 120 is stacked on the memory circuits 121-1 and 121-2.

Furthermore, through-holes (TSVs) 231 and 232 are formed in the memory circuits 121-1 and 121-2, and the solid-state imaging device 120 is electrically connected to the logic circuit 122 via the through-hole 231, and the memory circuit 121 is electrically connected to the logic circuit 122 via the through-hole 232. That is, the through-hole 232 functions as an interconnection wiring.

Furthermore, the order of the multilayer memory circuit 121 and the logic circuit 122 may be reversed. For example, the memory circuit 121 and the logic circuit 122 may be reversed upside down as shown in FIG. 47 .

In this structure, good memory circuits 121 and logic circuits 122 can be stacked to manufacture the solid-state imaging device 111, thereby increasing the theoretical yield and reducing the cost.

Furthermore, the memory circuit 121 or the logic circuit 122 may be further stacked in multiple layers by the same method, thereby increasing the capacity of the memory.

In particular, when using a solid-state imaging device 120 using an organic photoelectric conversion film 241 (FIG. 46), since there are pixel signals for each of the RGB wavelengths, a large-capacity memory is required to store data once before signal processing. Therefore, by setting a structure of a multi-stage multilayer memory circuit 121, the memory capacity can be effectively increased, thereby effectively utilizing the organic photoelectric conversion film 241.

<Manufacturing method of the solid-state imaging device of FIG. 47> Next, the manufacturing method of the solid-state imaging device 111 of FIG. 47 is described using FIG. 48 and FIG. 49.

Furthermore, it is assumed that the solid-state imaging device 120, the memory device substrate 201, and the logic circuit 122 are manufactured in the same manner as the memory circuit 121 and the logic circuit 122, and the logic circuit 122 is cut and good products are selected by inspection.

In the first step, as shown in the side cross-sectional view 48A of FIG. 48 , wiring 120 a and pad 120 b are formed in the solid-state imaging element 120 .

In the second step, as shown in the side cross-sectional view 48B of FIG. 48 , the logic circuit 122 is stacked on the solid-state imaging element 120, and the pads 120b and 122b are CuCu-bonded.

In the third step, as shown in the side cross-sectional view 48C of Fig. 48, the Si of the logic circuit 122 is thinned and through electrodes 231 and 232 are formed. The through electrode 231 is connected to the pad 120b of the solid-state imaging element 120, and the through electrode 232 is connected to the pad 122b of the logic circuit.

In the fourth step, as shown in the side cross-sectional view 48D of FIG. 48 , the memory circuits 121-1 and 121-2 are arranged on the logic circuit 122, and the through electrodes 231 and 232 are CuCu-connected to the pads 121b-1 and 121b-2 of the memory circuits 121-1 and 121-2.

In the fifth step, as shown in the side cross-sectional view 49A of FIG. 49 , the memory circuits 121-1 and 121-2 are formed by embedding the oxide film 133, and then the surface is flattened by CMP.

In the sixth step, as shown in the side sectional view 49B of FIG. 49 , the state of the side sectional view 49A is reversed upside down, and the memory circuits 121-1 and 121-2 are connected and fixed to the supporting substrate 132.

In the seventh step, as shown in the side cross-sectional view 49C of FIG. 49 , after the Si substrate of the solid-state imaging device 120 is thinned, a color filter and a wafer-mounted lens 131 are formed.

Furthermore, when further stacking the memory circuit 121, the fourth and fifth steps described with reference to the side sectional view 48D of FIG. 48 and the side sectional view 49A of FIG. 49 are repeated to stack the memory circuit 121 to the required number of stages.

In the solid-state imaging device 111 manufactured by the above process, the memory circuit 121 and the logic circuit 122 of good quality can also be stacked to manufacture the solid-state imaging device 111, so the theoretical yield can be improved, thereby reducing the cost.

Furthermore, by further stacking the memory circuit 121 into multiple stages, the memory capacity can be increased, thereby enabling more stable signal processing in the solid-state imaging device 120 using the organic photoelectric conversion film 241.

＜＜11. 9th Implementation Form＞＞ ＜Example of a solid-state imaging device in which a wiring layer is formed on the supporting substrate side and terminals for wire bonding are formed＞ The above describes an example of manufacturing a solid-state imaging device 111 by stacking a good memory circuit 121 and a logic circuit 122 on a solid-state imaging element 120. However, a wiring layer may be formed on the supporting substrate side and terminals for wire bonding may be formed.

FIG. 50 shows a configuration example of a solid-state imaging device 111 in which a wiring layer is formed on the supporting substrate side and terminals for wire bonding are formed.

In the solid-state imaging device 111 of FIG. 50 , a wiring 261a is formed on a supporting substrate 261 and is electrically connected to terminals 261b at the left and right ends. The wiring 261a is connected to the wirings 121a and 122a via through electrodes 251 and 252 of the Si substrate that penetrate the memory circuit 121 and the logic circuit 122. In addition, the pads 121b and 122b of the memory circuit 121 and the logic circuit 122 are CuCu-bonded to the wiring 120a of the solid-state imaging element 120, so the wiring 261a is also electrically connected to the solid-state imaging element 120 via the memory circuit 121 and the logic circuit 122.

A joint portion 271 connected to a wire 272 is provided at the terminal 261 b, so that the solid-state imaging device 111 is configured to be able to transmit and receive signals with an external device via the joint portion 271 and the wire 272 .

<Manufacturing method of solid-state imaging device of FIG. 50> Next, referring to FIG. 51 and FIG. 52, the manufacturing method of the solid-state imaging device 111 of FIG. 50 is described. Furthermore, it is assumed that the solid-state imaging element 120, the memory circuit 121, and the logic circuit 122 are manufactured and the memory circuit 121 and the logic circuit 122 are cut, and good products are selected by inspection.

Furthermore, it is assumed that wiring 120a and pad 120b are formed on the solid-state imaging element 120, and the memory circuit 121 and the logic circuit 122 are stacked on the solid-state imaging element 120, and the pad 120b is CuCu bonded with the pads 121b and 122b and buried with the oxide film 133, and then the Si of the memory circuit 121 and the logic circuit 122 is thinned and flattened, as described below.

In the first step, as shown in the side cross-sectional view 51A of FIG. 51 , through electrodes 251 and 252 are formed on the Si substrate of the memory circuit 121 and the logic circuit 122 for the wirings 121a and 122a.

In the second step, as shown in the side sectional view 51B of Fig. 51, the structure of the side sectional view 51A of Fig. 51 is reversed upside down and joined to the supporting substrate 261 formed with the wiring 261a and the terminal 261b. At this time, the through electrodes 251 and 252 are joined to the wiring 261a of the supporting substrate 261.

In the third step, as shown in the side cross-sectional view 51C of FIG. 51, the Si substrate of the solid-state imaging element 120 is thinned.

In the fourth step, as shown in the side cross-sectional view 52A of FIG. 52 , a color filter and a chip-mounted lens 131 are formed on the solid-state imaging device 120 .

In the fifth step, as shown in the side cross-sectional view 52B of FIG. 52, the oxide film 133 and the solid-state imaging element 120 existing on the upper portion of the terminal 261b surrounded by the dotted line in the figure are cut off, so that the terminal 261b is exposed.

In the sixth step, as shown in the side cross-sectional view 52C of FIG. 52 , the wire 272 and the terminal 261 b are connected via the joint 271 , thereby completing the solid-state imaging device 111 .

In this manufacturing method, the theoretical yield can also be increased, thereby reducing costs.

Furthermore, by utilizing this manufacturing process, for example, as shown in the upper left portion of FIG. 53 , if a through hole 282 is provided on the terminal 261b and the wire 272 is connected via the joint 271, it is necessary to ensure a distance from the lens 281, thereby hindering the low height of the solid-state imaging device 111.

That is, as shown in the upper left portion of FIG. 53 , when the wire 272 is routed through the through hole 282, the distance to the lens 281 must be set to a distance A in order to increase the space required for the routing corresponding to the bend of the wire 272.

In contrast, in the case of the solid-state imaging device 111 manufactured by the manufacturing method of the present invention, as shown in the upper right portion of FIG. 53 , the space required for winding the wire 272 can be reduced, so the distance between the solid-state imaging element 120 and the lens 281 can be set to a distance B that is smaller than the distance A.

As a result, the height of the solid-state imaging device 111 can be reduced.

Furthermore, as shown in the lower left portion of FIG. 53 , when the solid-state imaging element 120 is directly disposed on the supporting substrate 261 , there is a risk of ghosting or glare due to incident light reflected by the wire 272 , as indicated by the dotted arrow.

In contrast, in the case of the solid-state imaging device 111 manufactured by the manufacturing method of the present invention, as shown in the right portion of the lower section of FIG. 53 , the incident light reflected by the wire 272 is incident on the side surface of the solid-state imaging element 120 or the side surfaces of the memory circuit 121 and the logic circuit 122, thereby suppressing the generation of ghosting or glare.

＜＜12. Application example of the ninth embodiment＞＞ (First application example of the ninth embodiment) The above describes an example in which the through electrodes 251 and 252 are formed in the memory circuit 121 and the logic circuit 122, respectively, and the signal from the solid-state imaging element 120 is output to the outside through the memory circuit 121 and the logic circuit 122, the wiring 261a of the support substrate 261, and the terminal 261b and through the wire 272 connected to the joint 271.

However, for example, as shown in the side sectional view 54A of FIG. 54 , a through electrode 291 may be formed which does not penetrate the memory circuit 121 and the logic circuit 122 but penetrates the oxide film 133 to connect the pad 120b of the solid-state imaging element 120 to the wiring 261a of the supporting substrate 261.

In this case, the solid-state imaging device 120 is directly connected to the wiring 261a of the support substrate 261 via the through electrode 291. However, in this case, the memory circuit 121 and the logic circuit 122 are not electrically connected to the support substrate 261, but can be output to the outside via the wiring in the solid-state imaging device 120 and the through electrode 291.

(Second application example of the ninth embodiment) The above describes an example in which either the through electrodes 251, 252 or the through electrode 291 is provided, but a configuration in which all of them are provided may also be provided.

That is, as shown in the side sectional view 54B in FIG. 54 , a through electrode 291 connecting the pad 120b of the solid-state imaging element 120 and the wiring 261a of the supporting substrate 261, a through electrode 251 connecting the wiring 121a of the memory circuit 121 and the wiring 261a, and a through electrode 251 connecting the wiring 122a of the logic circuit 122 and the wiring 261a may be provided respectively.

In this case, the solid-state imaging device 120, the memory circuit 121, and the logic circuit 122 are each independently electrically connected to the support substrate 261, so there is no need to provide interconnecting wiring, etc.

(Third application example of the ninth embodiment) The above describes an example of providing any one of the through electrodes 251, 252, and the through electrode 291. However, the terminals may be provided in a state of being electrically connected to the wiring layers of the memory circuit 121 and the logic circuit 122 where the pads 121b and 122b are provided, instead of being output to the outside through the support substrate 261, instead of through the through electrodes 251, 252, and 271.

That is, in the solid-state imaging device 111 shown in the side cross-sectional view 54C of FIG. 54 , the terminal 261b′ is provided in a state of being electrically connected to the wiring layer on which the pads 121b and 122b of the memory circuit 121 and the logic circuit 122 are provided.

By adopting such a configuration, the terminal 261b' and the joint 271 can be formed at a position further back in the incident direction than the incident surface of the solid-state imaging element 120, so that a through electrode is not provided and the space for the winding of the wire 272 can be reduced. In this way, it is better to provide a through electrode in the solid-state imaging device 111 as described in the upper part of FIG. 53, and the distance from the lens can be shortened to achieve a low height.

＜＜13. 10th Implementation Form＞＞ The above describes an example in which a signal is output to the outside by leading a wire from the upper surface of the end of the supporting substrate and from the joint portion, but it is also possible to output the signal of the solid-state imaging element 120 directly from the back side of the supporting substrate.

FIG55 shows a configuration example of a solid-state imaging device 111, which can output a signal directly from a through electrode 301 connected to a solid-state imaging element 120 rather than from the back side of a supporting substrate 132 via a memory circuit 121 and a logic circuit 122.

By constructing the solid-state imaging device 111 as shown in FIG55 , the theoretical yield can be increased to reduce costs, and the signal from the solid-state imaging element 120 can be led out from the back side of the supporting substrate 132.

In this way, a signal processing circuit and the like can be stacked on the back side of the solid-state imaging device 111.

<Manufacturing method of the solid-state imaging device of FIG. 55> Next, referring to FIG. 56 and FIG. 57, the manufacturing method of the solid-state imaging device 111 of FIG. 55 is described. Furthermore, the side cross-sectional view 56A of FIG. 56 shows the state after the solid-state imaging device 111 of FIG. 12 is manufactured. The solid-state imaging device 111 of FIG. 55 is assumed to be produced by processing the solid-state imaging device 111 of FIG. 12, and the description is expanded.

In the first process, as shown in the side sectional view 56B of Figure 56, the structure of the side sectional view 56A of Figure 56 is reversed up and down, and the interference portion 312, which includes a resin having a heat resistance of more than 250°C and can protect the color filter on the solid-state imaging element 120 and the crystal-carrying lens 131, is placed on the supporting substrate 311.

In the second step, as shown in the side cross-sectional view 56C of FIG. 56 , the supporting substrate 132 is thinned.

In the third step, as shown in the side cross-sectional view 57A of Figure 57, a through electrode 301 is formed in a manner that penetrates the oxide film 133 from the supporting substrate 132 and reaches the wiring 120a of the solid-state imaging element 120.

In the fourth step, as shown in the side cross-sectional view 57B of Figure 57, the surface of the solid-state imaging element 120 including the color filter and the crystal-mounted lens 131 is peeled off from the interference portion 312 and then turned upside down as shown in the side cross-sectional view 57C, thereby completing the solid-state imaging device 111 of Figure 55.

By using the above manufacturing method, a solid-state imaging device 111 can be manufactured, and the solid-state imaging device 111 can directly lead out the signal of the solid-state imaging element 120 from the back side of the supporting substrate 132 of the solid-state imaging device 111.

＜＜14. First application example of the 10th embodiment＞＞ The above describes an example in which the signal of the solid-state imaging element 120 can be directly output by forming the through electrode 301 on the back side of the self-supporting substrate. However, the deeper the through electrode is, the thicker the sunken portion of the through electrode becomes due to the inclination. Therefore, it is also possible to form a through electrode by forming a through hole for each layer individually in the stacking process instead of forming the through electrode at once, thereby making the thickness of the through electrode finer.

Here, referring to Figures 58 to 60, a method for manufacturing a solid-state imaging device 111 in which a through electrode is formed individually for each layer and stacked.

Furthermore, the description here is based on the premise that good products from the memory circuit 121 and the logic circuit 122 are selected and placed on the redistribution substrate 151.

In the first step, a through electrode 371 of a specific depth is formed in advance on the support substrate 132 at a position corresponding to the through electrode 301 in FIG55. Then, as shown in the side cross-sectional view 58A of FIG58, the support substrate 132 is fixed on the memory circuit 121 and the logic circuit 122 placed on the rearrangement substrate 151 in a state of being reversed upside down.

In the second step, as shown in the side sectional view 58B of FIG. 58 , after the state of the side sectional view 58A of FIG. 58 is reversed upside down, the reconfigured substrate 151 is removed.

In the third step, as shown in the side cross-sectional view 58C of FIG. 58 , the memory circuit 121 and the logic circuit 122 are buried with the oxide film 133 and then planarized.

In the fourth step, as shown in the side cross-sectional view 59A of FIG59, after forming the interconnection wiring T and the pads 121b and 122b in the oxide film 133, the through electrode 381 is formed at a position corresponding to the through electrode 301 of FIG55. That is, the through electrode 381 is electrically connected to the through electrode 371.

In the fifth step, after the through electrode 391 is formed at the position of the solid-state imaging element 120 corresponding to the through electrode 301 in FIG. 55 , as shown in the side cross-sectional view 59B of FIG. 59 , it is turned upside down and connected to the memory circuit 121 and the logic circuit 122. That is, the through electrode 391 is electrically connected to the through electrode 381. That is, through the steps up to this point, the through electrodes 371, 381, and 391 constitute a single through electrode.

In the sixth step, as shown in the side cross-sectional view 59C of FIG. 59 , after the solid-state imaging element 120 is thinned, a color filter and a crystal-mounted lens 131 are formed on the imaging surface.

In the 7th process, as shown in the side sectional view 60A of Figure 60, in a state where the state of the side sectional view 59C of Figure 59 is reversed upside down, the interference portion 312, which includes a resin having a heat resistance of more than 250°C and which can protect the color filter on the solid-state imaging element 120 and the crystal-carrying lens 131, is placed on the supporting substrate 311.

In the eighth step, as shown in the side cross-sectional view 60B of FIG. 60 , the supporting substrate 132 is thinned to allow the through electrode 371 to protrude.

In the 9th process, as shown in the side cross-sectional view 60C of Figure 60, the interference portion 312 is peeled off from the surface of the solid-state imaging element 120 including the color filter and the crystal carrier 131 and then turned upside down, thereby completing the solid-state imaging device 111 of Figure 55.

By the above manufacturing method, when forming a through electrode that directly leads the signal of the solid-state imaging element 120 to the back side of the supporting substrate 132, through electrodes 371, 381, and 391 are formed in each layer, thereby forming a thinner through electrode than forming a deeper through electrode at one time.

＜＜15. Second application example of the tenth embodiment＞＞ The above describes an example in which a through electrode is formed and a through electrode is formed to directly lead out the signal of the solid-state imaging element 120 from the back surface of the supporting substrate 132 which becomes the back surface of the solid-state imaging device 111. However, through electrodes may be formed on the memory circuit 121 and the logic circuit 122 respectively and directly led out from the back surface of the supporting substrate 132.

That is, as shown in FIG. 61 , through electrodes 401 and 402 may be formed from the back surface of the supporting substrate 132 so as to be connected to the respective wirings 121a and 122a of the memory circuit 121 and the logic circuit 122 constituting the solid-state imaging device 111.

Furthermore, regarding the manufacturing method of the solid-state imaging device 111 of FIG61, since it is the same as the method for manufacturing the solid-state imaging device 111 of FIG55, in which the through electrode 301 or the through electrodes 371, 381, and 391 are formed, the description thereof will be omitted.

<<16. Applications in electronic devices>> The above-mentioned imaging element can be applied to various electronic devices such as digital still cameras or digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

FIG62 is a block diagram showing an example of the configuration of an imaging device as an electronic device to which the present technology is applicable.

The imaging device 501 shown in FIG62 includes an optical system 502, a shutter device 503, a solid-state imaging element 504, a driving circuit 505, a signal processing circuit 506, a monitor 507, and a memory 508, and can capture still images and moving images.

The optical system 502 is composed of one or more lenses, and guides light (incident light) from the object to be photographed to the solid-state imaging device 504 and forms an image on the light-receiving surface of the solid-state imaging device 504.

The shutter device 503 is disposed between the optical system 502 and the solid-state imaging element 504, and controls the light irradiation period and the light shielding period of the solid-state imaging element 504 according to the control of the driving circuit 505.

The solid-state imaging device 504 is composed of a package including the above-mentioned solid-state imaging device. The solid-state imaging device 504 stores signal charge for a fixed period of time according to the light formed on the light receiving surface via the optical system 502 and the shutter device 503. The signal charge stored in the solid-state imaging device 504 is transmitted according to the driving signal (timing signal) supplied by the self-driving circuit 505.

The driving circuit 505 outputs a driving signal for controlling the transmission action of the solid-state imaging element 504 and the shutter action of the shutter device 503, thereby driving the solid-state imaging element 504 and the shutter device 503.

The signal processing circuit 506 performs various signal processing on the signal charge output from the solid-state imaging element 504. The image (image data) obtained by the signal processing performed by the signal processing circuit 506 is supplied to the monitor 507 for display, or supplied to the memory 508 for storage (recording).

In the imaging device 501 constructed in this manner, by applying the solid-state imaging device 111 to the optical system 502 and the solid-state imaging element 204, the yield rate can be improved, thereby reducing the cost associated with manufacturing. ＜＜17. Example of use of the solid-state imaging device＞＞

FIG63 is a diagram showing an example of using the solid-state imaging device 111 described above.

As described below, the solid-state imaging device can be used to sense various examples of visible light, infrared light, ultraviolet light, X-rays, etc.

・Digital cameras or mobile devices with camera functions that take images for viewing ・In-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping or driver status recognition, surveillance cameras that monitor moving vehicles or roads, and distance-measuring sensors that measure distances between vehicles, etc. ・In-vehicle sensors that take images of the user's gestures and operate the device according to the gestures, etc., for use in TV (television), or home appliances such as refrigerators and air conditioners ・Medical or health care devices such as endoscopes or devices that take blood vessel images by receiving infrared light ・Security devices such as surveillance cameras for anti-theft purposes or cameras for person verification ・Device for beauty such as skin measuring devices that take pictures of the skin or microscopes that take pictures of the scalp ・Device for sports such as action cameras or wearable cameras ・Device for agricultural use such as cameras for monitoring the status of dry fields or crops

＜＜18. Application to endoscopic surgical system＞＞ The technology of the present invention (this technology) can be applied to various products. For example, the technology of the present invention can be applied to endoscopic surgical system.

FIG64 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology of the present invention (present technology) can be applied.

FIG64 shows a situation where a surgeon (doctor) 11131 performs surgery on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 or an energy surgical instrument 11112, a support arm device 11120 for supporting the endoscope 11100, and a trolley 11200 carrying various devices used for endoscopic surgery.

The endoscope 11100 includes a barrel 11101 inserted into a body cavity of a patient 11132 at a specific length from the front end, and a camera lens 11102 connected to the base end of the barrel 11101. In the example shown in the figure, the endoscope 11100 is a so-called rigid scope having a rigid barrel 11101, but the endoscope 11100 may also be a so-called flexible scope having a flexible barrel.

An opening portion in which an objective lens is embedded is provided at the front end of the barrel 11101. A light source device 11203 is connected to the endoscope 11100. The light generated by the light source device 11203 is guided to the front end of the barrel by a light guide member extending inside the barrel 11101, and irradiates the observed object in the body cavity of the patient 11132 through the objective lens. Furthermore, the endoscope 11100 can be a straight-view mirror, a strabismus mirror, or a side-view mirror.

An optical system and an imaging element are provided inside the camera lens 11102. The reflected light (observation light) from the observed object is focused on the imaging element by the optical system. The imaging element performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. The image signal is sent to the camera control unit (CCU: Camera Control Unit) 11201 in the form of raw (RAW) data.

The CCU 11201 includes a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), etc., and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera lens 11102, and performs various image processing such as development processing (demosaic processing) on the image signal to display an image based on the image signal.

The display device 11202 displays an image based on an image signal obtained by image processing performed by the CCU 11201 under the control of the CCU 11201.

The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing a surgical site.

The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various information or instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user inputs instructions to change the shooting conditions (type of irradiation light, magnification, and focal distance, etc.) of the endoscope 11100.

The surgical instrument control device 11205 controls the driving of the energy surgical instrument 11112 used for burning, cutting or closing of tissues. The pneumoperitoneum device 11206 inflates the body cavity of the patient 11132 and delivers gas into the body cavity through the pneumoperitoneum tube 11111 in order to ensure the visual field of the endoscope 11100 and the operating space of the surgeon. The recorder 11207 is a device that can record various information related to the surgery. The printer 11208 is a device that can print various information related to the surgery in various forms such as text, images or graphics.

Furthermore, the light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site may include, for example, a white light source composed of an LED, a laser light source, or a combination thereof. When a white light source is formed by a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. Moreover, in this case, by irradiating the observation object with laser light from each of the RGB laser light sources in a time-sharing manner and controlling the drive of the imaging element of the camera lens 11102 in synchronization with the irradiation timing, images corresponding to each of the RGB can also be captured in a time-sharing manner. According to this method, a color image can be obtained even if a color filter is not provided on the imaging element.

In addition, the light source device 11203 can be driven by changing the intensity of the light to be output at specific intervals. The driving of the imaging element of the camera lens 11102 is controlled synchronously with the timing of the change in the intensity of the light to obtain images in a time-sharing manner. By synthesizing the images, a high dynamic range image without so-called black saturation and bloom can be generated.

Furthermore, the light source device 11203 can also be configured to provide light of a specific wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow band light observation (Narrow Band Imaging) is performed, which utilizes the wavelength dependence of light absorption in human body tissues to irradiate light of a narrower frequency band than the irradiation light (i.e., white light) used in normal observation, thereby photographing specific tissues such as blood vessels on the surface of the mucosa with high contrast. Alternatively, in special light observation, fluorescent observation can also be performed to obtain images using fluorescence generated by irradiating excitation light. In fluorescence observation, the following operations can be performed: irradiating human tissue with excitation light and observing the fluorescence from the human tissue (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the human tissue and irradiating the human tissue with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 can be configured to supply narrowband light and/or excitation light corresponding to such special light observation.

FIG65 is a block diagram showing an example of the functional configuration of the camera lens 11102 and CCU 11201 shown in FIG64.

The camera lens 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera lens control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera lens 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so as to be communicable with each other.

The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. The observation light taken in from the front end of the lens barrel 11101 is guided to the camera lens 11102 and incident on the lens unit 11401. The lens unit 11401 is composed of a plurality of lens combinations including a zoom lens and a focusing lens.

The imaging unit 11402 is composed of imaging elements. The imaging element constituting the imaging unit 11402 may be one (so-called single-board type) or multiple (so-called multi-board type). When the imaging unit 11402 is composed of multiple boards, for example, each imaging element may generate image signals corresponding to RGB respectively, and a color image may be obtained by synthesizing these image signals. Alternatively, the imaging unit 11402 may also be constructed to include a pair of imaging elements for respectively obtaining image signals for the right eye and the left eye corresponding to 3D (3 Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue of the surgical site. Furthermore, when the imaging section 11402 is composed of multiple plates, the lens unit 11401 may be provided with a plurality of systems corresponding to each imaging element.

Furthermore, the imaging unit 11402 may not be disposed in the camera lens 11102. For example, the imaging unit 11402 may be disposed inside the lens barrel 11101 just behind the objective lens.

The driving unit 11403 is composed of an actuator, and moves the zoom lens and the focusing lens of the lens unit 11401 along the optical axis by a specific distance under the control of the camera lens control unit 11405. In this way, the magnification and focus of the image taken by the imaging unit 11402 can be appropriately adjusted.

The communication unit 11404 is composed of a communication device for transmitting and receiving various information with the CCU 11201. The communication unit 11404 transmits the image signal obtained by the camera unit 11402 as raw data to the CCU 11201 via the transmission cable 11400.

Furthermore, the communication unit 11404 receives a control signal for controlling the drive of the camera lens 11102 from the CCU 11201, and supplies it to the camera lens control unit 11405. The control signal includes information related to shooting conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value when shooting, and/or information specifying the magnification and focus of the captured image.

Furthermore, the above-mentioned shooting conditions such as frame rate or exposure value, magnification, focus, etc. can be appropriately specified by the user, or can be automatically set by the control unit 11413 of CCU11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with the so-called AE (Auto Exposure) function, AF (Auto Focus) function and AWB (Auto White Balance) function.

The camera lens control unit 11405 controls the drive of the camera lens 11102 based on the control signal from the CCU 11201 received via the communication unit 11404 .

The communication unit 11411 is composed of a communication device for transmitting and receiving various information with the camera lens 11102. The communication unit 11411 receives the image signal transmitted from the camera lens 11102 via the transmission cable 11400.

Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera lens 11102 to the camera lens 11102. The image signal or the control signal can be transmitted by electrical communication or optical communication.

The image processing unit 11412 performs various image processing on the image signal which is the original data sent from the camera lens 11102.

The control unit 11413 performs various controls related to the imaging of the surgical site, etc. using the endoscope 11100 and the display of the photographed image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the drive of the camera lens 11102.

Furthermore, the control unit 11413 displays the captured image reflecting the surgical site, etc. on the display device 11202 based on the image signal obtained by the image processing unit 11412. At this time, the control unit 11413 can also use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, and mist when using energy surgical instruments 11112 by detecting the shape or color of the edges of the objects contained in the captured image. The control unit 11413 can also use the recognition result when displaying the captured image on the display device 11202 to overlay various surgical support information on the image of the surgical site. By overlaying and displaying the surgical support information and providing prompts to the surgeon 11131, the burden on the surgeon 11131 can be reduced, or the surgeon 11131 can perform the surgery accurately.

The transmission cable 11400 connecting the camera lens 11102 and the CCU 11201 is an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable thereof.

Here, in the example shown in the figure, communication is performed in a wired manner using a transmission cable 11400, but communication between the camera lens 11102 and the CCU 11201 can also be performed in a wireless manner.

An example of an endoscopic surgical system to which the technology of the present invention can be applied is described above. The technology of the present invention can be applied to the endoscope 11100 or the camera lens 11102 (the imaging unit 11402 thereof) in the above-described configuration. Specifically, the solid-state imaging device 111 of the present invention can be applied to the imaging unit 10402. By applying the technology of the present invention to the endoscope 11100 or the camera lens 11102 (the imaging unit 11402 thereof), the yield can be improved, thereby reducing the cost associated with manufacturing.

Furthermore, here, an endoscopic surgical system is described as an example, but the technology of the present invention can also be applied to other systems such as a microscope surgical system.

＜＜19. Application to mobile objects＞＞ The technology of the present invention (this technology) can be applied to various products. For example, the technology of the present invention can also be realized as a device mounted on any mobile object such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile vehicle, an airplane, a drone, a ship, a robot, etc.

FIG66 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology of the present invention can be applied.

The vehicle control system 12000 has a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 66 , the vehicle control system 12000 has a drive system control unit 12010, a body system control unit 12020, an external vehicle information detection unit 12030, an internal vehicle information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network I/F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device such as a drive force generating device for generating a drive force for the vehicle such as an internal combustion engine or a drive motor, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a brake device for generating a brake force for the vehicle.

The body system control unit 12020 controls the actions of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless start system, a smart key system, an electric window device, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 can be input with radio waves or signals of various switches sent from a portable device that replaces the key. The body system control unit 12020 receives the input of such radio waves or signals and controls the door lock device, electric window device, lights, etc. of the vehicle.

The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to take images outside the vehicle and receive the taken images. The vehicle exterior information detection unit 12030 can also perform object detection processing or distance detection processing of people, vehicles, obstacles, signs, or text on the road surface based on the received images.

The imaging unit 12031 is a photo sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal in the form of an image or in the form of distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

The in-vehicle information detection unit 12040 detects information in the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 for detecting the driver's status. The driver status detection unit 12041 includes, for example, a camera for photographing the driver. The in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level based on the detection information input from the driver status detection unit 12041, and can also determine whether the driver is dozing off.

The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information inside and outside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for the purpose of realizing ADAS (Advanced Driver Assistance System) functions including collision avoidance or impact mitigation of the vehicle, following driving based on the distance between vehicles, speed maintenance driving, collision warning of the vehicle, or lane departure warning of the vehicle.

In addition, the microcomputer 12051 can perform coordinated control for the purpose of automatic driving, etc., in which the automatic driving is achieved by controlling the driving force generating device, steering mechanism or braking device, etc. based on the information about the surroundings of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and driving autonomously without relying on the driver's operation.

Furthermore, the microcomputer 12051 can output control instructions to the vehicle body system control unit 12020 based on the information outside the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can control the headlights to switch from high beam to low beam according to the position of the vehicle in front or oncoming vehicle detected by the vehicle outside information detection unit 12030, for the purpose of anti-glare coordination control.

The audio and video output unit 12052 sends an output signal of at least one of audio and video to an output device that can visually or auditorily notify the passengers of the vehicle or the outside of the vehicle of information. In the example of FIG. 66 , an audio speaker 12061, a display unit 12062, and a dashboard 12063 are illustrated as output devices. The display unit 12062 may also include at least one of a vehicle-mounted display and a head-up display.

FIG67 is a diagram showing an example of the installation position of the imaging unit 12031. FIG.

In FIG. 67 , a vehicle 12100 includes imaging units 12101 , 12102 , 12103 , 12104 , and 12105 as an imaging unit 12031 .

Camera units 12101, 12102, 12103, 12104, and 12105 are disposed, for example, at the front bumper, side mirrors, rear bumper, rear door, and upper portion of the front window glass in the vehicle 12100. Camera unit 12101 provided on the front bumper and camera unit 12105 provided on the upper portion of the front window glass in the vehicle mainly obtain images in front of the vehicle 12100. Camera units 12102 and 12103 provided on the side mirrors mainly obtain images on the sides of the vehicle 12100. Camera unit 12104 provided on the rear bumper or rear door mainly obtains images on the rear of the vehicle 12100. The images in front obtained by the camera units 12101 and 12105 are mainly used to detect the preceding vehicle or pedestrian, obstacles, signal lights, traffic signs or lanes, etc.

Furthermore, FIG. 67 shows an example of the photographing range of the camera units 12101 to 12104. The photographing range 12111 indicates the photographing range of the camera unit 12101 disposed on the front bumper, the photographing ranges 12112 and 12113 respectively indicate the photographing ranges of the camera units 12102 and 12103 disposed on the side mirrors, and the photographing range 12114 indicates the photographing range of the camera unit 12104 disposed on the rear bumper or the rear door. For example, by overlapping the image data captured by the camera units 12101 to 12104, a bird's-eye view image of the vehicle 12100 observed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer 12051 obtains the distance to each solid object within the imaging range 12111 to 12114 and the temporal change of the distance (relative to the relative speed of the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby selecting the solid object that is closest to the path of the vehicle 12100 and is traveling at a specific speed (e.g., 0 km/h or more) in the same direction as the vehicle 12100 as the leading vehicle. Furthermore, the microcomputer 12051 can set the distance between vehicles that should be ensured in advance in front of the leading vehicle and perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control), etc. In this way, coordinated control for the purpose of automatic driving, etc., which is to drive autonomously without depending on the driver's operation, can be performed.

For example, the microcomputer 12051 can classify the 3D object data related to the 3D object into 2-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, telephone poles, etc. or other 3D objects and select them for automatic obstacle avoidance based on the distance information obtained from the camera units 12101 to 12104. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Furthermore, the microcomputer 12051 determines the collision risk indicating the danger of collision with each obstacle, and when the collision risk is above a set value and there is a possibility of collision, an alarm is output to the driver via the audio speaker 12061 or the display unit 12062, or forced deceleration or evasive steering is performed via the drive system control unit 12010, thereby providing driving support for avoiding collision.

At least one of the imaging units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 may identify pedestrians by determining whether pedestrians exist in the images captured by the imaging units 12101 to 12104. The identification of pedestrians is performed, for example, by selecting feature points in the images captured by the imaging units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. If the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio and video output unit 12052 controls the display unit 12062 to display a square outline for emphasis on the recognized pedestrian. The audio and video output unit 12052 can also control the display unit 12062 to display an icon representing the pedestrian at a desired position.

An example of a vehicle control system to which the technology of the present invention can be applied is described above. The technology of the present invention can be applied to the above-described configuration, such as the imaging unit 12031. Specifically, the solid-state imaging device 111 of the present invention can be applied to the imaging unit 12031. By applying the technology of the present invention to the imaging unit 12031, the yield can be improved, thereby reducing the cost associated with manufacturing.

The technology of the present invention can be applied to the above solid-state imaging device.

Furthermore, the present invention may also be configured as follows. ＜1＞ A back-illuminated solid-state imaging device, comprising: a first semiconductor element having an imaging element that generates a pixel signal in pixel units; a second semiconductor element and a third semiconductor element, which are smaller than the first semiconductor element, and in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedded component; and an interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element. ＜2＞ A back-illuminated solid-state imaging device as in ＜1＞, wherein the interconnection wiring is formed on the same layer. <3> A back-illuminated solid-state imaging device as in <1> or <2>, wherein the second semiconductor element and the third semiconductor element are stacked on the back side of the first semiconductor element relative to the incident direction of the incident light, and the interconnection wiring is formed on the side of the first semiconductor element relative to the boundary between the first semiconductor element and the second semiconductor element and the third semiconductor element. <4> A back-illuminated solid-state imaging device as in <1> or <2>, wherein the second semiconductor element and the third semiconductor element are laminated on the back side of the first semiconductor element relative to the incident direction of the incident light, and the interconnection wiring is formed on the side of the second semiconductor element and the third semiconductor element relative to the boundary between the first semiconductor element and the second semiconductor element and the third semiconductor element. <5> A back-illuminated solid-state imaging device as in <4>, wherein the interconnection wiring is formed on the surface of the second semiconductor element and the third semiconductor element opposite to the incident direction of the incident light. <6> A back-illuminated solid-state imaging device as in <5>, wherein the surfaces on which the wiring is formed of the second semiconductor element and the third semiconductor element are formed on the surface opposite to the incident direction of the incident light. <7> A back-illuminated solid-state imaging device as in <5>, wherein the surfaces on which the wiring is formed of the second semiconductor element and the third semiconductor element are formed on the back side relative to the incident direction of the incident light. <8> A back-illuminated solid-state imaging device as in <7>, wherein the surfaces on which the wiring is formed of the second semiconductor element and the third semiconductor element are formed on the back side relative to the incident direction of the incident light, and the interconnection wiring is formed via through electrodes formed on each substrate. <9> A back-illuminated solid-state imaging device as in <5>, wherein a supporting substrate is connected to the back side of the second semiconductor element and the third semiconductor element relative to the incident light, and the interconnection wiring is formed on the supporting substrate. <10> A back-illuminated solid-state imaging device as in <4>, wherein the interconnection wiring is formed on the back side of the second semiconductor element and the third semiconductor element relative to the incident direction of the incident light. <11> A back-illuminated solid-state imaging device as in <10>, wherein the interconnection wiring is formed on the front surface of the supporting substrate on the back side of the second semiconductor element and the third semiconductor element relative to the incident direction of the incident light. <12> A back-illuminated solid-state imaging device as described in <4>, wherein the second semiconductor element and the third semiconductor element are electrically connected to the first semiconductor element by a through electrode penetrating the first semiconductor element. <13> A back-illuminated solid-state imaging device as described in <4>, wherein the first semiconductor element, the second semiconductor element, and the third semiconductor element are stacked in the order of the first semiconductor element, the second semiconductor element, and the third semiconductor element relative to the incident direction of the incident light, and function as the interconnection wiring by electrically connecting to the bonding pads formed opposite to the bonding surfaces of the second semiconductor element and the third semiconductor element. <14> A back-illuminated solid-state imaging device as described in <1>, wherein the first semiconductor element, the second semiconductor element and the third semiconductor element are stacked in the order of the first semiconductor element, the second semiconductor element and the third semiconductor element relative to the incident direction of the incident light, and the first semiconductor element and the third semiconductor element are electrically connected via a through electrode formed by penetrating the second semiconductor element. <15> A back-illuminated solid-state imaging device as in <4>, wherein a supporting substrate is connected to the back side of the second semiconductor element and the third semiconductor element relative to the incident light, the wiring of at least any one of the first semiconductor element, the second semiconductor element, and the third semiconductor element is connected by a through electrode and led to the back side of the supporting substrate relative to the incident direction of the incident light. <16> A back-illuminated solid-state imaging device as in <4>, wherein the interconnection wiring is routed within the range occupied by the first semiconductor element in the direction perpendicular to the incident light. <17> A back-illuminated solid-state imaging device as in <3>, wherein a supporting substrate is connected to the back side of the second semiconductor element and the third semiconductor element relative to the incident light, and wiring is formed on the supporting substrate, the wiring of the supporting substrate is connected to the wiring of at least one of the first semiconductor element, the second semiconductor element, and the third semiconductor element by a through electrode, and a terminal for leading out a signal line is formed on the outer side of the supporting substrate where the second semiconductor element and the third semiconductor element are formed. <18> An imaging device having a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising: a first semiconductor element having an imaging element that generates a pixel signal in pixel units; a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, and in which a signal processing circuit required for signal processing of the pixel signal is embedded in an embedded component; and an interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element. <19> An electronic device having a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising: a first semiconductor element having an imaging element that generates a pixel signal in pixel units; a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, and in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedded component; and an interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element. <20> A method for manufacturing a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising: a first semiconductor element, which is an imaging element that generates pixel signals in pixel units; a second semiconductor element and a third semiconductor element, which are smaller than the first semiconductor element, and the signal processing circuits required for signal processing of the pixel signals are embedded in the embedded component; and interconnection wiring, which electrically connects the second semiconductor element and the third semiconductor element; and the method for manufacturing a back-illuminated solid-state imaging device is formed by a semiconductor process. The wafer of the imaging element is further configured with the signal processing circuit including the second semiconductor element and the third semiconductor element formed by the semiconductor process, the second semiconductor element and the third semiconductor element judged as good by electrical inspection, and are embedded by the embedded component to form interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element, and the oxide film is bonded and stacked in a manner that electrically connects the wiring between the first semiconductor element and the second semiconductor element and the third semiconductor element, and then singulated. <21> A back-illuminated solid-state imaging device, comprising: a first semiconductor element layer having an imaging element that generates pixel signals in pixel units; a second semiconductor element layer having a second semiconductor element and a third semiconductor element, wherein the second semiconductor element and the third semiconductor element are smaller than the first semiconductor element, and a signal processing circuit required for signal processing of the pixel signal is embedded in an embedded component; and a supporting substrate; the second semiconductor element layer is disposed between the first semiconductor element layer and the supporting substrate, and the first semiconductor element layer and the second semiconductor element layer are bonded by direct bonding. <22> A back-illuminated solid-state imaging device as in <21>, wherein the interconnection wiring for electrically connecting the second semiconductor element and the third semiconductor element is disposed on the second semiconductor element layer or the supporting substrate. <23> A back-illuminated solid-state imaging device as in <22>, wherein the interconnection wiring is disposed on the first semiconductor element layer side of the second semiconductor element layer. <24> A back-illuminated solid-state imaging device as in <22>, wherein the interconnection wiring is disposed on the supporting substrate side of the second semiconductor element layer. <25> A back-illuminated solid-state imaging device as in <22> or <23>, wherein the supporting substrate further has a wiring layer on the side of the second semiconductor element layer, and the interconnecting wiring is arranged on the wiring layer of the supporting substrate. <26> A back-illuminated solid-state imaging device as in <22>, wherein the second semiconductor element and the third semiconductor element are stacked on the back side of the first semiconductor element relative to the incident direction of the incident light, and the interconnecting wiring is formed on the side of the second semiconductor element and the third semiconductor element relative to the boundary between the first semiconductor element and the second semiconductor element and the third semiconductor element. <27> A back-illuminated solid-state imaging device as in <26>, wherein the interconnection wiring is formed on the surface of the second semiconductor element and the third semiconductor element opposite to the incident direction of the incident light. <28> A back-illuminated solid-state imaging device as in <27>, wherein the surface on which the wiring is formed of the second semiconductor element and the third semiconductor element is formed on the surface opposite to the incident direction of the incident light. <29> A back-illuminated solid-state imaging device as in <27>, wherein the surface on which the wiring is formed of the second semiconductor element and the third semiconductor element is formed on the back side relative to the incident direction of the incident light. <30> A back-illuminated solid-state imaging device as described in <29>, wherein the surfaces of the second semiconductor element and the third semiconductor element on which wiring is formed are formed on the back side relative to the incident direction of the incident light, and the interconnection wiring is formed through through electrodes formed on each substrate. <31> A back-illuminated solid-state imaging device as described in <27>, wherein a supporting substrate is connected to the back side of the second semiconductor element and the third semiconductor element relative to the incident light, and the interconnection wiring is formed on the supporting substrate. <32> A back-illuminated solid-state imaging device as described in <26>, wherein the interconnection wiring is formed on the back side of the second semiconductor element and the third semiconductor element relative to the incident direction of the incident light. <33> A back-illuminated solid-state imaging device as described in <32>, wherein the interconnection wiring is formed on the front surface of the supporting substrate on the back side of the second semiconductor element and the third semiconductor element relative to the incident direction of the incident light.

1: Solid state imaging device 10: On-chip lens and on-chip color filter 11: Solid state imaging element 12: Memory circuit 13: Logic circuit 14: Support substrate 21-1: Wiring 21-2: Wiring 31: Bump 101: Wafer 102: Wafer 103: Wafer 104: Wafer 111: Solid state imaging device 120: Solid state imaging element 120a: Wiring 120b: Pad 120b-1: Pad 120b-2: Pad 120b-3: Pad 120b-4: Pad 120b-11: Pad 120b-12: Pad 120b-13: Pad Pad 120b-14: pad 120c: wiring 120c-1: wiring 120c-2: wiring 120c-3: wiring 120c-11: wiring 120c-12: wiring 120c-13: wiring 120c-14: wiring 121: memory circuit 121-1: memory circuit 121-2: memory circuit 121a: wiring 121a-1: wiring 121a-2: wiring 121a-3: wiring 121a-4: wiring 121a-11: wiring 121a-12: wiring 121a-13: wiring 121a-14: wiring Line 121b: Pad 121b': Pad 121b-1: Pad 121b-2: Pad 121b-3: Pad 121b-4: Pad 121b-11: Pad 121b-12: Pad 121b-13: Pad 121b-14: Pad 121c: Wiring 121c': Wiring 121c-1: Wiring 121c-2: Wiring 121c-3: Wiring 121c-4: Wiring 121c-11: Wiring 121c'-11: Wiring 121c-12: Wiring 121c-13: Wiring 121c-14: Wiring 1 21d: through electrode 121d': through electrode 121e: groove 121e': groove 121f: through hole 121f': through hole 121M: Si oxide film 122: logic circuit 122a: wiring 122a-1: wiring 122a-2: wiring 122a-3: wiring 122a-4: wiring 122a-11: wiring 122a-12: wiring 122a-13: wiring 122a-14: wiring 122b: solder pad 122b': solder pad 122b-1: solder pad 122b-2: solder pad 122b-3: solder pad 122 b-4: solder pad 122b-11: solder pad 122b-12: solder pad 122b-13: solder pad 122b-14: solder pad 122c: wiring 122c': wiring 122c-1: wiring 122c-2: wiring 122c-11: wiring 122c'-11: wiring 122c-12: wiring 122d: through electrode 122d': through electrode 122e: groove 122e': groove 122f: through hole 122f': through hole 122L: Si oxide film 131: color filter and crystal lens 132: support substrate 13 2a: Wiring 132b: Solder pad 133: Oxide film 134: Wiring 134-1: Wiring 134-2: Wiring 134A: Wiring 134B: Wiring 134C: Wiring 134D: Wiring 134E: Wiring 134F: Wiring 134G: Wiring 134H: Wiring 135: Oxide film bonding layer 151: Reconfiguration substrate 152: Adhesive 161: Support substrate 171: Support substrate 201: Memory element substrate 201a: Wiring 201b: Solder pad 201b': Solder pad 201c: Wiring 201d: Through electrode 221: Insulation film 22 2: groove 223: through hole 223': through hole 224: through hole 224': through hole 231: through electrode 232: through electrode 241: organic photoelectric conversion film 251: through electrode 252: through electrode 261: support substrate 261a: wiring 261b: terminal 261b': terminal 271: joint 272: wire 281: lens 282: through hole 291: through electrode 301: through electrode 311: support substrate 312: interference portion 371: through electrode 381: through electrode 391: through electrode 401: through electrode 402 :Through electrode 501: Camera device 502: Optical system 503: Shutter device 504: Solid-state imaging element 505: Driving circuit 506: Signal processing circuit 507: Monitor 508: Memory 11000: Endoscopic surgery system 11100: Endoscope 11101: Barrel 11102: Camera lens 11110: Surgical instrument 11111: Insufflation tube 11112: Energy surgical instrument 11120: Support arm device 11131: Surgeon 11132: Patient 11133: Bed 11200: Trolley 11201: CCU 11202: display device 11203: light source device 11204: input device 11205: surgical instrument control device 11206: pneumoperitoneum device 11207: recorder 11208: printer 11400: transmission cable 11401: lens unit 11402: imaging unit 11403: drive unit 11404: communication unit 11405: camera lens control unit 11411: communication unit 11412: image processing unit 11403: drive unit 11404: communication unit 11405: camera lens control unit 11412: image processing unit 11413: image processing unit 11414: image processing unit 11415: image processing unit 11416: image processing unit 11417: image processing unit 11418: image processing unit 11419: image processing unit 11420: image processing unit 11421: image processing unit 11422: image processing unit 11423: image processing unit 11424: image processing unit 11425: image processing unit 11426: image processing unit 11427: image processing unit 11428: image processing unit 11429: image processing unit 11429: image processing unit 11421: image processing unit 11429: image processing unit 11421: image processing unit 11423: image processing unit 11424: image processing unit 11425: image processing unit 11426: image processing unit 11427: image processing unit 11428: image processing unit 11429: image processing unit 11429: image processing unit 11429: image processing unit 11429: image processing unit 11429: image processing unit 11429 413: Control unit 12000: Vehicle control system 12001: Communication network 12010: Drive system control unit 12020: Body system control unit 12030: External information detection unit 12031: Camera unit 12040: Internal information detection unit 12041: Driver status detection unit 12050: Integrated control unit 12051: Microcomputer 12052: Sound and image output unit 12053: In-vehicle network I/F 12061: Speaker 12062: Display 12063: Instrument panel 12100: Vehicle 12101: Camera 12102: Camera 12103: Camera 12104: Camera 12105: Camera 12111: Camera range 12112: Camera range 12113: Camera range 12114: Camera range A: Height A: Distance B: Distance C: Measurement terminal d1: Connection distance d2: Connection distance E1: Semiconductor element layer E2: Semiconductor element layer F1: Connection Joint surface F2: Joint surface F4-1: Joint surface F4-2: Joint surface F5-1: Joint surface F5-2: Joint surface KD: Step difference LD: Embedding step difference MD: Embedding step difference T: Interconnection wiring T': Interconnection wiring T'': Interconnection wiring T''': Interconnection wiring T1: Interconnection wiring T2: Interconnection wiring T3: Interconnection wiring T4: Interconnection wiring T5: Interconnection wiring T6: Interconnection wiring Te: Groove Te': Groove TCV1: Through electrode TCV2: Through electrode W1: Wafer W2: Wafer W3: Wafer Z ₁ : Space Z ₂ : Space

FIG. 1 is a diagram for explaining the yield rate. FIG. 2 is a diagram for explaining the reduction of theoretical yield. FIG. 3 is a diagram for explaining the connection using bumps. FIG. 4 is a diagram for explaining the outline of the method for manufacturing the solid-state imaging device of the first embodiment of the present invention. FIG. 5 is a diagram for explaining the configuration example of the solid-state imaging device of the first embodiment of the present invention. FIG. 6 is a diagram for explaining the method for manufacturing the solid-state imaging device of FIG. 5. FIG. 7 is a diagram for explaining the method for manufacturing the solid-state imaging device of FIG. 5. FIG. 8 is a diagram for explaining the method for manufacturing the solid-state imaging device of FIG. 5. FIG. 9 is a diagram for explaining the method for manufacturing the solid-state imaging device of FIG. 5. FIG. 10 is a diagram illustrating an example of the interconnection wiring of the memory circuit and the logic circuit in the solid-state imaging device of the first embodiment of the present invention. FIG. 11 is a diagram illustrating the peripheral structure of the interconnection wiring of the memory circuit and the logic circuit in the solid-state imaging device of FIG. 10. FIG. 12 is a diagram illustrating an example of the structure of the solid-state imaging device of the second embodiment of the present invention. FIG. 13 is a diagram illustrating the peripheral structure of the interconnection wiring of the memory circuit and the logic circuit in the solid-state imaging device of FIG. 12. FIG. 14 is a flow chart illustrating a method for manufacturing the solid-state imaging device of FIG. 12. FIG. 15 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 12. FIG. 16 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 12. FIG. 17 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 12. FIG. 18 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 12. FIG. 19 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 12. FIG. 20 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 12. FIG. 21 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 12. FIG. 22 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 12. FIG. 23 is a diagram for explaining an application example of the solid-state imaging device of the second embodiment of the present invention. FIG. 24 is a diagram for explaining an example of the configuration of the solid-state imaging device of the third embodiment of the present invention. FIG. 25 is a flow chart for explaining a method for manufacturing the solid-state imaging device of FIG. 24. FIG. 26 is a diagram for explaining an example of the configuration of the solid-state imaging device of the fourth embodiment of the present invention. FIG. 27 is a flow chart for explaining a method for manufacturing the solid-state imaging device of FIG. 26. FIG. 28 is a diagram for explaining a method for manufacturing the solid-state imaging device of FIG. 26. FIG. 29 is a diagram for explaining a method for manufacturing the solid-state imaging device of FIG. 26. FIG. 30 is a diagram for explaining a method for manufacturing the solid-state imaging device of FIG. 26. FIG. 31 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 26. FIG. 32 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 26. FIG. 33 is a diagram illustrating a configuration example of the solid-state imaging device of the fifth embodiment of the present invention. FIG. 34 is a flow chart illustrating a method for manufacturing the solid-state imaging device of FIG. 33. FIG. 35 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 33. FIG. 36 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 33. FIG. 37 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 33. FIG. 38 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 33. FIG. 39 is a diagram illustrating an example of the configuration of the solid-state imaging device of the sixth embodiment of the present invention. FIG. 40 is a flow chart illustrating a method for manufacturing the solid-state imaging device of FIG. 39. FIG. 41 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 39. FIG. 42 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 39. FIG. 43 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 39. FIG. 44 is a diagram illustrating a method for manufacturing the solid-state imaging device of the seventh embodiment of the present invention. FIG. 45 is a diagram illustrating a method for manufacturing the solid-state imaging device of the seventh embodiment of the present invention. FIG. 46 is a diagram illustrating a method for manufacturing the solid-state imaging device of the seventh embodiment of the present invention. FIG. 47 is a diagram illustrating an example of the configuration of the solid-state imaging device of the eighth embodiment of the present invention. FIG. 48 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 47. FIG. 49 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 47. FIG. 50 is a diagram illustrating an example of the configuration of the solid-state imaging device of the ninth embodiment of the present invention. FIG. 51 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 50. FIG. 52 is a diagram illustrating a method for manufacturing the solid-state imaging device of FIG. 50. FIG. 53 is a diagram illustrating an effect of the solid-state imaging device of FIG. 50. FIG. 54 is a diagram illustrating an application example of the solid-state imaging device of the ninth embodiment of the present invention. FIG. 55 is a diagram illustrating a configuration example of a solid-state imaging device according to the tenth embodiment of the present invention. FIG. 56 is a diagram illustrating a method for manufacturing the solid-state imaging device according to FIG. 55. FIG. 57 is a diagram illustrating a method for manufacturing the solid-state imaging device according to FIG. 55. FIG. 58 is a diagram illustrating a first application example of the method for manufacturing the solid-state imaging device according to the tenth embodiment of the present invention. FIG. 59 is a diagram illustrating a first application example of the method for manufacturing the solid-state imaging device according to the tenth embodiment of the present invention. FIG. 60 is a diagram illustrating a first application example of the method for manufacturing the solid-state imaging device according to the tenth embodiment of the present invention. FIG. 61 is a diagram illustrating a second application example of the manufacturing method of the solid-state imaging device of the tenth embodiment of the present invention. FIG. 62 is a block diagram showing an example of the configuration of an imaging device as an electronic device to which the imaging device of the present invention is applied. FIG. 63 is a diagram illustrating an example of the use of the imaging device to which the technology of the present invention is applied. FIG. 64 is a diagram showing an example of the schematic configuration of an endoscopic surgery system. FIG. 65 is a block diagram showing an example of the functional configuration of a camera lens and a CCU. FIG. 66 is a block diagram showing an example of the schematic configuration of a vehicle control system. FIG. 67 is an explanatory diagram showing an example of the installation position of the vehicle external information detection unit and the imaging unit.

111: Solid-state imaging device

120: Solid-state imaging device

120a: Wiring

121:Memory circuit

121a: Wiring

122:Logic circuit

122a: Wiring

131: Crystal-mounted lens and crystal-mounted color filter

132: Support substrate

133: Oxide film

134: Wiring

135: Oxide film bonding layer

E1: semiconductor device layer

E2: semiconductor device layer

Claims (27)

A back-illuminated solid-state imaging device comprises: a first semiconductor element having an imaging element that generates pixel signals in pixel units; a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, and in which signal processing circuits required for signal processing of the pixel signals are embedded by embedded components; and interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element; wherein the second semiconductor element and the third semiconductor element are laminated on the back side of the first semiconductor element relative to the incident direction of incident light, and the interconnection wiring is formed on the second semiconductor element and the third semiconductor element side relative to the boundary between the first semiconductor element and the second semiconductor element and the third semiconductor element. As in claim 1, the back-illuminated solid-state imaging device, wherein the interconnection wiring is formed on the side of the first semiconductor element relative to the boundary between the first semiconductor element, the second semiconductor element, and the third semiconductor element. A back-illuminated solid-state imaging device as claimed in claim 1, wherein the interconnection wiring is formed on the surface of the second semiconductor element and the third semiconductor element that is opposite to the incident direction of the incident light. A back-illuminated solid-state imaging device as claimed in claim 3, wherein the surfaces on which the wiring is formed of the second semiconductor element and the third semiconductor element are formed on the surface opposite to the incident direction of the incident light. As in claim 3, the back-illuminated solid-state imaging device, wherein the surfaces on which the wiring is formed of the second semiconductor element and the third semiconductor element are formed on the back side relative to the incident direction of the incident light. As in claim 5, the back-illuminated solid-state imaging device, wherein the surfaces of the second semiconductor element and the third semiconductor element on which wiring is formed are formed on the back side relative to the incident direction of the incident light, and the interconnection wiring is formed through through electrodes formed on each substrate. As in claim 3, a back-illuminated solid-state imaging device, wherein a supporting substrate is connected to the back side of the second semiconductor element and the third semiconductor element relative to the incident light, and the interconnection wiring is formed on the supporting substrate. A back-illuminated solid-state imaging device as claimed in claim 1, wherein the interconnection wiring is formed on the back side of the second semiconductor element and the third semiconductor element relative to the incident direction of the incident light. A back-illuminated solid-state imaging device as claimed in claim 8, wherein the interconnection wiring is formed on the front surface of the supporting substrate on the back side of the second semiconductor element and the third semiconductor element relative to the incident direction of the incident light. As in claim 1, the back-illuminated solid-state imaging device, wherein the second semiconductor element and the third semiconductor element are electrically connected to the first semiconductor element via a through electrode penetrating the first semiconductor element. As in claim 1, the back-illuminated solid-state imaging device, wherein the first semiconductor element, the second semiconductor element, and the third semiconductor element are stacked in the order of the first semiconductor element, the second semiconductor element, and the third semiconductor element relative to the incident direction of the incident light, and the solder pads formed by electrical connection with the bonding surfaces of the second semiconductor element and the third semiconductor element facing each other function as the interconnection wiring. As in claim 1, the back-illuminated solid-state imaging device, wherein the first semiconductor element, the second semiconductor element, and the third semiconductor element are stacked in the order of the first semiconductor element, the second semiconductor element, and the third semiconductor element relative to the incident direction of the incident light, and at least the second semiconductor element and the third semiconductor element are electrically connected by a through electrode, thereby functioning as an interconnection wiring. A back-illuminated solid-state imaging device as claimed in claim 1, wherein a supporting substrate is connected to the back side of the second semiconductor element and the third semiconductor element relative to the incident light, and the wiring of at least any one of the first semiconductor element, the second semiconductor element, and the third semiconductor element is connected by a through electrode and led to the back side of the supporting substrate relative to the incident direction of the incident light. As in claim 1, the back-illuminated solid-state imaging device, wherein the interconnection wiring is arranged within the range of the shadow of the first semiconductor element relative to the incident direction of the incident light when observed from a direction perpendicular to the substrate. A back-illuminated solid-state imaging device as claimed in claim 2, wherein a supporting substrate is connected to the back side of the second semiconductor element and the third semiconductor element relative to the incident light, and wiring is formed on the supporting substrate, the wiring of the supporting substrate is connected to the wiring of at least any one of the first semiconductor element, the second semiconductor element, and the third semiconductor element through a through electrode, and a terminal for leading out a signal line is formed on the outer side of the supporting substrate where the second semiconductor element and the third semiconductor element are formed. A camera device having a back-illuminated solid-state camera device, the back-illuminated solid-state camera device comprising: a first semiconductor element having an imaging element that generates a pixel signal in pixel units; a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element and in which a signal processing circuit required for signal processing of the pixel signal is embedded in an embedded component; and interconnection wiring that connects the second semiconductor element to the third semiconductor element. The semiconductor element and the third semiconductor element are electrically connected to each other; wherein the second semiconductor element and the third semiconductor element are laminated on the back side of the first semiconductor element relative to the incident direction of the incident light, and the interconnection wiring is formed on the side of the second semiconductor element and the third semiconductor element relative to the boundary between the first semiconductor element and the second semiconductor element and the third semiconductor element. An electronic device having a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising: a first semiconductor element having an imaging element that generates a pixel signal in pixel units; a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element and in which a signal processing circuit required for signal processing of the pixel signal is embedded by an embedded component; and interconnection wiring that connects the first semiconductor element to the third semiconductor element. 2 semiconductor elements and the third semiconductor element; wherein the second semiconductor element and the third semiconductor element are laminated on the back side of the first semiconductor element relative to the incident direction of the incident light, and the interconnection wiring is formed on the side of the second semiconductor element and the third semiconductor element relative to the boundary between the first semiconductor element and the second semiconductor element and the third semiconductor element. A method for manufacturing a back-illuminated solid-state imaging device, the back-illuminated solid-state imaging device comprising: a first semiconductor element having an imaging element that generates a pixel signal in pixel units; a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, and in which a signal processing circuit required for signal processing of the pixel signal is embedded in an embedded component; and interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element; wherein the second semiconductor element and the third semiconductor element are laminated on the back side of the first semiconductor element relative to the incident direction of incident light, and the interconnection wiring is formed relative to the boundary between the first semiconductor element and the second semiconductor element and the third semiconductor element. On the side of the second semiconductor element and the third semiconductor element; and the manufacturing method of the back-illuminated solid-state imaging device is to arrange the second semiconductor element and the third semiconductor element formed by the semiconductor process in the signal processing circuit, and to bury the second semiconductor element and the third semiconductor element judged as good by electrical inspection in the wafer having the imaging element formed by the semiconductor process, and to bury them by the embedded component to form interconnection wiring that electrically connects the second semiconductor element and the third semiconductor element, and to bond the oxide film in a manner that electrically connects the wiring between the first semiconductor element and the second semiconductor element and the third semiconductor element, and then to single-chip. A back-illuminated solid-state imaging device comprises: a first semiconductor element layer having an imaging element that generates pixel signals in pixel units; a second semiconductor element layer having a second semiconductor element and a third semiconductor element, wherein the second semiconductor element and the third semiconductor element are smaller than the imaging element, and a signal processing circuit required for signal processing of the pixel signal is embedded in an embedded component; and a supporting substrate; the second semiconductor element layer is disposed between the first semiconductor element layer and the supporting substrate, and the first semiconductor element layer is disposed between the first semiconductor element layer and the supporting substrate. The body element layer and the second semiconductor element layer are bonded by direct bonding; and the interconnection wiring for electrically connecting the second semiconductor element and the third semiconductor element is provided on the support substrate; the second semiconductor element and the third semiconductor element are laminated on the back surface of the imaging element relative to the incident direction of the incident light, and the interconnection wiring is formed on the side of the second semiconductor element and the third semiconductor element relative to the boundary between the imaging element and the second semiconductor element and the third semiconductor element. As in claim 19, the back-illuminated solid-state imaging device, wherein the supporting substrate further has a wiring layer on the side of the second semiconductor element layer, and the interconnecting wiring is arranged on the wiring layer of the supporting substrate. As in claim 19, the back-illuminated solid-state imaging device, wherein the interconnection wiring is formed on the surface of the second semiconductor element and the third semiconductor element that is opposite to the incident direction of the incident light. As in claim 21, the back-illuminated solid-state imaging device, wherein the surfaces on which the wiring is formed of the second semiconductor element and the third semiconductor element are formed on the surface opposite to the incident direction of the incident light. As in claim 21, the back-illuminated solid-state imaging device, wherein the surfaces on which the wiring is formed of the second semiconductor element and the third semiconductor element are formed on the back side relative to the incident direction of the incident light. As in claim 23, the back-illuminated solid-state imaging device, wherein the surfaces of the second semiconductor element and the third semiconductor element on which wiring is formed are formed on the back side relative to the incident direction of the incident light, and the interconnection wiring is formed through through electrodes formed on each substrate. As in claim 21, a back-illuminated solid-state imaging device, wherein a supporting substrate is connected to the back side of the second semiconductor element and the third semiconductor element relative to the incident light, and the interconnection wiring is formed on the supporting substrate. As in claim 19, the back-illuminated solid-state imaging device, wherein the interconnection wiring is formed on the back side of the second semiconductor element and the third semiconductor element relative to the incident direction of the incident light. A back-illuminated solid-state imaging device as claimed in claim 26, wherein the interconnection wiring is formed on the front surface of the supporting substrate on the back side of the second semiconductor element and the third semiconductor element relative to the incident direction of the incident light.