TWI866658B - Magnetic memory structure - Google Patents

Abstract

A magnetic memory structure including a substrate and memory cells is provided. The memory cells are stacked on the substrate. Each of the memory cells includes a transistor, a first electrode layer, a magnetic tunnel junction (MTJ) structure, and a second electrode layer. The transistor includes a channel layer, a gate, and a gate dielectric layer. The channel layer has a first side and a second side opposite to each other. The gate is located on the first side of the channel layer. The gate dielectric layer is located between the gate and the channel layer. The first electrode layer, the MTJ structure, and the second electrode layer are located on the second side of the channel layer. The first electrode layer, the MTJ structure, and the second electrode layer are connected to the channel layer. The MTJ structure is located between the first electrode layer and the second electrode layer.

Description

Magnetic memory structure

The present invention relates to a memory structure, and in particular to a magnetic memory structure.

Magnetic memory has attracted more and more attention due to its advantages such as fast read and write speed, excellent durability, non-volatility and low power consumption. However, how to further reduce the size of memory cells, increase the density of memory cells and reduce the manufacturing cost is a continuous goal.

The present invention provides a magnetic memory structure which can effectively reduce the size of memory cells, increase the density of memory cells and reduce the manufacturing cost.

The present invention proposes a magnetic memory structure, including a substrate and a plurality of memory cells. The plurality of memory cells are stacked on the substrate. Each memory cell includes a transistor, a first electrode layer, a magnetic tunnel junction (MTJ) structure and a second electrode layer. The transistor includes a channel layer, a gate and a gate dielectric layer. The channel layer has a first side and a second side opposite to each other. The gate is located on the first side of the channel layer. The gate dielectric layer is located between the gate and the channel layer. The first electrode layer, the magnetic tunnel junction structure and the second electrode layer are located on the second side of the channel layer. The first electrode layer, the magnetic tunneling junction structure and the second electrode layer are connected to the channel layer. The magnetic tunneling junction structure is located between the first electrode layer and the second electrode layer.

According to an embodiment of the present invention, in the magnetic memory structure, the transistor and the magnetic tunneling junction structure can be connected in parallel via the first electrode layer and the second electrode layer.

According to an embodiment of the present invention, in the magnetic memory structure, a plurality of memory cells can share a channel layer.

According to an embodiment of the present invention, in the magnetic memory structure, the plurality of memory cells may include a plurality of transistors. The plurality of transistors may be stacked on a substrate. The plurality of transistors may include a plurality of gates. The plurality of gates may be separated from each other.

According to an embodiment of the present invention, in the magnetic memory structure, the plurality of memory cells may include a plurality of magnetic tunneling junction structures. The plurality of magnetic tunneling junction structures may be stacked on a substrate. The plurality of magnetic tunneling junction structures may be separated from each other.

According to an embodiment of the present invention, in the magnetic memory structure, the first electrode layer, the magnetic tunneling junction structure and the second electrode layer can directly contact the channel layer.

According to an embodiment of the present invention, in the magnetic memory structure, the magnetic tunneling junction structure may include a reference layer, a barrier layer and a free layer. The reference layer, the barrier layer and the free layer may be stacked on a substrate.

According to an embodiment of the present invention, in the magnetic memory structure, two adjacent memory cells can share a first electrode layer.

According to an embodiment of the present invention, in the magnetic memory structure, two adjacent memory cells can share the second electrode layer.

According to an embodiment of the present invention, the magnetic memory structure may further include a first selection transistor and a second selection transistor. Multiple memory cells may include multiple transistors. The first selection transistor, multiple transistors and the second selection transistor may be stacked on the substrate in sequence. The first selection transistor may include a first selection gate, a channel layer and a gate dielectric layer. The first selection gate is located on the first side of the channel layer. The gate dielectric layer may be located between the first selection gate and the channel layer, and the second selection transistor may include a second selection gate, a channel layer and a gate dielectric layer. The second selection gate is located on the first side of the channel layer. The gate dielectric layer may be located between the second selection gate and the channel layer. The first selection gate, the second selection gate, and the plurality of gates may be separated from each other.

Based on the above, in the magnetic memory structure proposed in the present invention, multiple memory cells are stacked on a substrate. Each memory cell includes a transistor, a first electrode layer, a magnetic tunneling junction structure and a second electrode layer. The transistor includes a channel layer, a gate and a gate dielectric layer. The gate is located on the first side of the channel layer. The first electrode layer, the magnetic tunneling junction structure and the second electrode layer are located on the second side of the channel layer and are connected to the channel layer. The magnetic tunneling junction structure is located between the first electrode layer and the second electrode layer. Therefore, the magnetic memory structure proposed by the present invention can be a three-dimensional magnetic memory structure, thereby effectively reducing the size of memory cells, increasing the density of memory cells and reducing the manufacturing cost.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The following examples are listed and illustrated in detail, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be indicated by the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size. In fact, the size of various features can be arbitrarily increased or decreased for the sake of clarity.

FIG1 is a cross-sectional view of a magnetic memory structure according to some embodiments of the present invention. FIG2 is a schematic diagram of performing an erase operation on the magnetic memory structure of FIG1. FIG3 is a schematic diagram of performing a programming operation on the magnetic memory structure of FIG1. FIG4 is a schematic diagram of performing a read operation on the magnetic memory structure of FIG1.

Referring to FIG. 1 , the magnetic memory structure 10 includes a substrate 100 and a plurality of memory cells MC. In some embodiments, the magnetic memory structure 10 may be a spin transfer torque magnetic random access memory (STT-MRAM) structure. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, although not shown in the figure, the substrate 100 may have required components (e.g., doping regions such as source regions or drain regions), and the description thereof is omitted here.

A plurality of memory cells MC are stacked on a substrate 100. Each memory cell MC includes a transistor 102, an electrode layer 104, a magnetic tunneling junction structure 106, and an electrode layer 108. The transistor 102 and the magnetic tunneling junction structure 106 may be connected in parallel. In this embodiment, the transistor 102 and the magnetic tunneling junction structure 106 may be connected in parallel via the electrode layer 104 and the electrode layer 108.

The transistor 102 includes a channel layer 110, a gate 112, and a gate dielectric layer 114. The channel layer 110 has a first side S1 and a second side S2 opposite to each other. A plurality of memory cells MC may share the channel layer 110. In some embodiments, the material of the channel layer 110 is, for example, polysilicon. The gate 112 is located at the first side S1 of the channel layer 110. In some embodiments, the material of the gate 112 may be a conductive material, such as tungsten, titanium, titanium nitride, or a combination thereof. The gate dielectric layer 114 is located between the gate 112 and the channel layer 110. In some embodiments, the material of the gate dielectric layer 114 is, for example, silicon oxide.

The plurality of memory cells MC may include a plurality of transistors 102. The plurality of transistors 102 may be stacked on the substrate 100. The plurality of transistors 102 may include a plurality of gates 112. The plurality of gates 112 may be separated from each other. The plurality of transistors 102 may share a channel layer 110. In some embodiments, the plurality of transistors 102 may share a gate dielectric layer 114.

The electrode layer 104, the magnetic tunneling junction structure 106, and the electrode layer 108 are located at the second side S2 of the channel layer 110. The electrode layer 104, the magnetic tunneling junction structure 106, and the electrode layer 108 are connected to the channel layer 110. The magnetic tunneling junction structure 106 is located between the electrode layer 104 and the electrode layer 108. In some embodiments, the electrode layer 104, the magnetic tunneling junction structure 106, and the electrode layer 108 can directly contact the channel layer 110. In some embodiments, two adjacent memory cells MC can share the electrode layer 104. In some embodiments, two adjacent memory cells MC may share the electrode layer 108. In some embodiments, the material of the electrode layer 104 and the electrode layer 108 may be a conductive material, such as tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), or molybdenum (Mo).

The magnetic tunneling junction structure 106 may include a reference layer 116, a barrier layer 118, and a free layer 120. The reference layer 116, the barrier layer 118, and the free layer 120 may be stacked on the substrate 100. In this embodiment, as shown in FIG. 1 , the reference layer 116, the barrier layer 118, and the free layer 120 may be sequentially stacked on the substrate 100. In other embodiments, although not shown in the figure, the free layer 120, the barrier layer 118, and the reference layer 116 may be sequentially stacked on the substrate 100. In some embodiments, the reference layer 116, the barrier layer 118, and the free layer 120 may directly contact the channel layer 110. In some embodiments, the material of the reference layer 116 is, for example, cobalt iron boron (CoFeB), cobalt (Co), palladium (Pd), nickel (Ni), cobalt iron (CoFe), or platinum (Pt). In some embodiments, the material of the barrier layer 118 is, for example, magnesium oxide (MgO) or aluminum oxide (AlO). In some embodiments, the material of the free layer 120 is, for example, cobalt iron carbon (CoFeC), cobalt iron (CoFe), or cobalt iron boron (CoFeB).

The plurality of memory cells MC may include a plurality of magnetic tunneling junction structures 106. The plurality of magnetic tunneling junction structures 106 may be stacked on the substrate 100. The plurality of magnetic tunneling junction structures 106 may be separated from each other.

The magnetic memory structure 10 may further include a selection transistor 122 and a selection transistor 124. The selection transistor 122, the plurality of transistors 102, and the selection transistor 124 may be sequentially stacked on the substrate 100.

The selection transistor 122 may include a selection gate 126, a channel layer 110, and a gate dielectric layer 114. The selection gate 126 is located at the first side S1 of the channel layer 100. The gate dielectric layer 114 may be located between the selection gate 126 and the channel layer 110. The selection transistor 122 and the plurality of transistors 102 may share the channel layer 110. In some embodiments, the selection transistor 122 and the plurality of transistors 102 may share the gate dielectric layer 114. In some embodiments, the material of the selection gate 126 may be a conductive material, such as tungsten, titanium, titanium nitride, or a combination thereof.

The select transistor 124 may include a select gate 128, a channel layer 110, and a gate dielectric layer 114. The select gate 128 is located at the first side S1 of the channel layer 100. The select gate 126, the select gate 128, and the plurality of gates 112 may be separated from each other. The gate dielectric layer 114 may be located between the select gate 128 and the channel layer 110. The select transistor 124 and the plurality of transistors 102 may share the channel layer 110. In some embodiments, the select transistor 122, the select transistor 124, and the plurality of transistors 102 may share the channel layer 110. In some embodiments, the select transistor 124 and the plurality of transistors 102 may share the gate dielectric layer 114. In some embodiments, the select transistor 122, the select transistor 124 and the plurality of transistors 102 may share the gate dielectric layer 114. In some embodiments, the material of the select gate 128 may be a conductive material, such as tungsten, titanium, titanium nitride or a combination thereof.

The magnetic memory structure 10 may further include a plurality of dielectric layers 130. The plurality of dielectric layers 130 may be located between the plurality of gates 112, between the bottom gate 112 and the select gate 126, between the top gate 112 and the select gate 128, between the bottom electrode layer 104 and the substrate 100, on the select gate 128, and on the top electrode layer 104. The materials of the plurality of dielectric layers 130 may be the same or different from each other. In some embodiments, the material of the dielectric layer 130 is, for example, silicon oxide.

In addition, although not shown in the figure, the magnetic memory structure 10 may further include other required components (such as source lines and bit lines, etc.), and their description is omitted here.

The operation method of the magnetic memory structure 10 of the above embodiment is described below with reference to FIG. 2 to FIG. 4 .

In the following embodiments, one end of the channel layer 110 adjacent to the select transistor 122 may be electrically connected to a source line (not shown), and one end of the channel layer 110 adjacent to the select transistor 124 may be electrically connected to a bit line (not shown).

Referring to FIG. 2 , the method for performing an erase operation on the selected memory cell MC1 may include the following steps. A voltage of 0.5V is applied to the source line, and a voltage of 0V is applied to the bit line. In addition, the transistor 102a of the memory cell MC1 is turned off, and the selection transistor 122, the selection transistor 124, and the transistors 102 of the remaining memory cells MC are turned on. In this way, the electron current EC1 can flow through the magnetic tunneling junction structure 106a of the memory cell MC1, so that the magnetic moment of the reference layer 116 and the magnetic moment of the free layer 120 are in an antiparallel state, whereby the magnetic tunneling junction structure 106a can be in a high resistance state (HRS). In some embodiments, all memory cells MC may be erased, that is, all magnetic tunneling junction structures 106 may be in a high resistance state (HRS). In some embodiments, when the magnetic tunneling junction structure 106 is in a high resistance state, the memory cell MC may be considered to store the first data (eg, data "0").

Referring to FIG. 3 , the method for programming the selected memory cell MC1 may include the following steps. A voltage of 0V is applied to the source line, and a voltage of 0.5V is applied to the bit line. In addition, the transistor 102a of the memory cell MC1 is turned off, and the selection transistor 122, the selection transistor 124, and the transistors 102 of the remaining memory cells MC are turned on. In this way, the electron current EC2 can flow through the magnetic tunneling junction structure 106a of the memory cell MC1, so that the magnetic moment of the reference layer 116 and the magnetic moment of the free layer 120 are flipped from the antiparallel state to the parallel state, whereby the magnetic tunneling junction structure 106a can be in a low resistance state (LRS). In some embodiments, when the magnetic tunneling junction structure 106 is in a low resistance state, the memory cell MC can be regarded as storing the second data (eg, data “1”).

Referring to FIG. 4 , the method for performing a read operation on the selected memory cell MC1 may include the following steps. A voltage of 0V is applied to the source line, and a voltage of 0.2V is applied to the bit line. In addition, the transistor 102a of the memory cell MC1 is turned off, and the selection transistor 122, the selection transistor 124, and the transistors 102 of the remaining memory cells MC are turned on. In this way, the electron current EC3 can flow through the magnetic tunneling junction structure 106a of the memory cell MC1, thereby reading the data stored in the magnetic tunneling junction structure 106a.

Based on the above, in the magnetic memory structure 10, a plurality of memory cells MC are stacked on the substrate 100. Each memory cell MC includes a transistor 102, an electrode layer 104, a magnetic tunneling junction structure 106, and an electrode layer 108. The transistor 102 includes a channel layer 110, a gate 112, and a gate dielectric layer 114. The gate 112 is located at a first side S1 of the channel layer 110. The electrode layer 104, the magnetic tunneling junction structure 106, and the electrode layer 108 are located at a second side S2 of the channel layer 110 and are connected to the channel layer 110. The magnetic tunneling junction structure 106 is located between the electrode layer 104 and the electrode layer 108. Therefore, the magnetic memory structure 10 can be a three-dimensional magnetic memory structure, thereby effectively reducing the size of the memory cell, increasing the density of the memory cell and reducing the manufacturing cost.

In summary, in the magnetic memory structure of the above-mentioned embodiment, a plurality of memory cells are stacked on a substrate. Each memory cell includes a transistor, a first electrode layer, a magnetic tunneling junction structure and a second electrode layer. The transistor includes a channel layer, a gate and a gate dielectric layer. The gate is located on the first side of the channel layer. The first electrode layer, the magnetic tunneling junction structure and the second electrode layer are located on the second side of the channel layer and are connected to the channel layer. The magnetic tunneling junction structure is located between the first electrode layer and the second electrode layer. Therefore, the magnetic memory structure of the above embodiment can be a three-dimensional magnetic memory structure, thereby effectively reducing the size of the memory cell, increasing the memory cell density and reducing the manufacturing cost.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10: Magnetic memory structure 100: Substrate 102,102a: Transistor 104: Electrode layer 106,106a: Magnetic tunneling junction structure 108: Electrode layer 110: Channel layer 112: Gate 114: Gate dielectric layer 116: Reference layer 118: Barrier layer 120: Free layer 122,124: Select transistor 126,128: Select gate 130: Dielectric layer EC1,EC2,EC3: Electron flow MC,MC1: Memory cell S1: First side S2: Second side

FIG. 1 is a cross-sectional view of a magnetic memory structure according to some embodiments of the present invention. FIG. 2 is a schematic diagram of performing an erase operation on the magnetic memory structure of FIG. 1 . FIG. 3 is a schematic diagram of performing a programming operation on the magnetic memory structure of FIG. 1 . FIG. 4 is a schematic diagram of performing a read operation on the magnetic memory structure of FIG. 1 .

10: Magnetic memory structure

100: Base

102: Transistor

104:Electrode layer

106: Magnetic tunneling junction structure

108:Electrode layer

110: Channel layer

112: Gate

114: Gate dielectric layer

116: Reference layer

118: Barrier layer

120: Free layer

122,124: Select transistor

126,128: Select gate

130: Dielectric layer

MC: Memory Cell

S1: First side

S2: Second side

Claims (10)

A magnetic memory structure comprises: a substrate; and a plurality of memory cells stacked on the substrate, wherein each of the memory cells comprises: a transistor comprising: a channel layer having a first side and a second side opposite to each other; a gate located on the first side of the channel layer; and a gate dielectric layer located between the gate and the channel layer; and a first electrode layer, a magnetic tunneling junction structure and a second electrode layer located on the second side of the channel layer and connected to the channel layer, wherein the magnetic tunneling junction structure is located between the first electrode layer and the second electrode layer. The magnetic memory structure as described in claim 1, wherein the transistor and the magnetic tunneling junction structure are connected in parallel via the first electrode layer and the second electrode layer. A magnetic memory structure as described in claim 1, wherein a plurality of the memory cells share the channel layer. A magnetic memory structure as described in claim 1, wherein the plurality of memory cells include a plurality of transistors, the plurality of transistors are stacked on the substrate, the plurality of transistors include a plurality of gates, and the plurality of gates are separated from each other. A magnetic memory structure as described in claim 1, wherein the plurality of memory cells include a plurality of magnetic tunneling junction structures, and the plurality of magnetic tunneling junction structures are stacked on the substrate and separated from each other. The magnetic memory structure as described in claim 1, wherein the first electrode layer, the magnetic tunneling junction structure and the second electrode layer directly contact the channel layer. A magnetic memory structure as described in claim 1, wherein the magnetic tunneling junction structure comprises: A reference layer, a barrier layer and a free layer, stacked on the substrate. The magnetic memory structure as described in claim 1, wherein two adjacent memory cells share the first electrode layer. The magnetic memory structure as described in claim 1, wherein two adjacent memory cells share the second electrode layer. The magnetic memory structure as described in claim 1 further includes: a first selection transistor and a second selection transistor, wherein a plurality of the memory cells include a plurality of the transistors, the first selection transistor, a plurality of the transistors and the second selection transistor are sequentially stacked on the substrate, the first selection transistor includes a first selection gate, the channel layer and the gate dielectric layer, the first selection gate is located on the first side of the channel layer, the gate dielectric layer is located between the first selection gate and the channel layer, the second selection transistor includes a second selection gate, the channel layer and the gate dielectric layer, the second selection gate is located on the first side of the channel layer, The gate dielectric layer is located between the second selection gate and the channel layer, and the first selection gate, the second selection gate and the plurality of gates are separated from each other.

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