TWI866591B - In-memory computing (imc) memory device and in-memory computing method - Google Patents

Abstract

An in-memory computing (IMC) memory device comprises a plurality of computing memory cells and a plurality of balance computing memory cells forming a plurality of memory strings. In programming, a first resistance state number of the balance computing memory cells is determined based on a first resistance state number of the computing memory cells of the memory string. In IMC operations, when a read voltage is applied to the computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents; the memory string currents charge a loading capacitor; a capacitor voltage of the loading capacitor is measured; and based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

Description

In-memory computing memory device and in-memory computing method

The present invention relates to an in-memory computing (IMC) memory device and an in-memory computing method.

For neural network computation and applications, vector-matrix multiplication, also known as perceptron operation, has been widely used. When implementing neural network computation in memory, weight values can be stored in a memory array and input values can be applied to the memory array to perform perceptron computation, thereby reducing power consumption and improving computational efficiency.

Due to the memory array architecture, the input values of sensor calculations or vector-matrix multiplication are usually input from the word line side or bit line side, and the calculation results are read out using sense amplifiers. Therefore, the number of input values will be limited by the size of the memory array and the total accumulated current of the sense amplifier.

Because the number of input values is limited, the current practice is to divide the input values into multiple input value groups and use multiple sense amplifiers to sense the individual currents of the input value groups. The reading results obtained by multiple different sense amplifiers must be summed up, but this summing up may cause reading errors and take more computing time and/or power consumption.

In addition, currently, there are two main architectures for evaluating in-memory computing (IMC) results, one is the sum-of-current architecture, and the other is the sum-of-voltage architecture.

For the existing current summing architecture, if the number of input values is too large, the summed current may be too high, so it is necessary to reduce the current of each unit cell or require a specially designed inductive amplifier. However, this will increase the design complexity.

For the existing voltage summing architecture, the resistance of each computational memory cell must be low in order to increase the induced current and reduce the body effect.

In addition, within a memory device, the weight values of each memory string may not be evenly distributed, which may reduce the linearity of the neural network calculation.

Therefore, there is a need for an in-memory computing (IMC) memory device and an in-memory computing method to improve the shortcomings of the current approach.

According to one aspect of the present invention, an in-memory computing (IMC) memory device is provided, comprising: a memory control circuit, and a memory array coupled to the memory control circuit. The memory array comprises: a plurality of computational memory cells and a plurality of balanced computational memory cells, forming a plurality of memory strings, wherein the computational memory cells store a plurality of weight values; a load capacitor coupled to the computational memory cells; and a measurement circuit coupled to the load capacitor. During programming, the memory control circuit determines the number of first impedance states of the balanced computational memory cells in the memory string according to the number of first impedance states of the computational memory cells in the memory string. When performing calculations, a plurality of input voltages are input to the calculation memory cells respectively, the input voltages are related to a plurality of input values, and the memory control circuit sets the input voltages according to the input values; a plurality of balanced input voltages are input to the balanced calculation memory cells respectively, the balanced input voltages are related to a plurality of balanced input values, the balanced input values are consistent input values, and the memory control circuit sets the balanced input voltages according to the balanced input values; a plurality of valid The impedance value is related to the input voltages and the weight values; when a read voltage is applied to the computational memory cells, the computational memory cells generate a plurality of memory cell currents, and the memory cell currents form a plurality of memory string currents; the memory string currents generated by the memory strings charge the load capacitor; the measuring circuit measures a capacitor voltage of the load capacitor; and, based on a relationship among the capacitor voltage of the load capacitor, at least a delay time and a predetermined voltage, a computation result of the input values and the weight values is determined.

According to another aspect of the present invention, an in-memory computing method is proposed and applied to an in-memory computing memory device, wherein the in-memory computing memory device includes a plurality of computing memory cells and a plurality of balancing computing memory cells constituting a plurality of memory strings. The in-memory calculation method includes: during programming, determining the number of first impedance states of the balanced computing memory cells in the memory string according to the number of first impedance states of the computing memory cells in the memory string; storing a plurality of weight values in a plurality of computing memory cells, the computing memory cells forming a plurality of memory strings; inputting a plurality of input voltages to the computing memory cells respectively, the input voltages being related to a plurality of input values, the plurality of effective impedance values of the computing memory cells being related to the input voltages and the weight values; inputting a plurality of balanced input voltages to the balanced computing memory cells respectively, the The balanced input voltage is related to a plurality of balanced input values, which are consistent input values, and the balanced input voltages are set according to the balanced input values; when a read voltage is applied to the computational memory cells, the computational memory cells generate a plurality of memory cell currents, and the memory cell currents form a plurality of memory string currents; the memory string currents generated by the memory strings charge the load capacitor; a capacitor voltage of the load capacitor is measured; and a computation result of the input values and the weight values is determined according to a relationship between the capacitor voltage of the load capacitor, at least a delay time and a predetermined voltage.

In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings:

The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the interpretation of these terms shall be subject to the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement part or all of the technical features in any embodiment, or selectively combine part or all of the technical features in these embodiments.

FIG. 1 shows a functional block diagram of an in-memory computing (IMC) memory device according to an embodiment of the present invention. The in-memory computing (IMC) memory device 10 according to an embodiment of the present invention includes a memory control circuit 20, a word line driver circuit 30, a bit line driver circuit 40 and a memory array 100. The memory control circuit 20 is used to control the word line driver circuit 30 and the bit line driver circuit 40 to output the word line driver voltage and the bit line driver circuit to the memory array 100. The operation and structure of the memory control circuit 20, the word line driver circuit 30, and the bit line driver circuit 40 are not particularly limited herein.

FIG. 2 shows a structural diagram of a memory array 100 of an in-memory computing memory device according to an embodiment of the present invention. As shown in FIG. 2, the memory array 100 of an in-memory computing (IMC) memory device according to an embodiment of the present invention includes: a plurality of computing memory cells C11-Cmn (m and n are positive integers), a plurality of balanced computing memory cells BC11-BCpn (p is a positive integer), a plurality of impedance elements RS1-RSn, a load capacitor C, and a measurement circuit 120. The computing memory cells C11-Cmn and the balanced computing memory cells BC11-BCpn are coupled to the load capacitor C and the measurement circuit 120. In one possible example, the measuring circuit 120 may be implemented by a sense amplifier. The measuring circuit 120 may compare the capacitance voltage VC of the load capacitor C with the reference voltage VREF.

The computing memory cells C11-Cmn are arranged in n vertical rows and m horizontal columns to perform in-memory computing (IMC). The balanced computing memory cells BC11-BCpn are arranged in n vertical rows and p horizontal columns to improve the performance of the in-memory computing (IMC) memory device according to an embodiment of the present invention when performing in-memory computing.

The computing memory cells and the balanced computing memory cells in each vertical row can form memory strings S1 to Sn. The memory string S1 includes computing memory cells C11, C21, ..., Cm1, balanced computing memory cells BC11, ... BCp1, and impedance element RS1. The rest can be deduced in the same way.

The computing memory cells C11 to Cmn receive input voltages V11 to Vmn, respectively. Specifically, the computing memory cells C11, C21, ..., Cm1 receive input voltages V11, V21, ..., Vm1, respectively; the computing memory cells C12, C22, ..., Cm2 receive input voltages V12, V22, ..., Vm2, respectively. The input voltages V11 to Vmn are related to a plurality of input values IN11 to INmn. The memory control circuit 20 sets the input voltages V11 to Vmn according to the input values IN11 to INmn.

The computational memory cells C11~Cmn store a plurality of weight values W11~Wmn.

The balanced computing memory cells BC11~BCpn receive balanced input voltages BV1~BVp respectively. Specifically, the balanced computing memory cells BC11, BC12...BC1n all receive balanced input voltage BV1, and the rest can be deduced accordingly. The input voltages BV1~BVp are related to a plurality of balanced input values BIN1~BINp. The memory control circuit 20 sets the balanced input voltages BV1~BVp according to the balanced input values BIN1~BINp. Furthermore, in an embodiment of the present case, the balanced computing memory cells BC11~BCpn electrically receive balanced input voltages BV1~BVp respectively. Although the balanced computing memory cells BC11-BC1n electrically receive the same balanced input voltage BV1, the balanced computing memory cells BC11-BC1n do not need to be physically connected in series. The balanced computing memory cells BC11-BC1n can also be distributed at different positions of the memory array 100, as long as the balanced computing memory cells BC11-BC1n can electrically receive the same balanced input voltage BV1. This is all within the spirit of the present invention.

The memory strings S1-Sn are connected in parallel. The memory string currents I1-In generated by the memory strings S1-Sn connected in parallel charge the load capacitor C.

In addition, the impedance elements RS1-RSn are selective elements.

In an embodiment of the present case, the computing memory cells C11-Cmn and the balanced computing memory cells BC11-BCpn can be programmed to be in a high impedance state or a low impedance state.

In an embodiment of the present case, in the programming stage, the operation memory cells C11~Cmn of the memory strings S1~Sn are programmed according to the IMC calculation to be executed by the in-memory computing memory device 10 according to an embodiment of the present case (that is, the operation memory cells C11~Cmn of the memory strings S1~Sn are programmed to a high impedance state or a low impedance state).

As for the programming stage, whether the balanced computing memory cells BC11-BCpn are programmed to a high impedance state or a low impedance state is determined according to the number of high impedance states of the computing memory cells C11-Cmn in the same memory string S1-Sn. That is, in the programming stage, the memory control circuit 20 determines the number of high impedance states of the balanced computing memory cells BC11-BCpn according to the number of high impedance states of the computing memory cells C11-Cmn in the same memory string S1-Sn.

Specifically, p=3 is used as an example for explanation, but it should be known that the present invention is not limited thereto. For memory string S1, when the number of high impedance states of the computational memory cells C11, C21, ..., Cm1 is 0 (i.e., the computational memory cells C11, C21, ..., Cm1 are all programmed to a low impedance state), the balanced computational memory cells BC11, BC21, and BC31 are all programmed to a high impedance state, i.e., the number of high impedance states of the balanced computational memory cells BC11, BC21, and BC31 is 3.

Similarly, for the memory string S1, when the number of high impedance states of the computing memory cells C11, C21, . . . , Cm1 is 1, the number of high impedance states of the balanced computing memory cells BC11, BC21 and BC31 is 2.

Similarly, for the memory string S1, when the number of high impedance states of the computing memory cells C11, C21, . . . , Cm1 is 2, the number of high impedance states of the balanced computing memory cells BC11, BC21 and BC31 is 1.

Similarly, for the memory string S1, when the number of high impedance states of the computing memory cells C11, C21, . . . , Cm1 is 3 or more, the number of high impedance states of the balanced computing memory cells BC11, BC21 and BC31 is 0.

In addition, when performing IMC calculation, the balanced input values BIN1-BINp are bit 1 (enable bit), so that the resistance values of the balanced operation memory cells BC11-BCpn can contribute to the memory strings.

Therefore, in an embodiment of the present case, when more balanced computing memory cells are set in each memory string, the number of high impedance states of the balanced computing memory cells in each memory string can be determined according to the above method in the programming stage.

That is, in one embodiment of the present case, in each of the memory strings, when the number of high impedance states of the computational memory cells is small, the number of high impedance states of the balanced computational memory cells will be large; and, in each of the memory strings, when the number of high impedance states of the computational memory cells is large, the number of high impedance states of the balanced computational memory cells will be small. This can improve the fast charging behavior of the memory strings.

In an embodiment of the present case, when performing an IMC operation (such as multiply-and-accumulation (MAC)), a read voltage Vread is applied to one end of the operation memory cells C11-Cmn of the memory device 10, so that the operation memory cells C11-Cmn will generate a plurality of cell currents. The cell currents generated by the operation memory cells of the same memory string are summed to become the memory string currents I1-In.

In an embodiment of the present case, when performing an IMC operation, a read voltage Vread is applied to one end (for example but not limited to, a drain end) of the computational memory cells C11-Cmn of the memory device 10, and a capacitance voltage VC of the load capacitor C is measured to measure the charging time (also referred to as a delay time) for the load capacitor C to be charged to a predetermined voltage. For the convenience of definition, the time point at which the read voltage Vread is applied is referred to as a first time point, and the time point at which the capacitance voltage VC of the load capacitor C is measured to be charged to the predetermined voltage is referred to as a second time point. In an embodiment of the present case, the delay time is defined as: from the first time point to the second time point. The capacitance voltage VC of the load capacitor C can be measured by the measuring circuit 120 to measure the delay time of the load capacitor C.

In an embodiment of the present case, the memory string resistance Ri (i=1~n) of the memory string Si (i=1~n) can be expressed as follows: .

Here, i represents the memory string number, k represents the number of the operation memory cell in the memory string, and a memory string has m operation memory cells.

Therefore, the memory string current Ii of the memory string Si can be expressed as follows: .

The weight values W11~Wmn of the computational memory cell are functions of the input values IN11~INmn, so the weight value Wki can be expressed as the impedance value Wki of the computational memory cell = .

In an embodiment of the present case, the charging time of the load capacitor C to be charged to the predetermined voltage can be used to represent the sum of products of the weight values W11~Wmn and the input values IN11~INmn of the computational memory cells C11~Cmn. This is because, in an embodiment of the present case, the sum of products of the weight values and the input values IN11~INmn of the computational memory cells C11~Cmn is a total current Itotal. Itotal can be expressed as follows: .

This total current Itotal is used to charge the load capacitor C. Therefore, the time point when the capacitance voltage VC of the load capacitor C is charged to the predetermined voltage is related to the capacitance value of the load capacitor C and the total current Itotal. In one embodiment of the present case, the capacitance value of the load capacitor C is known. Therefore, it can be known that in one embodiment of the present case, the time point when the capacitance voltage VC of the load capacitor C is charged to the predetermined voltage can be regarded as negatively related to the total current Itotal, that is, when the total current Itotal is larger, the time point when the capacitance voltage VC of the load capacitor C is charged to the predetermined voltage is shorter, and when the total current Itotal is smaller, the time point when the capacitance voltage VC of the load capacitor C is charged to the predetermined voltage is longer.

Therefore, in an embodiment of the present case, a predetermined relationship between the delay time for the load capacitor C to be charged to the predetermined voltage and the sum of the products of the weight values of the computational memory cells C11-Cmn and the input values IN11-INmn under a predetermined condition can be found in advance. In the subsequent IMC operation, the sum of the products of the weight values of the computational memory cells C11-Cmn and the input values IN11-INmn can be obtained by measuring the delay time.

In addition, in one embodiment of the present case, when the weight value and/or input value of the computational memory cell changes, the effective impedance value of the computational memory cell also changes accordingly, which will result in different delay times (charging times).

FIG. 3A and FIG. 3B are schematic diagrams showing a delay time measurement according to an embodiment of the present invention. In FIG. 3A and FIG. 3B, eRS1, eRS2 and eRS3 represent different total effective impedance values of the memory strings S1-Sn, wherein eRS1<eRS2<eRS3.

In FIG. 3A , the delay time is from a first time point when the read voltage is applied to a second time point when the capacitor voltage of the load capacitor is charged to a predetermined voltage, and the predetermined voltage is determined according to the read voltage. For example, but not limited to, the predetermined voltage may be 0.7 times the read voltage.

In FIG. 3A , when the different total effective impedance values of the memory strings S1 to Sn are eRS1, at time T1, the load capacitor C is charged to a predetermined voltage, so the delay time T1 represents that the sum of the products of the weight values W11 to Wmn and the input values IN11 to INmn is 001. Similarly, when the different total effective impedance values of the memory strings S1 to Sn are eRS2, at time T2, the load capacitor C is charged to a predetermined voltage, so the delay time T2 represents that the sum of the products of the weight values W11 to Wmn and the input values IN11 to INmn is 010. Similarly, when the different total effective impedance values of the memory strings S1-Sn are eRS3, at time T3, the load capacitor C is charged to a predetermined voltage, so the delay time T3 represents that the sum of the products of the weight values W11-Wmn and the input values IN11-INmn is 011. The rest can be deduced in the same way.

In addition, in another embodiment of the present invention, a plurality of predetermined delay times can be selected, and at these predetermined delay times, the capacitor voltage VC is compared with the reference voltage VREF, and the comparison result represents the operation result (sum of products) of the input values and the weight values, as shown in FIG. 3B. That is, a plurality of predetermined delay times (t0-t3) are selected, and at these predetermined delay times, it is checked whether the capacitor voltage VC reaches the predetermined voltage VREF to determine the operation result (sum of products) of the input values and the weight values. If the capacitor voltage VC reaches a predetermined voltage at the delay time t0, the calculation result (sum of products) of the input values and the weight values is determined to be 000; if the capacitor voltage VC reaches a predetermined voltage at the delay time t1, the calculation result (sum of products) of the input values and the weight values is determined to be 001; and the rest can be deduced in the same way.

In FIG. 3B , when the different total effective impedance values of the memory strings S1 to Sn are eRS1, at the delay time t1, the capacitor voltage VC reaches a predetermined voltage, and the calculation results (sum of products) of the input values and the weight values are determined to be 001. Similarly, when the different total effective impedance values of the memory strings S1 to Sn are eRS2, at the delay time t1, the capacitor voltage VC reaches a predetermined voltage, and the calculation results (sum of products) of the input values and the weight values are determined to be 001. When the different total effective impedance values of the memory strings S1-Sn are eRS3, at the delay time t3, the capacitor voltage VC reaches a predetermined voltage, and the calculation results (sum of products) of the input values and the weight values are determined to be 011.

Different examples of computational memory cells according to an embodiment of the present invention will now be described.

FIG. 4A is a circuit diagram of a computational memory cell C(a)mn of an embodiment of the present invention. The computational memory cell C(a)mn can be used to implement the computational memory cells C11~Cmn and the balanced computational memory cells BC11~BCpn of the memory array 100 of FIG. 2. The computational memory cell C(a)mn includes a transistor TRmn and a resistor R(a)mn. The transistor TRmn is connected in parallel to the resistor R(a)mn, and the resistor R(a)mn has a fixed resistance value. The computational memory cell C(a)mn is connected to the nth bit line BLn. The drain d and the source s of the transistor TRmn are connected to the bit line BLn, and the gate g of the transistor TRmn receives the input voltage Vmn. Resistor R(a)mn is also connected to bit line BLn.

The transistor TRmn is, for example, a floating gate transistor. The transistor TRmn has a threshold voltage Vt, and a programming voltage can be applied to adjust the voltage value of the threshold voltage Vt. When the transistor TRmn is in an erase state, the voltage value of the threshold voltage Vt is a first threshold voltage value VtL. When the transistor TRmn is in a programming state, the voltage value of the threshold voltage Vt can be programmed to a second threshold voltage value VtH. The second threshold voltage value VtH is greater than the first threshold voltage value VtL. The first critical voltage value VtL is, for example, 0.4V, and the second critical voltage value VtH is, for example, 4.8V. Furthermore, the critical voltage Vt corresponds to a weight value Wmn stored in the computational memory cell C(a)mn. When the critical voltage Vt is the first critical voltage value VtL, the weight value Wmn stored in the computational memory cell C(a)mn is "0". When the critical voltage Vt is the second critical voltage value VtH, the weight value Wmn stored in the computational memory cell C(a)mn is "1".

The gate g of the transistor TRmn receives the input voltage Vmn. The input voltage Vmn corresponds to the input value INmn received by the computational memory cell C(a)mn. When the voltage value of the input voltage Vmn is the first input voltage value VL, the corresponding input value INmn is "1". When the voltage value of the input voltage Vmn is the second input voltage value VH, the corresponding input value INmn is "0". The second input voltage value VH is greater than the first input voltage value VL. The second input voltage value VH is, for example, 3V. The first input voltage value VL is, for example, -1V. Furthermore, the second input voltage value VH is greater than the second critical voltage value VtH and the first critical voltage value VtL. Furthermore, the first input voltage value VL is less than the second critical voltage value VtH and greater than the first critical voltage value VtL.

The computational memory cell C(a)mn can receive a read voltage Vread via a bit line BLn to generate a cell current Imn. In operation, the computational memory cell C(a)mn may or may not generate a cell current Imn in response to different voltage values of the input voltage Vmn and the critical voltage Vt.

When the input voltage Vmn received by the computational memory cell C(a)mn is the second input voltage value VH, and the critical voltage Vt of the transistor TRmn is the first critical voltage value VtL or the second critical voltage value VtH, since the input voltage Vmn is greater than the critical voltage Vt, the transistor TRmn is turned-on (i.e., conductive), and thus the computational memory cell C(a)mn can generate a cell current Imn. In this case, the equivalent impedance of the computational memory cell C(a)mn is the equivalent resistance value Rtr of the transistor TRmn itself connected in parallel with the resistor R(a)mn. In one example, the resistance value of the resistor R(a)mn is much larger than the equivalent resistance value Rtr of the transistor TRmn, so the equivalent impedance of the computing memory cell C(a)mn is substantially equal to the equivalent resistance value Rtr of the transistor TRmn.

On the other hand, when the input voltage Vmn received by the computational memory cell C(a)mn is the first input voltage value VL and the critical voltage Vt of the transistor TRmn is the first critical voltage value VtL, since the input voltage Vmn is greater than the critical voltage Vt, the transistor TRmn is in the on state, and therefore, the computational memory cell C(a)mn can generate a cell current Imn. In this case, the equivalent impedance of the computational memory cell C(a)mn is substantially equal to the equivalent resistance value Rtr of the transistor TRmn.

Furthermore, when the input voltage Vmn received by the computational memory cell C(a)mn is the first input voltage value VL and the critical voltage Vt of the transistor TRmn is the second critical voltage value VtH, since the input voltage Vmn is less than the critical voltage Vt, the transistor TRmn is turned-off (i.e., open circuit state), and therefore, the computational memory cell C(a)mn does not generate the cell current Imn. In this case, the equivalent impedance of the computational memory cell C(a)mn is substantially equal to the resistor R(a)mn.

According to the operation mode of the computing memory cell C(a)mn described above, Table 1 shows the truth table of whether the computing memory cell C(a)mn generates the cell current Imn corresponding to the input value INmn and the weight value Wmn. Table 1 Wmn IN 0 1 0 Generates cell current Imn Generates cell current Imn 1 Generates cell current Imn No cell current Imn is generated

Referring to Table 1, when the input value INmn is "0" and the weight value Wmn is "0" or "1", the computational memory cell C(a)mn generates a cell current Imn. When the input value INmn is "1" and the weight value Wmn is "0", the computational memory cell C(a)mn generates a cell current Imn. When the input value INmn is "1" and the weight value Wmn is "1", the computational memory cell C(a)mn generates a smaller cell current Imn. Accordingly, the computational memory cell C(a)mn can perform a product operation of the input value INmn and the weight value Wmn, and the cell current Imn generated by the computational memory cell C(a)mn is related to the product of the input value INmn and the weight value Wmn.

FIG. 4B is a circuit diagram of a computing memory cell C(c)mn of another embodiment of the present invention. The computing memory cell C(c)mn can be used to implement the computing memory cells C11~Cmn and the balanced computing memory cells BC11~BCpn of the memory array 100 of FIG. 2. Compared with the computing memory cell C(a)mn of FIG. 4A, the resistor R(c)mn of the computing memory cell C(c)mn of FIG. 4B is a variable resistor having a variable resistance value, and the resistance value of the resistor R(c)mn can be dynamically adjusted when the memory device is operating. In another example, the resistor R(c)mn has a fixed resistance value, however, the process parameters can be adjusted to adjust the resistance value of the resistor R(c)mn during the manufacturing process. In FIG. 4B , transistor TRmn is a general transistor.

The resistor R(c)mn can be adjusted to four resistance values R0, R1, R2, and R3, for example, wherein the resistance value R0 approaches zero and is much smaller than the resistance values R1, R2, and R3. Furthermore, the equivalent resistance value Rtr of the transistor TRmn of the computing memory cell C(c)mn is also much smaller than the resistance values R1, R2, and R3.

When the weight value Wmn stored in the computational memory cell C(c)mn is "0", the resistor R(c)mn is adjusted to the resistance value R0. Similarly, when the weight value Wmn stored in the computational memory cell C(c)mn is "1", "2", or "3", the resistor R(c)mn is adjusted to the resistance values R1, R2, or R3.

When the input value INmn is "0", the input voltage Vmn is the second input voltage value VH of the high voltage value, the transistor TRmn is in the on state, the equivalent impedance of the computing cell C(c)mn is substantially equal to the equivalent resistance value Rtr of the transistor TRmn itself, and the computing cell C(c)mn generates a cell current Imn. In this case, regardless of whether the weight value Wmn is set to "0", "1", "2" or "3" (i.e., regardless of whether the resistor R(c)mn is adjusted to the resistance value R0, R1, R2 or R3), the computing cell C(c)mn generates a cell current Imn.

On the other hand, when the input value INmn is "1", the input voltage Vmn is the first input voltage value VL of the low voltage value, the transistor TRmn is in the off state, and the calculation memory cell C(c)mn does not generate the cell current Imn. When the weight value Wmn is set to "0", "1", "2", "3", the resistor R(c)mn is adjusted to the resistance value R0, R1, R2, R3, and the cell current Imn generated by the calculation memory cell C(c)mn is related to the resistance value R0, R1, R2, R3. Accordingly, the computational memory cell C(c)mn can perform a multiplication operation, where the cell current Imn generated by the computational memory cell C(c)mn is related to the product of the input value INmn and the weight value Wmn.

FIG. 4C is a circuit diagram of a computing memory cell C(d)mn of another embodiment of the present invention. The computing memory cell C(d)mn can be used to implement the computing memory cells C11~Cmn and the balancing computing memory cells BC11~BCpn of the memory array 100 of FIG. 2. Compared with the computing memory cell C(a)mn of FIG. 4A, the computing memory cell C(d)mn of FIG. 4C does not include a resistor. The weight value of the computing memory cell C(d)mn of FIG. 4C is determined according to the critical voltage of the transistor TRmn.

In other possible embodiments of the present invention, the computing memory cells C11~Cmn and the balanced computing memory cells BC11~BCpn may also have other possible implementation architectures, such as but not limited to, (1) the computing memory cells C11~Cmn and the balanced computing memory cells BC11~BCpn may include a multiplexer and a plurality of resistors; (2) the computing memory cells C11~Cmn and the balanced computing memory cells BC11~BCpn may include a plurality of switch elements and a plurality of resistors.

According to the above-mentioned different embodiments of the present case, the computational memory cells and the balanced computational memory cells are composed of one or more transistors and/or resistors. The critical voltage of the transistor can be adjusted to change the weight value stored in the computational memory cell, and the resistor can be adjusted to a high resistance value, a low resistance value or a resistance value of different proportions according to the weight value. In addition, the computational memory cell is controlled to operate in a "conduction state" or "open circuit state" according to the input voltage corresponding to the input value, and the read voltage is selectively applied to the transistor or resistor accordingly, so that the computational memory cell generates a corresponding cell current to represent the output value. The output value represents the result of the product operation of the input value and the weight value, and the sum of the products can be added up. In addition, the computational memory cell may also include a multiplexer. Through the operation of the multiplexer, the read voltage is selectively applied to the resistor on the selected path, so that the computational memory cell performs a logical operation of the input value and the weight value, or a logical operation between two-bit input values.

FIG. 5A to FIG. 5C show simulation diagrams according to an embodiment of the present invention. FIG. 5A to FIG. 5C are simulations of a case where the memory array 100 has 32 memory strings and each memory string has 32 computational memory cells. The high resistance of the computational memory cells and the balance computational memory cells is 555K ohms, and the low resistance of the computational memory cells and the balance computational memory cells is 13.5K ohms. The capacitance value CL of the load capacitor C is 1.5 pF.

In an embodiment of the present case, the capacitance value CL of the load capacitor C can be adjusted to adjust the delay time. In the following, the charging time required for the capacitance voltage VC of the load capacitor C to be charged to a predetermined voltage of 0.35V when the read voltage is 0.5V is used as an example for explanation, but it should be understood that the present case is not limited to this. That is, in this example, when the capacitance voltage VC of the load capacitor C reaches 0.7 times the read voltage, it is considered that the memory device 10 has generated a MAC (product sum) result.

In FIGS. 5A to 5C , curve 510A represents a case where the resistance of the impedance element is equal to the high resistance and there are three balanced computing memory cells in each memory string. Curve 510B represents a case where the resistance of the impedance element is equal to the high resistance and there are no balanced computing memory cells in each memory string. Curve 510C represents a case where each memory string has no balanced computing memory cells and no impedance element.

In Figure 5A, the numbers of high-impedance states of the computational memory cells of the 32 memory strings are [6, 6, 1, 4, 6, 7, 3, 5, 5, 7, 3, 6, 6, 2, 7, 8, 7, 4, 7, 6, 3, 3, 2, 8, 4, 7, 4, 3, 7, 3, 9, 5] respectively.

In FIG. 5B , the numbers of high-impedance states of the computational memory cells of the 32 memory strings are [24, 23, 22, 20, 22, 21, 17, 23, 21, 22, 20, 19, 20, 20, 23, 20, 22, 20, 20, 23, 21, 22, 18, 21, 24, 24, 18, 18, 22, 20, 24, 23] respectively.

In Figure 5C, the numbers of high-impedance states of the computational memory cells of the 32 memory strings are [7,  4,  7,  6,  3,  3,  2,  8,  4,  7,  4,  3,  7,  3,  9,  5, 24, 23, 22, 20, 22, 21, 17, 23, 21, 22, 20, 19, 20, 20, 23, 20].

As can be seen from FIG. 5A to FIG. 5C , in an embodiment of the present invention, the delay time is proportional to the sum of products. In an embodiment of the present invention, the function of the balanced computing memory cell is similar to an impedance element, which is used to limit the current to avoid the fast charging effect.

In addition, in an embodiment of the present case, since the balanced computation memory cell is introduced, when evaluating the IMC computation result (the sum of products), it is necessary to compensate for the influence of the balanced computation memory cell on the computation result. Taking the curve 510A (with the balanced computation memory cell) in FIG. 5C as an example, the delay time corresponding to the sum of products result of 400 is 0.4 μs, and the delay time corresponding to the sum of products result of 0 is 0.1 μs. On the contrary, taking the curve 510C (without any balanced computation memory cell) in FIG. 5C as an example, the delay time corresponding to the sum of products result of 400 is 0.25 μs, and the delay time corresponding to the sum of products result of 0 is 0.01 μs. Specifically, from the curve 510C of FIG. 5C (without any balancing operation memory cell), the delay time of 0.12 μs originally corresponds to the product-sum result of 200, but from the curve 510A of FIG. 5C (with balancing operation memory cell), the delay time of 0.25 μs corresponds to the product-sum result of 200. Therefore, in an embodiment of the present case, when compensating for the influence of the balancing operation memory cell on the operation result, the delay time is shifted backward by about 0.13 μs to correspond to the product-sum result.

In one embodiment of the present case, a portion of the computing memory cells or a plurality of portions of the computing memory cells of the memory array can be defined as balanced computing memory cells. Moreover, each memory string includes the same number of "NBW" balanced computing memory cells and the same number of "m" computing memory cells.

When an additional high impedance state cell is added to the memory string (the high impedance state cell can be caused by impedance elements RS1~RSn or balanced operation memory cells), the current change will be [(1⁄m)-(1⁄(m+1))] when there is no high impedance state cell in the memory string. For example, see the following table, m [(1⁄m)-(1⁄(m+1))] m [(1⁄m)-(1⁄(m+1))] 2 16.7% 5 3.3% 3 8.3% 6 2.4% 4 5.0% 7 1.8%

For example, in each memory string, if a high impedance state unit is added to make the current change 5%, then 4 high impedance state units need to be added to each memory string. Therefore, in an embodiment of the present case, 3 balanced operation memory cells and 1 impedance element can be allocated to each memory string.

Alternatively, if a smaller current variation is required, for example, a current variation of 2%, then 7 high impedance state cells need to be added to each memory string. Therefore, in an embodiment of the present case, 6 balanced operation memory cells and 1 impedance element can be allocated to each memory string.

In addition, in one embodiment of the present invention, the number of balanced computing memory cells can be further adjusted taking into account linearity, accuracy, chip area usage, and other parameters.

In one embodiment of the present case, for a given neural network model, the weight values and distribution are known and can be used to assign the values of the balanced computing memory cells. There are many ways to configure the values of the balanced computing memory cells. For example, if the minimum number of high-impedance state memory cells of a memory string is "Nmin", the input values of all balanced computing memory cells can be set to "1" and the number of high-impedance units of this memory string can be increased to "Nmin + NBW" to further limit the current. Then, the values of the balanced computing memory cells are assigned to other memory strings in this way so that the minimum number of high-impedance units of each memory string is "Nmin + NBW".

In addition, in one embodiment of the present case, "Nbw,Max" is defined to represent the number of balancing computing memory cells with a value of "1" in sensor calculation. The balancing computing memory cells may affect the charging time of sensor operation. The more balancing computing memory cells are assigned to "1", the longer the charging time and the greater the sensing overhead.

Therefore, in an embodiment of the present case, the number of "Nbw,Max" is limited to reduce the sensing overhead. For example, to limit the sensing overhead to 10%, the estimated maximum perceptron output value can be calculated, and "Nbw,Max" can be defined as 1/10 of the estimated maximum perceptron output value. For example, if the estimated maximum perceptron output value is about 164, then "Nbw,Max" can be defined as 16. Alternatively, in an embodiment of the present case, "Nbw,Max" may be defined as approximately half of the total number of balanced computational memory cells. This depends on the weight distribution.

In each memory string, the number of balanced operation memory cells can be 1 or more than 1, and each memory string has the same number of balanced operation memory cells.

The input value of the balance operation memory cell is set to "1" to enable the balance operation memory cell's contribution to each memory string.

The location of the balance operation memory cell can be placed at the beginning, end or other position of the memory string.

The impedance state of the balanced computation memory cell depends on the weight value distribution of the memory array.

In the prior art, when performing IMC operations, fast charging behavior may occur. Fast charging behavior means that when all computing memory cells of the same memory string are in a low impedance state or only a few computing memory cells of the same memory string are in a high impedance state, the equivalent impedance of the same memory string is too low, making the current of the same memory string too high, and the charging current of the load capacitor C is too high, causing the potential of the load capacitor C to rise rapidly, thereby leading to the possibility of misjudgment.

Therefore, in an embodiment of the present case, the memory strings S1~Sn are additionally provided with the balancing operation memory cells BC11~BCpn and/or impedance elements RS1~RSn to increase the equivalent impedance of the memory strings S1~Sn, so as to effectively reduce or avoid the fast charging behavior. Even when all the operation memory cells of the same memory string are in a low impedance state, due to the additional addition of the balancing operation memory cells BC11~BCpn and/or impedance elements RS1~RSn (impedance elements RS1~RSn), the equivalent impedance of the same memory string will not be too low, so that the current of the same memory string will not be too high, the charging current of the load capacitor C will not be too high, and the potential of the load capacitor C will not increase rapidly, thereby reducing the possibility of misjudgment.

In one embodiment of the present case, the computational memory cells and the balanced computational memory cells have at least two impedance states, a high impedance state and a low impedance state. When the computational memory cells are in the high impedance state (also referred to as the first impedance state), the computational memory cells have a high impedance value RH (also referred to as the first impedance value); and, when the computational memory cells are in the low impedance state (also referred to as the second impedance state), the computational memory cells have a low impedance value RL (also referred to as the second impedance value).

In an embodiment of the present invention, the equivalent impedance RS of the impedance elements RS1-RSn is, for example but not limited to, RS=2RL, or RS=5RL, which can effectively reduce the fast charging behavior. In an embodiment of the present invention, the equivalent impedance RS of the impedance elements RS1-RSn is, for example but not limited to, RS=10RL, or RS≧0.5*RH, which can effectively avoid or even completely avoid the fast charging behavior.

It can be seen that the embodiment of this case can indeed reduce or avoid fast charging behavior, thereby reducing the possibility of misjudgment.

In an embodiment of the present invention, the impedance elements RS1-RSn are, for example, but not limited to, a resistor formed by a process. Alternatively, in an embodiment of the present invention, the impedance elements RS1-RSn are, for example, but not limited to, a transistor. Alternatively, in an embodiment of the present invention, the impedance elements RS1-RSn are, for example, but not limited to, a combination of a transistor and a resistor, and when performing a programming operation or calculating a memory cell weight adjustment, the transistor is turned on, and when performing a sensing operation, the transistor is turned off.

In one embodiment of the present invention, the power consumption of the IMC operation of the IMC memory device can be adjusted to a reasonable range by adjusting the capacitance value of the load capacitor. In addition, for a given number of input values and number of operation memory cells, properly arranging the number of memory strings and the number of operation memory cells of each memory string can also help adjust the power consumption.

In one embodiment of the present invention, the number of computational memory cells in a memory string is at least greater than or equal to 2, and the number of memory strings in the memory array can be arbitrary. Furthermore, the impedance value of the computational memory cell can be changed by an input value.

In one embodiment of the present invention, when the memory device 10 is a NAND memory device, the read voltage Vread is lower than 1V.

In one embodiment of the present case, the memory device 10 can be applied to, for example but not limited to, neural network calculations, or multiplication and calculations, or comparing input data with stored data, etc.

In other possible embodiments of the present invention, the computational memory cells and the balanced computational memory cells have three or more impedance states (ie, three or more impedance values), which are all within the spirit and scope of the present invention.

In an embodiment of the present case, since a voltage summing architecture is not used for IMC, more input values can be calculated simultaneously, and only a single sensing amplifier can be used to satisfy IMC. This embodiment of the present case has the advantages of reducing reading errors and power consumption.

The IMC memory device of one embodiment of the present case is a hybrid mode of a current summing architecture and a voltage summing architecture, which allows more input values to be calculated simultaneously and can avoid the problems caused by the larger summed current in the current summing architecture and the problems caused by the low inductive current in the voltage summing architecture.

In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

10: Memory device 20: Memory control circuit 30: Word line driver circuit 40: Bit line driver circuit 100: Memory array I1~In: Memory string current BL1~BLn: Bit line V11~Vmn, BV1~BVp: Input voltage IN11~INmn, BIN1~BINp: Input value 100: Memory array IN11~INmn: Input value S1~Sn: Memory string C: Load capacitor 120: Measurement circuit Vread: Read voltage BC11~BCpn: Balanced operation memory cell RS1~RSn: Impedance element C(a)mn, C(c)mn, C(d)mn: computational memory cells R(a)mn, R(c)mn: resistors TRmn: transistors g: gate d: drain s: source 510A-510C: curves

FIG. 1 shows a functional block diagram of an in-memory computing (IMC) memory device according to an embodiment of the present invention. FIG. 2 shows an architecture diagram of a memory array of an in-memory computing memory device according to an embodiment of the present invention. FIG. 3A and FIG. 3B show schematic diagrams of measuring delay time according to an embodiment of the present invention. FIG. 4A is a circuit diagram of a computing memory cell according to an embodiment of the present invention. FIG. 4B is a circuit diagram of a computing memory cell according to an embodiment of the present invention. FIG. 4C is a circuit diagram of a computing memory cell according to an embodiment of the present invention. FIG. 5A to FIG. 5C show simulation diagrams according to an embodiment of the present invention.

I1~In: memory string current

BL1~BLn: bit line

V11~Vmn, BV1~BVp: input voltage

C11~Cmn: Calculation memory cells

100:Memory array

IN11~INmn, BIN1~BINp: input value

S1~Sn: memory string

C: Load capacitance

RS1~RSn: Impedance elements

120: Measurement circuit

Vread: read voltage

BC11~BCpn: Balanced computational memory cells

Claims (13)

An in-memory computing (IMC) memory device includes: a memory control circuit, and a memory array coupled to the memory control circuit, the memory array including: a plurality of computational memory cells and a plurality of balancing computational memory cells, forming a plurality of memory strings, the computational memory cells storing a plurality of weight values; a load capacitor coupled to the computational memory cells; and a measurement circuit coupled to the load capacitor, Wherein, when programming is performed, the memory control circuit determines the number of first impedance states of the balanced operation memory cells in the memory string according to the number of first impedance states of the operation memory cells in the memory string; Wherein, when performing operation, a plurality of input voltages are respectively input to the operation memory cells, the input voltages are related to a plurality of input values, the memory control circuit sets the input voltages according to the input values, a plurality of balanced input voltages are respectively input to the balanced operation memory cells, the balanced input voltages are related to a plurality of balanced input values, the balanced input values are consistent input values, the memory control circuit sets the balanced input voltages according to the balanced input values; The plurality of effective impedance values of the computational memory cells are related to the input voltages and the weight values. When a read voltage is applied to the computational memory cells, the computational memory cells generate a plurality of memory cell currents, and the memory cell currents form a plurality of memory string currents. The memory string currents generated by the memory strings charge the load capacitor. The measurement circuit measures a capacitor voltage of the load capacitor, and According to a relationship between the capacitor voltage of the load capacitor, at least a delay time and a predetermined voltage, an operation result of the input values and the weight values is determined. An in-memory computing (IMC) memory device as described in claim 1, wherein, the computational memory cells and the balanced computational memory cells have a first impedance value and a second impedance value, the first impedance value is higher than the second impedance value, the number of the first impedance states of the computational memory cells represents a number of the computational memory cells programmed to the first impedance value, and, the number of the first impedance states of the balanced computational memory cells represents a number of the balanced computational memory cells programmed to the first impedance value, each memory string includes at least 2 computational memory cells connected in series, the memory strings are connected in parallel, The delay time is from a first time point when the read voltage is applied to a second time point when the capacitor voltage of the load capacitor is charged to the predetermined voltage, and the predetermined voltage is determined according to the read voltage. An in-memory computing (IMC) memory device as described in claim 1, wherein at a plurality of predetermined delay times, it is checked whether the capacitor voltage reaches the predetermined voltage to obtain a comparison result, and the comparison result represents the operation result of the input values and the weight values. The in-memory computing (IMC) memory device as described in claim 1 further includes: A plurality of impedance elements formed in the memory strings, the impedance elements being connected in series to the computational memory cells and the balanced computational memory cells. An in-memory computing (IMC) memory device as described in claim 4, wherein, the computational memory cells and the balanced computational memory cells have a first impedance value and a second impedance value, the first impedance value being higher than the second impedance value; and an equivalent impedance of the impedance elements is equal to or higher than twice the second impedance value, or the equivalent impedance of the impedance elements is equal to or higher than half the first impedance value. An in-memory computing (IMC) memory device as described in claim 1, wherein, In the memory strings, the number of the balanced computing memory cells is 1 or more than 1, and the memory strings have the same number of the balanced computing memory cells; and In the memory strings, the balanced computing memory cells are located at the beginning, end, or other positions of the memory strings. An in-memory computing (IMC) memory device as described in claim 1, wherein the computing memory cells and the balanced computing memory cells have three or more impedance states. An in-memory calculation method is applied to an in-memory calculation memory device, the in-memory calculation memory device includes a plurality of operation memory cells and a plurality of balance operation memory cells constituting a plurality of memory strings, the in-memory calculation method includes: During programming, the number of first impedance states of the balance operation memory cells in the memory string is determined according to the number of first impedance states of the operation memory cells in the memory string; Storing a plurality of weight values in a plurality of operation memory cells, the operation memory cells constituting a plurality of memory strings; A plurality of input voltages are input to the computational memory cells respectively, the input voltages are related to a plurality of input values, and the effective impedance values of the computational memory cells are related to the input voltages and the weight values; A plurality of balanced input voltages are input to the balanced computational memory cells respectively, the balanced input voltages are related to a plurality of balanced input values, the balanced input values are consistent input values, and the balanced input voltages are set according to the balanced input values; When a read voltage is applied to the computational memory cells, the computational memory cells generate a plurality of memory cell currents, and the memory cell currents form a plurality of memory string currents; The memory string currents generated by the memory strings charge the load capacitor; Measure a capacitor voltage of the load capacitor; and Determine an operation result of the input values and the weight values according to a relationship between the capacitor voltage of the load capacitor, at least one delay time and a predetermined voltage. The in-memory computing method as described in claim 8, wherein, the computational memory cells and the balanced computational memory cells have a first impedance value and a second impedance value, the first impedance value is higher than the second impedance value, the number of the first impedance states of the computational memory cells represents a number of the computational memory cells programmed to the first impedance value, and, the number of the first impedance states of the balanced computational memory cells represents a number of the balanced computational memory cells programmed to the first impedance value, the delay time is from a first time point when the read voltage is applied to a second time point when the capacitor voltage of the load capacitor is charged to the predetermined voltage, the predetermined voltage being determined according to the read voltage. An in-memory calculation method as described in claim 8, wherein at a plurality of predetermined delay times, it is checked whether the capacitor voltage reaches the predetermined voltage to obtain a comparison result, and the comparison result represents the calculation result of the input values and the weight values. The in-memory computing method as described in claim 8, wherein the in-memory computing memory device further includes: a plurality of impedance elements formed in the memory strings, the impedance elements are connected in series to the computational memory cells and the balanced computational memory cells; The computational memory cells and the balanced computational memory cells have a first impedance value and a second impedance value, the first impedance value is higher than the second impedance value; and An equivalent impedance of the impedance elements is equal to or higher than twice the second impedance value, or the equivalent impedance of the impedance elements is equal to or higher than half the first impedance value. The in-memory computing method as described in claim 8, wherein, In the memory strings, the number of the balanced operation memory cells is 1 or more than 1, and the memory strings have the same number of the balanced operation memory cells; and In the memory strings, the balanced operation memory cells are located at the beginning, end or other positions of the memory strings. The in-memory computing method as described in claim 8, wherein the computing memory cells and the balanced computing memory cells have three or more impedance states.

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