TWI866423B - Image sensor and manufacturing method thereof - Google Patents

Abstract

An image sensor includes a semiconductor substrate, an isolation structure and a covering structure. The semiconductor substrate has a photosensitive element area and an auxiliary photosensitive element area. A first side of the semiconductor substrate has a recess overlapping the auxiliary photosensitive element area. The isolation structure is embedded in the semiconductor substrate and located between the photosensitive element area and the auxiliary photosensitive element area. The covering structure is located above the first side of the semiconductor substrate and filled into the recess. The covering structure filled in the recess overlaps the auxiliary photosensitive element area.

Description

Image sensor and manufacturing method thereof

The present invention relates to an image sensor and a method for manufacturing the same.

Complementary Metal-Oxide-Semiconductor Image Sensor (CIS) is a common image sensor technology used to convert optical signals into digital signals and used as a device to capture images. Due to its advantages such as low energy consumption, low cost, and high system integration, CIS is widely used in cameras, monitoring systems, scientific instruments, medical imaging, and autonomous driving.

Generally speaking, each pixel of a CIS contains tiny photosensitive elements, which are usually made of semiconductor materials. When light shines on the pixels of a CIS, the photons excite the electrons in the semiconductor, causing them to jump to the conduction band, generating electron-hole pairs. These electrons are captured and accumulated in the pixel, forming a charge. The amount of this charge is proportional to the intensity of the light absorbed by the photosensitive element. However, if the intensity of the light is too strong, the charge may reach saturation.

These charges accumulated in the pixels are converted into voltage signals and digital signals by circuits for further processing. Finally, these digital signals can be transmitted to computers or other devices for further processing, such as color correction, noise reduction, and image enhancement, to generate the final digital image that users see.

The present invention provides an image sensor that can improve recognition capabilities in high-intensity light environments.

At least one embodiment of the present invention provides an image sensor, including a semiconductor substrate, an isolation structure, and a covering structure. The semiconductor substrate has a photosensitive element area and an auxiliary photosensitive element area. The first side of the semiconductor substrate has a recess overlapping the auxiliary photosensitive element area. The isolation structure is embedded in the semiconductor substrate and is located between the photosensitive element area and the auxiliary photosensitive element area. The covering structure is located above the first side of the semiconductor substrate and filled in the recess. The covering structure filled in the recess overlaps the auxiliary photosensitive element area.

At least one embodiment of the present invention provides a method for manufacturing an image sensor, comprising the following steps. Provide a semiconductor substrate having a photosensitive element region and an auxiliary photosensitive element region; form an isolation structure between the photosensitive element region and the auxiliary photosensitive element region in the semiconductor substrate; form a recess overlapping the auxiliary photosensitive element region on the first side of the semiconductor substrate; form a covering structure filled in the recess above the first side of the semiconductor substrate, wherein the covering structure filled in the recess overlaps the auxiliary photosensitive element region.

Based on the above, the auxiliary photosensitive element area and the depression overlapping the auxiliary photosensitive element area can reduce the amount of light irradiated to the auxiliary photosensitive element area, thereby improving the recognition ability of the image sensor in a high-intensity light environment.

10,20,30,40: Image sensor

100,100’: semiconductor substrate

100a: First side

100b: Second side

101: Depression

101a: Bottom

101b: Side wall

102,102’: Auxiliary photosensitive element area

104: Photosensitive element area

110: Circuit structure

120: Isolation structure

122: Conductive column

124: Insulation materials

130: Passivation layer

140: Etch stop layer

150,150’: Matt material layer

150”: Matt layer

151: First through hole

152: Second through hole

160: Covering structure

162: First filter element

164: Second filter element

170: Micro-lens layer

172: First lens

174: Second lens

L: Light

PR1,PR2:Mask pattern

T1,T2,t1,t2,X1,X2,X3,X4:Thickness

w1,w2: width

Figures 1A to 1I are cross-sectional schematic diagrams of a method for manufacturing an image sensor according to an embodiment of the present invention.

Figure 2 is a cross-sectional schematic diagram of an image sensor according to another embodiment of the present invention.

Figure 3 is a cross-sectional schematic diagram of an image sensor according to another embodiment of the present invention.

FIG4 is a cross-sectional schematic diagram of an image sensor according to yet another embodiment of the present invention.

FIG. 1A to FIG. 1I are cross-sectional schematic diagrams of a method for manufacturing an image sensor 10 according to an embodiment of the present invention. Referring to FIG. 1A , a semiconductor substrate 100 is provided. The semiconductor substrate 100 has a photosensitive element region 104 and an auxiliary photosensitive element region 102. In some embodiments, the material of the semiconductor substrate 100 is, for example, silicon, germanium, gallium arsenide, indium phosphide, silicon carbide or other suitable materials. The photosensitive element region 104 and the auxiliary photosensitive element region 102 in the semiconductor substrate 100 are doped regions in the semiconductor substrate 100 and may also be referred to as photodiode regions. For example, the photosensitive element region 104 and the auxiliary photosensitive element region 102 each include an N-type semiconductor, a P-type semiconductor or a combination thereof. In some embodiments, the width w1 of the auxiliary photosensitive element area 102 is smaller than the width w2 of the photosensitive element area 104.

The semiconductor substrate 100 has a first side 100a and a second side 100b opposite to the first side 100a. In some embodiments, the circuit structure 110 is formed on the second side 100b of the semiconductor substrate 100. For example, the circuit structure 110 includes a gate structure (not shown separately), a well region doping structure (such as a source/drain structure, a floating diffusion node, a channel region, etc., not shown separately), a wire (not shown separately), a conductive hole (not shown separately) or other components. In some embodiments, the circuit structure 110 includes multiple conductive layers and multiple insulating layers. Through the arrangement of the conductive layers, various circuits such as vertical drive circuits, column signal processing circuits, horizontal drive circuits, output circuits, and control circuits can be formed on the second side 100b of the semiconductor substrate 100. In some embodiments, the circuit structure 110 includes a structure formed by a front end of line (FEOL) process and a structure formed by a back end of line (BEOL) process.

Referring to FIG. 1B , an isolation structure 120 is formed in a semiconductor substrate 100. For example, a first side 100a of the semiconductor substrate 100 is etched to form a plurality of openings on the first side 100a of the semiconductor substrate 100. Then, an isolation material is filled into the aforementioned openings. Then, a planarization process is performed to remove excess isolation material outside the openings to form the isolation structure 120. In this embodiment, the isolation structure 120 may also be referred to as a deep trench isolation structure. The material of the isolation structure 120 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, aluminum oxide or other suitable materials or a combination of the aforementioned materials. In some embodiments, the isolation structure 120 may also include a conductive column (such as metal) and an insulating material surrounding the conductive column.

The isolation structure 120 is located between the photosensitive element area 104 and the auxiliary photosensitive element area 102, and is used to reduce the optical crosstalk and electrical crosstalk between the photosensitive element area 104 and the auxiliary photosensitive element area 102.

In this embodiment, the isolation structure 120 extends continuously from the first side 100a of the semiconductor substrate 100 to the second side 100b of the semiconductor substrate 100 and contacts the circuit structure 110, but the present invention is not limited thereto. In other embodiments, the isolation structure 120 extends from the first side 100a of the semiconductor substrate 100 into the semiconductor substrate 100 and does not extend to the second side 100b. In other embodiments, the isolation structure 120 extends from the first side 100a of the semiconductor substrate 100 into the circuit structure 110.

Next, please refer to FIG. 1C to form a mask pattern PR1 on the first side 100a of the semiconductor substrate 100. In some embodiments, the material of the mask pattern PR1 includes a photoresist, and the method of forming the mask pattern PR1 includes a lithography process. In other embodiments, other hard mask materials, such as inorganic materials such as silicon nitride and silicon oxide, may be included between the mask pattern PR1 and the semiconductor substrate 100, and the mask pattern PR1 may be used as a mask to etch the aforementioned hard mask.

The semiconductor substrate 100 is etched using the mask pattern PR1 as a mask to form a semiconductor substrate 100' having a recess 101. The recess 101 is located at the first side 100a of the semiconductor substrate 100', and the recess 101 overlaps the auxiliary photosensitive element region 102'. In some embodiments, the thickness of the semiconductor substrate 100' at the recess 101 is T1, and the thickness of the semiconductor substrate 100' at the photosensitive element region 104 is T2, wherein T1 is less than T2. In some embodiments, the method of etching the semiconductor substrate 100' includes dry etching or wet etching, wherein the wet etching uses, for example, a mixture of hydrofluoric acid and nitric acid, tetramethylammonium hydroxide (TMAH), a mixture of diluted ammonia and hydrogen peroxide (dAPM), or other suitable components as an etching solution.

In the present embodiment, when the recess 101 is formed on the first side 100a of the semiconductor substrate 100', the thickness of the auxiliary photosensitive element area 102 is thinned, and an auxiliary photosensitive element area 102' having a thickness t1 is formed. The thickness t1 of the auxiliary photosensitive element area 102' is less than the thickness t2 of the photosensitive element area 104. The auxiliary photosensitive element area 102' is exposed to the bottom surface 101a of the recess 101. Although the recess 101 is used as an example to thin the auxiliary photosensitive element area 102' in the present embodiment, the present invention is not limited thereto. In other embodiments, the bottom surface 101a of the recess 101 may be separated from the top of the auxiliary photosensitive element area 102' by a distance. In other words, the etching process for forming the recess 101 may not etch to the auxiliary photosensitive element area 102'.

The recess 101 is surrounded by an isolation structure 120. In this embodiment, the isolation structure 120 is exposed to the sidewall 101b of the recess 101, but the present invention is not limited thereto. In other embodiments, the isolation structure 120 is separated from the sidewall 101b of the recess 101 by a distance. In other words, part of the semiconductor substrate 100' can be retained between the sidewall 101b of the recess 101 and the isolation structure 120.

Referring to FIG. 1D , the mask pattern PR1 is removed by an ashing process or other suitable process.

Next, a passivation layer 130 is formed to blanket the first side 100a of the semiconductor substrate 100'. A portion of the passivation layer 130 fills the recess 101 and covers the bottom surface 101a and the sidewall 101b of the recess 101. In the present embodiment, since the recess 101 exposes the auxiliary photosensitive element region 102' and the isolation structure 120, the passivation layer 130 contacts the auxiliary photosensitive element region 102' and the isolation structure 120. In other embodiments, the recess 101 does not expose the auxiliary photosensitive element region 102' and the isolation structure 120, and the passivation layer 130 does not contact the auxiliary photosensitive element region 102' and the isolation structure 120. In some embodiments, the material of the passivation layer 130 is, for example, silicon oxide, a high-k material (such as aluminum oxide, tantalum pentoxide (Ta ₂ O ₅ ), zirconium oxide (ZrO), etc.) or other suitable materials.

An etch stop layer 140 is formed to blanket the passivation layer 130. A portion of the etch stop layer 140 fills the recess 101. In some embodiments, the material of the etch stop layer 140 includes, for example, silicon nitride, silicon oxynitride, or other suitable materials.

Referring to FIG. 1E , a matte material layer 150 is formed on the etch stop layer 140, and a portion of the matte material layer 150 fills the recess 101. In some embodiments, the material of the matte material layer 150 includes metal (titanium, tantalum), nitride (such as titanium nitride, tantalum nitride) or other suitable materials or a combination of the above materials. In some embodiments, the method of forming the matte material layer 150 includes physical vapor deposition, chemical vapor deposition or other suitable processes.

In this embodiment, the thickness X1 of the matte material layer 150 at the bottom of the recess 101 is less than the thickness X2 of the matte material layer 150 outside the recess 101. Therefore, the matte material layer 150' formed by etching the matte material layer 150 by an etching back process can expose the bottom layer structure (such as the etching stop layer 140 or the passivation layer 130) in the recess 101, and at the same time retain the portion of the matte material layer 150' located outside the recess 101 and overlapping the photosensitive element area 104, as shown in FIG1F. The etching back process thins the matte material layer 150 on the entire surface.

In this embodiment, after the etching back process, the first through hole 151 of the matte material layer 150' exposes the etching stop layer 140 at the bottom of the recess 101.

Next, referring to FIG. 1G , a mask pattern PR2 is formed on the first side 100a of the semiconductor substrate 100' and filled into the recess 101 and the first through hole 151. In some embodiments, the material of the mask pattern PR2 includes a photoresist, and the method of forming the mask pattern PR2 includes a lithography process. In other embodiments, other hard mask materials, such as inorganic materials such as silicon nitride and silicon oxide, may be included between the mask pattern PR2 and the semiconductor substrate 100', and the aforementioned hard mask may be etched using the mask pattern PR2 as a mask.

The matte material layer 150' is etched using the mask pattern PR2 as a mask to form a matte layer 150" including a first through hole 151 and a second through hole 152. The first through hole 151 overlaps the auxiliary photosensitive element area 102', and the second through hole 152 overlaps the photosensitive element area 104. In some embodiments, the matte layer 150" has a grid structure, and from a top-down perspective, the matte layer 150" is located between the auxiliary photosensitive element area 102' and the photosensitive element area 104. In some embodiments, the matte layer 150" overlaps the isolation structure 120. In some embodiments, the thickness of the matte layer 150" on the sidewall 101b of the recess 101 is different from (e.g., less than) the thickness of the matte layer 150" outside the recess 101.

Please refer to FIG. 1H , the mask pattern PR2 is removed by an ashing process or other suitable process.

Next, a covering structure 160 is formed on the first side 100a of the semiconductor substrate 100'. The covering structure 160 is filled into the recess 101, and the covering structure 160 filled into the recess overlaps the auxiliary photosensitive element area 102. In this embodiment, the covering structure 160 contacts the etching stop layer 140 through the first through hole 151 and the second through hole 152 of the matte layer 150".

In this embodiment, the covering structure 160 is a color filter and includes a first filter element 162 and a second filter element 164. In some embodiments, the covering structure 160 also includes other filter elements (such as a third filter element). The covering structure 160 includes filter elements of different colors, thereby converting the light irradiated to the image sensor into light with a specific color. For example, the first filter element 162, the second filter element 164 and the third filter element (not shown) are red filter elements, green filter elements and blue filter elements, respectively. In some embodiments, the boundaries of filter elements of different colors overlap the extinction layer 150".

Referring to FIG. 1I , a microlens layer 170 is formed on the covering structure 160. In this embodiment, the microlens layer 170 includes a first lens 172 overlapping the auxiliary photosensitive element area 102' and a second lens 174 overlapping the photosensitive element area 104. In some embodiments, the thickness of the second lens 174 is less than the thickness of the first lens 172, but the present invention is not limited thereto. In other embodiments, the thickness of the second lens 174 and the thickness of the first lens 172 can be adjusted according to actual needs.

At this point, the image sensor 10 is substantially completed. In this embodiment, the image sensor 10 includes a semiconductor substrate 100', an isolation structure 120, a passivation layer 130, an etch stop layer 140, a matte layer 150", a covering structure 160 and a microlens layer 170.

The semiconductor substrate 100' has a photosensitive element area 104 and an auxiliary photosensitive element area 102'. The first side 100a of the semiconductor substrate 100 has a recess 101 overlapping the auxiliary photosensitive element area 102'. Each pixel of the image sensor 10 includes at least one photosensitive element area 104 and at least one auxiliary photosensitive element area 102'.

The isolation structure 120 is embedded in the semiconductor substrate 100' and is located between the photosensitive element area 104 and the auxiliary photosensitive element area 102'. The passivation layer 130 is blanketed on the first side 100a of the semiconductor substrate 100' and partially fills the recess 101. The etch stop layer 140 is blanketed on the passivation layer 130 and partially fills the recess 101. The matt layer 150" is located above the first side 100a of the semiconductor substrate 100' and at least partially fills the recess 101. The matt layer 150" is formed on the etch stop layer 140.

The covering structure 160 is located above the first side 100a of the semiconductor substrate 100' and is filled into the recess 101. The covering structure 160 filled into the recess 101 overlaps the auxiliary photosensitive element area 102'. The covering structure 160 is formed on the matte layer 150" and the etch stop layer 140, and the matte layer 150" in the recess 101 is laterally located between the covering structure 160 and the isolation structure 120. The microlens layer 170 is located above the covering structure 160.

In this embodiment, after the light L passes through the first lens 172 of the microlens layer 170, before reaching the auxiliary photosensitive element area 102', it will be weakened by the recess 101 and the extinction layer 150" therein, so that the amount of light irradiated to the auxiliary photosensitive element area 102' can be reduced to prevent the auxiliary photosensitive element area 102' from reaching charge saturation due to excessive light, thereby improving the recognition ability of the image sensor 10 in a high-intensity light environment.

FIG2 is a cross-sectional schematic diagram of an image sensor 20 according to another embodiment of the present invention. It must be noted that the embodiment of FIG2 uses the component numbers and partial contents of the embodiments of FIG1A to FIG1I, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the image sensor 20 of FIG. 2 and the image sensor 10 of FIG. 1I is that the matte layer 150" of the image sensor 20 does not have a first through hole at the bottom of the recess 101.

In this embodiment, after passing through the first lens 172 of the microlens layer 170, before reaching the auxiliary photosensitive element area 102, the light will not only be weakened by the extinction layer 150" on the side wall 101b of the recess 101, but will also be further weakened by the extinction layer 150" on the bottom surface 101a of the recess 101, thereby further reducing the amount of light irradiated to the auxiliary photosensitive element area 102.

In some embodiments, the thickness X3 of the matte layer 150" on the bottom surface 101a of the recess 101 is less than or equal to the thickness X4 of the matte layer 150" outside the recess 101. In some embodiments, the thickness X3 cannot be too thick, otherwise even if the light is very strong, it cannot pass through the matte layer 150" on the bottom surface 101a of the recess 101.

FIG3 is a cross-sectional schematic diagram of an image sensor 30 according to another embodiment of the present invention. It must be noted that the embodiment of FIG3 uses the component numbers and some contents of the embodiment of FIG2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the image sensor 30 of FIG. 3 and the image sensor 20 of FIG. 2 is that the isolation structure 120 of the image sensor 30 includes a conductive pillar 122 and an insulating material 124 surrounding the conductive pillar 122.

In some embodiments, a bias voltage may be applied to the conductive pillar 122 of the isolation structure 120 to suppress the generation of dark current in the image sensor 30.

FIG4 is a cross-sectional schematic diagram of an image sensor 40 according to another embodiment of the present invention. It must be noted that the embodiment of FIG4 uses the component numbers and partial contents of the embodiments of FIG1A to FIG1I, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the image sensor 40 of FIG. 4 and the image sensor 10 of FIG. 1I is that the extinction layer 150" of the image sensor 40 is only disposed in the recess 101 and does not extend outside the recess 101. Although FIG. 4 only depicts one of the auxiliary photosensitive element regions 102' and one of the recesses 101, the image sensor 40 may actually include multiple auxiliary photosensitive element regions 102' and multiple recesses 101. In this embodiment, the second through hole 152 of the extinction layer 150" is located between the extinction layers 150" in adjacent recesses 101.

In summary, through the design of the concave and matte layer, after the light passes through the microlens layer, before reaching the auxiliary photosensitive element area, it will be weakened by the concave and matte layer. Therefore, the amount of light irradiated to the auxiliary photosensitive element area can be reduced to prevent the auxiliary photosensitive element area from reaching charge saturation due to excessive light, thereby improving the recognition ability of the image sensor in a high-intensity light environment.

10: Image sensor

100’: semiconductor substrate

100a: First side

100b: Second side

101: Depression

101b: Side wall

102’: Auxiliary photosensitive element area

104: Photosensitive element area

110: Circuit structure

120: Isolation structure

130: Passivation layer

140: Etch stop layer

150”: Matt layer

152: Second through hole

160: Covering structure

162: First filter element

164: Second filter element

170: Micro-lens layer

172: First lens

174: Second lens

L: Light

Claims (10)

An image sensor includes: a semiconductor substrate, wherein the semiconductor substrate has a photosensitive element area and an auxiliary photosensitive element area, wherein the first side of the semiconductor substrate has a recess overlapping the auxiliary photosensitive element area; an isolation structure embedded in the semiconductor substrate and located between the photosensitive element area and the auxiliary photosensitive element area; a covering structure located above the first side of the semiconductor substrate and filled in the recess, wherein the covering structure filled in the recess overlaps the auxiliary photosensitive element area; and a matte layer located above the first side of the semiconductor substrate and at least partially filled in the recess, wherein the matte layer in the recess is laterally located between the covering structure and the isolation structure. An image sensor as described in claim 1, wherein the thickness of the auxiliary photosensitive element area is less than the thickness of the photosensitive element area. An image sensor as described in claim 1, wherein the recess is surrounded by the isolation structure. An image sensor as described in claim 1, wherein the matte layer includes a first through hole overlapping the auxiliary photosensitive element area and a second through hole overlapping the photosensitive element area. An image sensor as described in claim 1, wherein the thickness of the matte layer on the bottom surface of the recess is less than the thickness of the matte layer outside the recess. The image sensor as described in claim 1 further comprises: a passivation layer blanketing the first side of the semiconductor substrate and partially filling the recess; and an etch stop layer blanketing the passivation layer and partially filling the recess, wherein the matte layer is formed on the etch stop layer, and the covering structure is formed on the matte layer and the etch stop layer. An image sensor as described in claim 1, wherein the covering structure includes a color filter. The image sensor as described in claim 1 further comprises: a micro lens layer located above the covering structure, wherein the micro lens layer comprises a first lens overlapping the auxiliary photosensitive element area and a second lens overlapping the photosensitive element area, wherein the thickness of the first lens is less than the thickness of the second lens. A method for manufacturing an image sensor includes: providing a semiconductor substrate, wherein the semiconductor substrate has a photosensitive element region and an auxiliary photosensitive element region; forming an isolation structure in the semiconductor substrate, wherein the isolation structure is located between the photosensitive element region and the auxiliary photosensitive element region; forming a depression on a first side of the semiconductor substrate, wherein the depression overlaps the auxiliary photosensitive element region; forming a matte layer on the semiconductor substrate; The semiconductor substrate is formed on the first side of the semiconductor substrate, and at least a portion of the matte layer is filled into the recess; and a covering structure is formed on the first side of the semiconductor substrate, wherein the covering structure is filled into the recess, and the covering structure filled into the recess overlaps the auxiliary photosensitive element area, wherein the matte layer in the recess is laterally located between the covering structure and the isolation structure. The manufacturing method as described in claim 9, wherein when forming the recess on the first side of the semiconductor substrate, the thickness of the auxiliary photosensitive element area is reduced.