TWI866154B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a substrate having a first conductivity type, a first well regionhaving the first conductivity type and a second well region having a second conductivity type formed in the substrate. The semiconductor device also includes an isolation feature in the second well region and a third well region in the second well region, wherein the third well region has the first conductivity type and is in contact with the bottom surface of the isolation feature. The semiconductor device also includes a gate structure on the substrate and spans over the first well region and the second well region. The semiconductor device also includes a first doping region in the first well region and a second doping region in the second well region. The first doping region and the second doping region have the second conductivity type and are disposed at opposite sides of the gate structure. The isolation feature and the third well region are positioned between the first doping region and the second doping region. An interface between the first well region and the second well region is positioned between the isolation feature and the first doping region. The interface is apart from the third well region by a lateral distance.

Description

Semiconductor Devices

The present invention relates to a semiconductor device, and in particular to a semiconductor device with low on-resistance.

Semiconductor devices include a substrate and circuit components disposed on the substrate, and have been widely used in various electronic products, such as personal computers, mobile phones, digital cameras and other electronic equipment. The evolution of semiconductor devices continues to affect and improve people's lifestyles. Laterally diffused metal oxide semiconductors (LDMOS) in semiconductor devices have many advantages such as thermal stability, frequency stability and good heat dissipation, and are easily compatible with other MOS processes and are widely adopted. For example, they have been widely used in display driver IC components, power supplies, power management, communications, automotive electronics or industrial control.

However, the current semiconductor process is not satisfactory in every aspect. For example, in order to achieve the high on-resistance required by some applications to reduce the on-current, the existing lateral diffused metal oxide semiconductor device extends the length of the semiconductor device, thereby increasing the lateral size of the semiconductor device. Furthermore, the additional lateral space of each semiconductor device will also reduce the number of semiconductor devices manufactured on the wafer. Therefore, it is necessary to seek a new semiconductor device and its formation method to solve the above problems.

Some embodiments of the present disclosure provide a semiconductor device, comprising a substrate having a first conductivity type; a first well region disposed in the substrate, and the first well region has the first conductivity type; a second well region disposed in the substrate, the second well region has a second conductivity type, and the first well region surrounds the second well region; an isolation component disposed in the second well region; a third well region disposed in the second well region, and the third well region has the first conductivity type, wherein the third well region is adjacent to the isolation component. A bottom surface of the isolation component; a gate structure disposed on the substrate and straddling the first well region and the second well region; and a first doped region and a second doped region disposed in the first well region and the second well region and corresponding to two opposite sides of the gate structure, respectively, the first doped region and the second doped region having the second conductivity type, wherein the second well region and the first well region have an interface between the isolation component and the first doped region, and the third well region has a lateral distance from the interface.

The following disclosure provides a number of embodiments or examples for implementing different components of the provided semiconductor device. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first component formed on a second component, it may include an embodiment in which the first and second components are directly in contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that they are not directly in contact. In addition, the embodiments of the present invention may repeatedly refer to numbers and/or letters in different examples. Such repetition is for simplicity and clarity, and is not used to indicate the relationship between the different embodiments discussed.

Furthermore, spatially relative terms such as "under", "below", "below", "above", "above" and other similar terms may be used in the following description to simplify the description of the relationship between an element or component and other elements or other components as shown in the figure. These spatially relative terms include not only the direction depicted in the figure, but also different orientations of the device during use or operation. The device can be positioned in other directions (rotated 90 degrees or in other directions), and the spatially relative descriptions used herein should be interpreted accordingly.

Furthermore, the terms "about", "approximately", and "generally" usually mean within +/-20% of a given value, preferably within +/-10%, and more preferably within +/-5%, or within +/-3%, or within +/-2%, or within +/-1%, or within 0.5%. The numerical values given here are approximate values, that is, in the absence of specific description of "about", "approximately", and "generally", the given numerical values can still imply the meaning of "about", "approximately", and "generally".

It is understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or parts, these elements, components, regions, layers, and/or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or part discussed below may be referred to as a second element, component, region, layer, and/or part without departing from the teachings of the present disclosure.

Some variations of the embodiments are described below. Although the steps in some of the embodiments described are performed in a particular order, the steps may also be performed in other logical orders. In different embodiments, some of the steps described may be replaced or omitted, and some additional steps may be provided before, during, and/or after the steps described in some embodiments of the present invention. Furthermore, it is understood that other components may be added to the semiconductor device in some embodiments of the present invention. In different embodiments, some components may also be replaced or omitted.

The present disclosure provides a semiconductor device and a method for forming the same, which proposes a well region (e.g., the third well region proposed in the embodiment) adjacent to an isolation component, and the well region has a conductivity type different from that of the drain region, wherein the aforementioned isolation component is, for example, adjacent to a gate structure and a drain region, so as to increase the on-resistance (Ron) of the semiconductor device and reduce the on-current (on-current) of the semiconductor device. Furthermore, the well region (e.g., the third well region proposed below) proposed in the embodiment does not occupy additional lateral space of the device, and therefore does not increase the lateral size of the semiconductor device, thereby achieving the goal of reducing the on-current of the semiconductor device. In addition, the method for forming the semiconductor device proposed in the embodiment has a relatively simple process and is compatible with existing manufacturing processes. It does not require expensive manufacturing costs and can meet the requirements of the application device, so that the semiconductor device of the embodiment has a low conduction current.

Furthermore, the content of the embodiments can be applied to a metal-oxide-semiconductor (MOS) device, such as a laterally diffused MOS (LDMOS) device. In some of the following embodiments, the relevant structure of the laterally diffused MOS device is used as an example for explanation.

Figures 1A to 1E are schematic cross-sectional views of a semiconductor device 10 at various intermediate manufacturing stages according to some embodiments of the present disclosure.

1A, according to some embodiments, a substrate 100 is provided. Any substrate material suitable for semiconductor devices can be used. For example, the substrate 100 can be a bulk semiconductor substrate or a composite substrate formed of different materials. In some embodiments, the substrate may be an elemental semiconductor including silicon or germanium; a compound semiconductor including gallium nitride (GaN), silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; an alloy semiconductor including silicon germanium alloy (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium arsenide (GaInAs), gallium phosphide (GaInP) and/or gallium arsenide phosphide (GaInAsP), or a combination of the above materials. In some embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate, and the semiconductor on insulator substrate may include a base plate, a buried oxide layer disposed on the base plate, or a semiconductor layer disposed on the buried oxide layer.

Furthermore, in some embodiments, the substrate 100 may be doped with a p-type dopant or an n-type dopant to form the substrate 100 having a first conductivity type. In this embodiment, the first conductivity type is, for example, a p-type. For example, the p-type dopant may be boron (B), aluminum, gallium (Ga), BF ₂ , a similar material, or a combination of the foregoing materials, and the n-type dopant may be nitrogen, phosphorus (P), arsenic (As), antimony (Sb), a similar material, or a combination of the foregoing materials.

Afterwards, according to some embodiments, an isolation structure 110 is formed in the substrate 100. The isolation structure 110 includes a plurality of isolation components. These isolation components are, for example, separated in a first direction D1 and extend substantially in a second direction D2. The second direction D2 is, for example (but not limited to), perpendicular to the first direction D1. Furthermore, these isolation components are also formed from the top surface 100a of the substrate 100 toward the interior of the substrate 100. As shown in FIG. 1 , the isolation structure 110 includes a first isolation component 111, a second isolation component 112, a third isolation component 113, and a fourth isolation component 114. Furthermore, the top surface of the isolation structure 110 (e.g., the top surface 111a of the first isolation part 111, the top surface 112a of the second isolation part 112, the top surface 113a of the third isolation part 113, and the top surface 114a of the fourth isolation part 114) is coplanar with the top surface 100a of the substrate 100.

In some embodiments, the isolation structure 110 is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination of the aforementioned dielectric materials. Furthermore, in some embodiments, the isolation structure 110 can be formed by a local oxidation of silicon (LOCOS) isolation process, a shallow trench isolation (STI) process, or a combination of the aforementioned. In one example, the isolation structure 110 is a shallow trench isolation feature (STI features).

Referring to FIG. 1B , according to some embodiments, a first well region 121 is formed in the substrate 100, and the first well region 121 has a first conductivity type, such as a p-type. The first well region 121 has the same conductivity type as the substrate 100. Furthermore, according to some embodiments, a second well region 122 is formed in the substrate 100, and the second well region 122 has a second conductivity type, such as an n-type. The conductivity type of the second well region 122 is different from that of the first well region 121. Furthermore, the second well region 122 is adjacent to the first well region 121. The first well region 121 and the second well region 122 extend, for example, from the top surface 100a of the substrate 100 to the inside of the substrate 100.

According to some embodiments, when viewed from above the substrate 100, the first well region 121 surrounds the second well region 122. There is generally an interface between the first well region 121 and the second well region 122. Furthermore, the top surface 121a of the first well region 121 and the top surface 122a of the second well region 122 are generally coplanar with the top surface of the isolation structure 110 (e.g., the top surface 111a of the first isolation component 111, the top surface 112a of the second isolation component 112, the top surface 113a of the third isolation component 113, and the top surface 114a of the fourth isolation component 114) and the top surface 100a of the substrate 100.

In some semiconductor device applications, the first well region 121 may be a p-type well, and the second well region 122 may be an n-type well. Furthermore, in some high-voltage semiconductor device applications, the first well region 121 may be referred to as a high-voltage p-type well region (HVPW), and the second well region 122 may be referred to as a high-voltage n-type well region (HVNW).

According to some embodiments, the first well region 121 and the second well region 122 may be formed by an ion implantation process. For example, the first well region 121 and the second well region 122 having different conductivity types may be formed by two independent ion implantation processes. In some examples, the doping concentration of the first well region 121 is, for example, but not limited to, between about 1×10 ¹⁶ cm ^-3 and about 1×10 ¹⁸ cm ^-3 . The doping concentration of the second well region 122 is, for example, but not limited to, between about 1×10 ¹⁶ cm ^-3 and about 1×10 ¹⁸ cm ^-3 .

Furthermore, according to some embodiments, each isolation component included in the isolation structure 110 is located in a corresponding well area. Specifically, as shown in FIG. 1B, in one example, the first isolation component 111 is located in the second well area 122, and the second isolation component 112 is located in the first well area 121. Furthermore, in one example, the third isolation component 113 is located in the first well area 121 and the second well area 122, and the fourth isolation component 114 is located in the first well area 121 and the second well area 122, wherein the fourth isolation component 114 and the third isolation component 113 are located at two opposite sides of the first isolation component 111 and the second isolation component 112, respectively.

Referring to FIG. 1C , according to some embodiments, a third well region 130 is formed in the second well region 122, and the third well region 130 has a first conductivity type, such as a p-type. The third well region 130 has a different conductivity type from the second well region 122. The third well region 130 and other isolation components (such as the second isolation component 112, the third isolation component 113, and the fourth isolation component 114) other than the first isolation component 111 are separated in the first direction D1, and the third well region 130 extends substantially in the second direction D2.

According to some embodiments, the third well region 130 is adjacent to the first isolation member 111. For example, the third well region 130 directly contacts the bottom surface 111b of the first isolation member 111. For example, the third well region 130 may directly cover a portion or the entirety of the bottom surface 111b of the first isolation member 111. Furthermore, the third well region 130 of the embodiment is closer to the bottom surface 100b of the substrate 100 than the isolation member. More specifically, compared to the bottom surface 111b of the first isolation component 111, the bottom surface 112b of the second isolation component 112, the bottom surface 113b of the third isolation component 113, and the bottom surface 114b of the fourth isolation component 114, the bottom surface 130b of the third well region 130 is further inside the substrate 100 and closer to the bottom surface 100b of the substrate 100.

In addition, according to some embodiments of the present disclosure, the opposite side walls of the third well region 130 may be substantially flush with or uneven with the opposite sides of the bottom surface 111b of the first isolation member 111.

Specifically, in some examples, the third well region 130 includes a first sidewall 130S1 and a second sidewall 130S2 opposite to each other, and the first sidewall 130S1 is closer to the second isolation component 112, and the second sidewall 130S2 is closer to the third isolation component 113. The bottom surface 111b of the first isolation component 111 includes two opposite side edges 111b-S1 and 111b-S2. In one example, the first sidewall 130S1 of the third well region 130 is substantially flush with a side edge 111b-S1 of the bottom surface 111b of the first isolation component 111, as shown in FIG. 1C. In another example, the first sidewall 130S1 of the third well region 130 protrudes from one side 111b-S1 of the bottom surface 111b of the first isolation component 111. Furthermore, in one example, the second sidewall 130S2 of the third well region 130 is substantially flush with the other side 111b-S2 of the bottom surface 111b of the first isolation component 111, as shown in FIG. 1C. In another example, the second sidewall 130S2 of the third well region 130 is not flush with the other side 111b-S2 of the bottom surface 111b of the first isolation component 111, for example, the second sidewall 130S2 does not exceed or retracts from the other side 111b-S2 of the bottom surface 111b.

Therefore, according to the above, in some embodiments, the bottom surface 111b of the first isolation member 111 may be completely covered by the third well region 130, so that the bottom surface 111b does not contact the second well region 122 at all. Alternatively, in some other embodiments, the bottom surface 111b of the first isolation member 111 may be partially covered by the third well region 130, so that a portion of the bottom surface 111b is exposed in the second well region 122.

Furthermore, according to some embodiments, as shown in FIG. 1C , an interface 120S between the first well region 121 and the second well region 122 is located between the first isolation component 111 and the second isolation component 112, and the first sidewall 130S1 of the third well region 130 is separated from the interface 120S. For example, the first sidewall 130S1 of the third well region 130 is separated from the interface 120S by a lateral distance L1 in the first direction D1. In other words, the third well region 130 does not contact the interface 120S, that is, does not contact the first well region 121. According to some embodiments, by adjusting this lateral distance L1, a predetermined on-current value of the applied semiconductor device can be achieved. The smaller the lateral distance L1 is, the smaller the conduction current of the semiconductor device 10 is.

Furthermore, according to some embodiments, the third well area 130 may be offset or not offset from the first isolation component 111 above, and the present disclosure does not impose any restrictions thereon. Whether the offset setting between the upper and lower components occurs is determined by whether the center lines between the two side walls of the upper and lower components in the first direction D1 overlap. As shown in FIG. 1C , the center line C1 of the first isolation component 111 overlaps with the center line C2 of the third well area 130, and the third well area 130 is not offset from the first isolation component 111 above.

Furthermore, according to some embodiments, the third well region 130 can be formed at the bottom surface 111b adjacent to the first isolation member 111 by an ion implantation process. And after the ion implantation, the implanted dopant can be activated by heat treatment. The aforementioned heat treatment is, for example, a rapid thermal annealing (RTA) process or other suitable methods. In the application of a lateral diffused metal oxide semiconductor (LDMOS) device, the second well region 122 having a second conductivity type (e.g., n-type) can be used as a drift region of the semiconductor device 10. It is worth noting that in some embodiments, the doping concentration of the third well region 130 having the first conductivity type (e.g., p-type) is greater than the doping concentration of the second well region 122, so as to facilitate the inversion of the second conductivity type (e.g., n-type) to the first conductivity type (e.g., p-type). In some examples, the doping concentration of the third well region 130 is, for example (but not limited to), between about 1×10 ¹⁷ cm ^-3 and about 1×10 ¹⁹ cm ^-3 .

Referring to FIG. 1D , according to some embodiments, a gate structure 140 is formed on the substrate 100 (e.g., on the top surface 100a of the substrate 100), and the gate structure 140 is laterally arranged above the first well region 121 and the second well region 122. In some embodiments, the gate structure 140 includes a gate dielectric layer 141, a gate electrode 142 on the gate dielectric layer 141, and a gate spacer 143 on the opposite side of the gate electrode 142.

Furthermore, according to some embodiments, the gate structure 140 is located above the third well region 130, and a side edge _ES of the gate structure 140 closer to the first isolation member 111 is located on the top surface 111a of the first isolation member 111. The gate structure 140 extends in the first direction D1 without exceeding the top surface 111a of the first isolation member 111. Furthermore, specifically, as shown in FIG. 1D, a side wall 142S of the gate electrode 142 closer to the first isolation member 111 is correspondingly located above the third well region 130, and does not exceed the second side wall 130S2 of the third well region 130.

In some embodiments, the gate dielectric layer 141 may include a single or multiple gate dielectric material layers. In some examples, the gate dielectric layer 141 may include silicon oxide, silicon nitride, silicon oxynitride, similar materials, or a combination of the foregoing materials. A gate dielectric material layer may be formed on the substrate 100 by an oxidation process, a deposition process, a similar process, or a combination of the foregoing processes. The foregoing oxidation process may include, for example, a dry oxidation process or a wet oxidation process, and the foregoing deposition process may include, for example, a chemical deposition process. In some examples, a gate dielectric material layer may be formed using a thermal oxidation method or a similar process, and then a gate dielectric layer 141 may be formed through a suitable lithography patterning process and an etching process.

Furthermore, in some examples, the gate dielectric layer 141 may include a high-k dielectric material, such as a dielectric material with a dielectric constant greater than 3.9. For example, the high-k dielectric material may include (but is not limited to) metal oxides, metal nitrides, metal silicides, metal aluminates, zirconium silicates, zirconium aluminates, or combinations thereof. In some examples, the material of the gate dielectric layer 141 may include HfO ₂ , LaO ₂ , TiO ₂ , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₃ , HfZrO, ZrSiO ₂ , HfSiO ₄ , similar high-k dielectric materials, or combinations thereof. A gate dielectric material layer including a high-k dielectric material can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), similar deposition processes, spin coating processes, or a combination of the foregoing processes. In one example, the gate dielectric material layer includes a high-k dielectric material and is formed by a plasma enhanced CVD (PECVD), a suitable lithography patterning process, and an etching process.

According to some embodiments, the gate electrode 142 may include a single or multiple gate electrode material layers. In some examples, the gate electrode 142 may include amorphous silicon, polycrystalline silicon, metal nitride, conductive metal oxide, metal, other suitable materials, or a combination of the foregoing materials. The metal may include aluminum (Al), molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), halogen (Hf), or a combination of the foregoing metals, but is not limited to these metals. The conductive metal oxide may include ruthenium metal oxide or indium tin metal oxide, but is not limited to these metal oxides. In some embodiments, a gate electrode material layer may be formed by chemical vapor deposition, sputtering, resistive heating evaporation, electron beam evaporation, pulsed laser deposition, or other suitable methods. Thereafter, the gate electrode material layer is subjected to suitable lithography patterning and etching processes to form the gate electrode 142. The chemical vapor deposition mentioned above may be, for example, a low pressure chemical vapor deposition (LPCVD) process, a low temperature chemical vapor deposition (LTCVD) process, a rapid thermal CVD (RTCVD) process, a plasma enhanced CVD (PECVD) process, an atomic layer deposition (ALD) process, or other suitable methods.

In some examples, a gate spacer material layer (not shown) may be deposited on the substrate 100 and cover the gate dielectric material layer and the gate electrode 142. Thereafter, a portion of the gate spacer material layer and a portion of the gate dielectric material layer are removed by a suitable patterning process and an etching process, and a gate spacer 143 is formed on the sidewall of the gate electrode 142 and a gate dielectric layer 141 is formed under the gate electrode 142. In some examples, the gate spacer 143 may include a single or multiple layers of gate spacer material layers. The gate spacer 143 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing materials.

Referring to FIG. 1E , according to some embodiments, a first doped region 151 is formed in the first well region 121 and a second doped region 152 is formed in the second well region 122, and the first doped region 151 and the second doped region 152 have a second conductivity type, such as n-type. Furthermore, the first doped region 151 and the second doped region 152 correspond to two opposite sides of the gate structure 140, respectively. In some embodiments, as shown in FIG. 1E , the first isolation member 111 and the third well region 130 are located between the first doped region 151 and the second doped region 152.

Furthermore, in some examples, the interface 120S between the first well region 121 and the second well region 122 is located between the first isolation member 111 and the first doped region 151. The first sidewall 130S1 of the third well region 130 is adjacent to the first doped region 151, and the second sidewall 130S2 opposite to the first sidewall 130S1 is adjacent to the second doped region 152. According to some embodiments, a channel region 160 of the semiconductor device 10 is located between the sidewall 151S of the first doped region 151 and the interface 120S. The channel region 160 below the gate structure 140 has a channel length L _CH in the first direction D1.

In some embodiments, the first doped region 151 and the second doped region 152 may be formed by an ion implantation process or diffusion. After the ion implantation, the implanted dopants may be activated by a thermal treatment (e.g., rapid thermal annealing or other suitable methods). In the application of a lateral diffusion metal oxide semiconductor (LDMOS) device, the first doped region 151 and the second doped region 152 having a second conductivity type (e.g., n-type) may be used as a source region and a drain region of the semiconductor device 10, respectively. In some examples, the doping concentrations of the first doped region 151 and the second doped region 152 are, for example (but not limited to), between about 1×10 ¹⁸ cm ⁻³ and about 1×10 ²¹ cm ⁻³ . The doping concentration of the first doped region 151 is greater than the doping concentration of the first well region 121 , and the doping concentration of the second doped region 152 is greater than the doping concentration of the second well region 122 .

Furthermore, in some embodiments, after forming the doping concentration of the first doping region 151 and the second doping region 152, a third doping region 153 is further formed in the first well region 121, and the third doping region 153 has a first conductivity type, such as a p-type. In this example, the first doping region 151 is located between the third doping region 153 and the first isolation component 111. More specifically, the third doping region 153 is located between the second isolation component 112 and the fourth isolation component 114. In the application of a lateral diffused metal oxide semiconductor (LDMOS) device, the third doping region 153 having the first conductivity type (e.g., p-type) is used as a bulk region of the semiconductor device 10. In some examples, the doping concentration of the third doped region 153 is, for example but not limited to, between about 1×10 ¹⁸ cm ⁻³ and about 1×10 ²¹ cm ⁻³ .

It is worth noting that according to some embodiments of the present disclosure, the doping concentration of the third well region 130 having the first conductivity type (e.g., p-type) is less than the doping concentration of the first doping region 151 and the doping concentration of the second doping region 152, and is also less than the doping concentration of the third doping region 153, so that the semiconductor device 10 has a sufficiently high breakdown voltage (BDV).

When the semiconductor device 10 of the embodiment is operated, the current flows from the first doped region 151 (source region) through the channel region 160, and along one side wall of the first isolation member 111, the first side wall 130S1 of the third well region 130, the bottom surface of the third well region 130, the second side wall 130S2 of the third well region 130, and the other side wall of the first isolation member 111 to the second doped region 152 (drain region). The current flow direction is shown by the dotted line segment I1 in FIG. 1E. Compared to the current of a conventional semiconductor device flowing along the surface of the isolation component, the current of the semiconductor device 10 of the embodiment will enter deeper into the substrate 100 and have a longer current path, thereby reducing the current density when the semiconductor device 10 is turned on. That is, the current of the semiconductor device 10 will have a longer current path in the second well region 122 (drift region). Furthermore, according to the setting of the third well region 130 of the embodiment, a limiting effect will be produced on the current that is intended to flow into the region 162 (located between the junction 120S and the side edge _E1 of the first isolation component 111), thereby reducing the current entering the second well region 122 (drift region), thereby reducing the current density when the semiconductor device 10 is turned on. Therefore, according to the above, the semiconductor device 10 with the third well region 130 of the embodiment can reduce its on-current. In addition, the closer the third well region 130 is to the boundary 120S (that is, the smaller the lateral distance L1 discussed in FIG. 1C above), the smaller the on-current of the semiconductor device 10.

FIG. 2 is a schematic top view of a semiconductor device according to some embodiments of the present disclosure. Please refer to FIG. 1E and FIG. 2. FIG. 1E is, for example, a schematic cross-sectional view taken along a section line 1E-1E of FIG. 2. The same or similar components in FIG. 2 and FIG. 1E use the same or similar reference numbers, and the contents of these components in the above embodiments can be referred to.

Referring to FIG. 2 , according to some embodiments, when viewed from above the substrate, a first well region 121 having a first conductivity type (e.g., p-type) surrounds a second well region 122 having a second conductivity type (e.g., n-type). The gate structure 140 is laterally disposed above the first well region 121 and the second well region 122. A first doped region 151 (e.g., serving as a source region) and a second doped region 152 (e.g., serving as a drain region) having a second conductivity type (e.g., n-type) are separated in a first direction D1 and extend along a second direction D2. The first doped region 151 and the second doped region 152 are respectively located at two opposite sides of the gate structure 140. In some embodiments, when viewed from above the substrate, the third doped region 153 (e.g., serving as a base region) having a first conductivity type (e.g., p-type) is a ring-shaped doped region that surrounds the first doped region 151, the gate structure 140, the second well region 122, and the second doped region 152 in a closed manner.

Furthermore, in some embodiments, when viewed from above the substrate, the third well region 130 is in the shape of a long strip, and the third well region 130, the first doped region 151, and the second doped region 152 extend in the same direction (e.g., the second direction D2). The annular third doped region 153 also surrounds the periphery of the third well region 130.

More specifically, as shown in FIG. 2 , the two sides of the third well region 130 in a strip shape are separated from the first doped region 151 and the second doped region 152 in a first direction D1, wherein the third well region 130, the first doped region 151 and the second doped region 152 extend in a second direction D2, which is different from the first direction D1. The first isolation member 111 and the third well region 130 extend between the first doped region 151 and the second doped region 152. Therefore, in this example, the third well region 130 extends only below the first isolation member 111 and on one side of the corresponding gate structure 140, and the third well region 130 does not surround the first doped region 151 or the gate structure 140.

Furthermore, in some embodiments, the third well region 130 can be electrically connected to the third doped region 153 (for example, as a substrate region). The strip-shaped third well region 130 can extend to the second well region 122 (as shown in FIG. 2 ) or exceed the second well region 122 and contact the first well region 121. More specifically, two edges 130-1 and 130-2 of the third well region 130 in the second direction D2 can respectively exceed two edges 122-1 and 122-2 of the second well region 122 in the second direction D2. In other words, in some examples, an extension length of the third well region 130 in the second direction D2 is greater than an extension length of the second well region 122 in the second direction D2. As shown in FIG. 2, since the third doped region 153 contacts the first well region 121, the third well region 130 contacting the first well region 121 is also electrically connected to the third doped region 153. When the semiconductor device is operating, the third doped region 153 is grounded, and the charge accumulated in the third well region 130 can be discharged through the electrically connected third doped region 153, so that the electrical performance of the semiconductor device (such as the voltage-current curve (I-V curve)) is more stable. However, the present disclosure is not limited to this example.

In some other examples, the third well region 130 may also be electrically insulated from the first well region 121 and the third doped region 153 and be in a floating state. For example, the strip-shaped third well region 130 is retracted into the second well region 122 and does not contact the first well region 121 (not shown). More specifically, the two edges 130-1 and 130-2 of the third well region 130 in the second direction D2 do not contact or exceed the two edges 122-1 and 122-2 of the second well region 122 in the second direction D2.

The details of the configuration, materials and manufacturing methods of the substrate 100, the first well region 121, the second well region 122, the isolation structure 110, the third well region 130, the gate structure 140, the first doped region 151, the second doped region 152 and the third doped region 153 in the above-mentioned Figure 2 can be referred to the description of the relevant contents of the above-mentioned Figures 1A to 1E, and will not be repeated here.

In addition, in the above-mentioned embodiment, the sidewalls of the third well region 130 are roughly flush with the two sides of the first isolation component 111, and the third well region 130 has a roughly symmetrical cross-sectional shape, but the present disclosure is not limited thereto.

Figures 3A to 3C are schematic cross-sectional views of a semiconductor device 20 at various intermediate manufacturing stages according to some embodiments of the present disclosure. The same or similar components in Figures 3A to 3C as those in Figures 1A to 1E use the same or similar reference numbers, and the contents of these components in the above embodiments can be referred to.

As shown in FIG. 1E, the opposite side walls of the third well region 130 are substantially flush with the opposite sides of the bottom surface 111b of the first isolation component 111, but the present disclosure is not limited thereto. In some examples, as shown in FIG. 3C, the opposite side walls of the third well region 330 are not flush with the opposite sides of the bottom surface 111b of the first isolation component 111, and in particular, the third well region 330 may protrude from one side 111b-S1 of the bottom surface 111b of the first isolation component 111 toward the interface 120S between the first well region 121 and the second well region 122. Furthermore, the third well region 330 has an asymmetric cross-sectional shape.

Referring to FIG. 3A, according to some embodiments, a first conductive type (e.g., p-type) dopant is implanted into a region 33 by ion implantation, and the region 33 is adjacent to the bottom surface 111b of the first isolation member 111. The region 33 includes a first sidewall 33S1 that is closer to the second isolation member 112 and a second sidewall 33S2 that is closer to the third isolation member 113. Furthermore, in this example, the first sidewall 33S1 of the region 33 is substantially flush with one side 111b-S1 of the bottom surface 111b of the first isolation member 111, and the second sidewall 33S2 does not exceed (i.e., is retracted to) the other side 111b-S2 of the bottom surface 111b.

The details of the configuration, materials and manufacturing methods of the substrate 100, the first well area 121, the second well area 122 and the isolation structure 110 in the structure of Figure 3A can be found in the description of the relevant contents of Figures 1A to 1B above, and will not be repeated here.

Referring to FIG. 3B , according to some embodiments, after the ion implantation, a heat treatment is performed, such as a rapid thermal annealing (RTA) process or other suitable method, to activate the implanted first conductivity type (e.g., p-type) dopant, so that the region 33 diffuses outward to form a third well region 330.

In some embodiments, the third well region 330 includes a first sidewall 330S1 closer to the second isolation component 112 and a second sidewall 330S2 closer to the third isolation component 113. In some examples, the first sidewall 330S1 of the third well region 330 protrudes from one side 111b-S1 of the bottom surface 111b of the first isolation component 111, and the second sidewall 330S2 is, for example, substantially flush with or retracted from the other side 111b-S2 of the bottom surface 111b. As shown in FIG. 3B, more specifically, in some examples, the third well region 330 directly covers at least a portion of the bottom surface 111b of the first isolation component 111, and extends to the first side wall 111S1 of the first isolation component 111 (the side wall closer to the interface 120S between the first well region 121 and the second well region 122), and covers the lower portion of the first side wall 111S1. Therefore, as shown in FIG. 3B, the first side wall 130S1 of the third well region 330 protrudes further from the first side wall 111S1 of the first isolation component 111, and is closer to the interface 120S between the first well region 121 and the second well region 122.

In addition, as shown in FIG. 3B, according to some embodiments, the third well region 330 has an asymmetric cross-sectional shape. Furthermore, the center line C1 of the first isolation component 111 and the center line C2' of the third well region 330 do not coincide, and the position of the third well region 330 is offset from the position of the first isolation component 111 above.

Then, referring to FIG. 3C , according to some embodiments, a gate structure 140 is formed on the substrate 100, and a first doped region 151, a second doped region 152, and a third doped region 153 are formed. The gate structure 140 is located above the third well region 130, and a channel region 160 of the semiconductor device 20 is formed between the sidewall 151S of the first doped region 151 and the interface 120S. Similar to the example of FIG. 1E above, in the example of FIG. 3C , the channel region 160 located below the gate structure 140 has a channel length L _CH in the first direction D1. The remaining details of the configuration, materials and manufacturing methods of the gate structure 140, the first doped region 151, the second doped region 152 and the third doped region 153 in FIG. 3C can be referred to the description of the relevant contents of the above-mentioned FIGS. 1D to 1E, which will not be repeated here.

When the semiconductor device 20 of the embodiment is operated, the current flows from the first doped region 151 (source region) through the channel region 160 and the region 162, and along one side wall of the first isolation member 111, the first side wall 330S1, the bottom surface and the second side wall 330S2 of the third well region 330, and the other side wall of the first isolation member 111 to the second doped region 152 (drain region). The current flow direction is shown by the dotted line segment I2 in FIG. 3C .

Therefore, in the semiconductor device 20 shown in FIG. 3C , the first side wall 330S1 of the third well region 330 protrudes beyond the bottom surface 111b of the first isolation component 111 and is closer to the interface 120S between the first well region 121 and the second well region 122, thereby limiting the current that wants to flow into the region 162 (located between the interface 120S and the side edge _E1 of the first isolation component 111), thereby reducing the current that enters the second well region 122 (drift region), thereby reducing the conduction current of the semiconductor device 20.

Furthermore, compared to the third well region 130 shown in FIG. 1E, the lateral distance L1' between the third well region 330 and the junction 120S shown in FIG. 3C is smaller than the lateral distance L1 between the third well region 130 and the junction 120S, so the semiconductor device 20 shown in FIG. 3C has a lower conduction current.

In addition, according to some embodiments, a shielding member may be formed above the substrate 100 corresponding to the third well region 330 to increase the breakdown voltage (BDV) of the semiconductor device.

FIG. 4 is a cross-sectional schematic diagram of a semiconductor device 30 according to some embodiments of the present disclosure. The same or similar components in FIG. 4 as those in FIGS. 1A to 1E use the same or similar reference numbers, and the contents of the components in the above embodiments can be referred to. Furthermore, the remaining details of the configuration, materials and manufacturing methods of the components in FIG. 4, such as the substrate 100, the first well region 121, the second well region 122, the isolation structure 110, the gate structure 140, the first doped region 151, the second doped region 152 and the third doped region 153, can be referred to the description of the relevant contents of the above FIGS. 1A to 1E, which will not be repeated here.

Unlike FIG. 1E, in the semiconductor device 30 shown in FIG. 4, a conductive portion 442 is formed above the substrate 100, and the conductive portion 442 is located on one side of the gate electrode 142 of the gate structure 140. In some embodiments, the conductive portion 442 is located above the first isolation component 111 and the third well region 130. Specifically, in one example, the conductive portion 442 has a first sidewall 442S1 closer to the gate electrode 142 and a second sidewall 442S2 farther from the gate electrode 142, wherein the second sidewall 442S2 does not exceed the range of the first isolation component 111.

Furthermore, according to some embodiments, the conductive portion 442 is disposed between two opposite first side walls 111S1 and second side walls 111S2 of the first isolation member 111; that is, the conductive portion 442 is disposed within the first side walls 111S1 and second side walls 111S2 of the first isolation member 111. Therefore, in one example, a vertical projection range of the first isolation member 111 on the substrate 100 covers a vertical projection range of the conductive portion 442 on the substrate 100.

In some embodiments, the conductive portion 442 may include the same material as the gate electrode 142, and a portion of the gate electrode material layer is removed by a suitable patterning process and an etching process, so that the gate electrode material layer is separated into two independent parts, which are used as the subsequent gate electrode 142 and the conductive portion 442. Thereafter, a gate spacer material layer is deposited on the gate electrode 142 and the conductive portion 442, and conformally covers the gate electrode 142 and the conductive portion and fills the gap between the gate electrode 142 and the conductive portion 442. Afterwards, a suitable patterning process and etching process are used to remove part of the gate spacer material layer and part of the gate dielectric material layer, and the remaining part of the gate spacer material layer forms a gate spacer 143 and an insulating member filled between the gate electrode 142 and the conductive part 442. The material of the conductive part 442 can refer to the relevant content of the above-mentioned gate electrode 142, which will not be repeated here.

Furthermore, according to some embodiments, the conductive portion 442 is electrically isolated from the gate electrode 142. In some examples, the conductive portion 442 is grounded. For example, the conductive portion 442 can be electrically connected to the third doped region 153 (e.g., as a substrate region) by connecting to the first well region 121. In some examples, the conductive portion 442 can also be electrically connected to the drain region 152 to increase the breakdown voltage.

Although FIG. 4 is an example of a third well region 130 having a substantially symmetrical cross-sectional shape and not offset from the first isolation component 111 above as shown in FIG. 1E, the present disclosure is not limited thereto. The semiconductor device may also select a third well region 330 having an asymmetrical cross-sectional shape as shown in FIG. 3C or a third well region with other cross-sectional shapes. Furthermore, the third well region may also be offset from the first isolation component 111 above, wherein the offset setting is defined by the fact that the center line of the first isolation component 111 does not coincide with the center line of the third well region.

In summary, according to some embodiments of the present disclosure, a semiconductor device and a method for forming the same are provided to obtain a semiconductor device including a well region (e.g., a third well region 130 or 330) adjacent to an isolation component (e.g., a first isolation component 111 adjacent to a gate structure and a drain region), wherein the well region has a conductivity type (e.g., p-type) different from that of the drain region, so as to increase the on-resistance of the semiconductor device and reduce the on-current of the semiconductor device. According to some embodiments, the interface 120S between the sidewall (e.g., first sidewall 130S1 or 330S1) of the third well region 130 or 330 and the first well region 121 and the second well region 122 below the gate structure 140 is separated by a lateral distance L1 or L1′. The smaller the lateral distance L1 or L1' is, the smaller the on-current of the semiconductor device is. By adjusting the lateral distance L1 or L1' of the embodiment, the current flowing into the region 162 (located between the junction 120S and the side edge _E1 of the first isolation component 111; FIG. 1E) can be controlled, so that the applied semiconductor device reaches its predetermined on-current value. Furthermore, the third well region formed in the semiconductor device proposed in the embodiment does not occupy additional lateral space (e.g., along the first direction D1) of the device, and therefore does not increase the lateral size of the semiconductor device, which can reduce the on-current value of the semiconductor device.

Furthermore, the third well region 130 proposed in the present disclosure may be arranged not offset from the first isolation member 111 as shown in the embodiments of FIGS. 1E and 4; or, the third well region 130 may be arranged offset from the first isolation member 111 as shown in the embodiment of FIG. 3C, and the present disclosure does not impose any restrictions thereon. Furthermore, the third well region 130 may have a symmetrical cross-sectional shape as shown in the exemplary embodiment of FIG. 1E; or, the third well region 330 may have an asymmetrical cross-sectional shape as shown in the exemplary embodiment of FIG. 3C, and the present disclosure does not impose any restrictions thereon. Furthermore, in some embodiments, a shielding member electrically isolated from the gate electrode 142, such as a grounded conductive portion 442 (FIG. 4), may be provided on one side of the gate electrode 142, and the shielding member corresponds to the first isolation member 111 and the third well region 130 to further increase the breakdown voltage of the semiconductor device. In addition, the method for forming the semiconductor device proposed in the embodiment can be used to manufacture a semiconductor device with a third well region through a simple process compatible with existing manufacturing, so the manufacturing process of the embodiment is simple and does not require expensive manufacturing costs.

Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure content of some embodiments of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described here, they can be used according to some embodiments of the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application scope constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each patent application scope and embodiment.

10,20,30:Semiconductor devices

100: Base

110: Isolation structure

111: First isolation component

112: Second isolation component

113: The third isolation component

114: Fourth isolation component

120S: Interface

121: First well area

122: Second well area

130,330: The third well area

111S1,130S1,33S1,330S1,442S1: First side wall

111S2,130S2,33S2,330S2,442S2: Second side wall

140: Gate structure

141: Gate dielectric layer

142: Gate electrode

143: Gate spacer

E _S ,E _I : Side edge

142S: Side wall of gate electrode

151: First mixed area

151S; side wall of the first doping zone

152: Second mixed area

153: The third mixed area

160: Channel area

162,33: Area

442: Conductive part

100a,111a,112a,113a,114a,121a,122a: top surface

100b,111b,112b,113b,114b,130b: bottom surface

111b-S1,111b-S2: Side

130-1,130-2,122-1,122-2: Edge

L1,L1’: horizontal distance

C1,C2,C2’: center line

L _CH : Channel length

D1: First direction

D2: Second direction

I1, I2: current flow direction

Figures 1A, 1B, 1C, 1D, and 1E are schematic cross-sectional views of a semiconductor device at various intermediate manufacturing stages according to some embodiments of the present disclosure.

FIG. 2 is a schematic top view of a semiconductor device according to some embodiments of the present disclosure.

Figures 3A, 3B, and 3C are schematic cross-sectional views of a semiconductor device at various intermediate manufacturing stages according to some embodiments of the present disclosure.

FIG. 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

10: semiconductor device 100: substrate 111: first isolation member 112: second isolation member 113: third isolation member 114: fourth isolation member 120S: interface 121: first well region 122: second well region 130: third well region 130S1, 130S2, 142S, 151S: sidewall 140: gate structure 141: gate dielectric layer 142: gate electrode 143: gate spacer 151: first doped region 152: second doped region 153: third doped region 160: channel region 162: region 111a: top surface I1: current flow direction E _I : Side L1: Horizontal distance L _CH : Channel length D1: First direction D2: Second direction

Claims (16)

A semiconductor device includes: a substrate having a first conductivity type; a first well region disposed in the substrate and having the first conductivity type; a second well region disposed in the substrate and having a second conductivity type; an isolation component disposed in the second well region; a third well region disposed in the second well region and having the first conductivity type, wherein the third well region is adjacent to a bottom surface of the isolation component; a gate structure disposed on the substrate and straddling the first well region and the second well region; and A first doped region and a second doped region are respectively disposed in the first well region and the second well region and correspond to two opposite sides of the gate structure, respectively. The first doped region and the second doped region have the second conductivity type, wherein the second well region and the first well region have an interface between the isolation component and the first doped region, and the third well region has a lateral distance from the interface. A semiconductor device as claimed in claim 1, wherein the third well region directly covers a portion or the entirety of the bottom surface of the isolation component. A semiconductor device as claimed in claim 1, wherein a doping concentration of the third well region is greater than a doping concentration of the second well region. A semiconductor device as claimed in claim 1, wherein a doping concentration of the third well region is less than a doping concentration of the first doping region. A semiconductor device as claimed in claim 1, wherein the third well region comprises: a first sidewall adjacent to the first doped region; and a second sidewall opposite to the first sidewall and adjacent to the second doped region; wherein the first sidewall protrudes from a side of the bottom surface of the isolation component. A semiconductor device as claimed in claim 5, wherein the second side wall does not extend beyond the other side of the bottom surface of the isolation component. A semiconductor device as claimed in claim 1, wherein the third well region further covers a portion of a side wall of the isolation component, and the side wall is adjacent to the first doped region. As in the semiconductor device of claim 1, wherein the third well region is in the shape of a long strip when viewed from above the substrate, and the first doped region, the third well region and the second doped region extend in the same direction. A semiconductor device as claimed in claim 1, wherein the third well region is electrically connected to the first well region. A semiconductor device as claimed in claim 1, wherein the third well region is electrically isolated from the first well region. The semiconductor device of claim 1 further includes: A conductive portion located above the substrate and on one side of a gate electrode of the gate structure, and the conductive portion is electrically isolated from the gate electrode; wherein the conductive portion is located above the isolation component. A semiconductor device as claimed in claim 11, wherein the conductive portion is located correspondingly above the third well region. The semiconductor device of claim 1 further comprises: A third doped region disposed in the first well region, and the third doped region has the first conductivity type; wherein the first doped region is located between the third doped region and the isolation component, and a doping concentration of the third well region is less than a doping concentration of the third doped region. As in the semiconductor device of claim 13, wherein the third doped region is an annular doped region viewed from above the substrate and surrounds the first doped region, the gate structure, the second well region, the third well region and the second doped region in a closed manner. A semiconductor device as claimed in claim 13, wherein the isolation component is a first isolation component, and the semiconductor device further comprises: a second isolation component disposed in the first well region, and the second isolation component is located between the third doped region and the first doped region; wherein a bottom surface of the third well region is closer to a bottom surface of the substrate than a bottom surface of the second isolation component. The semiconductor device of claim 15 further comprises: a third isolation component located in the first well region and the second well region, and the second doped region is located between the first isolation component and the third isolation component; and a fourth isolation component located in the first well region and the second well region, and located on two opposite sides of the gate structure with the third isolation component, and the third doped region is located between the fourth isolation component and the second isolation component; wherein, compared with a bottom surface of the third isolation component and a bottom surface of the fourth isolation component, the bottom surface of the third well region is closer to a bottom surface of the substrate.

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