TWI865275B - Logical address transformation device and method - Google Patents

Abstract

A transformation method comprises the following steps. A logical address is received, wherein the logical address is for accessing a memory unit of a memory device. A vertical coordinate is generated according to the logical address and a row rule. A horizontal coordinate is generated according to the logical address and a column rule. A physical address is generated according to the vertical coordinate and the horizontal coordinate, wherein the physical address indicates a position of the memory unit in a physical space of the memory device.

Description

Logical address conversion device and method

The present disclosure relates to an address conversion device and method, and more particularly to a device and method for converting a logical address of a storage device into a physical address.

In order to detect the location of a faulty particle in a storage device (e.g., dynamic random access memory (DRAM)), it is necessary to convert the logical address detected by the computer as inaccessible or accessed incorrectly into the physical address of the faulty particle in the physical space of the storage device, so that subsequent engineers can detect the faulty particle and further analyze the cause of the failure.

However, the specifications of various storage device products are different, and the rules for converting logical addresses to physical addresses are also different. It is necessary to refer to the architecture of each product and use the storage device product test machine to perform the conversion. The operation is complicated and inconvenient to use. In addition, since the test machine is not designed for converting logical addresses, mapping errors are prone to occur.

The present disclosure provides a conversion method comprising the following steps: receiving a first logical address, the first logical address being used to access a first storage unit in a storage device; generating a first vertical coordinate according to the first logical address and a row rule; generating a first horizontal coordinate according to the first logical address and a line rule; and generating a first physical address according to the first vertical coordinate and the first horizontal coordinate, wherein the first physical address is used to indicate a first position of the first storage unit in the physical space of the storage device.

The present disclosure also provides a conversion device, which includes a processor. The processor is used to perform the following operations: receiving a first logical address, the first logical address is used to access a first storage unit in a storage device; generating a first vertical coordinate according to the first logical address and a row rule; generating a first horizontal coordinate according to the first logical address and a row rule; and generating a first physical address according to the first vertical coordinate and the first horizontal coordinate, wherein the first physical address is used to indicate a first position of the first storage unit in a physical space of the storage device.

The present disclosure also provides a non-transitory computer-readable storage medium having at least one instruction stored thereon. When a processing unit executes the instructions, the instructions execute the above-mentioned conversion method.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the disclosure as claimed.

In order to make the description of the present disclosure more detailed and complete, reference may be made to the attached drawings and various embodiments described below, in which the same numbers in the drawings represent the same or similar elements.

Please refer to FIG. 1, which is a schematic diagram of a conversion device 12 and a display device 14 in some embodiments of the present disclosure. As shown in FIG. 1, the conversion device 12 includes a processor 122 and is coupled to the display device 14. The conversion device 12 is used to convert a logical address of a storage device into a physical address, and generate a mark image including a mark according to the physical address.

The storage device includes a plurality of storage units, the logical address is used to access one of the storage units, and the physical address is used to indicate the physical location of one of the storage units in the storage unit, that is, the location where one of the storage units is set in the physical space within the storage unit. In one embodiment, the storage device may include a dynamic random access memory (DRAM).

In some embodiments, the conversion device 12 may include a personal computer that runs a Windows operating system. In some embodiments, the processor 122 may include a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC) and/or a suitable computing unit.

The display device 14 is used to display the image received from the conversion device 12, such as a marked picture including a physical location mark. In some embodiments, the display device 14 may include a display screen.

Please refer to FIG. 2, which is a schematic diagram of a conversion method 20 in some embodiments of the present disclosure. The conversion method 20 includes steps S202, S204, S206, S208, S210, S212, S214 and S216, and is used to convert the logical address of the storage device into a physical address, and generate a label image including a label according to the physical address. In some embodiments, the conversion method 20 can be executed by the conversion device 12 shown in FIG. 1.

In step S202, the conversion method 20 generates a drawing, wherein the drawing is used to represent the physical space of the storage device. In one embodiment, the conversion method 20 generates the drawing according to a drawing rule, wherein the drawing rule includes the distribution of storage units of different storage device types in the physical space. In one embodiment, the conversion method 20 generates the drawing through an Excel program, wherein at least one storage unit is represented by a cell in a worksheet.

In step S204, the conversion method 20 receives a logical address. In some embodiments, the logical address can be received in the form of a text file. In some embodiments, the logical address is a csv file, a txt file, an xls file, an xlsx file, or a combination thereof.

In one embodiment, the logical address received by the conversion method 20 may be a storage unit in the corresponding storage device that cannot be accessed. However, the logical address received by the conversion method 20 is not limited to the aforementioned storage unit that cannot be read. In another embodiment, the logical address received by the conversion method 20 may be a storage unit in the storage device that is read most frequently.

In step S206, the conversion method 20 converts the format of the logical address. In some embodiments, the logical address has a data bit width format, and the data bit width format is one of a 4-bit width format, an 8-bit width format, and a 16-bit width format, and the conversion method 20 converts the logical address into a 4-bit width format in response to the received logical address being in an 8-bit width format; and converts the logical address into a 4-bit width format in response to the received logical address being in a 16-bit width format.

In step S208, the conversion method 20 generates vertical coordinates according to the logical address and the row rule. The row rule is used to convert all or part of the logical address to generate the vertical coordinates; the vertical coordinates are used to indicate the vertical position of the storage unit in the physical space.

In step S210, the conversion method 20 generates horizontal coordinates according to the logical address and the row rule. The row rule is used to convert all or part of the logical address to generate horizontal coordinates; the horizontal coordinates are used to indicate the horizontal position of the storage unit in the physical space.

In step S212, the conversion method 20 generates a physical address according to the vertical coordinate and the horizontal coordinate. According to the vertical coordinate and the horizontal coordinate, the conversion method 20 can generate a physical address for indicating the location of the storage unit in the physical space.

In step S214, the conversion method 20 marks the drawing according to the physical address. After the conversion method 20 generates the physical address, a mark is generated at the position corresponding to the physical address in the drawing, and the mark is used to indicate the position of the storage unit corresponding to the physical address (that is, the storage unit corresponding to the logical address) in the drawing.

It should be noted that after the marking is completed in step S214, the conversion method 20 can then return to step S204 to receive another logical address, and execute S206 to S214 according to the other logical address until all the logical addresses that need to be converted and marked are completed.

In step S216, the conversion method 20 generates a marked image based on the marked drawing. After completing one or more marks in the drawing, the conversion method 20 generates a marked image, wherein the marked image includes a mark indicating the physical location of the storage unit corresponding to the logical address.

Please refer to FIG. 3, which is a schematic diagram of a user interface 30 in some embodiments of the present disclosure. In some embodiments, the conversion device 12 provides the user interface 30 through the display device 14, and the user adjusts the parameters of the conversion device 12 when performing the conversion of the logical address by operating the user interface 20. As shown in the figure, the user interface 30 includes device-specific settings, which allows the user to select the storage device type corresponding to the logical address to be converted. Further, the conversion device 12 will convert the logical address with the corresponding conversion parameters according to the storage device type selected by the user.

In addition, the user interface 30 also includes a check box for conversion format settings. When the user checks the box, the conversion device 12 will convert the logical address into a specific format before converting the logical address. In one embodiment, the logical address has a data bit width format, and the data bit width format is one of a four-bit width format (x4), an eight-bit width format (x8), and a sixteen-bit width format (x16/xF). The four-bit width indicates that a storage unit (e.g., a chip) in the corresponding storage device can store four bits. By analogy, the eight-bit width and the sixteen-bit width respectively indicate that a storage unit in the corresponding storage device can store eight bits and sixteen bits.

In this embodiment, when the user checks the check box of the conversion format setting in the user interface 30, the conversion device 12 converts the logical address into a 4-bit width format before converting the logical address into a physical address. The details of the conversion device 12 converting the logical address format will be described in the following paragraphs.

Furthermore, the user interface 30 also includes other setting fields, which provide the user with field settings for confirming the input logical address data, as well as drawing-related settings for drawing marker images (for example: whether to generate a frame line, the color of the marker in the image). The conversion device 12 will convert the logical address according to the field settings in the user interface 30, and generate a marker image according to the drawing settings.

After the user selects the device type as memory A in the user interface 30, the conversion device 12 accesses the conversion parameters and performs operations of generating a drawing and converting a logical address according to the conversion parameters. Please refer to FIG. 4, which is a schematic diagram of the conversion parameters 40 in some embodiments of the present disclosure. The conversion parameters 40 include a device type 402, a drawing rule 404, a row rule 406, and a line rule 408.

The device type 402 is used to indicate the storage device corresponding to the conversion parameter 40. In this embodiment, the conversion parameter 40 corresponds to the A memory.

The drawing rule 404 is used to indicate the distribution of the storage units of the A memory in the physical space, and the conversion device 12 can generate a drawing corresponding to the A memory according to the drawing rule 404. The drawing rule 404 includes specification parameters corresponding to the A memory. In this embodiment, the drawing rule 404 includes the number of banks (Number_of_Bank shown in the figure) of 16, the number of rows (Number_of_Row shown in the figure) of 2097152, and the number of columns (Number_of_Col shown in the figure) of 1024, which are used to indicate the number of storage units at each level in the A memory.

Secondly, the drawing rule 404 also includes a J/K bit (J/K Bit shown in the figure) as RA16 and a P/Q bit (P/Q Bit shown in the figure) as RA15, which are respectively used to indicate that the RA16 bit in the logical address is the J/K bit and the RA15 bit in the logical address is the P/Q bit.

In addition, when the conversion device 12 draws the marked image, due to the large number of storage units in the memory device, each storage unit cannot be represented by a data cell and needs to be compressed, so that one data cell represents multiple storage units. Therefore, the drawing rule 404 also includes a row compression amount (Row_Compress shown in the figure) of 512 and a line compression amount (Col_Compress shown in the figure) of 512, which are used to indicate that 512 storage units are a data row and 512 storage units are a data row, that is, one data cell represents 512*512 storage units.

The row rule 406 is a rule used by the conversion device 12 to convert a logical address into a vertical coordinate, and the specific rules of the row rule 406 will be described in the following paragraphs. On the other hand, the row rule 408 is a rule used by the conversion device 12 to convert a logical address into a horizontal coordinate, and similarly, the specific rules of the row rule 408 will be described in the following paragraphs.

Further, the conversion device 12 generates a drawing 50 according to the drawing rule 404 in the conversion parameter 40. Please refer to Figure 5, which is a schematic diagram of the drawing 50 in the embodiment of the present disclosure. The drawing 50 includes 16 libraries B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14 and B15. Each library includes 16 data rows and 2 data lines, a total of 32 data cells. Since the row compression amount in the drawing rule 404 is 512 and the row compression amount is 512, each data cell represents 512*512 storage units. In one embodiment, the drawing 50 is drawn using an Excel program.

Next, the conversion device 12 receives the logic address. Please refer to FIG. 6, which is a schematic diagram of the logic address LA in some embodiments of the present disclosure, wherein the logic address LA includes a row address RA, a row address CA, and a DQ index address DA. The row address RA (i.e., x4_Row field), the row address CA (i.e., x4_Col field), and the DQ index address DA (i.e., x4_DQ field) in the logic address LA are represented by hexadecimal values; and the row address RA, the row address CA, and the DQ index address DA further include bits represented by binary.

In the present embodiment, the row address RA includes 17 bits (i.e., RA0, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, RA11, RA12, RA13, RA14, RA15, and RA16 fields) to indicate the address of the row corresponding to the logical address LA. It should be noted that in the present embodiment, the row address RA also includes an address (i.e., BA0, BA1, BG0, and BG1 fields) to indicate the library corresponding to the logical address LA. In other embodiments, the logical address LA may also include a library address to indicate the address of the library where the storage unit is located.

In this embodiment, the row address CA includes 10 bits (i.e., CA0, CA1, CA2, CA3, CA4, CA5, CA6, CA7, CA8 and CA9 fields) for indicating the address of the row corresponding to the logical address LA.

In this embodiment, the DQ index address DA includes 4 bits (ie, DA0, DA1, DA2, and DA3 fields) for indicating the address of the DQ index corresponding to the logical address LA.

It should be noted that the present embodiment is only used as an example. In other embodiments, the number of bits and the representation method included in the column address RA, the row address CA and the DQ index address DA may vary depending on the corresponding storage device or actual needs.

After receiving the logical address LA, the conversion device 12 determines whether to convert the format of the logical address LA to a 4-bit width format according to whether the user has selected to convert the format of the logical address LA in the check box of the user interface 30. If the user has selected, the format conversion is performed. In this embodiment, the logical address LA is in a 4-bit width format, so no conversion is required.

For the description of the logical address format conversion, please refer to FIG. 7, which is a schematic diagram of the logical address format comparison tables 72 and 74 in some embodiments of the present disclosure. The logical address format comparison tables 72 and 74 list the comparison of the logical addresses located at the same physical location expressed in a 4-bit width format (x4), an 8-bit width format (x8) and a 16-bit width format (x16), respectively, wherein the bank address (Bank), row address (Row), row address (Col) and DQ index address (DQ) are all values composed of multiple bits, and for simplicity, they are expressed in hexadecimal values in FIG. 7.

It should be noted that the logical address represented by the four-bit width format, since one storage unit can store 4 bits, the DQ index address value is between 0x0 and 0x3; the logical address represented by the eight-bit width format, since one storage unit can store 8 bits, the DQ index address value is between 0x0 and 0x7; and the logical address represented by the sixteen-bit width format, since one storage unit can store 16 bits, the DQ index address value is between 0x0 and 0xF (i.e., 0x15).

In this embodiment, if the conversion device 12 wants to convert the logical address of the eight-bit width format into the four-bit width format, it is necessary to determine whether its DQ index address value is between 0x0 and 0x3. If so, it is necessary to add 1 to the 17th bit of the column address value, that is, add 1 to the 5th bit in the hexadecimal representation to obtain the column address value of the four-bit width format; otherwise, no adjustment is required.

Please refer to the logical address format comparison table 72, where the DQ index address value (i.e., 0x2) of the second row in the eight-bit width format is between 0x0 and 0x3. Therefore, the conversion device 12 adds 1 to the fifth bit of its row address value (i.e., 0x01234), which is equal to the row address value (i.e., 0x11234) of the four-bit width format of the first row, and the remaining addresses do not need to be adjusted.

Please continue to refer to the logical address format comparison table 74, where the DQ index address value of the 8-bit width format in the second row (i.e., 0x7) is not between 0x0 and 0x3, so its row address value and other addresses do not need to be adjusted.

On the other hand, in the present embodiment, if the conversion device 12 wants to convert the logical address in the 16-bit width format into the 4-bit width format, it is necessary to determine whether its DQ index address value is between 0x0 and 0x3 or between 0x8 and 0xB (i.e., 0x11). If so, it is necessary to add 1 to the 17th bit of the column address value, that is, add 1 to the 5th bit in the hexadecimal representation, to obtain the column address value in the 4-bit width format; otherwise, no adjustment is required.

Next, the conversion device 12 needs to further determine whether its inventory address value is less than 0x8. If so, it needs to add 8 to the inventory address value to obtain the inventory address value in a four-bit width format; otherwise, no adjustment is required.

Please refer to the logical address format comparison table 72, where the DQ index address value of the 16-bit width format of the third row (i.e., 0x2) is between 0x0 and 0x3. Therefore, the conversion device 12 adds 1 to the 5th digit of its row address value (i.e., 0x01234), which is equal to the row address value of the 4-bit width format of the first row (i.e., 0x11234); then, the inventory address value of the 16-bit width format of the third row (i.e., 0x2) is less than 0x8. Therefore, the conversion device 12 adds 8 to its inventory address value, which is equal to the inventory address value of the 4-bit width format of the first row (i.e., 0xA), and the remaining addresses do not need to be adjusted.

Please continue to refer to the logical address format comparison table 74. The DQ index address value (i.e., 0xF) in the third row of the 16-bit width format is not between 0x0 and 0x3, so its row address value does not need to be adjusted; then, the inventory address value (i.e., 0xB) in the third row of the 16-bit width format is not less than 0x8. Therefore, its inventory address value does not need to be adjusted, and the remaining addresses do not need to be adjusted either.

It should be noted that the conversion format rules described in the present disclosure are only used as examples. In other embodiments, the conversion device 12 can convert the logical address format according to other rules, such as converting the DQ index address value by table lookup. In addition, the conversion device 12 can also convert the logical address format according to different rules according to different storage devices.

Thereafter, the conversion device 12 generates a vertical coordinate according to the logical address LA and the row rule 406. In some embodiments, the row rule 406 includes a logical operation, and the conversion device 12 performs the logical operation of the row rule 406 with the row address bits of the row address RA to generate the vertical coordinate. In some embodiments, the logical operation may include a NOT operation, an XOR operation, or an AND operation.

Please refer to FIG. 8 , which is a schematic diagram of converting the row address RA to generate a vertical coordinate 802 in some embodiments of the present disclosure.

In the embodiment of FIG. 8 , the logical operation of the row rule 406 is to inversely operate the bit of the column RA13 in the row address RA. As shown in the figure, the conversion device 12 inversely operates the bit of the column RA13 in the row address RA (i.e., 1) to generate the bit of the column RA13 of the vertical coordinate 802 (i.e., 0). In other words, the difference between the vertical coordinate 802 and the row address RA is that the bit of the column RA13 has an opposite value.

In other embodiments, the logical operation for converting the row address RA may have different operation methods according to different types of storage devices. Please refer to FIG. 9 , which is a schematic diagram of converting the row address RA to generate a vertical coordinate 902 in some embodiments of the present disclosure.

In the embodiment of FIG. 9 , the conversion device 12 performs an exclusive OR operation on the bits of the column RA11 and the column RA15 in the row address RA. As shown in the figure, the exclusive OR operation on the bit of the column RA11 (i.e., 1) and the bit of the column RA15 (i.e., 1) in the column address RA generates the bit of the column RA11 (i.e., 0) of the vertical coordinate 902. In other words, after the conversion device 12 performs a logical operation, the bit of the column RA11 in the vertical coordinate 802 is obtained based on the bit operation of the column RA11 and the column RA15 in the column address RA.

Please further refer to FIG. 10 , which is a schematic diagram of converting the row address RA to generate a vertical coordinate 1002 in some embodiments of the present disclosure.

In the embodiment of FIG. 10 , the conversion device 12 performs an AND operation on the bits of the column RA7 and the column RA12 in the column address RA. As shown in the figure, the bit of the column RA7 (i.e., 0) and the bit of the column RA12 (i.e., 1) in the column address RA are mutually exclusive ORed to generate the bit of the column RA12 (i.e., 0) of the vertical coordinate 902. In other words, after the conversion device 12 performs a logical operation, the bit of the column RA12 in the vertical coordinate 802 is obtained based on the bit operation of the column RA7 and the column RA12 in the column address RA.

Further, the conversion device 12 generates horizontal coordinates according to the logical address LA and the row rule 408. In some embodiments, the row rule 408 includes a lookup table. In the operation of generating the horizontal coordinates, the conversion device 12 includes determining which of the libraries B0 to B15 in the storage unit. The conversion device 12 also includes determining the area P or area Q in the specific library. The conversion device 12 also includes determining the row plane in the specific area. The conversion device 12 also includes determining the horizontal coordinates in the specific row plane.

In this embodiment, first, the conversion device 12 determines a bank in the storage unit according to the fields BG1, BG0, BA1 and BA0 bits of the row address RA. The address of the bank corresponding to the fields BG1, BG0, BA1 and BA0 bits is 0000, which is converted to a decimal value of 0, corresponding to the bank B0 in FIG. 50 .

It should be noted that in other embodiments, the value of the address of the bank corresponding to the vertical coordinate corresponds to the bank number. For example, if the address is 0100, the corresponding decimal value is 4, which corresponds to bank B4 in Figure 50; if the address is 1110, the corresponding decimal value is 14, which corresponds to bank B14 in Figure 50.

Since the conversion device 12 determines that the logical address LA corresponds to the bank B0 in FIG. 50 , please further refer to FIG. 11 , which is a schematic diagram of the bank B0 in FIG. 50 in some embodiments of the present disclosure, wherein the bank B0 includes regions P and Q. Similarly, other banks in FIG. 50 also include regions P and Q.

Next, the conversion device 12 determines the area P or area Q of the bank B0 according to the RA15 bit of the column address RA.

Please also refer to the drawing rule 404 of FIG. 4 , in which the P/Q bit of the logic address LA is described as field RA15. In other words, if the value of field RA15 is 1, the position corresponding to the logic address LA is in area P; conversely, if the value of field RA15 is 0, the position corresponding to the logic address LA is in area Q. In this embodiment, the conversion device 12 determines that the value of field RA15 of the logic address LA is 1, and determines that the logic address LA corresponds to area P.

Thereafter, the conversion device 12 looks up a lookup table using the 16-bit field RA of the row address RA, the 2-bit field CA of the row address CA, and the DQ index address DA to determine one of the row planes in the region P.

Please continue to refer to FIG. 11. As shown in the figure, the region P is divided into 8 column planes by vertical dotted lines, which are column planes 0 to 7 from right to left.

On the other hand, please refer to the row rule 408 in Figure 4. The row rule 408 includes a lookup table for converting the bits in the logical address LA into the row plane, which describes combining the J/K bits in the logical address LA, the column CA2 bits and the DQ index address, and then looking up the lookup table to obtain the horizontal coordinates.

Please refer to FIG. 12, which is a schematic diagram of generating a row plane according to the row rule 408 in some embodiments of the present disclosure. In this embodiment, the J/K bit of the logical address LA (i.e., the 16-bit field RA) is 1, the bit of the field CA2 is 0, and the DQ index address is 0. After combining the above three values into a reference value 1202 (i.e., 100), the conversion device 12 looks up the reference table of the row rule 408 to obtain the row plane as 7.

Finally, the conversion device 12 determines the horizontal coordinate in the row plane according to the field CA9 bit of the row address CA. Please continue to refer to Figure 11, in which each row plane can be cut vertically into two horizontal coordinates on the left and right sides. In other words, the area P can be cut into 8 row planes, and each row plane can be cut into 2 horizontal coordinates, that is, the area P contains 16 horizontal coordinates. Among them, the horizontal coordinates increase to the right with 0 on the leftmost side, that is, row plane 7 contains horizontal coordinates 0 and 1, plane 6 contains horizontal coordinates 2 and 3, and so on. It should be noted that the area Q is also divided into 16 horizontal coordinates in the same way.

Further, if the bit of field CA9 is 0, the conversion device 12 determines the horizontal coordinate to be the horizontal coordinate on the left side of the row plane; conversely, if the bit of field CA9 is 1, the conversion device 12 determines the horizontal coordinate to be the horizontal coordinate on the right side of the row plane. In the present embodiment, if the bit of field CA9 of row address CA is 0, the conversion device 12 determines the horizontal coordinate to be the horizontal coordinate on the left side of row plane 7 (i.e., the horizontal coordinate is 0).

Please further refer to FIG. 13 , which is a schematic diagram of generating a mark D in FIG. 50 in some embodiments of the present disclosure. As mentioned above, the logic address LA corresponds to the horizontal coordinate 0 in the row plane 7 , so the horizontal position of the mark D is located at the far left, that is, the left side in the row plane 7 .

On the other hand, the vertical position of mark D is determined according to the bit values of fields RA14 to RA0 in the vertical coordinate 802, wherein the bit value range of fields RA14 to RA0 is 00000000000000 to 1111111111111111, which is converted to decimal from 0 to 32767, for a total of 32768 vertical coordinates.

Furthermore, the row compression ratio of drawing rule 404 is 512, so 64 vertical coordinates can be obtained by dividing 32768 by 512. That is, library B0 needs to be divided into 64 vertical coordinates in the vertical axis (Y axis) direction.

Returning to the present embodiment, the bits of the field RA14 to RA0 in the vertical coordinate 802 are 101110000000000, which is converted to a decimal value of 23552, and the row compression rate is 512. Dividing the two gives a value of 46, so the vertical position of the marker D is the 46th coordinate from the origin below.

In summary, the conversion device 12 generates a marker D in the library B0 in FIG. 50 , wherein the marker D is located at the coordinate position (0, 46).

In some embodiments, the conversion device 12 may further continue to receive other logical addresses, and convert the logical addresses into physical addresses according to the aforementioned operation, and further generate other marks in FIG. 50 .

Finally, after the conversion device 12 completes all the markings, it generates a marked picture according to the marked drawing 50. Please refer to Figure 14, which is a schematic diagram of a logical address table 1402 and a marked picture 1404 in some embodiments of the present disclosure. The conversion device 12 generates marks in the drawing 50 after converting the logical addresses in the logical address table 1402 into physical addresses. After completing the conversion of all the logical addresses in the logical address table 1402 and generating the marks, the conversion device 12 generates a marked picture 1404 according to the drawing 50. In some embodiments, the marked picture 1404 is a picture file.

In summary, the conversion device 12 and conversion method 20 provided by the present disclosure can convert a logical address into a physical address and generate a marking image to provide the user with the physical location of the storage unit corresponding to the logical address in the storage device. When the user needs to detect and analyze the cause of the faulty storage unit, the user can quickly obtain the location of the storage unit and further perform the detection and analysis.

Although several embodiments are described in detail above as examples, the logical address conversion device, method, and non-transitory computer-readable storage medium proposed in the present disclosure can also be implemented by other systems, hardware, software, storage media, or a combination thereof. Therefore, the protection scope of the present disclosure should not be limited to the specific implementation method described in the embodiments of the present disclosure, but should be defined by the scope of the attached patent application.

It is obvious to those with ordinary knowledge in the art to which the present disclosure belongs that various modifications and changes can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the protection scope of the present disclosure also covers modifications and changes made within the scope of the attached patent application.

12: Conversion device 122: Processor 14: Display device 20: Conversion method S202~S216: Steps 30: User interface 40: Conversion parameters 402: Device type 404: Drawing rule 406: Row rule 408: Row rule 50: Drawing B0~B15: Library LA: Logical address RA: Column address CA: Row address DA: DQ index address 72,74: Logical address format comparison table 802,902,1002: Vertical coordinates P,Q: Region 1202: Comparison value D: Mark 1402: Logical address table 1404: Mark image

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more clear and easy to understand, the attached drawings are described as follows: Figure 1 is a schematic diagram of the conversion device and the display device in some embodiments of the present disclosure; Figure 2 is a flow chart of the conversion method in some embodiments of the present disclosure; Figure 3 is a schematic diagram of the user interface in some embodiments of the present disclosure; Figure 4 is a schematic diagram of the conversion parameters in some embodiments of the present disclosure; Figure 5 is a schematic diagram of the drawings in some embodiments of the present disclosure; Figure 6 is a schematic diagram of the logical address in some embodiments of the present disclosure; Figure 7 is a schematic diagram of the logical address format comparison table in some embodiments of the present disclosure; Figure 8 is a schematic diagram of the generation of vertical coordinates according to the first row rule in some embodiments of the present disclosure; Figure 9 is a schematic diagram of generating vertical coordinates according to row rules in another embodiment of the present disclosure; Figure 10 is a schematic diagram of generating vertical coordinates according to row rules in another embodiment of the present disclosure; Figure 11 is a schematic diagram of a library in a drawing in some embodiments of the present disclosure; Figure 12 is a schematic diagram of generating a row plane according to row rules in some embodiments of the present disclosure; Figure 13 is a schematic diagram of generating a mark in a drawing in some embodiments of the present disclosure; and Figure 14 is a schematic diagram of a logical address and a mark image in some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

20: Conversion method S202~S216: Steps

Claims (10)

A conversion method comprises: receiving a first logical address, the first logical address being used to access a first storage unit in a storage device; and generating a first physical address according to the first logical address and a conversion rule, wherein the first physical address is used to indicate a first position of the first storage unit in a physical space of the storage device. The conversion method as described in claim 1 further comprises the following steps: Generate a drawing, wherein the drawing is used to represent the physical space of the storage device; Mark the first position of the first storage unit in the drawing according to the first physical address; and Generate a marked image according to the marked drawing, wherein the marked image includes a mark corresponding to the first position. The conversion method as described in claim 2, wherein the step of generating the drawing further includes: Generating the drawing based on a drawing rule, wherein the drawing rule includes a library quantity, a row quantity, and a row quantity of the storage device. A conversion method as described in claim 3, wherein the drawing rule further includes a row compression amount and a row compression amount, the row compression amount is used to indicate that a data row in the drawing corresponds to the number of storage units in the storage device, and the row compression amount is used to indicate that a data row in the drawing corresponds to the number of storage units in the storage device. The conversion method as described in claim 1, wherein the first logical address has a data bit width format, the data bit width format is one of a four-bit width format, an eight-bit width format, and a sixteen-bit width format, and the conversion method further comprises: In response to the first logical address being received in an eight-bit width format, converting the first logical address into a four-bit width format; and In response to the first logical address being received in a sixteen-bit width format, converting the first logical address into a four-bit width format. The conversion method as described in claim 1 further comprises the following steps: Receiving a second logical address, the second logical address is used to access a second storage unit in the storage device; and Based on the second logical address and the conversion rule, generating a second physical address, wherein the second physical address is used to indicate a second position of the second storage unit in the physical space. A conversion device includes: A processor for performing the following operations: Receiving a first logical address, the first logical address is used to access a first storage unit in a storage device; and Based on the first logical address and a conversion rule, generating a first physical address, wherein the first physical address is used to indicate a first position of the first storage unit in a physical space of the storage device. The conversion device as described in claim 7, wherein the processor is further used to perform the following operations: Generate a drawing, wherein the drawing is used to represent the physical space of the storage device; Mark the first position of the first storage unit in the drawing according to the first physical address; and Generate a marked image according to the marked drawing, wherein the marked image includes a mark corresponding to the first position. The conversion device as described in claim 8, wherein the processor is further used to perform the following operations: Generate the drawing based on a drawing rule, wherein the drawing rule includes a library quantity, a row quantity, and a row quantity of the storage device. A conversion device as described in claim 9, wherein the drawing rule further includes a row compression amount and a row compression amount, the row compression amount is used to indicate that a data row in the drawing corresponds to the number of storage units in the storage device, and the row compression amount is used to indicate that a data row in the drawing corresponds to the number of storage units in the storage device.

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