TWI864753B - Interconnect structure with increased decoupling capacitance - Google Patents

Abstract

A semiconductor chip device includes a substrate with a first dielectric material of a first permittivity value. A power input line and ground line are positioned in the substrate and arranged to form a decoupling capacitor. A region of the substrate in between the power input line and the ground line is doped with a second dielectric material of a second permittivity value that is higher than the first permittivity value. The region doped with the second dielectric material lacks a signal body. By incorporating a region with higher permittivity, in what is generally unused space for power delivery, the region becomes a decoupling capacitor for nearby power delivery elements. By adding decoupling capacitance to the previously unused space, noise in a circuit is more easily controlled and the chip device becomes more reliable.

Description

Interconnect structure with increased decoupling capacitance

The present invention relates generally to electrical devices and, more particularly, to an interconnect structure with increased decoupling capacitance.

Current applications using computing chips can vary widely in their demands for operational reliability. Some consumer products, such as cell phones, can operate satisfactorily using chips whose reliability requirements are not so stringent. However, there are many applications involving high-performance computing that seek to avoid chip failures. For example, banking networks, airport control systems, and government agency servers need to be up and running as uninterrupted as possible. For applications that require 99.9% reliability, spikes from the power supply cannot be tolerated because the noise from the spikes can corrupt the processing output. Sudden increases in power can cause current spikes that sometimes damage the device, causing partial failures if not total device failure.

According to one embodiment of the present invention, a semiconductor chip device is provided. The semiconductor device includes a substrate. The substrate includes a first dielectric material having a first dielectric constant value. A first power input line is positioned in the substrate. A first ground line is positioned adjacent to the first power line and is configured to form a first decoupling capacitor in cooperation with the first power input line. A region of the substrate between the first power input line and the first ground line is doped with a second dielectric material having a second dielectric constant value. The second dielectric constant material value is higher than the first dielectric constant value. The region does not have a signal body. By incorporating a region with a higher dielectric constant in a power delivery space that is typically, for example, unused (due to the absence of a signal body), the region becomes a decoupling capacitor for nearby power delivery elements. By adding decoupling capacitors to the previously unused space, noise in a circuit is easier to control and the chip device becomes more reliable.

In one embodiment that may be combined with the previous embodiments, the region of the substrate doped with the second dielectric material includes a disconnected metal fill body. The metal fill body is typically a passive element used to control the metal density in the chip device and typically does not play a role in power delivery. However, some embodiments may connect the metal fill body to the power input line (or the ground line). By connecting the metal fill body to one of the adjacent power delivery components, the amount of decoupling capacitance can be controlled for the application, thereby making the previously inactive area of the device more suitable for power delivery design.

According to one embodiment of the present invention, a computer processor implementation method for designing a power delivery network in a semiconductor substrate is provided. The method includes identifying the locations of power input lines, ground lines, signal lines, and metal-filled bodies in the semiconductor substrate. The semiconductor substrate includes a first dielectric material having a first dielectric constant value. Identifying a region of the substrate located between the power input line and the ground line that includes one or more metal-filled bodies. Determining a desired decoupling capacitance for a selected region between the identified regions. Determining an amount of a second dielectric material having a second dielectric constant value to provide the desired decoupling capacitance in the selected regions. The second dielectric constant value is greater than the first dielectric constant value, and the amount of the second dielectric material required is based in part on an amount of metal material present in the one or more metal-filled bodies present in the selected regions. A volume of the selected regions is determined for depositing the determined amount of the second dielectric material. A lithography and/or etching pattern mask is generated for the power delivery network. The masks include the locations of the power input lines, the ground lines, the signal lines, the metal-filled bodies, and the locations of the selected regions including the second dielectric material.

In an embodiment that may be combined with the previous embodiments, the method includes identifying a selected pair of a power input line and a ground line, the power input line and the ground line having a selected region between the selected pair. The method further positions a second power input line in a layer above or below the selected region. The second power input line spans the selected region and is orthogonal to the selected pair. The method further includes patterning a first through hole in the second power input line, the first through hole connecting the second power input line to the power input line of the selected pair. This embodiment further adds flexibility to create decoupling capacitance in previously unused areas. By connecting the original power input line to another power input line, additional connections can be made in the power delivery network, including, for example, connections to metal-filled bodies in high dielectric regions. The second power input line allows for increased power delivery design options when designing decoupling capacitors because the spacing between elements defining the capacitor can be reduced by jumping the power input to a metal fill body closer to the ground line (or vice versa). The jump may be necessary when other metal fill bodies are present in the high-k dielectric region.

According to one embodiment of the present invention, a manufacturing method for forming interconnections in a semiconductor substrate is provided. The method includes depositing a first layer of a first dielectric material. Selectively removing an area of the first layer of the first dielectric material for placing a first metal filling body. Depositing a second dielectric material in the area of the selectively removed first dielectric material. The second dielectric material has a dielectric constant value higher than that of the first dielectric material. Placing the first metal filling body in the second dielectric material. Placing a first power input line in the first layer of the first dielectric material adjacent to the second dielectric material and on a first side of the second dielectric material. Placing a first ground line in the layer of the first dielectric material adjacent to the second dielectric material and on a second side of the second dielectric material. The first power input line, the second dielectric material and the first ground line are arranged to form a decoupling capacitor.

In one embodiment that may be combined with the previous embodiments, the method includes determining a desired decoupling capacitance for the decoupling capacitor. A position of the metal fill body in the region of the selectively removed first dielectric material relative to either the first power input line or the first ground line is determined to provide the determined desired decoupling capacitance. As will be appreciated, the metal filler in the semiconductor device can be used as an active element, its position in the device serving the dual purpose of providing material density and actively providing a capacitive relationship with one of the power delivery lines. The position of the metal fill body becomes adjustable so that the decoupling capacitance in the region of the device can be controlled.

The technology described in this article can be implemented in many ways. An example implementation is provided below with reference to the following figure.

Overview

In the following embodiments, many specific details are described by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings can be practiced without such details. In other cases, well-known methods, procedures, components and/or circuit systems have been described at a relatively high level without details to avoid unnecessarily obscuring the aspects of the present teachings.

In one aspect, spatially relative terms such as "front," "rear," "top," "bottom," "under," "below," "lower," "above," "upper," "side," "left," "right," and the like are used with reference to the orientation of the figures being described. Because the components of embodiments of the present invention can be positioned in a variety of different orientations, directional terms are used for illustrative purposes and are in no way limiting. Therefore, it should be understood that in addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as "below" or "under" other elements or features will be oriented as "above" the other elements or features. Thus, for example, the term "below" can encompass both an orientation of above as well as below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

As used herein, the terms "lateral," "planar," and "horizontal" describe an orientation parallel to a first surface of a wafer or substrate.

As used herein, the term "vertical" describes an orientation that is configured perpendicular to a first surface of a chip, a chip carrier, a chip substrate, or a semiconductor body.

As used herein, the terms "coupled" and/or "electrically coupled" are not intended to mean that elements must be directly coupled together - intervening elements may be disposed between the "coupled" or "electrically coupled" elements. In contrast, if an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. The term "electrically connected" refers to a low-ohmic electrical connection between elements that are electrically connected together.

Although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. Describing an element as "first" or "second", etc. does not necessarily mean that any of the elements have an order or priority. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Example embodiments are described herein with reference to cross-sectional drawings that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). Thus, variations from the shapes depicted due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, the regions depicted in the figures are schematic in nature, and their shapes do not necessarily depict the actual shape of regions of the device and are not limiting in scope. It should be understood that the drawings and/or diagrams accompanying the present invention are illustrative, non-limiting, and not necessarily drawn to scale.

It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the scope of the patent application. The description of the embodiments is not limiting. In particular, the elements of the embodiments described below may be combined with elements of different embodiments.

Power delivery structures in computing chips are often subject to noise in the circuit and the reliability of the power delivery. Power supply buses are a common source of noise because the input voltage can fluctuate. If the system detects that a logic block is not producing the proper output, the system can invoke a fail-safe mechanism to avoid using the damaged device. However, the device remains unusable and must be replaced. One common method of reducing noise includes using decoupling capacitors to stabilize the voltage signal provided to the circuit elements.

Conventional decoupling capacitors may be too large to be used in newer semiconductor chip devices. While some configurations place ground signal lines in close proximity to power signal lines in the die substrate to form decoupling capacitors, the available area for routing signals in the device is very valuable. Constraints exist in positioning certain circuit components near other components on the chip die that limit the use of the chip substrate. The placement of decoupling capacitors within the normally used power delivery area limits the area available for signaling.

Figure 1 shows a diagram of a cross section of a known signal routing system in a semiconductor device. The power input line _VDD is separated from the ground line _VSS by a region of standby substrate space. Signal lines may be positioned adjacent to the standby space but disconnected from any material or features in the standby space. For example, in some devices, the standby space may include a metal fill body that exists to increase the metal density in the device but is not otherwise used to carry signals. There may be some unused standby space in a semiconductor device. As can be seen, when used to occupy the fill body, the standby space does not contribute to actual power delivery and represents an inefficient occupied area in the device.

Reference is now made to FIG. 2 , which shows a cross section of a semiconductor device 200 (sometimes generally referred to as “device 200”) according to one embodiment. It should be understood that semiconductor device 200 may include several more elements than shown in other portions of device 200, but for illustration purposes, the focus of the description is on the configuration of the features shown in the figure. In addition, although the elements in the figure are shown as being configured in parallel, some features (such as power lines, signal lines, and ground lines) may change direction in other portions of device 200.

Referring back to FIG. 2 , semiconductor device 200 includes features that reduce noise in the device and improve the reliability of the device. The prior art device of FIG. 1 is repeated throughout the figure so that a side-by-side comparison of the prior art and the subject semiconductor device embodiments can be viewed simultaneously. Device 200 includes a substrate 210 having a low dielectric constant dielectric material (ultra-low k dielectric), which may be, for example, porous silicon dioxide. The k value of the dielectric material used for substrate 210 is typically less than 4.2 (and as the k value is typically not close to 4.2) and behaves as an insulator. Power input line 220 and ground line 230 may be positioned on a first layer of substrate 210. The sections of the power input line 220 and the ground line 230 may be parallel and separated by low- k dielectric material and in some sections by the signal line body 280. The default capacitance between the power input line 220 and the ground line 230 may be considered weak (to reiterate, acting as an insulator) due to the fact that the dielectric material of the substrate 210 is of the ultra-low- k variety. An embodiment of the device 200 includes a region 250 (which is typically unused idle space) doped with a dielectric material 260 having a higher dielectric constant (high- k value) than the dielectric material of the substrate 210. In the present invention, high- k value means that the dielectric material 260 has a k value of 4.2 or higher and is typically in the range of 6 to 7 as a k value.

As can be appreciated, by incorporating a high- k dielectric into region 250, a decoupling capacitor 205 structure is provided to the device 200 that (when operating in conjunction with the power input line 220 and the ground line 230) effectively provides decoupling capacitance to the nearby signal line body 280. In some embodiments, the volume of dielectric material 260 in region 250 can be selectively controlled to provide a desired amount of capacitance. Although region 250 is shown as extending from the power input line 220 to the ground line 230, in some embodiments, the volume of dielectric material 260 may occupy less than the entire region 250. Additionally, although FIG. 2 shows one of the signal line bodies in contact with the dielectric material 260 , as depicted by the other signal line body 280 , it is not necessarily required to be in contact with the dielectric material 260 in some embodiments.

In some embodiments, the region 250 having a high- k dielectric material may include one or more floating metal-filled bodies 270. When "floating," the metal-filled body 270 may generally be disconnected from any other signal line 280 or power feature, and generally does not include vias or any other interconnecting elements. As a passive element in the region 250, the metal-filled body 270 may not affect the decoupling capacitance to any significant extent. However, some embodiments may include a conductive line 275 connecting the metal-filled body 270 to either a power input line 220 or a ground line 230. Figure 2 shows a conductive line 275 connecting a metal-filled body in a region 250 adjacent to a power input line 220 to the power input line 220. As can be appreciated, the metal-filled body 270 connected to the power input line 220 becomes a conductor when power is provided to the power input line 220. In the embodiment discussed, the effective decoupling capacitor 205 includes the metal-filled body 270 as one conductor, the dielectric material 260, and the ground line 230 as a parallel conductor. As can be seen, by connecting the metal-filled body 270 to one of the wires (220 or 230), the decoupling capacitance in the subject area can be manipulated to achieve the desired output. Although only a single metal-filled body 270 is shown in the figure, it should be understood that there can be multiple filling bodies 270. Therefore, there can be a conductive connection 275 connecting each of the power input line 220 and the ground line 230 to the respective metal-filled body 270.

FIG. 3 illustrates a process 300 for fabricating a semiconductor device incorporating a design for a power delivery network according to an embodiment of the present invention. As a general starting point, in block 310, a low- k material is selected as a substrate for deposition. In block 320, a mask pattern for blocking areas designated for integration of high- k dielectric material may be positioned on the substrate. Substrate material may be removed (e.g., etched) from areas designated for high- k dielectric material. In block 330, high- k dielectric material may be deposited onto the substrate in areas designated for providing decoupling capacitors. In block 340, a chemical mechanical polishing (or planarization) (CMP) process may be used to polish the areas having high -k dielectric material. In block 350, conductive lines (power input, ground, signaling and conductive connections), metal fill bodies and vias (or other inter-layer connections) may be positioned in one or more mask patterns for lithography and/or etching processes. In block 360, metallization may be deposited to create the conductive lines, metal fill bodies and vias. Generally, depositing the metallization includes positioning at least one power input line adjacent to and on one side of a region including high- k dielectric material, and positioning a ground line on an opposite side of the region of high -k dielectric material. It is further implied that the specific conductive elements described above and further below are configured as part of the process steps for mask patterning and metallization. Additionally, additional substrate layers may be deposited onto the substrate layer shown in block 310, or the substrate layer of block 310 may be deposited onto another substrate layer that includes one or more of the elements described herein.

FIG. 4 shows a semiconductor device 400 that is similar to device 200, except that additional interconnect structures may be incorporated into substrate layers (not shown for illustration purposes) above and/or below the substrate layer of region 250. In one embodiment, semiconductor device 400 includes a power input line 420 that may be positioned above (or below) region 250. Power input line 420 may be positioned orthogonal to power input line 220 such that power input line 420 crosses region 250 from at least one plane defined by power input line 220 to at least one plane defined by ground line 230. Power input line 420 may include a first via 415 connecting power input line 420 to power input line 220. In some embodiments, region 250 may include one or more metal-filled bodies 270. The power input line 420 may include a second through hole 425 that connects the power input line 420 to one of the metal-filled bodies 270. As shown, in some embodiments, the power input line 420 can be used to jump over one or more metal-filled bodies 270 to control the decoupling capacitance with the ground line 230. In the embodiment shown, the power input line 420 is connected to the metal-filled body 270 that is closely spaced from the ground line 230. The jumped metal-filled body 270 becomes an actual new power input line to achieve the purpose of forming a decoupling capacitor with the ground line 230.

It will be appreciated that, although not shown in this manner, in another embodiment, the conductive element used to connect to the power input line 220 may instead be used to connect to the ground line 230. The via 425 may connect the jumper to one of the metal-filled bodies 270, which in effect changes the ground-side conductive element to the metal-filled body 270 in the decoupling capacitor.

Fig. 5 shows a semiconductor device 500 with two variations using the jumper element disclosed in Fig. 4. The semiconductor device 500 includes the simultaneous integration of a jumper 520 that connects the power input line 220 to the metal-filled body 270 in the region 250. The semiconductor device 500 also includes a jumper 530 that connects the ground line 230 (via a via 515) to another metal-filled body 270 in the region 250 (via a via 525).

As can be appreciated, by using jumper-type conductive lines, the decoupling capacitance of a region can be controlled based in part on connecting different distances of metal-filled bodies 270 to either the power input line 220 or the ground line 230, while being able to avoid metal-filled bodies 270 that can be inserted between any of the capacitor elements (when necessary). The effective distance between the capacitor conductive elements can be controlled so that the capacitance range is based on the width of the region 250, the distance of the metal-filled body 270 to the power input line 220 or the ground line 230, or the distance between any two metal-filled bodies 270 connected to their respective power input lines 220 and ground lines 230. As shown, the decoupling capacitance field can be based on the narrow spacing between two metal-filled bodies 270. Furthermore, the location of the decoupling capacitor field output can be shifted depending on which two features are used to decouple the capacitor; for example, using a metal fill body 270 and a power input line 220 shifts the field upward; using a ground line 230 and a metal field body shifts the field downward, and using two metal fill bodies can shift the field upward or downward depending on the location of the respective fill bodies.

FIG. 6 shows another embodiment of a semiconductor device 600 that is similar to semiconductor device 500, except that semiconductor device 600 also incorporates jumpers 620 and 630 that are non-planar with region 250. Jumper 630 is not shown connected to anything, but is included to show how various connections can be made to one or more of the other components while avoiding connections to signal line 280. In semiconductor device 600, one (or more) of metal-filled bodies 670 is initially floating. Metal-filled bodies 670 are at least partially within region 250 and extend to the exterior of region 250. Jumper elements 620 and 630 can be located away from region 250 (non-planar with region 250) to connect to either power input line 220 or ground line 230, respectively. Jumper 620 may be connected to power input line 220 via via 615. Jumper 620 may be connected to metal-filled body 670 via via 625. The illustrated embodiment provides both increased decoupling capacitance and local resistance reduction in the power delivery network. The local resistance reduction is due to the addition of an additional parallel conduction path in the power delivery network. The additional signal line added between at least two other existing power lines acts as an additional resistance path, thereby reducing the parallel resistance of the power grid. Conclusion

Descriptions of various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Although the foregoing has described what is considered to be the best state and/or other examples, it should be understood that various modifications may be made therein, and the subject matter disclosed herein may be implemented in various forms and embodiments, and the teachings may be applied to many applications, only some of which are described herein. The following claims are intended to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

The components, steps, features, objectives, benefits and advantages discussed herein are illustrative only. None of them and the discussion therein is intended to limit the scope of protection. Although various advantages have been discussed herein, it should be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, quantities, sizes and other specifications set forth in this specification (including in the scope of subsequent patent applications) are approximate and not exact. They are intended to have a reasonable range consistent with their relevant functions and the practice of the art to which they belong.

Numerous other embodiments are also contemplated. These include embodiments with fewer, additional and/or different components, steps, features, objectives, benefits and advantages. These embodiments also include embodiments in which components and/or steps are differently configured and/or ordered.

Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" is intended only as an example, not the best or optimal. Except for the content just described above, any content described or illustrated is not intended or should not be interpreted as making any component, step, feature, goal, benefit, advantage exclusive or equivalent to public use, regardless of whether it is described in the scope of the patent application.

It is to be understood that the terms and expressions used herein have the ordinary meanings accorded to such terms and expressions with respect to their corresponding respective inquiries and areas of study, unless specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another entity or action and do not necessarily require or imply any such actual relationship or order between such entities or actions. The terms "comprises" or "comprising" or any variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further constraints, an element preceded by "a" or "an" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising the element.

The summary of the present invention is provided to allow the reader to quickly determine the nature of the technical disclosure. It is understood that it will not be used to interpret or limit the scope or meaning of the scope of the claims. In addition, in the aforementioned embodiments, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the present invention. This disclosure method should not be interpreted as reflecting the following intention: the claimed embodiments have more features than are explicitly described in each claim. Rather, as reflected in the following claims, the subject matter of the present invention lies in less than all of the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the embodiments, with each claim being a separately claimed subject matter in its own right.

200: semiconductor device 210: substrate 220: power input line 230: ground line 250: area 260: dielectric material 270: floating metal filling body 275: conductive line/conductive connection 280: signal line body/signal line 300: process 310: step 320: step 330: step 340: step 350: step 360: step 400: semiconductor device 415: first through hole 420: power input line 425: second through hole 500: semiconductor device 515: through hole 520: jumper line 525: through hole 530: jumper wire 600: semiconductor device 615: through hole 620: jumper wire 625: through hole 630: jumper wire 670: metal filled body VDD: power input line VSS: ground line

The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or alternatively. Details that may be obvious or unnecessary may be omitted to save space or for more efficient illustration. Some embodiments may be practiced with additional components or steps and/or without all components or steps illustrated. When the same number appears in different drawings, it refers to the same or similar components or steps.

FIG. 1 is a simplified diagram of a cross-section of a known semiconductor device signal routing scheme having unused areas of a substrate.

2 is a simplified cross-sectional view of a semiconductor device signal routing scheme that incorporates high-k dielectric material into unused space in a device substrate according to one embodiment.

FIG. 3 is a diagram illustrating a series of process flow steps for a method of manufacturing a semiconductor device according to another embodiment.

FIG. 4 is a simplified diagram of a cross section of the semiconductor device of FIG. 2 incorporating bridged power lines according to one embodiment.

FIG. 5 is a simplified cross-sectional view of the semiconductor device of FIG. 4 incorporating a bridge ground line according to one embodiment.

6 is a simplified diagram of a cross-section of the semiconductor device of FIG. 2 with expanded power lines and additional jumpers according to one embodiment.

200:Semiconductor devices

210: Substrate

220: Power input line

230: Ground wire

250: District

260: Dielectric materials

270: Floating metal filled body

275: Conductive wire/conductive connection

280: Signal cable body/signal cable

VDD: power input line

VSS: ground wire

Claims (24)

A semiconductor chip device comprises: a substrate including a first dielectric material having a first dielectric constant value; a first power input line in the substrate; a first ground line located adjacent to the first power line and configured to form a first decoupling capacitor in cooperation with the first power input line; a region of the substrate between the first power input line and the first ground line doped with a second dielectric material having a second dielectric constant value, wherein the second dielectric constant material value is higher than the first dielectric constant value and the region does not have a signal body; and a disconnected metal filling body in the region of the substrate doped with the second dielectric material. The semiconductor chip device of claim 1 further comprises a connection line from the first power input line to the metal-filled body. A semiconductor chip device as claimed in claim 1, further comprising a second power input line connected to the first power input line, wherein: the first power input line and the first ground line are positioned in a first layer of the substrate; the second power input line is positioned in a second layer of the substrate; the metal-filled body is connected to the second power input line; the metal-filled body is connected to the first power input line via the connection to the second power input line; and the metal-filled body is positioned adjacent to the first ground line and is configured to form a second decoupling capacitor in cooperation with the first ground line. A semiconductor chip device as claimed in claim 3, further comprising a conductive connection from the first power input line to the second power input line, wherein: the second power input line is orthogonal to the first power input line and is non-planarly positioned with respect to the region of the substrate doped with the second dielectric material; and the metal filling body extends from the region of the substrate doped with the second dielectric material and intersects with a plane orthogonal to the second power input line. A semiconductor chip device as claimed in claim 1, further comprising a second ground line connected to the first ground line, wherein: the first power input line and the first ground line are positioned in a first layer of the substrate; the second ground line is positioned in a second layer of the substrate; the metal-filled body is connected to the second ground line; the metal-filled body is connected to the first ground line via the connection to the second ground line; and the metal-filled body is positioned adjacent to the first power input line and is configured to cooperate with the first power input line to form a second decoupling capacitor. The semiconductor chip device of claim 1 further comprises: a first metal-filled body and a second metal-filled body in the region of the substrate doped with the second dielectric material; a second power input line connected to the first power input line; and a second ground line connected to the first ground line, wherein: the first power input line and the first ground line are positioned in a first layer of the substrate, the second power input line and the second ground line are positioned in a second layer of the substrate, the first metal-filled body is connected to the second power input line, and the The first metal-filled body is connected to the first power input line via the connection to the second power input line, the second metal-filled body is connected to the second ground line, the second metal-filled body is connected to the first ground line via the connection to the second ground line, the first metal-filled body is positioned adjacent to the first power input line and is configured to cooperate with the first power input line to form a second decoupling capacitor, and the second metal-filled body is positioned adjacent to the first ground line and is configured to cooperate with the first ground line to form a third decoupling capacitor. A semiconductor chip device as claimed in claim 1, wherein the region of the substrate doped with the second dielectric material does not have a signal line. A computer processor implementation method for designing a power delivery network in a semiconductor substrate, comprising: identifying positions of power input lines, ground lines, signal lines, and metal-filled bodies in the semiconductor substrate, wherein the semiconductor substrate comprises a first dielectric material having a first dielectric constant value; identifying regions of the substrate located between the power input lines and the ground lines and comprising one or more metal-filled bodies; determining a desired decoupling capacitor for a selected region between the identified regions; determining a desired decoupling capacitor having a second dielectric constant value required for the determined desired decoupling capacitor in the selected regions; an amount of a second dielectric material, wherein the second dielectric constant value is greater than the first dielectric constant value, and the amount of the second dielectric material required is based in part on an amount of metal material present in the one or more metal-filled bodies present in the selected regions; determining a volume of the selected regions for depositing the determined amount of the second dielectric material; and generating a lithographic and/or etch pattern mask for the power delivery network, which includes the power input lines, the ground lines, the signal lines, the locations of the metal-filled bodies, and the locations of the selected regions including the second dielectric material. The computer processor implementation method of claim 8 further comprises: identifying at least one of the one or more metal-filled bodies in the selected areas and an adjacent power input line among the power input lines; including in the pattern masks a conductive connection line connecting the identified metal-filled body to the adjacent power input line. The computer processor implementation method of claim 8 further comprises: identifying at least one of the one or more metal-filled bodies in the selected areas and an adjacent grounding line among the grounding lines; and including in the pattern masks a conductive connection line connecting the identified metal-filled body to the adjacent grounding line. A computer processor implementation method as claimed in claim 8, further comprising: identifying a selected pair, the selected pair comprising one of the power input lines and one of the ground lines having a selected region between the selected pair; positioning a second one of the power input lines in a layer above or below the selected region between the selected pair, wherein the second power input line spans the selected region and is orthogonally above or below the selected pair; and including a first via pattern in the second power input line, the first via pattern connecting the second power input line to the power input line of the selected pair. The computer processor implementation method of claim 11 further comprises: positioning a third power input line in the layer above or below the selected area, in a position that is non-planar to the selected area and parallel to the second power input line; including a second through-hole pattern in the third power input line, the second through-hole pattern connecting the third power input line to the second power input line; and including a third through-hole pattern in the third power input line, the third through-hole pattern connecting the third power input line to a fourth power input line. A computer processor implementation method as claimed in claim 8, further comprising: identifying a selected pair, the selected pair comprising one of the power input lines and one of the ground lines having a selected region between the selected pair; positioning another of the ground lines in a layer above or below the selected region between the selected pair, wherein the other ground line spans the selected region and is orthogonally above or below the selected pair; and including a through-hole pattern in the other ground line, the through-hole pattern connecting the other ground line to the ground line of the selected pair. The computer processor implementation method of claim 13 further comprises: positioning a third ground line in the layer above or below the selected area, in a position that is non-planar in the selected area and parallel to the second ground line; including a second through-hole pattern in the third ground line, the second through-hole pattern connecting the third ground line to the second ground line; and including a third through-hole pattern in the third ground line, the third through-hole pattern connecting the third ground line to a fourth ground line. A computer processor implementation method as claimed in claim 8, further comprising: identifying a selected first pair, the selected first pair comprising one of the power input lines and one of the ground lines having a selected region between the selected pair; positioning a second pair of lines comprising another of the power input lines and another of the ground lines in a layer above or below the selected region between the selected first pair, wherein the lines of the second pair span the selected region and are orthogonally above or below the selected first pair; including a first through-hole pattern in the other power input line, the first through-hole pattern connecting the other power input line to the power input line of the selected first pair; and including a second through-hole pattern in the other ground line, the second through-hole pattern connecting the other ground line to the ground line of the selected first pair. A method for forming interconnects in a semiconductor substrate comprises: depositing a first layer of a first dielectric material; selectively removing a region of the first layer of the first dielectric material to place a first metal fill body; depositing a second dielectric material in the region of the selectively removed first dielectric material, wherein the second dielectric material has a higher dielectric constant value than the first dielectric material; and placing the first metal fill body in the region of the selectively removed first dielectric material. A first power input line is placed in the second dielectric material; a first power input line is placed in the first layer of the first dielectric material adjacent to the second dielectric material on a first side of the second dielectric material; and a first ground line is placed in the layer of the first dielectric material adjacent to the second dielectric material on a second side of the second dielectric material, wherein the first power input line, the second dielectric material and the first ground line are arranged to form a decoupling capacitor. The manufacturing method of claim 16 further comprises forming a conductive connection between the first power input line and the first metal-filled body. The manufacturing method of claim 16 further comprises forming a conductive connection between the first grounding wire and the first metal-filled body. The manufacturing method of claim 16 further comprises: depositing a second layer of the first dielectric material on the first layer of the first dielectric material; placing a second power input line in the second layer of the first dielectric material, wherein the second power input line is placed adjacent to and orthogonal to the first power input line; forming a first through-hole connection connecting the first power input line to the second power input line; and forming a second through-hole connection connecting the second power input line to the first metal-filled body. The manufacturing method of claim 19 further comprises: placing a third power input line in the second layer of the first dielectric material, wherein the third power input line is parallel to the second power input line and is non-planarly placed with the second dielectric material in the region of the selectively removed first dielectric material; forming a third through-hole connection connecting the third power input line to the first power input line; and forming a fourth through-hole connection connecting the third power input line to the first metal-filled body, wherein the first metal-filled body extends outside the second dielectric material and the region of the selectively removed first dielectric material. The manufacturing method of claim 16 further comprises: depositing a second layer of the first dielectric material on the first layer of the first dielectric material; placing a second grounding line in the second layer of the first dielectric material, wherein the second grounding line is placed adjacent to and orthogonal to the first grounding line; forming a first through-hole connection connecting the first grounding line to the second grounding line; and forming a second through-hole connection connecting the second grounding line to the first metal-filled body. The manufacturing method of claim 21 further comprises: placing a third ground line in the second layer of the first dielectric material, wherein the third ground line is parallel to the second ground line and is non-planarly placed with the second dielectric material in the region of the selectively removed first dielectric material; forming a third through-hole connection connecting the third ground line to the first ground line; and forming a fourth through-hole connection connecting the third ground line to the first metal-filled body, wherein the first metal-filled body extends outside the second dielectric material and the region of the selectively removed first dielectric material. The manufacturing method of claim 16 further comprises: forming a second metal filling body in the area selectively removed from the first layer of the first dielectric material; depositing a second layer of the first dielectric material on the first layer of the first dielectric material; placing a second power input line in the second layer of the first dielectric material, wherein the second power input line is adjacent to and orthogonal to the first power input line; placing a second ground line in the second layer of the first dielectric material; layer, wherein the second grounding line is adjacent to and orthogonal to the first grounding line and is placed parallel to the second power input line; forming a first through-hole connection connecting the first power input line to the second power input line; forming a second through-hole connection connecting the second power input line to the first metal-filled body; forming a third through-hole connection connecting the first grounding line to the second grounding line; and forming a fourth through-hole connection connecting the second grounding line to the second metal-filled body. The manufacturing method of claim 16 further comprises: determining a desired decoupling capacitance for the decoupling capacitor; and selecting a position of the first metal-filled body in the region of the selectively removed first dielectric material relative to the first power input line or the first ground line to provide the determined desired decoupling capacitance.