TWI864560B - Planar transformer - Google Patents

Abstract

A planar transformer includes: a first primary winding layer; a second primary winding layer disposed adjacent to the first primary winding layer; a shielding layer disposed adjacent to the first primary winding layer; a first secondary winding layer disposed adjacent to the shielding layer; a second secondary winding layer disposed adjacent to the first secondary winding layer. The first primary winding layer and the second primary winding layer are located at one side of the shielding layer. The first secondary winding layer and the second secondary winding layer are located at another side of the shielding layer.

Description

Planar transformer

The present disclosure relates to a transformer, and in particular to a planar transformer.

In related technologies, high-end power products are developing towards high efficiency and high power density. With the pursuit of power density in switching power supplies, the application of high-frequency operation and planarization of transformers is becoming more and more widespread. The higher the operating frequency, the smaller the size of the transformer. Planar transformers have obvious advantages in size and flexibility compared to traditional transformers.

Planar transformers have better consistency than traditional winding transformers, but in the stacked structure of related technologies, the inter-layer capacitance caused by the mask layer will affect the switching speed of the switching power supply under high-frequency operation, resulting in reduced efficiency.

Therefore, how to find a planar transformer structure that can reduce interlayer capacitance is one of the most pressing problems to be solved.

The present disclosure provides a planar transformer that can reduce interlayer capacitance and improve the switching speed of a switching power supply.

The present disclosure provides a planar transformer, comprising: a first primary side coil layer; a second primary side coil layer, adjacent to the first primary side coil layer; a mask layer, adjacent to the first primary side coil layer; a first secondary side coil layer, adjacent to the mask layer; and a second secondary side coil layer, adjacent to the first secondary side coil layer. The first primary side coil layer and the second primary side coil layer are located on one side of the mask layer, and the first secondary side coil layer and the second secondary side coil layer are located on the other side of the mask layer.

In some embodiments, a distance between the first primary side coil layer and the mask layer is within a preset range. In some embodiments, the preset range is greater than 0.4 cm and less than 0.6 cm.

In some embodiments, a distance between the first secondary side coil layer and the mask layer is within a preset range. In some embodiments, the preset range is greater than 0.4 cm and less than 0.6 cm.

In some embodiments, a distance between the first primary side coil layer and the mask layer is the same as a distance between the first secondary side coil layer and the mask layer.

In some embodiments, a horizontal width of the first primary side coil layer is less than a horizontal width of the mask layer. In some embodiments, a horizontal width of the first secondary side coil layer is less than a horizontal width of the mask layer.

The present disclosure also provides a planar transformer, comprising: a mask layer; a first primary side coil layer, located on one side of the mask layer; a first secondary side coil layer, located on the other side of the mask layer; a second primary side coil layer, located on the other side of the first primary side coil layer opposite to the mask layer; and a second secondary side coil layer, located on the other side of the first secondary side coil layer opposite to the mask layer.

The present disclosure also provides a planar transformer, comprising: a primary coil group having at least two primary coil layers; a secondary coil group having at least two secondary coil layers; and a mask layer located between the primary coil group and the secondary coil group.

In some embodiments, a distance between the primary side coil set and the mask layer is within a preset range. In some embodiments, a distance between the secondary side coil set and the mask layer is within a preset range.

In some embodiments, a distance between the primary side coil group and the mask layer is the same as a distance between the secondary side coil group and the mask layer.

In summary, the planar transformer disclosed in the present invention arranges two primary-side coil layers and two secondary-side coil layers on both sides of a mask layer, thereby reducing the inter-layer capacitance caused by the mask layer in the structure of the related technology, so as to avoid affecting the switching speed of the switching power supply under high-frequency operation, resulting in reduced efficiency. In other words, the planar transformer disclosed in the present invention can reduce the inter-layer capacitance caused by the mask layer and reduce the efficiency lost during high-frequency operation.

1, 2, 2A, 3, 4, 5: Planar transformer

11: Primary side loop layer

12: Secondary side coil layer

13, 23, 33, 43, 53: Mask layer

21, 31, 41, 51: Beginner side coil set

211, 311, 411, 511: First primary side coil layer

212, 312, 412, 512: Second primary side coil layer

22, 32, 42, 52: Secondary coil assembly

221, 321, 421, 521: First secondary side coil layer

222, 322, 422, 522: Secondary side coil layer

24: Shell

241: Upper shell

242: Lower shell

L1, L2: spacing

D1, D2, D3: horizontal width

The following drawings and descriptions describe details of one or more embodiments of the subject matter described in this specification. Other features, aspects and advantages of the subject matter of this specification will become apparent from the description, drawings and patent application, including:

Figure 1 is a cross-sectional view of a planar transformer of related technology.

FIG2A is an exploded view of a planar transformer of the first embodiment of the present disclosure.

FIG2B is a cross-sectional view of the planar transformer along the A-A line in FIG2A.

FIG3 is an exploded view of a planar transformer in a different state according to the first embodiment of the present disclosure.

FIG4 is a cross-sectional view of a planar transformer of the second embodiment of the present disclosure.

FIG5 is a cross-sectional view of a planar transformer of the third embodiment of the present disclosure.

FIG6 is a cross-sectional view of a planar transformer of the fourth embodiment of the present disclosure.

As used herein, terms such as "first", "second", etc. describe various elements, components, regions, layers and/or parts, which should not be limited by these terms. These terms can only be used to distinguish one element, component, region, layer or part from another. Unless the context clearly indicates otherwise, the terms such as "first", "second" used in this document do not imply a sequence or order.

FIG1 is a cross-sectional view of a planar transformer 1 of the related art. As shown in FIG1 , the planar transformer of the related art includes: a primary side coil layer 11, a secondary side coil layer 12, and a mask layer 13. The planar transformer 1 of the related art has two primary side coil layers 11. In the primary side coil layer 11, the wiring harness of the primary side coil is formed by six turns of arranged wires. The planar transformer 1 of the related art has two secondary side coil layers 12, which are respectively located at the top layer and the bottom layer. Moreover, in each secondary side coil layer 12, the wiring harness of the secondary side coil is formed by one turn of wire. The planar transformer 1 of the related art has two mask layers 13 respectively located between each primary side coil layer 11 and each secondary side coil layer 12. A conductor is formed in the mask layer 13. Each long rectangle in the mask layer 13 represents a cross-section of the conductor.

In the planar transformer 1 of the related art, the total distributed capacitance between the primary and secondary sides is composed of the distributed capacitance C1 between the primary side winding layer 11 and the shield layer 13, the distributed capacitance C2 between the secondary side winding layer 12 and the shield layer 13, and the distributed capacitance C3 between the primary side winding layer 11 and the secondary side winding layer 12.

However, since the planar transformer 1 is a multi-layer board, the relative positions of the coils on different layers will inevitably have certain errors during the manufacturing process, and the errors will cause changes in one, two or three of the three components C1, C2 and C3 of the total distributed capacitance, thereby causing errors in the final total distributed capacitance. Furthermore, in the structure of the planar transformer 1 of the related art, the inter-layer capacitance caused by the mask layer 13 will affect the switching speed of the switching power supply under high-frequency operation, resulting in reduced efficiency.

FIG2A is an exploded view of the planar transformer 2 of the first embodiment of the present disclosure. FIG2B is a cross-sectional view of the planar transformer 2 along the A-A line of FIG2A. The planar transformer 2 of the present embodiment includes a primary coil group 21, a secondary coil group 22, and a mask layer 23. The planar transformer 2 is, for example, a printed circuit board (PCB) planar transformer. In some embodiments, the primary coil group 21, the secondary coil group 22, and the mask layer 23 are disposed on a printed circuit board (not shown).

The primary side coil assembly 21 has at least two primary side coil layers. In some embodiments, the primary side coil assembly 21 has, for example, a first primary side coil layer 211 and a second primary side coil layer 212. The second primary side coil layer 212 is adjacent to the first primary side coil layer 211. Furthermore, the first primary side coil layer 211 is located on one side of the mask layer 23. The second primary side coil layer 212 is located on the other side of the first primary side coil layer 211 relative to the mask layer 23. In other words, the first primary side coil layer 211 and the second primary side coil layer 212 are located on the same side of the mask layer 23, and the first primary side coil layer 211 is located between the second primary side coil layer 212 and the mask layer 23.

In the first primary side coil layer 211 and the second primary side coil layer 212, the primary side coil harness is composed of five turns of wire arranged respectively, and each small rectangle in the first primary side coil layer 211 and the second primary side coil layer 212 represents the cross section of one turn of wire. It should be noted that the number of turns of wire in the first primary side coil layer 211 and the second primary side coil layer 212 is not restrictive, and different numbers of turns can be provided according to requirements.

The secondary coil assembly 22 has at least two secondary coil layers. In some embodiments, the secondary coil assembly 22 has, for example, a first secondary coil layer 221 and a second secondary coil layer 222. The first secondary coil layer 221 is adjacent to the mask layer 23. The second secondary coil layer 222 is adjacent to the first secondary coil layer 221. Furthermore, the first secondary coil layer 221 is located on the other side of the mask layer 23. The second secondary coil layer 222 is located on the other side of the first secondary coil layer 221 relative to the mask layer 23. In other words, the first secondary side coil layer 221 and the second secondary side coil layer 222 are located on the same side of the mask layer 23, and the first secondary side coil layer 221 is located between the second secondary side coil layer 222 and the mask layer 23.

In the first secondary coil layer 221 and the second secondary coil layer 222, the secondary coil harness is formed by one turn of wire, and the rectangle in the first secondary coil layer 221 and the second secondary coil layer 222 represents the cross section of one turn of wire. It should be noted that the number of turns of wire in the first secondary coil layer 221 and the second secondary coil layer 222 is not restrictive, and different numbers of turns can be provided according to requirements.

The mask layer 23 is located between the primary side coil group 21 and the secondary side coil group 22. The mask layer 23 is adjacent to the first primary side coil layer 211 and the first secondary side coil layer 221. The first primary side coil layer 211 and the second primary side coil layer 212 are located on one side of the mask layer 23, and the first secondary side coil layer 221 and the second secondary side coil layer 222 are located on the other side of the mask layer 23. In other words, the primary side coil group 21 and the secondary side coil group 22 are located on both sides of the mask layer 23, respectively. A conductor is formed in the mask layer 23, and each long rectangle in the mask layer 23 represents a cross-section of the conductor. Here, the cross-section of the conductor in the mask layer 23 is taken as an example of a long rectangle and two short rectangles, but it is not restrictive and can be designed in different ways according to needs.

As described above, the planar transformer 2 of the present embodiment has two primary-side coil layers 211, 212 and two secondary-side coil layers 221, 222 disposed on both sides of a mask layer 23, thereby reducing the inter-layer capacitance caused by the mask layer in the structure of the related art, so as to avoid affecting the switching speed of the switching power supply under high-frequency operation, resulting in reduced efficiency. Specifically, the planar transformer 2 of the present embodiment can increase the switching speed of the switching power supply by about 30% to 40% compared to the planar transformer of the related art (e.g., the planar transformer 1 of FIG. 1 ), and can reduce the interlayer capacitance between the primary side winding layers 211, 212 and the mask layer 23 by about 40% to 50%, and reduce the interlayer capacitance between the secondary side winding layers 221, 222 and the mask layer 23 by about 40% to 50%. In other words, the planar transformer 2 of the present embodiment can reduce the interlayer capacitance caused by the mask layer 23 and reduce the efficiency lost during high-frequency operation.

FIG3 is an exploded view of a variation of the planar transformer 2A of the first embodiment of the present disclosure. In this embodiment, the planar transformer 2A further has a housing 24. The housing 24 includes an upper housing 241 and a lower housing 242. The upper housing 241 and the lower housing 242 cover the primary side coil layers 211, 212, the secondary side coil layers 221, 222 and the mask layer 23.

In this way, the planar transformer 2A can be protected from damage, and the primary side coil layers 211, 212 and the secondary side coil layers 221, 222 can be protected from external electromagnetic interference.

FIG4 is a cross-sectional view of the planar transformer 3 of the second embodiment of the present disclosure. It should be noted that FIG4 is a cross-sectional view of the planar transformer 3 along the A-A straight line of FIG2A. The planar transformer 3 of this embodiment includes a primary coil assembly 31, a secondary coil assembly 32 and a mask layer 33. It is worth mentioning that in FIG4, the primary coil assembly 31 is located on the lower side of the mask layer 33, and the secondary coil assembly 32 is located on the upper side of the mask layer 33, but it is only a difference in the observation direction. That is, if the observation direction is opposite, the primary coil assembly 31 is located on the upper side of the mask layer 33, and the secondary coil assembly 32 is located on the lower side of the mask layer 33.

The primary side coil assembly 31 has at least two primary side coil layers. In some embodiments, the primary side coil assembly 31 has, for example, a first primary side coil layer 311 and a second primary side coil layer 312. The second primary side coil layer 312 is adjacent to the first primary side coil layer 311. Furthermore, the first primary side coil layer 311 is located on one side of the mask layer 33. The second primary side coil layer 312 is located on the other side of the first primary side coil layer 311 relative to the mask layer 33. In other words, the first primary side coil layer 311 and the second primary side coil layer 312 are located on the same side of the mask layer 33, and the first primary side coil layer 311 is located between the second primary side coil layer 312 and the mask layer 33.

In the first primary side coil layer 311 and the second primary side coil layer 312, the primary side coil wire harness is formed by six turns of wire arranged respectively, and each small rectangle in the first primary side coil layer 311 and the second primary side coil layer 312 represents the cross section of one turn of wire. It should be noted that the number of turns of wire in the first primary side coil layer 311 and the second primary side coil layer 312 is not restrictive, and different numbers of turns can be provided according to requirements.

The secondary side coil group 32 has at least two secondary side coil layers. In some embodiments, the secondary side coil group 32 has, for example, a first secondary side coil layer 321 and a second secondary side coil layer 322. The first secondary side coil layer 321 is adjacent to the mask layer 33. The second secondary side coil layer 322 is adjacent to the first secondary side coil layer 321. Furthermore, the first secondary side coil layer 321 is located on the other side of the mask layer 33. The second secondary side coil layer 322 is located on the other side of the first secondary side coil layer 321 relative to the mask layer 33. In other words, the first secondary side coil layer 321 and the second secondary side coil layer 322 are located on the same side of the mask layer 33, and the first secondary side coil layer 321 is located between the second secondary side coil layer 322 and the mask layer 33.

In the first secondary coil layer 321 and the second secondary coil layer 322, the secondary coil harness is formed by one turn of wire, and the rectangle in the first secondary coil layer 321 and the second secondary coil layer 322 represents the cross section of one turn of wire. It should be noted that the number of turns of wire in the first secondary coil layer 321 and the second secondary coil layer 322 is not restrictive, and different numbers of turns can be provided according to requirements.

The mask layer 33 is located between the primary side coil group 31 and the secondary side coil group 32. The mask layer 33 is adjacent to the first primary side coil layer 311 and the first secondary side coil layer 321. The first primary side coil layer 311 and the second primary side coil layer 312 are located on one side of the mask layer 33, and the first secondary side coil layer 321 and the second secondary side coil layer 322 are located on the other side of the mask layer 33. In other words, the primary side coil group 31 and the secondary side coil group 32 are located on both sides of the mask layer 33, respectively. A conductor is formed in the mask layer 33, and the long rectangle in the mask layer 33 represents the cross section of the conductor. Here, the cross-section of the conductor in the mask layer 33 is taken as an example of a long rectangular strip, but it is not restrictive and can be designed in different ways according to needs.

In this embodiment, the distance L1 between the first primary side coil layer 311 and the mask layer 33 is within a preset range. The preset range of the distance L1 is, for example, 0.4 cm (mm) or more and 0.6 mm or less. That is, the first primary side coil layer 311 and the mask layer 33 must be at least 0.4 mm apart. On the other hand. In order to avoid the volume of the planar transformer 3 being too large, the distance L1 between the first primary side coil layer 311 and the mask layer 33 is preferably less than 0.6 mm. In this way, the inter-layer capacitance caused by the mask layer 33 can be further reduced, and the efficiency lost during high-frequency operation can be reduced.

Furthermore, in this embodiment, the horizontal width D1 of the first primary side coil layer 311 and the second primary side coil layer 312 of the primary side coil set 31 is smaller than the horizontal width D2 of the mask layer 33. It should be noted that in the primary side coil layers 311 and 312, the wire bundle of the primary side coil is formed by the arranged wires and the gaps therebetween, and the wire bundle of the primary side coil formed by the arranged wires has a horizontal width D1.

Thus, even when the voltage error is the largest, the error in the total distributed capacitance between the primary and secondary coil groups 31 and 32 caused by the voltage error can be reduced.

As described above, the planar transformer 3 of the present embodiment has two primary-side coil layers 311, 312 and two secondary-side coil layers 321, 322 disposed on both sides of a mask layer 33, thereby reducing the inter-layer capacitance caused by the mask layer in the structure of the related art, so as to avoid affecting the switching speed of the switching power supply under high-frequency operation, resulting in reduced efficiency. Furthermore, by making the distance L1 between the first primary-side coil layer 311 and the mask layer 33 within a preset range, the inter-layer capacitance caused by the mask layer 33 can be further reduced, and the efficiency loss during high-frequency operation can be reduced. Furthermore, by making the horizontal width D1 of the primary coil assembly 31 smaller than the horizontal width D2 of the mask layer 33, the error of the total distributed capacitance between the primary and secondary coil assemblies 31 and 32 caused by the pressing error can be reduced.

FIG5 is a cross-sectional view of a planar transformer 4 according to a third embodiment of the present disclosure. It should be noted that FIG5 is a cross-sectional view of the planar transformer 4 along the A-A line of FIG2A. The planar transformer 4 of this embodiment includes a primary-side coil assembly 41, a secondary-side coil assembly 42, and a mask layer 43. The primary-side coil assembly 41, for example, includes a first primary-side coil layer 411 and a second primary-side coil layer 412. The secondary-side coil assembly 42, for example, includes a first secondary-side coil layer 421 and a second secondary-side coil layer 422. The mask layer 43 is located between the primary-side coil assembly 41 and the secondary-side coil assembly 42. The mask layer 43 is adjacent to the first primary side coil layer 411 and the first secondary side coil layer 421. The difference between the planar transformer 4 of the present embodiment and the planar transformer 3 described above is that the spacing L2 between the first secondary side coil layer 421 and the mask layer 43 is within a preset range, and the horizontal width D3 of the first secondary side coil layer 421 and the second secondary side coil layer 422 of the secondary side coil group 42 is smaller than the horizontal width D2 of the mask layer 43.

Specifically, the preset range of the spacing L2 is, for example, 0.4 mm or more and 0.6 mm or less. That is, the first secondary side coil layer 421 and the mask layer 43 must be at least 0.4 mm apart. On the other hand, in order to prevent the volume of the planar transformer 4 from being too large, the spacing L2 between the first secondary side coil layer 421 and the mask layer 43 is preferably less than 0.6 mm. In this way, the inter-layer capacitance caused by the mask layer 43 can be further reduced, and the efficiency loss during high-frequency operation can be reduced.

As described above, the planar transformer 4 of this embodiment has two primary-side coil layers 411, 412 and two secondary-side coil layers 421, 422 disposed on both sides of a mask layer 43, thereby reducing the inter-layer capacitance caused by the mask layer in the structure of the related art, so as to avoid affecting the switching speed of the switching power supply under high-frequency operation, resulting in reduced efficiency. Furthermore, by making the distance L2 between the first secondary-side coil layer 421 and the mask layer 43 within a preset range, the inter-layer capacitance caused by the mask layer 43 can be further reduced, and the efficiency loss during high-frequency operation can be reduced. Furthermore, by making the horizontal width D3 of the secondary coil assembly 42 smaller than the horizontal width D2 of the mask layer 33, the error of the total distributed capacitance between the primary and secondary coil assemblies 41 and 42 caused by the pressing error can be reduced.

FIG6 is a cross-sectional view of a planar transformer 5 according to a fourth embodiment of the present disclosure. It should be noted that FIG6 is a cross-sectional view of the planar transformer 5 along the A-A line of FIG2A. The planar transformer 5 of this embodiment includes a primary-side coil assembly 51, a secondary-side coil assembly 52, and a mask layer 53. The primary-side coil assembly 51, for example, includes a first primary-side coil layer 511 and a second primary-side coil layer 512. The secondary-side coil assembly 52, for example, includes a first secondary-side coil layer 521 and a second secondary-side coil layer 522. The mask layer 53 is located between the primary-side coil assembly 51 and the secondary-side coil assembly 52. The mask layer 53 is adjacent to the first primary side coil layer 511 and the first secondary side coil layer 521. The difference between the planar transformer 5 of this embodiment and the above-mentioned planar transformers 3 and 4 is that the spacing L1 between the first primary side coil layer 511 and the mask layer 53 is within the preset range, the spacing L2 between the first secondary side coil layer 521 and the mask layer 53 is within the preset range, and the horizontal widths D1 and D3 of the primary side coil group 51 and the secondary side coil group 52 are both smaller than the horizontal width D2 of the mask layer 53.

Specifically, the preset range of the spacing L1 and L2 is, for example, 0.4 mm or more and 0.6 mm or less. That is, the first primary side coil layer 511 and the first secondary side coil layer 521 need to be at least 0.4 mm apart from the mask layer 53. On the other hand, in order to prevent the volume of the planar transformer 5 from being too large, the spacing L1 and L2 between the first primary side coil layer 511 and the first secondary side coil layer 521 and the mask layer 53 are preferably less than 0.6 mm. In this way, the inter-layer capacitance caused by the mask layer 53 can be further reduced, and the efficiency loss during high-frequency operation can be reduced.

It is worth mentioning that the spacing L1 between the first primary side coil layer 511 and the mask layer 53 can be the same as or different from the spacing L2 between the first secondary side coil layer 521 and the mask layer 53, but it is not restrictive.

As mentioned above, by making the spacing L1 between the first primary side coil layer 511 and the mask layer 53 and the spacing L2 between the first secondary side coil layer 521 and the mask layer 53 within the preset range, the inter-layer capacitance caused by the mask layer 53 can be further reduced, and the efficiency loss during high-frequency operation can be reduced. Moreover, by making the horizontal width D1 of the primary side coil group 51 and the horizontal width D3 of the secondary side coil group 52 smaller than the horizontal width D2 of the mask layer 53, the error of the total distributed capacitance between the primary and secondary side coil groups 51 and 52 caused by the press-fit error can be reduced.

It should be noted that the combination of the horizontal width of the primary side coil group being smaller than the horizontal width of the mask layer (hereinafter referred to as feature 1), the horizontal width of the secondary side coil group being smaller than the horizontal width of the mask layer (hereinafter referred to as feature 2), the distance between the first primary side coil layer and the mask layer being within a preset range (hereinafter referred to as feature 3), and the distance between the first secondary side coil layer and the mask layer being within a preset range (hereinafter referred to as feature 4) is not limited to the above-mentioned embodiments. In other words, feature 1 can also be combined with feature 4, or feature 2 can also be combined with feature 3.

In summary, the planar transformer disclosed in the present invention arranges two primary-side coil layers and two secondary-side coil layers on both sides of a mask layer, thereby reducing the inter-layer capacitance caused by the mask layer in the structure of the related art, so as to avoid affecting the switching speed of the switching power supply under high-frequency operation, resulting in reduced efficiency. Specifically, the planar transformer disclosed in the present invention can increase the switching speed of the switching power supply by about 30% to 40% compared with the planar transformer of the related art, and can reduce the inter-layer capacitance between the primary-side coil layer and the mask layer by about 40% to 50% and reduce the inter-layer capacitance between the secondary-side coil layer and the mask layer by about 40% to 50%. In other words, the planar transformer disclosed herein can reduce the inter-layer capacitance caused by the mask layer and reduce the efficiency loss during high-frequency operation.

Furthermore, the present disclosure can further reduce the interlayer capacitance caused by the mask layer and reduce the efficiency lost during high-frequency operation by making the spacing between the first primary side coil layer and the mask layer 33 and/or the spacing between the first secondary side coil layer and the mask layer within a preset range. Furthermore, the present disclosure can reduce the error of the total distributed capacitance between the primary and secondary side coil groups caused by the press-fit error by making the horizontal width of the primary side coil group and/or the horizontal width of the secondary side coil group smaller than the horizontal width of the mask layer.

As used herein and not otherwise defined, the terms "substantially" and "approximately" are used to describe and describe small variations. When used in conjunction with an event or circumstance, the terms may include the exact time at which the event or circumstance occurred, as well as the event or circumstance occurring to a close approximation. For example, when used in conjunction with a numerical value, the terms may include a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

The above summarizes the components of several embodiments so that those with ordinary knowledge in the art to which the present invention belongs can better understand the concepts of the embodiments of the present invention. Those with ordinary knowledge in the art to which the present invention belongs should understand that the embodiments of the present invention can be used as a basis to design or modify other processes and structures to achieve the same purpose and/or achieve the same benefits as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present invention belongs should also understand that these equivalent structures do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and other options can be made here without deviating from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined as the scope of the attached patent application.

2: Planar transformer

21: Beginner side coil set

211: First primary side coil layer

212: Second primary side coil layer

22: Secondary coil assembly

221: First secondary side coil layer

222: Second secondary side coil layer

23: Mask layer

Claims (20)

A planar transformer comprises: a first primary side coil layer; a second primary side coil layer adjacent to the first primary side coil layer; a mask layer adjacent to the first primary side coil layer; a first secondary side coil layer adjacent to the mask layer; and a second secondary side coil layer adjacent to the first secondary side coil layer, wherein the first primary side coil layer and the second primary side coil layer are located on one side of the mask layer, and the first secondary side coil layer and the second secondary side coil layer are located on the other side of the mask layer. A planar transformer as described in claim 1, wherein a distance between the first primary side coil layer and the mask layer is within a preset range. A planar transformer as described in claim 2, wherein the preset range is greater than 0.4 cm and less than 0.6 cm. A planar transformer as described in claim 1, wherein a distance between the first secondary side coil layer and the mask layer is within a preset range. A planar transformer as described in claim 4, wherein the preset range is greater than 0.4 cm and less than 0.6 cm. A planar transformer as described in claim 1, wherein a distance between the first primary side coil layer and the mask layer is the same as a distance between the first secondary side coil layer and the mask layer. A planar transformer as described in claim 1, wherein a horizontal width of the first primary side coil layer is smaller than a horizontal width of the mask layer. A planar transformer as described in claim 1, wherein a horizontal width of the first secondary side coil layer is smaller than a horizontal width of the mask layer. A planar transformer comprises: a mask layer; a first primary side coil layer located on one side of the mask layer; a first secondary side coil layer located on the other side of the mask layer; a second primary side coil layer located on the other side of the first primary side coil layer opposite to the mask layer; and a second secondary side coil layer located on the other side of the first secondary side coil layer opposite to the mask layer. A planar transformer as described in claim 9, wherein a distance between the first primary side coil layer and the mask layer is within a preset range. A planar transformer as described in claim 10, wherein the preset range is greater than 0.4 cm and less than 0.6 cm. A planar transformer as described in claim 9, wherein a distance between the first secondary side coil layer and the mask layer is within a preset range. A planar transformer as described in claim 12, wherein the preset range is greater than 0.4 cm and less than 0.6 cm. A planar transformer as described in claim 9, wherein a distance between the first primary side coil layer and the mask layer is the same as a distance between the first secondary side coil layer and the mask layer. A planar transformer as described in claim 9, wherein a horizontal width of the first primary side coil layer is smaller than a horizontal width of the mask layer. A planar transformer as described in claim 9, wherein a horizontal width of the first secondary side coil layer is smaller than a horizontal width of the mask layer. A planar transformer comprises: a primary coil group having at least two primary coil layers; a secondary coil group having at least two secondary coil layers; and a mask layer located between the primary coil group and the secondary coil group. A planar transformer as described in claim 17, wherein a distance between the primary side coil set and the mask layer is within a preset range. A planar transformer as described in claim 17, wherein a distance between the secondary side coil set and the mask layer is within a preset range. A planar transformer as described in claim 17, wherein a distance between the primary side coil group and the mask layer is the same as a distance between the secondary side coil group and the mask layer.

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