TWI864466B - Etching system for fabricating semiconductor device structure - Google Patents

Abstract

The present application discloses an etching system. The etching system includes an etch module executing a first etching recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first etching recipe to a second etching recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second etching recipe taking into consideration at least one of an etching rate of a second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.

Description

Etching systems for fabricating semiconductor device structures

This application claims priority to U.S. Patent Application Nos. 17/848,513 and 17/808,940 (i.e., priority date is "June 24, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to an etching system for preparing semiconductor device structures. More specifically, the present disclosure relates to an etching system for preparing semiconductor device structures using an artificial intelligence module.

Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the growing demand for computing power. However, various problems arise during the shrinking process, and these problems are increasing. Therefore, challenges remain in improving quality, yield, performance and reliability, and reducing complexity.

The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present case.

One aspect of the present disclosure provides a semiconductor device structure preparation system, including an etching module, which executes a first etching recipe on a first wafer to transform the first wafer from a first wafer state to a second wafer state; a first measurement module, which collects the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module, which is coupled to the first measurement module and the etching module, and is configured to analyze the first set of data, and when the first set of data is not within a predetermined range, update the first etching recipe to generate a second etching recipe. The second etching recipe is configured as a second wafer to be processed after the first wafer.

Another aspect of the present disclosure provides a semiconductor device structure preparation system, including a deposition module, which is configured to execute a first deposition recipe on a first wafer to transform the first wafer from a first wafer state to a second wafer state; a first measurement module, which is used to collect the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module, which is coupled to the first measurement module and the deposition module, and is configured to analyze the first set of data, and when the first set of data is not within a predetermined range, update the first deposition recipe to generate a second deposition recipe. The second deposition recipe is configured to be applied to a second wafer to be processed after the first wafer.

Another aspect of the present disclosure provides a semiconductor device structure preparation system, including an implantation module configured to execute a first carrier implantation recipe on a first wafer to transform the first wafer from a first wafer state to a second wafer state; a first measurement module for collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the implantation module, configured to analyze the first set of data, and update the first carrier implantation recipe to generate a second carrier implantation recipe when the first set of data is not within a predetermined range. The second carrier implantation recipe is configured to be applied to a second wafer to be processed after the first wafer.

Due to the design of the manufacturing system disclosed herein, the relevant process recipe can be updated (or adjusted) within the wafer-to-wafer time frame through the artificial intelligence module and the feedback data measured by the first measurement module. As a result, the yield and/or reliability of the wafer will be improved.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

The following description of the present disclosure is accompanied by the drawings incorporated in and constituting a part of the specification, which illustrate embodiments of the present disclosure, but the present disclosure is not limited to the embodiments. In addition, the following embodiments can be appropriately integrated with the following embodiments to complete another embodiment.

"One embodiment", "embodiment", "exemplary embodiment", "other embodiments", "another embodiment", etc. refer to embodiments described in the present disclosure that may include specific features, structures or characteristics, but not every embodiment must include the specific features, structures or characteristics. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

In order to make the present disclosure fully understandable, the following description provides detailed steps and structures. Obviously, the implementation of the present disclosure is not limited to the specific details known to those skilled in the art. In addition, the known structures and steps are not described in detail to avoid unnecessarily limiting the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to the detailed description, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the content of the detailed description, but is defined by the scope of the patent application.

In this disclosure, semiconductor devices generally refer to devices that can utilize semiconductor properties. Electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices all fall within the scope of semiconductor devices.

It should be noted that, in the description of the present invention, the upper side (or up) corresponds to the direction of the arrow in the Z direction, and the lower side (or down) corresponds to the opposite direction of the arrow in the Z direction.

FIG1 is a flowchart illustrating a method 10 for manufacturing a semiconductor device using a manufacturing system 100A according to an embodiment of the present disclosure. FIG2 is an exemplary block diagram illustrating a manufacturing system 100A according to an embodiment of the present disclosure.

1 and 2 , in step S11 , an etching recipe is executed on a current wafer by the etching module 110 of the fabrication system 100A.

2, which includes a material process flow shown in solid lines and an information flow shown in dotted lines. The material process flow includes a portion of a process for etching a semiconductor substrate, such as a chip (or wafer).

2, in some embodiments, the first event E1 may be a wafer-in event that transfers a current wafer (also referred to as a first wafer W1) to an etching module 110, and the etching module 110 provides a method for changing the current wafer from a first wafer state S1 (or referred to as the first state S1) to a second wafer state S2 (or referred to as the second state S2). In this embodiment, the material processing flow includes an etching process for the current wafer. In some embodiments, before being processed by the etching module 110, the top of the current wafer includes a patterned photoresist layer or a patterned hard mask layer. In some embodiments, the current chip may be in a front-end-of-line stage, such as forming word lines, forming gate structures, or forming contacts, but not limited thereto. In some embodiments, the current chip may be in a back-end-of-line stage, such as forming plugs, forming top metals, or forming capacitors, but not limited thereto.

It should be noted that in the first event E1, multiple chips may be processed in batches; therefore, referring to a chip in the singular in this embodiment does not necessarily limit the disclosure to a single chip, but may include multiple chips, multiple batches, or any materials processed in groups.

In some embodiments, the etching module 110 may include one or more etching chambers not shown separately. The current wafer may be placed in the etching chamber and then an etching process using an etching recipe may be performed. The etching recipe for the current wafer may also be referred to as a first etching recipe R1. In some embodiments, the first etching recipe R1 may be a nominal recipe.

In some embodiments, the etching module 110 may include a graphical user interface (GUI) component (not shown for clarity) and a database (not shown for clarity). GUI components are provided to enable the user to: view tool status; create and edit x-y graphs of summarized or raw (trace) parameter data for a selected wafer; view module warning logs; set up data collection schedules, specify conditions for writing data to a database or exporting files; import files into statistical process control (SPC) charting, modeling, and spreadsheet programs; review wafer process information for a specific wafer, and view data currently saved to the database; create and edit SPC graphs of process parameters, set SPC alerts, and generate email alerts; run multivariate principal component analysis (PCA) and/or partial least squares (PLS) model; and/or view the diagnostic screen to troubleshoot and report problems with the etching module 110.

In some embodiments, the raw data and trace data from the etching module 110 can be stored as files in a database. The amount of data may depend on the data collection plan set by the user, as well as the frequency of executing the process and the process module running. The data obtained from the etching module 110 can be stored in a table. In some embodiments, the GUI component of the etching module 110 and the database of the etching module 110 are not necessary.

2 , the preparation system 100A includes an artificial intelligence (AI) module 300 and a first measurement module 210. In some embodiments, the artificial intelligence module 300 is coupled to the etching module 110. In some embodiments, the artificial intelligence module 300 and the etching module 110 are independent components physically separated from each other. The communication between the artificial intelligence module 300 and the etching module 110 can use any suitable communication technology, such as analog technology (e.g., relay logic), digital technology (e.g., RS232, Ethernet or wireless), network technology (e.g., local area network (LAN), wide area network (WAN), Internet), Bluetooth technology, near field communication technology and/or any other suitable communication technology. The communication between the artificial intelligence module 300 and the etching module 110 complies with the general equipment module/semiconductor equipment communications standard (GEM SECS) communication protocol.

In some embodiments, the artificial intelligence module 300 can be integrated into the etching module 110.

In some embodiments, the artificial intelligence module 300 is coupled to the first measurement module 210. In some embodiments, the artificial intelligence module 300 and the first measurement module 210 are independent components that are physically separated from each other. The communication between the artificial intelligence module 300 and the first measurement module 210 can use any suitable communication technology, such as analog technology (e.g., relay logic), digital technology (e.g., RS232, Ethernet or wireless), network technology (such as local area network, wide area network, Internet), Bluetooth technology, near field communication technology and/or any other suitable communication technology. The communication between the artificial intelligence module 300 and the first measurement module 210 complies with the common device module/semiconductor device communication standard communication protocol.

In some embodiments, the artificial intelligence module 300 can operate as a single input single output (SISO) device, a single input multiple output (SIMO) device, a multiple input single output (MISO) device, and a multiple input multiple output (MISO) device.

In some embodiments, the artificial intelligence module 300 may include any suitable hardware (which may execute software or applications in some embodiments), such as a computer, a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), a field-programmable gate array (FGPAs), and a digital signal processor (DSP) (any of which may be considered a hardware processor), an encoder, a circuit for reading the encoder, a storage device (including one or more EPROMS, one or more EEPROMs, dynamic random access memory (DRAM), static random access memory (SRAM), and/or flash memory), and/or any other suitable hardware element.

The artificial intelligence module 300 may include a GUI component (not shown for clarity) and a database (not shown for clarity). The GUI component of the artificial intelligence module 300 may provide an interactive method between the artificial intelligence module 300 and the user. Authorized users and administrators may use the GUI component to modify the settings and default parameters of the artificial intelligence module 300. Configuration data may be stored in the database.

In some embodiments, the GUI component of the artificial intelligence module 300 may include a status component for displaying the current status of the artificial intelligence module 300. In addition, the status component may include a chart component for presenting system-related and process-related data to the user using one or more different types of charts.

In some embodiments, the database of the artificial intelligence module 300 can be used to archive input and output data. For example, the artificial intelligence module 300 can archive the input received, the output sent, and the actions taken by the artificial intelligence module 300 in a searchable database.

In some embodiments, the artificial intelligence module 300 may include means for data backup and recovery. In addition, the searchable database may include model information, setting information, and historical information, and the artificial intelligence module 300 may use the database component to back up and restore historical and current model information and model setting information.

In some embodiments, the artificial intelligence module 300 may include multiple applications, including at least one machine-related application, at least one module-related application, at least one sensor-related application, at least one interface-related application, at least one database-related application, at least one GUI-related application, and/or at least one configuration application.

In some embodiments, the artificial intelligence module 300 may include one or more of the following algorithms alone or in combination: machine learning, hidden Markov model; recursive neural network; convolutional neural network; Bayesian symbolic method; general adversarial network; support vector machine; and/or any other suitable artificial intelligence algorithm.

In some embodiments, the artificial intelligence module 300 may include at least one process model that can predict the second state S2 of the current chip. For example, a process model of etching rate can be used together with process time to calculate etching depth, and a process model of deposition rate can be used together with process time to calculate deposition thickness. In some embodiments, the process model may include an SPC chart, a PLS model, a PCA model, a fault detection/correction (FDC) model, and a multivariate analysis (MVA) model. In some embodiments, the artificial intelligence module 300 can receive and utilize externally provided data as limits for process parameters in the etching module 110. For example, a GUI component of the artificial intelligence module 300 may provide a means for manually inputting limits for process parameters.

In some embodiments, the artificial intelligence module 300 can be used to configure any number of process modules. The artificial intelligence module 300 can collect, provide, process, store and display data from process modules and/or measurement modules related to the process.

2 , after the etching process of the etching module 110 using the first etching recipe, the wafer state of the current wafer may be changed from a first wafer state (before the etching process) to a second wafer state (after the etching process) by the etching module 110 .

1 and 2 , in step S13 , the first measurement module 210 generates a set of data of the current chip.

2, in some embodiments, the processed current wafer is transferred to the first measurement module 210 after the etching process is completed. The first measurement module 210 can collect a set of data (also referred to as the first set of data D1) of the second state S2 of the processed current wafer. In some embodiments, the first measurement module 210 can include a single measurement device or multiple measurement devices. The first measurement module 210 can include a measurement device related to the process module and/or an external measurement device.

In some embodiments, the first metrology module 210 may be an after-etching-inspection (AEI) metrology tool. The AEI metrology tool may investigate and inspect defects, contamination, and critical dimensions (CD) after an etching process. In some embodiments, the first metrology module 210 may include an optical spectroscopy (e.g., optical critical dimension, OCD) metrology tool for measuring CD and/or the profile of etched features.

In some embodiments, the first measurement module 210 may include a chip probe (CP) module 210-1 configured to measure electrical characteristics. For example, the CP module 210-1 may measure a leakage current of a gate through a resistor, but is not limited thereto.

In some embodiments, the first measurement module 210 may include a wafer acceptance test module (WAT) module 210-3 configured to measure electrical characteristics. For example, the WAT module 210-3 may measure the gate current of a transistor through a resistor, or measure the drain leakage current of a transistor through a resistor, but is not limited thereto.

In some embodiments, the first metrology module 210 may include a statistical process control (SPC) module 210-5 configured to provide data related to the profile (or topography) of a layer. For example, the SPC module 210-5 may provide data related to the profile (or topography) of a tungsten layer of a word line or the thickness variation of a gate oxide layer, but is not limited thereto.

1 and 2 , in step S15 , the artificial intelligence module 300 will analyze the data of the current chip, and when the data of the current chip is not within a predetermined range, the artificial intelligence module 300 may update the etching recipe.

2 , in some embodiments, the first set of data D1 of the processed current wafer collected by the first measurement module 210 after the etching process can be analyzed by the artificial intelligence module 300 to determine whether the data is within a predetermined range PR (predetermined range, for example, acceptance criteria or specifications). If the first set of data D1 is not within the predetermined range PR, the first set of data D1 of the processed current wafer collected by the first measurement module 210 will be fed back to the artificial intelligence module 300 coupled to the etching module 110 (as shown by the dotted arrow FB1). The artificial intelligence module 300 can update the first etching recipe R1 based on the feedback data and provide the second etching recipe R2 for the next wafer (as shown by the dotted arrow UD1). The next wafer can also be referred to as the second wafer W2.

In some embodiments, parameters (PM) of the first etching recipe R1, such as gas ratios and/or flow rates, may be updated by the artificial intelligence module 300 to generate a second etching recipe R2. In some embodiments, the etching rate of the first etching recipe R1 may be updated by the artificial intelligence module 300 based on feedback data. In some embodiments, the artificial intelligence module 300 may update the tilt angle of the wafer configured by the first etching recipe R1 based on the feedback data. In some embodiments, the artificial intelligence module 300 may update the rotation rate of the wafer configured by the first etching recipe R1 based on the feedback data. Conversely, when the data is within a predetermined range PR, the first etching recipe R1 may be retained and applied to the next wafer. In other words, the etch recipe can be updated or adjusted instantly within a wafer-to-wafer time frame.

In some embodiments, the artificial intelligence module 300 can use the data of the processed current wafer collected by the first measurement module 210 after the etching process to calculate a set of process deviations. The calculated process deviations can be determined based on target data and the data of the processed current wafer collected by the first measurement module 210 after the etching process. The calculated process deviations can be used to determine the correction of the first etching recipe R1 for the next wafer to be processed. In the description of the present disclosure, the target data represents the desired specification after the processing is completed.

In some embodiments, the artificial intelligence module 300 may use table-based and/or formula-based techniques. For example, the recipe may be in a table, and the artificial intelligence module 300 performs a table lookup to determine which correction or corrections provide the best solution. Alternatively, a set of formulas may be used to determine the corrections, and the artificial intelligence module 300 determines which correction formula or formulas provide the best solution.

When the artificial intelligence module 300 uses a table-based technique, the variables of the feedback control are configurable. For example, the variables can be constants or coefficients in a table. In addition, there can be multiple tables that can be switched based on rules based on input ranges or output ranges.

When the artificial intelligence module 300 uses formula-based control, the variables of the feedback control are configurable. For example, the variables can be constants or coefficients in the formula. In addition, there can be multiple formula combinations that can be switched based on rules based on input ranges or output ranges.

2, the second event E2 may represent a subsequent processing process of the processed current chip. In this embodiment, the second event E2 may be a celan process, a deposition process, or other applicable processes.

By using the artificial intelligence module 300 coupled with the etching module 110 and the first metrology module 210, the relevant process recipe (e.g., the etching recipe in the present embodiment) can be updated (or adjusted) according to the data collected by the first metrology module 210. The next wafer can adopt the updated (or adjusted) recipe to obtain parameters within the acceptance criteria. As a result, the yield and/or reliability of the wafer will be improved.

In some embodiments, the first measurement module 210 may include a CP module 210-1, a WAT module 210-3, and an SPC module 210-5. The processed current chip can be transmitted to each module to collect data. The data collected by each module can be fed back to the artificial intelligence module 300 respectively. For example, the SPC module 210-5 can collect data related to the profile (or morphology) of the tungsten layer of the word line of the chip. The data collected by the SPC module 210-5 can be fed back to the artificial intelligence module 300. Then, the chip can continue the preparation process of forming the gate. The CP module 210-1 and/or the WAT module 210-3 can collect the resistance data of the chip gate and feed it back to the artificial intelligence module 300 respectively.

In some embodiments, the first measurement module 210 may be integrated into the etching module 110. In some embodiments, the first measurement module 210 may be a set of sensors that may monitor process-related parameters, such as gas flow, gas ratio, or other applicable process-related parameters.

In some embodiments, the first measurement module 210 can provide feedback data to the artificial intelligence module 300 in real time. Therefore, the artificial intelligence module 300 can immediately update the etching recipe. For example, the first etching recipe can be a multi-stage recipe, such as a two-stage recipe. The first measurement module 210 can continuously monitor process-related parameters during the first stage of the first etching recipe R1 and provide feedback to the artificial intelligence module 300 (as shown by the dotted arrow FB1).

At the same time, the artificial intelligence module 300 can analyze the feedback data to determine whether to update the second stage of the first etching recipe R1. If the first stage of the first etching recipe R1 contains process deviations, the artificial intelligence module 300 can correct and update the second stage of the first etching recipe R1 (as shown by the dotted arrow UD1) so that the processed wafer has parameters (e.g., CD, resistance and/or profile) within the acceptance standard.

Accordingly, the first metrology module 210 can also continuously monitor process-related parameters during and after the second phase of the first etching recipe R1 and provide feedback to the artificial intelligence module 300. At the same time, the artificial intelligence module 300 can analyze the feedback data to determine whether to update the first etching recipe R1 for the next wafer to be processed.

In some embodiments, the artificial intelligence module 300 can be configured to determine an etching rate of a material layer on a wafer and control a rotation rate of the wafer in response to the determined etching rate/tilt angle, thereby controlling a final thickness profile of the material layer.

FIG. 3 illustrates in cross-sectional view a first wafer W1 processed by the etching module 110 using a first etching recipe R1 and a second wafer W2 processed by the etching module 110 using a second etching recipe R2 according to an embodiment of the present disclosure.

3 , a first wafer W1 (i.e., a current wafer) may include a substrate W11 and a dielectric layer W13 disposed on the substrate W11. An etching process using an etching module 110 using a first etching recipe R1 is performed on the first wafer W1 to form a groove W15 along the dielectric layer W13. The first wafer W1 including the groove W15 may be referred to as a processed current wafer. Relevant parameters of the groove W15, such as CD and/or profile, may be measured by the first measurement module 210 to generate a first set of data D1. The artificial intelligence module 300 may analyze the first set of data D1 to decide whether to update the first etching recipe R1. As shown in FIG3 , the CD and/or profile may not be within a predetermined range (the sidewall profile of the groove W15 is not straight and symmetrical). Therefore, the artificial intelligence module 300 may update the parameters of the first etching recipe R1, such as the tilt angle, etching rate and/or rotation rate of the first etching recipe R1, to generate the second etching recipe R2.

In contrast, a second wafer W2 (i.e., a next wafer) including a substrate W21 and a dielectric layer W23 disposed on the substrate W21 may be processed by the etching module 110 using a second etching recipe R2 having updated recipe parameters (e.g., tilt angle α). By adopting the second etching recipe R2, relevant parameters of the second wafer (e.g., a sidewall profile of the groove W25) may be within a predetermined range.

4 to 6 illustrate exemplary block diagrams of manufacturing systems 100B, 100C, 100D according to some embodiments of the present disclosure.

4 , a block diagram may illustrate a preparation system 100B similar to that illustrated in FIG. 2 . The same or similar elements in FIG. 4 as those in FIG. 2 are labeled with the same or similar reference numerals, and repeated descriptions are omitted.

4 , before the etching module 110 processes the current wafer of the first event E1, the trace data of the etching module 110, such as module trace data, maintenance data, end point detection (EPD) data, and/or other process-related data can be fed back to the artificial intelligence module 300 (as indicated by the dotted arrow FF1). The artificial intelligence module 300 can analyze the trace data of the etching module 110 to adjust the etching recipe for processing the current wafer (as indicated by the dotted arrow AD1). After the process is completed, the artificial intelligence module 300 can also update the adjusted etching recipe according to the feedback data of the first measurement module 210.

5 , the block diagram may illustrate a preparation system 100C similar to that illustrated in FIG. 2 . The same or similar elements in FIG. 5 as those in FIG. 2 have been labeled with the same or similar reference numerals, and repeated descriptions are omitted.

5 , the current wafer may be transferred to a second metrology module 220 before being processed by the etching module 110. In some embodiments, the second metrology module 220 may include a single metrology device or multiple metrology devices. The second metrology module 220 may include module-related metrology equipment and/or external metrology equipment. In this embodiment, the second metrology module 220 may be an after-development-inspection (ADI) metrology machine. In some embodiments, the second metrology module 220 may include an optical spectroscopy (e.g., optical critical dimension OCD) metrology machine for measuring CD and/or the profile of the etched features. The second metrology module 220 measures the critical dimensions and profile of the patterned photoresist layer on top of the current wafer. The measured CD can be fed forward to the artificial intelligence module 300 (as shown by the dotted arrow FF2). The CD measured by the second measurement module 220 can be called the second set of data D2.

Before the etching module 110 processes the current wafer, the artificial intelligence module 300 can use the difference between the feedback data of the second measurement module 220 and the target CD to select or calculate a set of process parameters to achieve the desired result. The adjusted recipe can be applied to the etching module 110 to process the current wafer (as shown by the dotted arrow AD2). In some embodiments, the feedforward data may also include data associated with the current wafer, such as lot number data, batch data, run data, composition data, and wafer history data. After the process is completed, the artificial intelligence module 300 may also update the adjusted etching recipe based on the feedback data of the first measurement module 210.

6 , a block diagram may illustrate a preparation system 100D similar to that illustrated in FIG. 5 . The same or similar elements in FIG. 6 as those in FIG. 5 are labeled with the same or similar reference numerals, and repeated descriptions are omitted.

6 , before the etching module 110 processes the current wafer of the first event E1, the tracking data of the etching module 110, such as module tracking data, maintenance data, endpoint detection data, and/or other process-related data can be fed forward to the artificial intelligence module 300 (as shown by the dotted arrow FF1). In addition, the measurement data of the second measurement module 220 can also be fed forward to the artificial intelligence module 300 (as shown by the dotted arrow FF2). The artificial intelligence module 300 can analyze the tracking data of the etching module 110 and the data measured by the second measurement module 220 to adjust the etching recipe used to process the current wafer (as shown by the dotted arrow AD3). After the process is completed, the artificial intelligence module 300 can also update the adjusted etching recipe based on the feedback data of the first measurement module 210.

FIG7 is a flowchart illustrating a method 20 for manufacturing a semiconductor device using a manufacturing system 100E according to another embodiment of the present disclosure. FIG8 is an exemplary block diagram illustrating a manufacturing system 100E according to another embodiment of the present disclosure.

7 and 8, in step S21, a deposition recipe is executed on the current wafer by the deposition module 120 of the fabrication system 100E.

8, in some embodiments, the first event E1 may be a chip-in event that transfers the current chip (also referred to as the first chip W1) to the deposition module 120, and the deposition module 120 provides a method for changing the current chip from the first chip state S1 to the second chip state S2. In this embodiment, the material processing flow includes a deposition process for the current chip. In some embodiments, the current chip may be in a front-end process stage, such as forming a word line, forming a gate structure, or forming a contact plug, but not limited thereto. In some embodiments, the current chip may be in a back-end process stage, such as forming a plug, forming a top metal, or forming a capacitor, but not limited thereto.

It should be noted that in the first event E1, multiple chips may be processed in batches; therefore, referring to a chip in the singular in this embodiment does not necessarily limit the disclosure to a single chip, but may include multiple chips, multiple batches, or any materials processed in groups.

In some embodiments, the deposition module 120 may include a deposition chamber that is not shown separately. The current wafer may be placed in the deposition chamber and then a deposition process using a deposition recipe may be performed. The deposition recipe of the current wafer may also be referred to as a first deposition recipe R1. In some embodiments, the first deposition recipe R1 may be a nominal recipe.

In some embodiments, the deposition module 120 may include a GUI component and a database, which are similar to the GUI component and the database of the etching module 110 illustrated in FIG. 2 , and are not described again herein.

8 , the artificial intelligence module 300 may be coupled to the deposition module 120. The communication between the deposition module 120 and the artificial intelligence module 300 may be similar to the communication between the etching module 110 and the artificial intelligence module 300 shown in FIG. 2 , and will not be described again herein. In some embodiments, the artificial intelligence module 300 may be integrated into the deposition module 120.

8 , after a deposition process of the deposition module 120 using a first deposition recipe, the wafer state of the current wafer may be changed from a first wafer state (before the deposition process) to a second wafer state (after the deposition process) through the deposition module 120 .

7 and 8 , in step S23 , the first measurement module 210 generates a set of data of the current chip.

8, after the deposition process is completed, the processed current wafer can be transferred to the first measurement module 210. The first measurement module 210 can collect a set of data (also referred to as the first set of data D1) of the second state of the processed current wafer. In some embodiments, the first measurement module 210 may include a single measurement device or multiple measurement devices. The first measurement module 210 may include a measurement device associated with the process module and/or an external measurement device. In this embodiment, the first measurement module 210 may be a measurement machine for measuring the thickness of a thin film.

In some embodiments, the first measurement module 210 may include a chip probe (CP) module 210-1 configured to measure electrical characteristics. For example, the CP module 210-1 may measure a leakage current of a gate through a resistor, but is not limited thereto.

In some embodiments, the first measurement module 210 may include a wafer acceptance test module (WAT) module 210-3 configured to measure electrical characteristics. For example, the WAT module 210-3 may measure the gate current of a transistor through a resistor, or measure the drain leakage current of a transistor through a resistor, but is not limited thereto.

In some embodiments, the first metrology module 210 may include a statistical process control (SPC) module 210-5 configured to provide data related to the profile (or morphology) of a layer. For example, the SPC module 210-5 may provide data related to the profile (or morphology) of a tungsten layer of a word line or the thickness variation of a gate oxide layer, but is not limited thereto.

7 and 8, in step S25, the artificial intelligence module 300 may analyze the data of the current chip, and when the data of the current chip is not within a predetermined range, the artificial intelligence module 300 may update the first deposition recipe.

8 , in some embodiments, the first set of data D1 of the processed current wafer collected by the first metrology module 210 after the deposition process can be analyzed by the artificial intelligence module 300 to determine whether the data is within a predetermined range PR. If the first set of data D1 is not within the predetermined range PR (e.g., acceptance criteria or specifications), the first set of data D1 of the processed current wafer collected by the first metrology module 210 will be fed back to the artificial intelligence module 300 coupled to the deposition module 120 (as shown by the dotted arrow FB1). The artificial intelligence module 300 can update the first deposition recipe R1 based on the fed-back data and provide the second deposition recipe R2 for the next wafer (as shown by the dotted arrow UD1). The next wafer can also be referred to as the second wafer W2.

In some embodiments, the parameters PM of the first deposition recipe R1, such as the deposition time, may be updated to generate the second deposition recipe R2. In some embodiments, the tilt angle of the wafer of the first deposition recipe R1 may be updated according to the feedback data. In some embodiments, the wafer rotation rate of the first deposition recipe R1 may be updated according to the feedback data. Conversely, when the data is within a predetermined range PR, the first deposition recipe R1 may be retained and applied to the next wafer. In other words, the deposition recipe may be updated or adjusted immediately within a wafer-to-wafer time frame.

In some embodiments, the artificial intelligence module 300 may calculate a set of process deviations using the first set of data D1 of the processed current wafer collected by the first metrology module 210 after the deposition process. The calculated process deviations may be determined based on the target data and the data of the processed current wafer collected by the first metrology module 210 after the deposition process. The calculated process deviations may be used to determine a correction to the first deposition recipe R1 of the next wafer to be processed.

In some embodiments, the artificial intelligence module 300 may use table-based and/or formula-based techniques. For example, the recipe may be in a table, and the artificial intelligence module 300 performs a table lookup to determine which correction or corrections provide the best solution. Alternatively, a set of formulas may be used to determine the corrections, and the artificial intelligence module 300 determines which correction formula or formulas provide the best solution.

When the artificial intelligence module 300 uses a table-based technique, the variables of the feedback control are configurable. For example, the variables can be constants or coefficients in a table. In addition, there can be multiple tables that can be switched based on rules based on input ranges or output ranges.

When the artificial intelligence module 300 uses formula-based control, the variables of the feedback control are configurable. For example, the variables can be constants or coefficients in the formula. In addition, there can be multiple formula combinations that can be switched based on rules based on input ranges or output ranges.

2, the second event E2 may represent a subsequent process of the currently processed chip. In this embodiment, the second event E2 may be a planarization process, or other applicable processes.

By using the artificial intelligence module 300 coupled to the deposition module 120 and the first metrology module 210, the relevant process recipe (e.g., the deposition recipe in the present embodiment) can be updated (or adjusted) based on the data collected by the first metrology module 210. The next wafer can adopt the updated (or adjusted) recipe to obtain parameters within the acceptance criteria. As a result, the yield and/or reliability of the wafer will be improved.

In some embodiments, the first measurement module 210 may include a CP module 210-1, a WAT module 210-3, and an SPC module 210-5. The processed current chip can be transmitted to each module to collect data. The data collected by each module can be fed back to the artificial intelligence module 300 respectively. For example, the SPC module 210-5 can collect data related to the profile (or morphology) of the tungsten layer of the word line of the chip. The data collected by the SPC module 210-5 can be fed back to the artificial intelligence module 300. Then, the chip can continue the preparation process of forming the gate. The CP module 210-1 and/or the WAT module 210-3 can collect the resistance data of the chip gate and feed it back to the artificial intelligence module 300 respectively.

In some embodiments, the first metrology module 210 may be integrated into the deposition module 120. In some embodiments, the first metrology module 210 may be a set of sensors that may monitor process-related parameters, such as thickness, profile, or other applicable process-related parameters.

In some embodiments, the first measurement module 210 can provide feedback data to the artificial intelligence module 300 in real time. Therefore, the artificial intelligence module 300 can immediately update the deposition recipe. For example, the first deposition recipe can be a multi-stage recipe, such as a two-stage recipe. The first measurement module 210 can continuously monitor process-related parameters during the first stage of the first deposition recipe R1 and provide feedback to the artificial intelligence module 300 (as shown by the dotted arrow FB1).

At the same time, the artificial intelligence module 300 can analyze the feedback data to determine whether to update the second stage of the first deposition recipe R1. If the first stage of the first deposition recipe R1 contains process deviations, the artificial intelligence module 300 can correct and update the second stage of the first deposition recipe R1 (as shown by the dotted arrow UD1) so that the processed wafer has parameters (e.g., thickness, resistance and/or profile) within the acceptance standard.

Accordingly, the first metrology module 210 can also continuously monitor process-related parameters during and after the second phase of the first deposition recipe R1 and provide feedback to the artificial intelligence module 300. At the same time, the artificial intelligence module 300 can analyze the feedback data to determine whether to update the first deposition recipe R1 for the next wafer to be processed.

In some embodiments, the artificial intelligence module 300 can be configured to determine a deposition rate of a material layer to be formed on a wafer, and control the rotation rate/tilt angle of the wafer in response to the determined deposition rate, thereby controlling the final thickness profile of the material layer. In some embodiments, some other process-related parameters PM of the deposition recipe can also be configured by the artificial intelligence module 300.

FIG. 9 illustrates in cross-sectional view a first wafer W1 processed by a deposition module 120 using a first deposition recipe R1 and a second wafer W2 processed by a deposition module 120 using a second deposition recipe R2 according to another embodiment of the present disclosure.

9 , a first wafer W1 (i.e., a current wafer) may include a substrate W11, a dielectric layer W13 disposed on the substrate W11, and a groove W15 along the dielectric layer W13. A deposition process using a deposition module 120 using a first deposition recipe R1 may be performed on the first wafer W1 to conformally form an oxide layer W17 on the groove W15 and the dielectric layer W13. The first wafer W1 including the oxide layer W17 may be referred to as a processed current wafer. The first measurement module 210 may measure relevant parameters such as thickness, coverage, step coverage, and/or profile of the oxide layer W17 to generate a first set of data D1. The artificial intelligence module 300 may analyze the first set of data D1 to determine whether to update the first deposition recipe R1. 9 , the step coverage and/or profile may not be within a predetermined range (the oxide layer W17 is discontinuous). Therefore, the artificial intelligence module 300 may update the parameters of the first deposition recipe R1, such as the tilt angle, deposition rate and/or rotation rate of the first deposition recipe R1, to generate a second deposition recipe R2.

In contrast, a second wafer W2 (i.e., a next wafer) including a substrate W21, a dielectric layer W23 disposed on the substrate W21, and a groove W25 along the dielectric layer W23 may be processed by the deposition module 120 using a second deposition recipe R2 with updated recipe parameters (e.g., tilt angle α). By adopting the second deposition recipe R2, the relevant parameters of the second wafer W2 (e.g., the coverage of the oxide layer W27) may be within a predetermined range.

FIG. 10 illustrates a manufacturing system 100F according to another embodiment of the present disclosure using an exemplary block diagram.

10 , a block diagram may illustrate a preparation system 100F similar to that illustrated in FIG. 8 . The same or similar elements in FIG. 10 as those in FIG. 8 have been labeled with the same or similar reference numerals, and repeated descriptions are omitted.

10 , before the deposition module 120 processes the current wafer of the first event E1, tracking data of the deposition module 120, such as module tracking data, maintenance data and/or other process-related data, can be fed forward to the artificial intelligence module 300 (as indicated by the dashed arrow FF1). The artificial intelligence module 300 can analyze the tracking data of the deposition module 120 to adjust the deposition recipe used to process the current wafer (as indicated by the dashed arrow AD1). After the process is completed, the artificial intelligence module 300 can also update the adjusted deposition recipe based on the feedback data of the first measurement module 210.

FIG11 is a flowchart illustrating a method 30 for manufacturing a semiconductor device using a manufacturing system 100G according to another embodiment of the present disclosure. FIG12 is an exemplary block diagram illustrating a manufacturing system 100G according to another embodiment of the present disclosure.

11 and 12, in step S31, the implant module 130 of the fabrication system 100G executes a carrier implant recipe on the current wafer.

Referring to FIG. 12 , in some embodiments, the first event E1 may be a chip-in event that transfers the current chip (also referred to as the first chip W1) to the implantation module 130, which provides a method for changing the current chip from the first chip state S1 to the second chip state S2. In this embodiment, the material processing flow includes an implantation process for the current chip. In some embodiments, the current chip may be in a front-end process stage, such as forming a word line, forming a gate structure, or forming a contact plug, but not limited thereto. In some embodiments, the current chip may be in a back-end process stage, such as forming a plug, forming a top metal, or forming a capacitor, but not limited thereto.

It should be noted that in the first event E1, multiple chips may be processed in batches; therefore, referring to a chip in the singular in this embodiment does not necessarily limit the disclosure to a single chip, but may include multiple chips, multiple batches, or any materials processed in groups.

In some embodiments, the implantation module 130 may include an implantation chamber that is not shown separately. The current wafer may be placed in the implantation chamber, and then the implantation process may be performed using a carrier implantation recipe. The carrier implantation recipe of the current wafer may also be referred to as a first carrier implantation recipe R1. In some embodiments, the first carrier implantation recipe R1 may be a nominal recipe.

In some embodiments, the implantation module 130 may include a GUI component and a database, which are similar to the GUI component and the database of the etching module 110 illustrated in FIG. 2 , and are not described again here.

12 , the artificial intelligence module 300 may be coupled to the implant module 130. The communication between the implant module 130 and the artificial intelligence module 300 may be similar to the communication between the etching module 110 and the artificial intelligence module 300 shown in FIG. 2 , and will not be repeated here. In some embodiments, the artificial intelligence module 300 may be integrated into the implant module 130.

12 , after the implantation process of the implantation module 130 using the first carrier implantation recipe, the chip state of the current chip can be changed from the first chip state (before the implantation process) to the second chip state (after the implantation process) through the implantation module 130 .

11 and 12 , in step S33 , the first measurement module 210 generates a set of data of the current chip.

12 , after the implantation process is completed, the processed current chip can be transferred to the first measurement module 210. The first measurement module 210 can collect a set of data (also referred to as the first set of data D1) of the second chip state S2 of the processed current chip. In some embodiments, the first measurement module 210 may include a single measurement device or multiple measurement devices. The first measurement module 210 may include a measurement device related to the process module and/or an external measurement device. In this embodiment, the first measurement module 210 may be a measurement machine for measuring electrical properties such as resistance or for measuring an implantation profile.

In some embodiments, the first measurement module 210 may include a chip probe (CP) module 210-1 configured to measure electrical characteristics. For example, the CP module 210-1 may measure a leakage current of a gate through a resistor, but is not limited thereto.

In some embodiments, the first measurement module 210 may include a wafer acceptance test module (WAT) module 210-3 configured to measure electrical characteristics. For example, the WAT module 210-3 may measure the gate current of a transistor through a resistor, or measure the drain leakage current of a transistor through a resistor, but is not limited thereto.

In some embodiments, the first metrology module 210 may include a statistical process control (SPC) module 210-5 configured to provide data related to the profile (or morphology) of a layer. For example, the SPC module 210-5 may provide data related to the profile (or morphology) of a tungsten layer of a word line or the thickness variation of a gate oxide layer, but is not limited thereto.

11 and 12 , in step S35 , the artificial intelligence module 300 may analyze the data of the current chip, and when the data of the current chip is not within a predetermined range, the artificial intelligence module 300 may update the first carrier implantation recipe.

Referring to FIG. 12 , in some embodiments, the first set of data D1 of the processed current wafer collected by the first measurement module 210 after the implantation process can be analyzed by the artificial intelligence module 300 to determine whether the data is within the predetermined range PR. If the first set of data D1 is not within the predetermined range PR, the first set of data D1 of the processed current wafer collected by the first measurement module 210 will be fed back to the artificial intelligence module 300 coupled to the implantation module 130 (as shown by the dotted arrow FB1). The artificial intelligence module 300 can update the first carrier implantation recipe R1 based on the feedback data and provide the second carrier implantation recipe R2 for the next wafer (as shown by the dotted arrow UD1). The next wafer can also be referred to as the second wafer W2.

In some embodiments, the parameters PM of the first carrier implantation recipe R1, such as implantation dose and/or implantation energy, may be updated to generate the second carrier implantation recipe R2. In some embodiments, the tilt angle of the wafer of the first carrier implantation recipe R1 may be updated according to the feedback data. Conversely, when the data is within a predetermined range PR, the first carrier implantation recipe R1 may be retained and applied to the next wafer. In other words, the first carrier implantation recipe R1 may be updated or adjusted immediately within a wafer-to-wafer time frame.

In some embodiments, the artificial intelligence module 300 may calculate a set of process deviations using the first set of data D1 of the processed current wafer collected by the first metrology module 210 after the implantation process. The calculated process deviations may be determined based on the target data and the data of the processed current wafer collected by the first metrology module 210 after the implantation process. The calculated process deviations may be used to determine corrections to the first carrier implantation recipe R1 of the next wafer to be processed.

In some embodiments, the artificial intelligence module 300 may use table-based and/or formula-based techniques. For example, the recipe may be in a table, and the artificial intelligence module 300 performs a table lookup to determine which correction or corrections provide the best solution. Alternatively, a set of formulas may be used to determine the corrections, and the artificial intelligence module 300 determines which correction formula or formulas provide the best solution.

When the artificial intelligence module 300 uses a table-based technique, the feedback control variables are configurable. For example, the variables can be constants or coefficients in a table. In addition, there can be multiple tables that can be switched based on rules based on input ranges or output ranges.

When the artificial intelligence module 300 uses formula-based control, the variables of the feedback control are configurable. For example, the variables can be constants or coefficients in the formula. In addition, there can be multiple formula combinations that can be switched based on rules based on input ranges or output ranges.

12, the second event E2 may represent a subsequent process of the currently processed chip. In this embodiment, the second event E2 may be a deposition process or other applicable processes.

By using the artificial intelligence module 300 coupled with the implantation module 130 and the first metrology module 210, the relevant process recipe (e.g., the carrier implantation recipe in the present embodiment) can be updated (or adjusted) according to the data collected by the first metrology module 210. The next wafer can adopt the updated (or adjusted) recipe to obtain parameters within the acceptance criteria. As a result, the yield and/or reliability of the wafer will be improved.

In some embodiments, the first measurement module 210 can be integrated into the implant module 130. In some embodiments, the first measurement module 210 can be a set of sensors that can monitor process-related parameters, such as resistance, implant profile, implant concentration, or other suitable process-related parameters.

In some embodiments, the first measurement module 210 can provide feedback data to the artificial intelligence module 300 in real time. Therefore, the artificial intelligence module 300 can immediately update the carrier implantation recipe. For example, the first carrier implantation recipe R1 can be a multi-stage recipe, such as a two-stage recipe. The first measurement module 210 can continuously monitor process-related parameters during the first stage of the first carrier implantation recipe R1 and provide feedback to the artificial intelligence module 300 (as shown by the dotted arrow FB1).

At the same time, the artificial intelligence module 300 can analyze the feedback data to determine whether to update the second stage of the first carrier implantation recipe R1. If the first stage of the first carrier implantation recipe R1 contains process deviations, the artificial intelligence module 300 can correct and update the second stage of the first carrier implantation recipe R1 (as indicated by the dotted arrow UD1) so that the processed wafer has parameters (e.g., thickness, resistance and/or profile) within the acceptance criteria.

Accordingly, the first metrology module 210 can also continuously monitor process-related parameters during and after the second phase of the first carrier implant recipe R1 and provide feedback to the artificial intelligence module 300. At the same time, the artificial intelligence module 300 can analyze the feedback data to determine whether to update the first carrier implant recipe R1 for the next wafer to be processed.

In some embodiments, the artificial intelligence module 300 can be configured to monitor the initial implantation profile of the carrier implantation recipe and automatically adjust the tilt angle of the implantation module 130/wafer to provide an updated carrier implantation recipe with a desired implantation profile, wherein the updated carrier implantation recipe takes into account the following factors: the initial implantation profile and the desired implantation profile.

In some embodiments, the artificial intelligence module 300 can derive an initial implant profile based on characteristics measured by a setup detector, a beam profiler, and an incident angle detector of the implant module 130.

FIG. 13 illustrates in cross-sectional view a first chip W1 processed by an implantation module 130 using a first carrier implantation recipe R1 and a second chip W2 processed by an implantation module 130 using a second carrier implantation recipe R2 according to another embodiment of the present disclosure.

13 , a first chip W1 (i.e., a current chip) may include a substrate W11 and a gate W13 disposed on the substrate W11. An implantation process using an implantation module 130 using a first carrier implantation recipe R1 is performed on the first chip W1 to form a source/drain W15 in the substrate W11. The first chip W1 including the source/drain W15 may be referred to as a processed current chip. The first measurement module 210 may measure relevant parameters such as resistance, implantation concentration, and/or implantation profile of the source/drain W15 to generate a first set of data D1. The artificial intelligence module 300 may analyze the first set of data D1 to determine whether to update the first deposition recipe R1. As shown in FIG. 13 , the step coverage and/or profile may not be within the predetermined range (the implant profile of the source/drain W15 is asymmetric). Therefore, the artificial intelligence module 300 may update the parameters of the first carrier implantation recipe R1, such as the tilt angle, implantation dose and/or implantation energy of the first carrier implantation recipe R1, to generate the second carrier implantation recipe R2.

In contrast, a second wafer W2 (i.e., a next wafer) including a substrate W21 and a gate W23 disposed on the substrate W21 may be processed by the implantation module 130 using a second carrier implantation recipe R2 having updated recipe parameters (e.g., tilt angle α). By adopting the second carrier implantation recipe R2, the relevant parameters of the second wafer W2 (e.g., the implantation profile of the source/drain W25) may be within a predetermined range.

FIG. 14 illustrates an exemplary block diagram of a preparation system 100H according to another embodiment of the present disclosure.

14 , a block diagram may illustrate a preparation system 100H similar to that illustrated in FIG. 12 . The same or similar elements in FIG. 14 as those in FIG. 12 have been labeled with the same or similar reference numerals, and repeated descriptions are omitted.

14 , before the implant module 130 processes the current wafer of the first event E1, the tracking data of the implant module 130, such as module tracking data, maintenance data and/or other process-related data, can be fed back to the artificial intelligence module 300 (as indicated by the dashed arrow FF1). The artificial intelligence module 300 can analyze the tracking data of the implant module 130 to adjust the carrier implant recipe used to process the current wafer (as indicated by the dashed arrow AD1). After the process is completed, the artificial intelligence module 300 can also update the adjusted carrier implant recipe based on the feedback data of the first measurement module 210.

One aspect of the present disclosure provides a preparation system, including an etching module configured to execute a first etching recipe on a first wafer to transform a first wafer state of the first wafer into a second wafer state; a first measurement module for collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etching module, configured to analyze the first set of data, and update the first etching recipe to generate a second etching recipe when the first set of data is not within a predetermined range. The second etching recipe is configured to be applied to a second wafer to be processed after the first wafer.

Another aspect of the present disclosure provides a preparation system, including a deposition module configured to execute a first deposition recipe on a first wafer to transform a first wafer state of the first wafer into a second wafer state; a first measurement module for collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the deposition module, configured to analyze the first set of data, and update the first deposition recipe to generate a second deposition recipe when the first set of data is not within a predetermined range. The second deposition recipe is configured to be applied to a second wafer to be processed after the first wafer.

Another aspect of the present disclosure provides a preparation system, including an implantation module configured to execute a first carrier implantation recipe on a first wafer to transform a first wafer state of the first wafer into a second wafer state; a first measurement module for collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the implantation module, configured to analyze the first set of data, and update the first carrier implantation recipe to generate a second carrier implantation recipe when the first set of data is not within a predetermined range. The second carrier implantation recipe is configured to be applied to a second wafer to be processed after the first wafer.

Due to the design of the fabrication system disclosed herein, the relevant process recipe can be updated (or adjusted) within a wafer-to-wafer time frame through the artificial intelligence module 300 and the feedback data measured by the first measurement module 210. As a result, the yield and/or reliability of the wafer will be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure as defined by the scope of the patent application. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

10: Method 20: Method 30: Method 100A: Preparation system 100B: Preparation system 100C: Preparation system 100D: Preparation system 100E: Preparation system 100F: Preparation system 100G: Preparation system 100H: Preparation system 110: Etching module 120: Deposition module 130: Implantation module 210: First measurement module 210-1: Chip probe module 210-3: Wafer acceptance test module 210-5: Statistical process control module 220: Second measurement module 300: Artificial intelligence module AD1: Dashed arrow AD2: Dashed arrow AD3: Dashed arrow D1: First set of data D2: First set of data E1: First event E2: Second event FB1: Dashed arrow FF1: Dashed arrow FF2: Dashed arrow PM: Parameter PR: Predetermined range R1: First deposition recipe R1: First etch recipe R1: First carrier implant recipe R2: Second deposition recipe R2: Second etch recipe R2: Second carrier implant recipe S1: First chip status S2: Second chip status UD1: Dashed arrow W1: First chip W11: Substrate W13: Dielectric layer W13: Gate W15: Recess W15: Source/Drain W17: Oxide layer W21: Substrate W23: Dielectric layer W23: Gate W25: Recess W25: Source/Drain W27: Oxide layer α: Tilt angle

When referring to the embodiments and the drawings together with the scope of the patent application, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements. FIG. 1 illustrates a method for preparing a semiconductor device using a preparation system according to an embodiment of the present disclosure with a flowchart; FIG. 2 illustrates a preparation system according to an embodiment of the present disclosure with an exemplary block diagram; FIG. 3 illustrates a first chip processed by an etching module using a first etching recipe and a second chip processed by an etching module using a second etching recipe according to an embodiment of the present disclosure with a cross-sectional diagram; FIGS. 4 to 6 illustrate preparation systems according to some embodiments of the present disclosure with exemplary block diagrams; FIG. 7 illustrates a method for preparing a semiconductor device using a preparation system according to another embodiment of the present disclosure with a flowchart; FIG. 8 illustrates a preparation system according to another embodiment of the present disclosure with an exemplary block diagram; FIG. 9 illustrates a first chip processed by a deposition module using a first deposition formula and a second chip processed by a deposition module using a second deposition formula in another embodiment of the present disclosure in a cross-sectional view; FIG. 10 illustrates a preparation system according to another embodiment of the present disclosure in an exemplary block diagram; FIG. 11 illustrates a method for preparing a semiconductor device using a preparation system in another embodiment of the present disclosure in a flow chart; FIG. 12 illustrates a preparation system according to another embodiment of the present disclosure in an exemplary block diagram; FIG. 13 illustrates a first chip processed by an implantation module using a first carrier implantation formula and a second chip processed by an implantation module using a second carrier implantation formula in another embodiment of the present disclosure in a cross-sectional view; FIG. 14 illustrates a preparation system according to another embodiment of the present disclosure using an exemplary block diagram.

10: Etching module

100A: Preparation system

210: First measurement module

210-1: Chip probe module

210-3: Wafer acceptance test module

210-5: Statistical process control module

300: Artificial Intelligence Module

D1: The first set of data

E1: First event

E2: Second Event

PM: parameters

PR: Predetermined range

R1: First deposition formula

R1: First Etching Recipe

S1: First chip status

S2: Second chip status

UD1: Dashed arrow

W1: First chip

W2: Second chip

Claims (11)

An etching system for preparing a semiconductor device structure includes: an etching module, which executes a first etching recipe on a first wafer to change the first wafer from a first wafer state to a second wafer state; a first measurement module, which collects the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module, which is coupled to the first measurement module and the etching module, configured to analyze the first set of data, and update the first etching recipe to generate a second etching recipe when the first set of data is not within a predetermined range; wherein the second etching recipe is configured for a second wafer to be processed after the first wafer; wherein, The artificial intelligence module is configured to generate the second etching recipe, which takes into account at least one of an etching rate of the second wafer, a rotation rate of the second wafer, a tilt angle of the second wafer, a carrier placement recipe of the first wafer, and a deposition recipe of the first wafer; wherein the etching module is configured to feed a tracking data of the etching module to the artificial intelligence module before executing the first etching recipe on the first wafer, and the artificial intelligence module is configured to analyze the tracking data of the etching module to adjust the first etching recipe; wherein the tracking data of the etching module includes module tracking data, maintenance data or end point detection (EPD) data. An etching system as described in claim 1, wherein the artificial intelligence module is integrated into the etching module. An etching system as described in claim 2, wherein the artificial intelligence module is configured to execute one or more of the following algorithms, alone or in combination: machine learning, hidden Markov model; recursive neural network; convolutional neural network; Bayesian symbolic method; general adversarial network; or support vector machine. The etching system as described in claim 1 further includes a second measurement module, which is coupled to the artificial intelligence module and configured to collect the first wafer state of the first wafer before the etching module executes the first etching recipe on the first wafer to generate a second set of data to feed forward to the artificial intelligence module, and the artificial intelligence module is configured to simultaneously analyze the second set of data parameters to adjust the first etching recipe. An etching system as described in claim 4, wherein the second measurement module includes a post-development inspection measurement machine for measuring a critical dimension. An etching system as described in claim 1, wherein the artificial intelligence module and the first measurement module communicate with each other through analog technology, digital technology, network technology, Bluetooth technology or near field communication technology. An etching system as described in claim 1, wherein the first measurement module includes a chip probe module, and the chip probe module is configured to collect electrical characteristics of the second chip state of the first chip. An etching system as described in claim 1, wherein the first measurement module includes a wafer acceptance test module, and the wafer acceptance test module is configured to collect electrical characteristics of the second wafer state of the first wafer. An etching system as described in claim 1, wherein the first metrology module includes a statistical process control module, the statistical process control module is configured to collect data related to the profile of the second wafer state of the first wafer. An etching system as described in claim 1, wherein the artificial intelligence module is configured to receive at least one tracking data of the first chip state of the first chip. An etching system as described in claim 1, wherein the artificial intelligence module is also configured to generate the second etching recipe taking into account a characteristic profile of the second wafer state of the first wafer.