TWI864126B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Description

Semiconductor device and method for forming the same

The present invention relates to a method for forming a semiconductor device with reduced space between nanostructured field effect transistors.

The integrated circuit manufacturing industry has experienced exponential growth over the past several decades. As integrated circuits develop, the minimum structural dimensions can be continuously reduced to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like), so that more electronic components can be integrated into a given area. The process of shrinking dimensions can provide many advantages, such as increased throughput, reduced manufacturing costs, increased device performance, or the like. One of the advances in the integrated circuit industry to shrink semiconductor devices is the multi-gate field effect transistor. Some examples of multi-gate field effect transistors include bi-gate field effect transistors, tri-gate field effect transistors, Ω-gate field effect transistors, or fully wound gate field effect transistors.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a semiconductor fin protruding vertically from a semiconductor substrate. A plurality of semiconductor nanostructures are directly located on the semiconductor fin and stacked vertically. A gate structure is located on the semiconductor fin and surrounds the semiconductor nanostructure. A dielectric fin is located on the semiconductor substrate, wherein the gate structure and the semiconductor nanostructure are located on a first side of the dielectric fin, and wherein the upper surface of the dielectric fin is lower than the upper surface of the gate structure. A dielectric structure is directly located on the dielectric fin, wherein the first upper surface of the dielectric structure is higher than the upper surface of the gate structure. A dielectric layer is at least partially disposed on a semiconductor substrate, wherein the dielectric layer is disposed on the second side of the dielectric fin, and the first side and the second side of the dielectric fin are opposite to each other, wherein the upper surface of the dielectric layer is higher than the upper surface of the gate structure and the first upper surface of the dielectric structure, and wherein the lower surface of the dielectric layer is lower than the upper surface of the dielectric fin.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a first semiconductor fin and a second semiconductor fin, which protrude vertically from a semiconductor substrate, wherein the second semiconductor fin is laterally separated from the first semiconductor fin in a first direction, wherein the first semiconductor fin and the second semiconductor fin extend laterally in a second direction and are parallel to each other, and wherein the second direction is substantially perpendicular to the first direction. A first gate structure is located on the first semiconductor fin. A second gate structure is located on the second semiconductor fin and is laterally separated from the first gate structure in the first direction. A first dielectric fin is disposed on the semiconductor substrate, wherein the first dielectric fin is disposed between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure. A second dielectric fin is disposed on the semiconductor substrate and is laterally separated from the first dielectric fin in a first direction, wherein the second dielectric fin is disposed between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure. A first dielectric structure is disposed on the first dielectric fin. A second dielectric structure is disposed on the second dielectric fin and is laterally separated from the first semiconductor fin in the first direction. A dielectric layer is at least partially disposed on a semiconductor substrate, wherein a first dielectric structure laterally separates the dielectric layer from a first portion of a first gate structure, and a second dielectric structure laterally separates the dielectric layer from a first portion of a second gate structure.

Some embodiments of the present invention provide a method for forming a semiconductor device. The method includes receiving a workpiece. The workpiece includes a first dielectric fin, located on a semiconductor substrate and laterally located between a first plurality of semiconductor nanostructures and a second plurality of semiconductor nanostructures; a second dielectric fin, located on the semiconductor substrate and laterally located between a third plurality of semiconductor nanostructures and the second plurality of semiconductor nanostructures; a first conductive gate structure, located on the semiconductor substrate and surrounding the first plurality of semiconductor nanostructures; a second conductive gate structure, located on the semiconductor substrate and surrounding the second plurality of semiconductor nanostructures; a third conductive gate structure, located on the semiconductor substrate and surrounding A third plurality of semiconductor nanostructures, wherein the second conductive gate structure is located between the first conductive gate structure and the third conductive gate structure and is laterally separated from the first conductive gate structure and the third conductive gate structure; a first dielectric structure is directly located on the first dielectric fin, wherein the first dielectric structure and the first dielectric fin laterally separate the first conductive gate structure from the second conductive gate structure; and a second dielectric structure is directly located on the second dielectric fin, wherein the second dielectric structure and the second dielectric fin laterally separate the third conductive gate structure from the second conductive gate structure. A first dielectric layer is formed on a first dielectric fin, a second dielectric fin, a first plurality of semiconductor nanostructures, a second plurality of semiconductor nanostructures, a third plurality of semiconductor nanostructures, a first dielectric structure, a second dielectric structure, a first conductive gate structure, a second conductive gate structure, and a third conductive gate structure. A first opening is formed in the first dielectric layer, wherein the first opening at least partially overlaps with the first dielectric structure, the second dielectric structure, and the second conductive gate structure. The second conductive gate structure is removed. A portion of the first dielectric structure under the first opening is removed to form a third dielectric structure directly on the first dielectric fin. A portion of the second dielectric structure under the first opening is removed to form a fourth dielectric structure directly on the second dielectric fin. The second plurality of semiconductor nanostructures are removed to form a second opening under the first opening. A second dielectric layer is formed in the first opening and the second opening, and at least partially covers the third dielectric structure and the fourth dielectric structure.

A-A, B-B: section line

D ₁ : First distance

D ₂ : Second distance

H ₁ : First height

H ₂ : Second height

H ₃ : The third height

H ₄ : Fourth height

H ₅ : Fifth height

H ₆ : Sixth height

W ₁ : First width

W ₂ : Second width

102: Base semiconductor structure

104: Stacking of semiconductor layers

106: First semiconductor layer

108: Second semiconductor layer

110: Hard mask layer

202: First hard mask structure

204: The first stack of semiconductor structures

206: First semiconductor structure

208: Second semiconductor structure

210: Fins

210a: First fin

210b: Second fin

210c: Third fin

210d: Fourth fin

210e: Fifth fin

210f: Sixth fin

212: Substrate

214: First groove

302: Pad layer

304: First dielectric layer

402: Isolation structure

404: Cover structure

406: Second groove

502: Dielectric fins

502a: first dielectric fin

502b: Second dielectric fin

502c: Third dielectric fin

502d: Fourth dielectric fin

502e: Fifth dielectric fin

504: Dielectric tape

602: Virtual gate structure

604: Virtual gate dielectric structure

606: Virtual gate material structure

608: Second hard mask structure

610: The third hard mask structure

612: Fourth hard mask structure

702: First side wall spacer

704: The first plurality of dielectric structures

704a: first dielectric structure

704b: Second dielectric structure

704b/704d: Retained dielectric structure

704c: The third dielectric structure

704d: Fourth dielectric structure

704e: Fifth dielectric structure

705: Second stack of semiconductor structures

706: The third semiconductor structure

708: Fourth semiconductor structure

802: Second side wall spacer

902: First source/drain region

902a: The first pair

902b: Second pair

902c: The fifth pair

902d: The sixth pair

904: Second source/drain region

904a: The third pair

904b: The fourth pair

1002: First etching stop layer

1004: Interlayer dielectric layer

1102: The third groove

1104: First mask structure

1106: Fifth hard mask structure

1302: Nanostructure stacking

1302a: First nanostructure stacking

1302b: Second nanostructure stacking

1302c: The third nanostructure stack

1302d: The fourth nanostructure stack

1302e: The fifth nanostructure stack

1302f: The sixth nanostructure stack

1304:Nanostructure

1402: Interface layer

1404: Gate dielectric layer

1406: Gate layer

1502: Gate structure

1502a: First gate structure

1502b: Second gate structure

1502c: Third gate structure

1504: Second etch stop layer

1506: Fourth dielectric layer

1602: First opening

1604: Second mask structure

1801: Second opening

1802: Recessed dielectric fins

1804a: First recessed semiconductor fin

1804b: Second recessed semiconductor fin

1806: Second dielectric structure

1806a: Sixth dielectric structure

1806b: The seventh dielectric structure

1808: Gate dielectric structure

1808a: First gate dielectric structure

1808b: Second gate dielectric structure

1810:Nanostructure Field Effect Transistor

1810a: The first nanostructured field effect transistor

1810b: The second nanostructure field effect transistor

1902: Fifth dielectric layer

1904: Semiconductor devices

2002: First medial sidewall

2004: Second medial sidewall

2102: Vertical section

2102a: First vertical section

2102b: Second vertical section

2104: Horizontal part

2104a: First horizontal part

2104b: Second horizontal part

2106: Region

2202: The first peripheral part

2204: Second peripheral part

2208: First upper surface

2210: Second upper surface

2300: Flowchart

2302,2304,2306,2308,2310,2312,2314,2316: Steps

Figures 1 to 19 are various diagrams of methods used to form a semiconductor device with reduced spacing between nanostructured field effect transistors in some embodiments.

Figures 20A to 20C are various diagrams of semiconductor devices with reduced spacing between nanostructured field effect transistors in some embodiments.

FIG. 21 is a cross-sectional view of the semiconductor device of FIGS. 20A to 20C along the section line B-B of FIG. 20A in some embodiments.

FIG. 22 is a perspective view of a region of a semiconductor device in some embodiments.

FIG. 23 is a flow chart of a method for forming a semiconductor device with reduced spacing between nanostructured field effect transistors in some embodiments.

The following content refers to the drawings to illustrate the embodiments of the present invention. Similar labels are used to mark similar units, and the structures shown in the drawings are not necessarily drawn to scale. It should be understood that the detailed description and the corresponding drawings do not limit the scope of the embodiments of the present invention, and the detailed description and drawings only provide some examples to illustrate some ways to implement the concepts of the present invention.

The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of specific components and configurations are used to simplify the content of the present invention but are not intended to limit the present invention. For example, the description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are separated by other additional components but not in direct contact. In addition, multiple embodiments of the present invention may repeatedly use the same number for simplicity, but components with the same number in multiple embodiments and/or configurations do not necessarily have the same corresponding relationship.

In addition, spatially relative terms such as "below", "beneath", "below", "above", "above", or similar terms can be used to simplify the relative relationship of one component to another component in the diagram. Spatially relative terms can be extended to components used in other orientations, not limited to the orientation of the diagram. Components can also be rotated 90° or other angles, so directional terms are only used to describe the orientation in the diagram.

In some embodiments, a semiconductor device (such as an integrated circuit) may include a first nanostructure field effect transistor (such as a fully wound field effect transistor), and a second nanostructure field effect transistor laterally separated from the first nanostructure field effect transistor. The first nanostructure field effect transistor includes a first metal gate extending around a first plurality of nanostructures and extending laterally between a pair of first source/drain regions. The second nanostructure field effect transistor includes a second metal gate extending around a second plurality of nanostructures and extending laterally between a pair of second source/drain regions.

Generally, the method of forming the semiconductor device includes forming a metal layer that extends continuously over the first plurality of nanostructures and the second plurality of nanostructures. The metal layer may then be selectively etched to form separate metal gates, thereby forming a first metal gate and a second metal gate. The step of selectively etching the metal layer removes a portion of the metal layer between the first metal gate and the second metal gate, thereby forming an opening laterally located between the first metal gate and the second metal gate. A dielectric layer is then deposited in the opening. The dielectric layer is provided to improve the device performance of the semiconductor device (e.g., to reduce the leakage current between the first nanostructure field effect transistor and the second nanostructure field effect transistor) and/or to reduce the manufacturing cost (e.g., a self-aligned contact process can be used later).

One of the challenges of the above methods is that as the minimum structure size continues to shrink (e.g., to the 3 nm technology node or below), the above methods do not provide sufficient control to reliably pattern separate metal gates. For example, as the spacing between a first nanostructure field effect transistor and a second nanostructure field effect transistor shrinks (e.g., the lateral spacing between the first plurality of nanostructures and the second plurality of nanostructures decreases to less than 40 nm), the above methods are insufficient to ensure that portions of the metal layer are selectively etched to remove only predefined portions of the metal layer. Poor overlay control of multiple patterning processes may cause the step of selectively etching the metal layer to unintentionally remove portions of the metal layer other than the predefined removal. In other words, the above methods may unintentionally remove other portions of the metal layer. Since the above method unintentionally removes part of the metal layer, as the minimum structure size continues to shrink, the above method may cause electrical short circuits (such as electrical short circuits between the first metal gate and the second metal gate), adversely affect device performance (due to unintentional reduction of the size of the first metal gate and the second metal gate), or similar problems, thereby reducing production capacity.

Various embodiments of the present invention relate to methods for forming a semiconductor device (e.g., an integrated circuit) with reduced spacing between nanostructured field effect transistors. The method includes forming a first dielectric structure on a first dielectric fin and forming a second dielectric structure on a second dielectric fin. The first dielectric structure and the first dielectric fin laterally separate a first conductive structure from a second conductive structure. The second dielectric structure and the second dielectric fin laterally separate the second conductive structure from a third conductive structure. The first conductive structure extends around a first plurality of semiconductor nanostructures, the second conductive structure extends around a second plurality of semiconductor nanostructures, and the third conductive structure extends around a third plurality of semiconductor nanostructures. The second conductive structure is located between the first conductive structure and the third conductive structure, and is laterally separated from the first conductive structure and the third conductive structure.

A first dielectric layer is formed on the first dielectric fin, the second dielectric fin, the first plurality of semiconductor nanostructures, the second plurality of semiconductor nanostructures, the third plurality of semiconductor nanostructures, the first dielectric structure, the second dielectric structure, the first conductive structure, the second conductive structure, and the third conductive structure. The first dielectric layer is then selectively etched to form a first opening in the first dielectric layer, which at least partially covers the second conductive structure, the first dielectric structure, and the second dielectric structure. A first etching process is then performed through the first opening to remove the second conductive structure. A second etching process is then performed through the first opening to remove the second plurality of semiconductor nanostructures to form a second opening below the first opening. In addition, the second etching process removes a portion of the first dielectric structure to form a third dielectric structure on the first dielectric fin, and removes a portion of the second dielectric structure to form a fourth dielectric structure on the second dielectric fin. Then, a second dielectric layer is formed in the first opening and the second opening, and partially covers the third dielectric structure and the fourth dielectric structure. Since the first dielectric structure is formed on the first dielectric fin and the second dielectric structure is formed on the second dielectric fin, the etching process tolerance for forming the first opening can be increased. For example, the first dielectric structure and the second dielectric structure may form a first opening of greater width (due to resolution limitations in lithography) and/or laterally offset the first opening from a predefined position (due to poor overlay control), but still ensure that the first opening only covers the desired structure (such as the second conductive structure).

In addition, when removing the second conductive structure, the first dielectric structure and the second dielectric structure can serve as a barrier so that the first etching process can selectively remove the second conductive structure. For example, since the first dielectric structure separates the first conductive structure from the second conductive structure laterally, and the second dielectric structure separates the second conductive structure from the third conductive structure laterally, the first dielectric structure and the second dielectric structure serve as a barrier to prevent the first etching process from unintentionally removing a portion of the first conductive structure and/or a portion of the second conductive structure.

In addition, since the second etching process removes a portion of the first dielectric structure (e.g., to form the third dielectric structure) and removes a portion of the second dielectric structure (e.g., to form the fourth dielectric structure), the second dielectric layer can be formed in a self-aligned manner. For example, after the second etching process, the third dielectric structure can be located on the third fin, and the fourth dielectric structure can be located on the fourth fin. Therefore, when the second dielectric layer is formed, the second dielectric layer can be self-aligned to the sidewalls of the third dielectric structure and the fourth dielectric structure. In summary, as the structure size continues to shrink, the method can form a semiconductor device with a reduced space between nanostructure field effect transistors (the lateral space between the first plurality of nanostructures and the third plurality of nanostructures is less than 40nm), thereby increasing production capacity, improving device performance, and avoiding electrical short circuits, etc.

FIGS. 1-19 are various diagrams of methods of forming a semiconductor device 1904 with reduced spacing between nanostructured field effect transistors 1810 in some embodiments. FIGS. 1-11 are a series of perspective views showing various stages of a method of forming a semiconductor device 1904 with reduced spacing between nanostructured field effect transistors 1810. FIGS. 12-19 are a series of cross-sectional views showing various stages of a method of forming a semiconductor device 1904 with reduced spacing between nanostructured field effect transistors 1810. The cross-sectional views of FIGS. 12-19 are along the section line A-A of FIG. 11 and continue from the stage shown in FIG. 11. For example, FIG. 12 shows a first stage after the stage shown in FIG. 11 and along the section line A-A of FIG. 11. FIG. 13 shows the second stage after the first stage shown in FIG. 12 and along the section line A-A of FIG. 11. FIG. 14 shows the third stage after the second stage shown in FIG. 13 and along the section line A-A of FIG. 11, and so on.

As shown in FIG. 1 , a base semiconductor structure 102 is provided. The base semiconductor structure 102 includes any type of semiconductor body (such as single crystal silicon, complementary metal oxide semiconductor substrate, silicon germanium, silicon on an insulating layer, or the like), which may be doped (such as doped with n-type or p-type doping) or undoped. The base semiconductor structure 102 may be a semiconductor wafer (such as a disk-shaped silicon wafer) or a portion of a semiconductor wafer.

As shown in FIG. 1 , a stack of semiconductor layers 104 is formed on a base semiconductor structure 102. The stack of semiconductor layers 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The stack of semiconductor layers 104 may include any number of first semiconductor layers 106 and any number of second semiconductor layers 108.

The first semiconductor layer 106 may be or include a first semiconductor material such as silicon, silicon germanium, germanium, gallium arsenide, indium arsenide, indium phosphide, or the like. The second semiconductor layer 108 may be or include a second semiconductor material such as silicon, silicon germanium, germanium, gallium arsenide, indium arsenide, indium phosphide, or the like, and the second semiconductor material is different from the first semiconductor material. For example, the first semiconductor material is silicon germanium and the second semiconductor material is silicon. In these embodiments, the stack of semiconductor layers 104 includes alternating silicon germanium layers and silicon layers. The first semiconductor layer 106 may or may not be doped, depending on the design of the semiconductor device 1904. The second semiconductor layer 108 may or may not be doped, depending on the design of the semiconductor device 1904. The first semiconductor material may be different from the semiconductor material of the base semiconductor structure 102. For example, the semiconductor material of the base semiconductor structure 102 may be silicon, and the first semiconductor material may be silicon germanium.

In some embodiments, the formation process of the stack of semiconductor layers 104 includes epitaxially forming a first semiconductor layer 106 and a second semiconductor layer 108. For example, the method of growing the first of the first semiconductor layers 106 on the base semiconductor structure 102 can be a first epitaxial process, such as vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, some other epitaxial process, or a combination thereof. Thereafter, the first of the second semiconductor layers 108 is grown on the first of the first semiconductor layers 106, and the growth method can be a second epitaxial process such as vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, some other epitaxial process, or a combination thereof. The first epitaxial process and the second epitaxial process are repeated in an alternating manner until the semiconductor layer stack 104 has a predetermined number of first semiconductor layers 106 and a predetermined number of second semiconductor layers 108. In some embodiments, after the semiconductor layer stack 104 is formed, a planarization process such as chemical mechanical polishing, an etching back process, or a similar process may be performed to planarize the upper surface of the uppermost semiconductor layer of the semiconductor layer stack 104 (such as the uppermost first semiconductor layer 106).

In some embodiments, the first epitaxial process and the second epitaxial process may be performed in the same process chamber (e.g., an epitaxial growth chamber). In these embodiments, a first set of precursors used to grow the first semiconductor layer 106 and a second set of precursors used to grow the second semiconductor layer 108 may be circulated and pumped into the process chamber. The first set of precursors includes precursors used to form a first semiconductor material (e.g., silicon germanium), and the second set of precursors includes precursors used to form a second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., gerane), and the second set of precursors includes a silicon precursor without a germanium precursor. Therefore, a silicon precursor may be flowed into the process chamber, and then the following steps may be performed periodically: (1) the germanium precursor is allowed to flow into the process chamber when the first semiconductor layer 106 is grown; and (2) the germanium precursor is prohibited from flowing into the process chamber when the second semiconductor layer 108 is grown. It should be understood that in some embodiments, one or more purge steps may be performed when forming the stack of semiconductor layers 104 (e.g., purging the process chamber between the growth of the first semiconductor layer 106 and the second semiconductor layer 108).

As shown in FIG. 1 , a hard mask layer 110 is formed on the semiconductor layer stack 104. The hard mask layer 110 covers the semiconductor layer stack 104. For example, the hard mask layer 110 may be or include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), some other hard mask material, or a combination thereof. In some embodiments, one of the processes for forming the hard mask layer 110 includes depositing or growing the hard mask layer 110 on the upper surface of the semiconductor layer stack 104. The deposition or growth method of the hard mask layer 110 may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, some other deposition or growth process, or a combination thereof. In other embodiments, the hard mask layer 110 may include multiple layers. For example, the hard mask layer 110 may include an oxide layer (such as silicon oxide) and a nitride layer (such as silicon nitride) on the oxide layer.

As shown in FIG2 , a first hard mask structure 202, a first stack 204 of multiple semiconductor structures, a first semiconductor structure 206, a second semiconductor structure 208, and a semiconductor fin 210 are formed. For the sake of clarity, only some of the first stacks 204, the first semiconductor structure 206, the second semiconductor structure 208, and the semiconductor fin 210 are specifically marked. As shown in FIG2 , the base semiconductor structure 102 is recessed to form a semiconductor substrate 212. The semiconductor substrate 212 can be regarded as a substrate later.

The semiconductor fins 210 protrude vertically from the substrate 212. The semiconductor fins 210 are separated laterally (along the z-axis). For example, the first body fin 210a, the second fin 210b, the third fin 210c, the fourth fin 210d, the fifth fin 210e, and the sixth fin 210f are separated laterally (along the z-axis) from each other. The semiconductor fins 210 extend laterally (along the x-axis) on the substrate 212 and are parallel to each other.

The first stacks 204 of semiconductor structures respectively cover the fins 210 of the semiconductor. The first stacks 204 of semiconductor structures are separated laterally (along the z-axis). The first stacks 204 of semiconductor structures extend laterally (along the x-axis) on the fins 210 of the semiconductor and are parallel to each other. Each of the first stacks 204 of semiconductor structures may include staggered first semiconductor structures 206 and second semiconductor structures 208. The first hard mask structure 202 covers the first stacks 204 of semiconductor structures.

In some embodiments, the process of forming the first hard mask structure 202 includes forming a first patterned mask layer (not shown, such as positive photoresist and/or negative photoresist) on the hard mask layer 110. The first patterned mask layer may be formed by forming a mask layer (not shown) on the hard mask layer 110, developing the mask layer to a pattern (such as by a lithography process such as photolithography, extreme ultraviolet lithography, or the like), and developing the mask layer to form the first patterned mask layer. The first patterned mask layer may then be used and a first etching process may be performed on the hard mask layer 110 to remove the unmasked portion of the hard mask layer 110. The masked portion of the hard mask layer 110 is then retained as the first mask structure 202. The first etching process may be a dry etching process, a wet etching process, a reactive ion etching process, some other etching process, or a combination thereof. The first patterned mask layer may then be stripped off.

Then, the first hard mask structure 202 is used as an etching mask, and the first stack 204 of the semiconductor structure, the first semiconductor structure 206, the second semiconductor structure 208, the semiconductor fin 210, and the substrate 212 are etched. With the first hard mask structure 202, a second etching process can be performed on the semiconductor layer stack 104 and the base semiconductor structure (see FIG. 1). The second etching process can remove the unmasked portion of the semiconductor layer stack 104 to retain the masked portion of the semiconductor layer as the first stack 204 of the semiconductor structure. In other words, the second etching process removes the unmasked portions of the first semiconductor layer 106 and the second semiconductor layer 108 to retain the masked portion of the first semiconductor layer 106 as the first semiconductor structure 206, and retain the masked portion of the second semiconductor layer 108 as the second semiconductor structure 208. The second etching process can also recess the unmasked portion of the base semiconductor structure 102 to retain a portion of the base semiconductor structure 102 (such as the masked portion and the recessed portion) as the substrate 212 and the semiconductor fin 210. The second etching process can be a dry etching process, a wet etching process, a reactive ion etching process, some other etching process, or a combination thereof.

In addition, the process of forming the first hard mask structure 202, the first stack of semiconductor structures 204, the first semiconductor structure 206, the second semiconductor structure 208, the semiconductor fin 210, and the substrate 212 can form first trenches 214 on the substrate 212. For the sake of clarity of the figure, only some of the first trenches 214 are specifically marked. The first trenches 214 are separated laterally (along the z-axis). The semiconductor fin 210 can separate the first trenches 214 laterally (along the z-axis). In other words, the first trenches 214 are located on both sides of the semiconductor fin 210. The first trenches 214 extend laterally (along the x-axis) on the substrate 212 and are parallel to each other.

It should be understood that the first hard mask structure 202, the first stack of semiconductor structures 204, the first semiconductor structure 206, the second semiconductor structure 208, the semiconductor fin 210, and the substrate 212 may be formed by any suitable method. For example, the first hard mask structure 202, the first stack of semiconductor structures 204, the first semiconductor structure 206, the second semiconductor structure 208, the semiconductor fin 210, and the substrate 212 may be formed by one or more photolithography processes, such as a double patterning process, a multi-patterning process, or the like. The semiconductor fin 210 may then be considered a fin.

As shown in FIG3 , the liner layer 302 is formed along the sidewalls of the first trench 214 and the lower surface (see FIG2 ) of the first trench 214. In other words, the liner layer 302 may be formed along the sidewalls of the fins 210, the upper surface of the substrate 212 (e.g., the upper surface between the fins 210), the sidewalls of the first stack 204 of semiconductor structures, and the sidewalls of the first hard mask structure 202. In one embodiment, the liner layer 302 may be formed on the upper surface of the first hard mask structure 202. In other embodiments, the formation process of the liner layer 302 includes growing or depositing the liner layer 302, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, epitaxial process, some other deposition or growth process, or a combination thereof.

The liner layer 302 may be or include a semiconductor material (such as silicon, silicon germanium, or the like). In some embodiments, the semiconductor material of the liner layer 302 may be the same as the semiconductor material of the fin 210 (such as the semiconductor material of the base semiconductor structure 102). In other embodiments, the semiconductor material of the liner layer 302 may be the same as the semiconductor material of the first semiconductor structure 206 (such as the first semiconductor material). In other embodiments, the liner layer 302 is a compliant layer.

As shown in FIG3 , a first dielectric layer 304 is formed on the substrate 212, the first hard mask structure 202, and the liner layer 302. The first dielectric layer 304 is formed after the liner layer 302 is formed. The first dielectric layer 304 is formed to fill the first trench 214 (see FIG2 ). The first dielectric layer 304 may have a planarized upper surface. For example, the first dielectric layer 304 may be or include a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), silicon carbonitride, silicon carbonitride, a metal oxide (such as aluminum oxide, yttrium oxide, zirconium oxide, or yttrium oxide), some other dielectric material, or a combination thereof. In some embodiments, the more specific first dielectric layer 304 is a carbon nitride silicon oxide having a first carbon nitride silicon oxide composition. In other embodiments, the process of forming the first dielectric layer 304 includes depositing the first dielectric layer 304 in the first trench 214, on the liner layer 302, and on the first hard mask structure 202, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof.

As shown in FIG. 4 , isolation structures 402 are formed on substrate 212 and between fins 210. For clarity of the drawing, only some of the isolation structures 402 are specifically labeled. The isolation structures 402 can be considered as shallow trench isolation structures. The isolation structures 402 are separated laterally (along the z-axis). The fins 210 separate the isolation structures 402 laterally (along the z-axis). In some embodiments, the isolation structures 402 extend laterally (along the x-axis) on substrate 212 and are parallel to each other. In other embodiments, the isolation structure 402 may be part of one or more continuous isolation structures that laterally surround one or more fins 210 (e.g., some portions of the larger shallow trench isolation structure extend laterally along the x-axis, while some other portions extend laterally along the z-axis, so that the larger shallow trench isolation structure laterally surrounds one or more fins 210).

The upper surface of the isolation structure 402 may be substantially flat. In other embodiments, the isolation structure 402 may have a convex or concave upper surface. The upper surface of the isolation structure 402 is substantially aligned with (e.g., flush with) the upper surface of the fin 210. In other embodiments, the upper surface of the isolation structure 402 may be higher or lower than the upper surface of the fin 210.

In some embodiments, the process of forming the isolation structure 402 includes recessing the first dielectric layer 304 (see FIG. 3 ). The method of recessing the first dielectric layer 304 may be to perform a third etching process on the first dielectric layer 304. Therefore, the third etching process recesses the first dielectric layer 304 to a predetermined height to retain a lower portion of the first dielectric layer 304 as the isolation structure 402. In some embodiments, the third etching process also removes an upper portion of the liner layer 302 to retain the lower portion of the liner layer 302 along the sidewall of the fin 210 and the upper surface of the substrate 212, as shown in FIG. 4 . In other embodiments, the third etching process has a greater selectivity to the first dielectric layer 304 than to the liner layer 302, so as to retain the liner layer 302 along the sidewalls of the first stack 204 of the semiconductor structure, the sidewalls of the first hard mask structure 202, and the upper surface of the first hard mask structure 202. For example, the third etching process can be a dry etching process, a wet etching process, some other etching process, or a combination thereof. In some embodiments, the third etching process can be regarded as the first etching process.

As shown in FIG. 4 , the capping structures 404 are formed on the first stack 204 of semiconductor structures. The capping structures 404 are also formed on the isolation structure 402, the liner layer 302, and the first hard mask structure 202. For the sake of clarity, only some of the capping structures 404 are specifically marked. The capping structure 404 may be or include a semiconductor material such as silicon, silicon germanium, or the like. In some embodiments, the semiconductor material of the capping structure 404 is the same as the semiconductor material of the first semiconductor structure 206 (such as the first semiconductor material). For example, the capping structure 404 is silicon germanium, and the first semiconductor structure 206 is silicon germanium.

In some embodiments, the process of forming the cap structure 404 includes growing or depositing the cap structure 404 on the first stack 204 of the semiconductor structure and the first hard mask structure 202. For example, the growth or deposition method of the cap structure 404 can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, epitaxial process, some other deposition or growth process, or a combination thereof. In other embodiments, the cap structure 404 is selectively grown from the exposed surface of the liner layer 302 (for example, by an epitaxial process), so that the upper surface of the isolation structure 402 does not contain the cap structure 404.

In addition, the process of forming the isolation structure 402 and the cover structure 404 also forms second trenches 406 on the substrate 212. The second trenches 406 are also formed on the isolation structure 402. For the sake of clarity, only some of the second trenches 406 are specifically marked. The second trenches 406 are separated laterally (along the z-axis). The cover structure 404 separates the second trenches 406 laterally (along the z-axis). In other words, the second trenches 406 are located on both sides of the cover structure 404 and the isolation structure 402. The second trenches 406 extend laterally (along the x-axis) on the isolation structure 402 and are parallel to each other.

As shown in FIG. 5 , dielectric fins 502 are formed on substrate 212 and fins 210. Dielectric fins 502 are formed on (e.g., directly on) isolation structures 402. Dielectric fins 502 are separated laterally (along the z-axis). For example, first dielectric fin 502a, second dielectric fin 502b, third dielectric fin 502c, fourth dielectric fin 502d, and fifth dielectric fin 502e are separated laterally (along the z-axis) from each other. Cover structure 404 separates dielectric fins 502 laterally (along the z-axis). In other words, the dielectric fins 502 are located on both sides of the cap structure 404 and on the isolation structure 402. The dielectric fins 502 extend laterally (along the x-axis) on the isolation structure 402 and are parallel to each other.

The upper surface of the dielectric fin 502 is lower than the upper surface of the first stack of semiconductor structures 204. Specifically, the upper surface of the dielectric fin 502 is lower than the upper surface of the uppermost semiconductor structure of the first stack of semiconductor structures 204 (e.g., the upper surface of the uppermost first semiconductor structure 206 of the first stack of semiconductor structures 204). In some embodiments, the upper surface of the dielectric fin 502 is substantially aligned with the upper surface of the uppermost second semiconductor structure 208 of the first stack of semiconductor structures 204. In other embodiments, the upper surface of the dielectric fin 502 is lower than or higher than the upper surface of the uppermost second semiconductor structure 208 of the first stack of semiconductor structures 204. In other embodiments, the upper surface of the dielectric fin 502 may be substantially flat. In other embodiments, the upper surface of the dielectric fin 502 may be convex or concave.

For example, dielectric fin 502 may be or include a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), a silicon carbonitride, a silicon carbonitride oxide, a metal oxide (such as aluminum oxide, yttrium oxide, zirconium oxide, or yttrium oxide), some other dielectric material, or a combination thereof. In some embodiments, more specifically dielectric fin 502 is a silicon carbonitride oxide having a second silicon carbonitride oxide composition. In some embodiments, the second silicon carbonitride oxide composition is different from the first silicon carbonitride oxide composition.

In some embodiments, the process of forming the dielectric fin 502 includes forming a second dielectric layer (not shown) on the substrate 212, the isolation structure 402, the liner layer 302, the capping structure 404, and the first hard mask structure 202.

A second dielectric layer is formed to fill the second trench 406 (see FIG. 4 ). The second dielectric layer may have a flat upper surface. For example, the second dielectric layer may be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), a carbon nitride silicon oxide, some other dielectric material, or a combination thereof. In some embodiments, the second dielectric layer is a carbon nitride silicon oxide having a second carbon nitride silicon oxide composition. In some embodiments, the process of forming the second dielectric layer includes depositing the second dielectric layer in the second trench 406, on the isolation structure 402, and on the cap structure 404, and the formation method thereof may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof.

The second dielectric layer is then recessed to a predetermined height. The second dielectric layer may be recessed by a fourth etching process. The selectivity of the fourth etching process to the second dielectric layer is greater than the selectivity to other structures under the second dielectric layer (such as the cap structure 404 and the first hard mask structure 202). Therefore, the fourth etching process may recess the second dielectric layer to a predetermined height to retain the lower portion of the second dielectric layer as a dielectric fin 502. For example, the fourth etching process may be a dry etching process, a wet etching process, some other etching process, or a combination thereof. In some embodiments, the fourth etching process may be regarded as a second re-etching process.

As shown in FIG. 5 , dielectric tapes 504 are formed on substrate 212. Dielectric tapes 504 are also formed on (e.g., directly on) dielectric fins 502. For clarity of the drawing, only some dielectric tapes 504 are specifically labeled. Dielectric tapes 504 are separated laterally (along the z-axis). Cover structure 404 separates dielectric tapes 504 laterally (along the z-axis). In other words, dielectric tapes 504 are located on both sides of cover structure 404 and on dielectric fins 502. Dielectric tapes 504 extend laterally (along the x-axis) on dielectric fins 502 and are parallel to each other.

The dielectric tape 504 extends vertically (along the y-axis) from the upper surface of the dielectric fin 502. In other words, the dielectric tape 504 contacts the upper surface of the dielectric fin 502 and extends vertically from the upper surface of the dielectric fin 502 to the upper surface of the dielectric tape 504. The upper surface of the dielectric tape 504 is substantially flat. The upper surface of the dielectric tape 504 is substantially aligned with the upper surface of the cover structure 404 and the upper surface of the first hard mask structure 202.

For example, dielectric tape 504 may be or include an oxide (e.g., silicon oxide), a high dielectric constant dielectric layer (e.g., bismuth oxide, zirconium oxide, bismuth aluminum oxide, bismuth silicate, or some other dielectric material with a dielectric constant greater than 3.9), silicon carbonitride, a metal oxide (e.g., aluminum oxide, bismuth oxide, zirconia, or yttrium oxide), some other dielectric material, or a combination thereof. Dielectric tape 504 and dielectric fin 502 include different dielectric materials. For example, dielectric tape 504 is bismuth oxide, and dielectric fin 502 is silicon oxycarbonitride. In some embodiments, since the dielectric fin 502 includes a first dielectric material (such as silicon oxycarbon nitride) and the dielectric tape 504 includes a second dielectric material (such as bismuth oxide) different from the first dielectric material, the dielectric fin 502 and the corresponding dielectric tape 504 can be considered as a hybrid fin. For example, the first of the hybrid fins includes a first of the dielectric fin 502 and a first of the dielectric tape 504 located on the first of the dielectric fin 502.

In some embodiments, the process of forming the dielectric tape 504 includes forming a third dielectric layer (not shown) on the substrate 212, the dielectric fin 502, the capping structure 404, and the first hard mask structure 202. For example, the third dielectric layer can be or include an oxide (such as silicon oxide), a high dielectric constant dielectric layer (such as bismuth oxide, zirconia, bismuth aluminate, bismuth silicate, or some other dielectric material with a dielectric constant greater than 3.9), silicon carbonitride, a metal oxide (such as aluminum oxide, bismuth oxide, zirconia, or yttrium oxide), some other dielectric material, or a combination thereof. The third dielectric layer and the second dielectric layer include different dielectric materials. For example, the third dielectric layer is bismuth oxide, and the second dielectric layer is silicon oxycarbonitride. In some embodiments, the method of forming the third dielectric layer includes depositing the third dielectric layer on the dielectric fin 502, the cap structure 404, and the first hard mask structure 202, and the formation method thereof can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof.

A planarization process may then be performed on the third dielectric layer. The planarization process removes the upper portion of the third dielectric layer, thereby retaining the lower portion of the third dielectric layer to serve as the dielectric tape 504, respectively. A planarization process is also performed on the first hard mask structure 202 and the cap structure 404. Therefore, the planarization process removes the upper portion of the first hard mask structure 202 and the cap structure 404, so that the upper surface of the dielectric tape 504, the upper surface of the first hard mask structure 202, and the upper surface of the cap structure 404 are coplanar.

6 , a dummy gate structure 602 is formed on the substrate 212, the fin 210, the first stack of semiconductor structures 204, the isolation structure 402, the liner layer 302, the capping structure 404, the dielectric fin 502, the dielectric tape 504, and the first hard mask structure 202. In some embodiments, the dummy gate structure 602 includes a dummy gate dielectric structure 604 and a dummy gate material structure 606. The dummy gate material structure 606 covers the dummy gate dielectric structure 604. In order to make the diagram clear, only some dummy gate structures 602, dummy gate dielectric structures 604, and dummy gate material structures 606 are specifically marked.

The dummy gate structure 602 is laterally separated (along the x-axis). The dummy gate structure 602 extends laterally (along the z-axis) over the substrate 212, the fin 210, the first stack of semiconductor structures 204, the isolation structure 402, the liner layer 302, the capping structure 404, the dielectric fin 502, the dielectric tape 504, and the first hard mask structure 202. For example, the dummy gate material structure 606 may be or include polysilicon, but the dummy gate material structure 606 may be or include other materials. For example, the virtual gate dielectric structure 604 may be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), some other dielectric material, or a combination thereof.

In some embodiments, the process of forming the dummy gate structure 602 includes depositing a dummy gate dielectric layer (not shown) on the substrate 212, the fin 210, the first stack of semiconductor structures 204, the isolation structure 402, the liner layer 302, the capping structure 404, the dielectric fin 502, the dielectric tape 504, and the first hard mask structure 202. The dummy gate dielectric layer can be deposited as a compliant layer. For example, the dummy gate dielectric layer can be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), some other dielectric material, or a combination thereof. In some embodiments, the deposition method of the dummy gate dielectric layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof.

A dummy gate material (not shown) is then deposited on and covers the dummy gate dielectric layer. For example, the dummy gate dielectric material may be or include polysilicon, but the dummy gate dielectric material may be or include other materials. For example, the deposition method of the dummy gate material may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof.

A first hard mask layer (not shown) is then deposited or grown on the dummy gate material to cover the dummy gate material. For example, the first hard mask layer may be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), some other hard mask material, or a combination thereof. For example, the deposition or growth method of the first hard mask layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, some other deposition or growth process, or a combination thereof.

A second hard mask layer (not shown) is then deposited on the first hard mask layer and covers the first hard mask layer. For example, the second hard mask layer may be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), some other hard mask material, or a combination thereof. The second hard mask layer and the first hard mask layer may include different hard mask materials. For example, the first hard mask may be silicon oxide, and the second hard mask may be silicon nitride. The deposition or growth method of the second hard mask layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof.

A second patterned mask layer (not shown, such as positive photoresist and/or negative photoresist) is then formed on the second hard mask layer. In the presence of the second patterned mask layer, a fifth etching process is performed to remove the unmasked portion of the second hard mask layer to retain the masked portion of the second hard mask layer as a second hard mask structure 608. In a state where the second hard mask structure 608 is located on the first hard mask layer, a sixth etching process is then performed to remove the unmasked portion of the first hard mask layer to retain the masked portion of the first hard mask layer as a third hard mask structure 610. The second hard mask structure 608 and the third hard mask structure 610 can be collectively regarded as a fourth hard mask structure 612. For example, the fifth etching process may be a dry etching process, a wet etching process, a reactive ion etching process, some other etching process, or a combination thereof. For example, the sixth etching process may be a dry etching process, a wet etching process, a reactive ion etching process, some other etching process, or a combination thereof.

Then, with the fourth hard mask structure 612 located on the dummy gate material layer and the dummy gate dielectric layer, a seventh etching process is performed on the dummy gate material layer and the dummy gate dielectric layer to form the dummy gate structure 602. The seventh etching process removes the unmasked portion of the dummy gate material layer to retain the masked portion of the dummy gate material layer as the dummy gate material structure 606. The seventh etching process also removes the unmasked portion of the dummy gate dielectric layer to retain the masked portion of the dummy gate dielectric layer as the dummy gate dielectric structure 604. Thus, the dummy gate structure 602 is formed. For example, the seventh etching process can be a dry etching process, a wet etching process, a reactive ion etching process, some other etching process, or a combination thereof.

As shown in FIG. 7 , first sidewall spacers 702 are formed along the sidewalls of the dummy gate material structure 606. In some embodiments, first sidewall spacers 702 are also formed along the sidewalls of the fourth hard mask structure 612. For clarity of the drawings, only some first sidewall spacers 702 are specifically marked.

In some embodiments, the process of forming the first sidewall spacer 702 includes depositing a first spacer layer on the structure shown in Figure 6. The first spacer layer can be conformally deposited on the structure shown in Figure 6. For example, the first spacer layer can be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), some other hard mask material, or a combination thereof. An eighth etching process may then be performed on the first spacer layer to remove horizontal portions of the first spacer layer (e.g., portions on the fourth hard mask structure 612, the first hard mask structure 202, the capping structure 404, and the dielectric tape 504) to retain vertical portions of the first spacer layer as first sidewall spacers 702 (e.g., portions along the sidewalls of the dummy gate dielectric structure 604, the dummy gate material structure 606, the third hard mask structure 610, and the second hard mask structure 608). For example, the eighth etching process may be a dry etching process, a wet etching process, a reactive ion etching process, some other etching process, or a combination thereof.

As shown in FIG. 7 , a portion of the first hard mask structure 202, a portion of the first stack 204 of the semiconductor structure, a portion of the cap structure 404, and a portion of the dielectric tape 504 outside the boundary of the first sidewall spacer 702 (e.g., outside the outer sidewall of the first sidewall spacer 702) are removed (see FIG. 6 ). In some embodiments, the process of removing a portion of the first hard mask structure 202, a portion of the first stack 204 of the semiconductor structure, a portion of the cap structure 404, and a portion of the dielectric tape 504 outside the boundary of the first sidewall spacer 702 includes performing a ninth etching process on the first hard mask structure 202, the first stack 204 of the semiconductor structure, the cap structure 404, and the dielectric tape 504.

The ninth etching process may be anisotropic etching. For example, the ninth etching process may be a dry etching process, reactive ion etching, some other etching process, or a combination thereof. The etchant used in the ninth etching process is selective to the first hard mask structure 202, the first semiconductor structure 206, the second semiconductor structure 208, the cap structure 404, and the dielectric tape 504 (for example, the etching rate of these materials is higher than the etching rate of the dielectric fin 502 and/or the isolation structure 402).

During the ninth etching process, the dummy gate structure 602, the fourth hard mask structure 612, and the first sidewall spacer together serve as an etching mask. Therefore, the ninth etching process removes the portion of the first hard mask structure 202 outside the boundary of the first sidewall spacer 702, the portion of the first stack 204 of the semiconductor structure, the portion of the cap structure 404, and the portion of the dielectric tape 504. The ninth etching process exposes the upper surface of the fin 210. In some embodiments, the ninth etching process stops at the upper surface (or near the upper surface) of the isolation structure 402.

The ninth etch process forms a first plurality of dielectric structures 704. For example, the ninth etch process forms a first dielectric structure 704a, a second dielectric structure 704b, a third dielectric structure 704c, a fourth dielectric structure 704d, and a fifth dielectric structure 704e. The first plurality of dielectric structures 704 are separated portions of the dielectric tape 504 remaining after the ninth etch process. The first plurality of dielectric structures 704 are formed on (e.g., directly on) the dielectric fins 502 and formed on (e.g., directly on) the first sidewall spacers 702 and the dummy gate structures 602. The first plurality of dielectric structures 704 are separated from each other (along the z-axis and/or along the x-axis). It should be understood that the first plurality of dielectric structures 704 may include more dielectric structures than those listed (e.g., the first plurality of dielectric structures 704 may include other separated portions of the dielectric tape 504 that remain below other dummy gate structures 602, but are not shown due to perspective).

The ninth etching process also forms a second stack 705 of multiple semiconductor structures. The second stack 705 of each semiconductor structure includes a third semiconductor structure 706 and a fourth semiconductor structure 708 that are interlaced. The third semiconductor structure 706 is a portion of the first semiconductor structure 206 that is retained after the ninth etching process. The fourth semiconductor structure 708 is a portion of the second semiconductor structure 208 that is retained after the ninth etching process. In order to make the figure clear, only the second stack 705, the third semiconductor structure 706, and the fourth semiconductor structure 708 of some semiconductor structures are specially marked.

The second stack of semiconductor structures 705 is formed on (e.g., directly on) the fin 210 and is formed on (e.g., directly on) the first sidewall spacer 702 and the dummy gate structure 602. Specifically, the second stack of semiconductor structures 705 is formed on (e.g., directly on) the fin 210 and is formed on (e.g., directly on) the separated portions of the first hard mask structure 202. The separated portions of the first hard mask structure 202 are formed by the ninth etching process. The separated portions of the first hard mask structure 202 are the separated portions of the first hard mask structure 202 that remain after the ninth etching process. The separated portions of the first hard mask structure 202 are separated laterally (along the z-axis). The separated portions of the first hard mask structure 202 are laterally located (along the z-axis) between the capping structures 404. The separated portions of the first hard mask structure 202 are respectively located on (such as directly located on) the second stack 705 of the semiconductor structure, and located under (such as directly located on) the first sidewall spacer 702 and the dummy gate structure 602.

Since the ninth etching process is an anisotropic etching process, the outer sidewalls (separated laterally along the x-axis) of each of the first plurality of dielectric structures 704, each of the separated portions of the first hard mask structure 202, each of the third semiconductor structure 706, and each of the fourth semiconductor structure 708 are substantially aligned with the outer sidewalls (separated laterally along the x-axis) of the first sidewall spacers 702. In addition, since the ninth etching process is an anisotropic etching process, the portion of the capping structure 404 remaining after the ninth etching process also has outer sidewalls (separated laterally along the x-axis) that are substantially aligned with the outer sidewalls (separated laterally in the x-axis) of the first sidewall spacers 702. In some embodiments, the first plurality of dielectric structures 704 can be considered as first plurality of dielectric fin caps because they cover and protect portions of the upper surface of the dielectric fin 502 during subsequent process steps.

As shown in FIG. 8 , the second sidewall spacers 802 are formed along the outer sidewalls (separated laterally along the x-axis) of each third semiconductor structure 706. The second sidewall spacers 802 are also formed along the outer sidewalls (separated laterally along the z-axis) of the cover structure 404. In addition, the second sidewall spacers 802 may be partially formed along both sidewalls (separated laterally along the z-axis) of the separated portion of the first hard mask structure 202. For the sake of clarity of the figure, only some of the second sidewall spacers 802 are specifically marked. In some embodiments, the second sidewall spacers 802 may be regarded as inner sidewall spacers.

In some embodiments, the process of forming the second sidewall spacer 802 includes performing a tenth etching process to laterally (along the x-direction) etch the third semiconductor structure 706 and the capping structure 404. The tenth etching process is selective to the material of the third semiconductor structure 706 and the capping structure 404 (e.g., the first semiconductor material, such as silicon germanium), and thus the third semiconductor structure 706 and the capping structure 404 may be laterally recessed. After the tenth etching process, the outer sidewalls of each third semiconductor structure 706 and the outer sidewalls of each capping structure 404 may be recessed relative to the outer sidewalls of the first hard mask structure 202, the outer sidewalls of the first sidewall spacer 702, and the outer sidewalls of the first plurality of dielectric structures 704.

A second spacer layer (not shown) may then be formed to fill the recess formed by the tenth etching process. The second spacer layer may be formed by depositing the second spacer layer in the recess formed by the tenth etching process and on the substrate 212, the fin 210, the pad layer 302, the isolation structure 402, the dielectric fin 502, the second stack of semiconductor structures 705, the first hard mask structure 202, the first plurality of dielectric structures 704, the first sidewall spacer 702, the dummy gate structure 602, and the fourth hard mask structure 612. In some embodiments, the second spacer layer may be deposited as a compliant layer. In other embodiments, the second spacer layer may be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), some other dielectric material, or a combination thereof. For example, the deposition method of the second spacer layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof.

Then, an eleventh etching process is performed on the second spacer layer to partially remove the second spacer layer, and a portion of the second spacer layer may be retained along the outer sidewalls of the third semiconductor structure 706 and the outer sidewalls of the capping structure 404 to serve as the second sidewall spacers 802. Specifically, the eleventh etching process is anisotropic, which may trim the second spacer layer, so that only a portion of the second spacer layer remains in the recess formed by the tenth etching process. Therefore, the sidewalls of the second sidewall spacers 802 may be substantially aligned with the outer sidewalls of the first hard mask structure 202, the outer sidewalls of the first sidewall spacers 702, and the outer sidewalls of the first plurality of dielectric structures 704. For example, the eleventh etching process may be a plasma etching process, a dry etching process, a reactive ion etching process, some other etching process, or a combination thereof.

As shown in FIG9 , a plurality of pairs of first source/drain regions 902 and a plurality of pairs of second source/drain regions 904 are formed on the fins 210. For clarity of the drawing, only some of the first source/drain regions 902 and some of the second source/drain regions 904 are specifically labeled. The first source/drain regions 902 are formed on (e.g., directly formed on) some of the fins 210, and the second source/drain regions 904 are formed on (e.g., directly formed on) some of the other fins 210. For example, the first source/drain region 902 of the first pair 902a is formed on (e.g., directly formed on) the first fin 210a, the first source/drain region 902 of the second pair 902b is formed on (e.g., directly formed on) the second fin 210b, the second source/drain region 904 of the third pair 904a is formed on (e.g., directly formed on) the third fin 210c, the second source/drain region 904 of the fourth pair 904b is formed on (e.g., directly formed on) the fourth fin 210d, The first source/drain regions 902 of the fifth pair 902c are formed on (e.g., directly on) the fifth fin 210e, and the first source/drain regions 902 of the sixth pair 902d are formed on (e.g., directly on) the sixth fin 210f. The first source/drain regions 902 of multiple pairs of first source/drain regions 902 (e.g., the first pair 902a, the second pair 902b, the fifth pair 902c, and the sixth pair 902d) are laterally separated (along the x-axis) and located on both sides of the dummy gate structure 602. The second source/drain regions 904 of the plurality of pairs of second source/drain regions 904 (e.g., the third pair 904a and the fourth pair 904b) are separated laterally (along the x-axis) and are located on both sides of the dummy gate structure 602. The plurality of pairs of first source/drain regions 902 are separated laterally (along the z-axis) from the plurality of pairs of second source/drain regions 904. The dielectric fins 502 separate laterally (along the z-axis) the plurality of pairs of first source/drain regions 902 from the plurality of pairs of second source/drain regions 904. In other words, multiple pairs of first source/drain regions 902 and multiple pairs of second source/drain regions 904 are located on both sides of the dielectric fin 502.

The fourth semiconductor structures 708 on the corresponding fins 210 extend laterally (along the x-axis) between the source/drain regions of the multiple pairs of source/drain regions on the corresponding fins 210. For example, one of the second stacks 705 of semiconductor structures on the first fin 210a is located between the first source/drain regions 902 of the first pair 902a, and the fourth semiconductor structure 708 of one of the second stacks 705 of semiconductor structures on the first fin 210a extends laterally (along the x-axis) between the first source/drain regions 902 of the first pair 902a. The second sidewall spacers 802 on the corresponding fins 210 are respectively located between the source/drain regions of the multiple pairs of source/drain regions on the corresponding fins 210. For example, one of the second sidewall spacers 802 is along the outer sidewall of the third semiconductor structure 706 of one of the second stacks 705 of semiconductor structures on the first fin 210a, and is located between the first source/drain regions 902 of the first pair 902a.

For example, the first source/drain region 902 can be or include silicon, germanium, silicon germanium, silicon carbide, some other semiconductor material, or a combination thereof. In some embodiments, the first source/drain region 902 is an epitaxial semiconductor material, such as a semiconductor material formed by an epitaxial process such as epitaxial silicon, epitaxial germanium, epitaxial silicon germanium, epitaxial silicon carbide, or the like. For example, the second source/drain region 904 can be or include silicon, germanium, silicon germanium, silicon carbide, some other semiconductor material, or a combination thereof. In some embodiments, the second source/drain region 904 is an epitaxial semiconductor material, such as a semiconductor material formed by an epitaxial process such as epitaxial silicon, epitaxial germanium, epitaxial silicon germanium, epitaxial silicon carbide, or the like.

In some embodiments, the first source/drain region 902 and the second source/drain region 904 include the same semiconductor material. In other embodiments, the first source/drain region 902 and the second source/drain region 904 include different semiconductor materials. In other embodiments, the first source/drain region 902 has a first doping type (e.g., p-type). In other embodiments, the second source/drain region 904 has a second doping type (e.g., n-type) opposite to the first doping type.

In some embodiments, the process of forming the first source/drain region 902 and the second source/drain region 904 includes epitaxially forming the first source/drain region 902 and the second source/drain region 904. A third epitaxial process is performed to grow the first source/drain region 902 from the upper surface corresponding to the fin 210. For example, the first source/drain regions 902 of the first pair 902a may be grown from the upper surface of the first fin 210a, the first source/drain regions 902 of the second pair 902b may be grown from the upper surface of the second fin 210b, the first source/drain regions 902 of the fifth pair 902c may be grown from the upper surface of the fifth fin 210e, and the first source/drain regions 902 of the sixth pair 902d may be grown from the upper surface of the sixth fin 210f. In some embodiments, the third epitaxial process may be vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, some other epitaxial process, or a combination thereof. The third epitaxial process can in-situ dope the first doping type dopant (e.g., p-type dopant such as boron atoms) into the first source/drain region 902.

A fourth epitaxial process may be performed to grow the second source/drain regions 904 from the upper surface of the corresponding fin 210. For example, the second source/drain regions 904 of the third pair 904a may be formed from the upper surface of the third fin 210c, and the second source/drain regions 904 of the fourth pair 904b may be formed from the upper surface of the fourth fin 210d. In some embodiments, the fourth epitaxial process may be vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, some other epitaxial process, or a combination thereof. The fourth epitaxial process may in-situ dope the second source/drain regions 904 with a second doping type (e.g., an n-type dopant such as phosphorus atoms). It should be understood that in the third epitaxial process, the upper surface of the fin 210 (which can grow the second source/drain region 904) can be masked by the mask layer. It should be understood that in the fourth epitaxial process, the first source/drain region 902 can be masked by the mask layer.

As shown in FIG. 10 , a first etch stop layer 1002 (such as a contact etch stop layer) is formed on the structure shown in FIG. 9 , and a first interlayer dielectric layer 1004 is formed on the first etch stop layer 1002. For example, the first etch stop layer 1002 may be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), some other dielectric material, or a combination thereof. For example, the interlayer dielectric layer 1004 may be or include a low dielectric constant dielectric layer (such as a dielectric material having a dielectric constant less than about 3.9), an oxide (such as silicon oxide), or the like.

In some embodiments, the process of forming the first etch stop layer 1002 and the interlayer dielectric layer 1004 includes depositing the first etch stop layer 1002 on and covering the structure shown in FIG. 9 . In some embodiments, the first etch stop layer 1002 is deposited as a conforming layer. For example, the deposition method of the first etch stop layer 1002 can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof. Thereafter, the interlayer dielectric layer 1004 can be deposited on and covering the first etch stop layer 1002 and the structure shown in FIG. 9 . Then, a planarization process is performed on the interlayer dielectric layer 1004, the first etch stop layer 1002, the fourth hard mask structure 612 (see FIG. 9 ), and the first sidewall spacer 702. The planarization process can remove the interlayer dielectric layer 1004, the first etch stop layer 1002, the fourth hard mask structure 612, and the upper portion of the first sidewall spacer 702 to form the structure shown in FIG. 10 . Therefore, the planarization process can make the interlayer dielectric layer 1004, the first etch stop layer 1002, and the upper surface of the first sidewall spacer 702 coplanar.

As shown in FIG. 11 , the dummy gate structure is removed to form a third trench 1102 between the inner sidewalls of the first sidewall spacers 702. For clarity of the drawing, only some of the third trenches 1102 are specifically labeled. The third trenches 1102 expose portions of the first plurality of dielectric structures 704 and portions of the first hard mask structure 202 between the inner sidewalls of the first sidewall spacers 702. In some embodiments, the process of removing the dummy gate structure 602 includes performing a twelfth etching process (e.g., a wet etching process, a dry etching process, or the like) that selectively removes the dummy gate dielectric structure 604 and the dummy gate material structure 606. It should be understood that multiple etching processes may be used to remove the dummy gate structure 602 (for example, after the twelfth etching process removes the dummy gate material structure 606, a subsequent etching process removes the dummy gate dielectric structure 604).

As shown in FIG. 11 , a first mask structure 1104 is formed in the third trench 1102. The upper surface of the first mask structure 1104 may be located above the upper surface of the interlayer dielectric layer 1004. For example, the first mask structure 1104 includes a positive photoresist material, a negative photoresist material, or the like. A fifth hard mask structure 1106 is formed on the first mask structure 1104. For example, the fifth hard mask structure 1106 may be or include an oxide (such as silicon oxide), a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), some other hard mask material, or a combination thereof.

In some embodiments, the process of forming the first mask structure 1104 and the fifth hard mask structure 1106 includes depositing a photoresist layer (such as a positive photoresist material and/or a negative photoresist material), and the deposition method can be chemical vapor deposition, spin coating, or a similar process. The photoresist layer is deposited in the third trench 1102 (such as filling the third trench 1102) and on the upper surface of the interlayer dielectric layer 1004, the first etch stop layer 1002, and the first sidewall spacer 702. A hard mask layer (not shown) may then be deposited on the photoresist layer and cover the photoresist layer, and the deposition method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a similar process. A third patterned mask layer may then be formed on the hard mask layer. The third patterned mask layer is used, and a thirteenth etching process (such as a wet etching process, a dry etching process, a reactive ion etching process, or a similar process) is performed on the hard mask layer to remove the unmasked portion of the hard mask layer, thereby retaining the masked portion of the hard mask layer as the fifth hard mask structure 1106. The third patterned mask layer may then be stripped off.

Then, a fourteenth etching process (such as a wet etching process, a dry etching process, a reactive ion etching process, or a similar process) can be performed on the photoresist layer to form a first mask structure 1104. During the fourteenth etching process, the fifth hard mask structure 1106 serves as an etching mask. Therefore, the fourteenth etching process removes the unmasked portion of the photoresist layer and retains the remaining portion of the photoresist layer as the first mask structure 1104. In some embodiments, the first mask structure 1104 can be regarded as a cutting metal gate mask.

12 to 19 show a series of cross-sectional views of various stages of a method of forming a semiconductor device 1904 with a reduced nanostructured field effect transistor 1810. The cross-sectional views of FIG12 to 19 are along the section line A-A of FIG11 and continue the stages shown in FIG11. For example, FIG12 shows a first stage after the stage shown in FIG11 and along the section line A-A of FIG11. FIG13 shows a second stage after the first stage shown in FIG12 and along the section line A-A of FIG11. FIG14 shows a third stage after the second stage shown in FIG13 and along the section line A-A of FIG11, and so on. Since the cross-sectional views of FIGS. 12 to 19 are along the section line A-A of FIG. 11 , the various stages of the method of forming the semiconductor device 1904 with reduced space between the nanostructure field effect transistors 1810 shown in FIGS. 12 to 19 only show the process (such as removal, formation, recessing, or similar process) of the structure that can be seen by the section line A-A of FIG. 11 . However, in some embodiments, it should be understood that similar structures (such as structures similar to those processed in FIGS. 12 to 19 ) can be processed at the various stages shown in FIGS. 12 to 19 , such as being processed in a manner similar to FIGS. 12 to 19 , but not shown because they are along the section line A-A of FIG. 11 .

As shown in FIG12, the first plurality of dielectric structures 704 are removed, exposing the third trench 1102 (see FIG11) and not masked by the first mask structure 1104. For example, the third trench 1102 is exposed and the first mask structure 1104 does not mask the first dielectric structure 704a, the third dielectric structure 704c, and the fifth dielectric structure 704e (see FIG9), so the above dielectric structures are removed. Although FIG12 shows the removal of the first dielectric structure 704a, the third dielectric structure 704c, and the fifth dielectric structure 704e, it should be understood that any combination of dielectric structures of the first plurality of dielectric structures 704 may be removed (such as forming a first mask structure 1104 in a predefined pattern). In some embodiments, the dielectric structures of the first plurality of dielectric structures 704 exposed by the third trench 1102 and not covered by the first mask structure 1104 are removed (e.g., completely removed). In other embodiments, only a portion of the dielectric structures of the first plurality of dielectric structures 704 exposed by the third trench 1102 and not covered by the first mask structure 1104 is removed, such as retaining the remaining portions of the first plurality of dielectric structures 704 directly under the first sidewall spacer 702.

12 , the portion of the cover structure 404 exposed by the third trench 1102 and not covered by the first mask structure 1104 is removed, so that the inner sidewall of the cover structure 404 is inclined. For example, the third trench 1102 is exposed and the first mask structure 1104 does not cover the cover structure 404 along the sidewalls of the first dielectric fin 502a, the third dielectric fin 502c, and the fifth dielectric fin 502e. Therefore, the portion of the cap structure 404 along the sidewalls of the first dielectric fin 502a, the third dielectric fin 502c, and the fifth dielectric fin 502e is removed, so that the inner sidewalls of the cap structure 404 along the sidewalls of the first dielectric fin 502a, the third dielectric fin 502c, and the fifth dielectric fin 502e are tilted. The tilted sidewalls of the cap structure 404 can tilt from the corresponding dielectric fin 502 to the corresponding stack of the second stack 705 of semiconductor structures. For example, the first inclined inner sidewall of one of the cap structures 404 along the first sidewall of the third dielectric fin 502c can be inclined from the third dielectric fin 502c to the second stack 705 of semiconductor structures between the third dielectric fin 502c and the second dielectric fin 502b. The second inclined inner sidewall of the other of the cap structures 404 along the second sidewall of the third dielectric fin 502c (in the opposite direction to the first inclined inner sidewall) can be inclined from the third dielectric fin 502c to the second stack 705 of semiconductor structures between the third dielectric fin 502c and the fourth dielectric fin 502d.

In some embodiments, the step of removing the first plurality of dielectric structures 704 exposed by the third trench 1102 and not covered by the first mask structure 1104 includes performing a fifteenth etching process on the structure shown in FIG. 11 to selectively remove the first plurality of dielectric structures 704 exposed by the third trench 1102 and not covered by the first mask structure 1104. During the fifteenth etching process, the first mask structure 1104 serves as an etching mask, which can prevent the fifteenth etching process from etching and removing the first plurality of dielectric structures 704 (and a portion of the capping structure 404) covered by the first mask structure 1104. Therefore, the fifteenth etching process selectively removes the first plurality of dielectric structures 704 exposed by the third trench 1102 and not covered by the first mask structure 1104. In addition, the fifteenth etching process can remove the portion of the cap structure 404 exposed by the third trench 1102 and not masked by the first mask structure 1104, thereby tilting the inner sidewall of the cap structure 404. In some embodiments, the fifteenth etching process can be a dry etching process, a wet etching process, some other etching process, or a combination thereof. As shown in FIG. 12 , the fifth hard mask structure 1106 can be removed by the fifteenth etching process.

After the fifteenth etching process, the first plurality of dielectric structures 704 may remain, and may be collectively referred to as the remaining dielectric structures 704b/704d. Taking FIG. 12 as an example, the remaining dielectric structures 704b/704d include the second dielectric structure 704b and the fourth dielectric structure 704d (because the second dielectric structure 704b and the fourth dielectric structure 704d remain after the fifteenth etching process). It should be understood that other dielectric structures of the first plurality of dielectric structures 704 may remain after the fifteenth etching process, such as other dielectric structures of the first plurality of dielectric structures 704 that are separated (along the x-axis) from the second dielectric structure 704b and the fourth dielectric structure 704d (not shown because the cross-sectional view is along the section line A-A of FIG. 11). It should be understood that the retained dielectric structure is labeled "704b/704d" for clarity, but it does not mean that the retained dielectric structure 704b/704d is limited to only the second dielectric structure 704b and the fourth dielectric structure 704d. On the contrary, after the fifteenth etching process, the retained dielectric structure 704b/704d may include one or more (and/or any combination) of the first plurality of dielectric structures 704.

In some embodiments, the remaining dielectric structures 704b/704d can be considered as a second plurality of dielectric fin caps because they cover (and protect in subsequent process steps) portions of the upper surface of the corresponding dielectric fins 502. For example, the second dielectric structure 704b covers (and protects in subsequent process steps) a portion of the upper surface of the second dielectric fin 502b, and the fourth dielectric structure 704d covers (and protects in subsequent process steps) a portion of the upper surface of the fourth dielectric fin 502d. Therefore, the second dielectric structure 704b can be regarded as a first dielectric fin cap of a second plurality of dielectric fin caps, and the fourth dielectric structure 704d can be regarded as a second dielectric fin cap of a second plurality of fin caps.

As shown in FIG. 13 , the first mask structure 1104 is removed. In some embodiments, the process of removing the first mask structure 1104 includes performing a mask removal process on the structure shown in FIG. 12 . For example, the mask removal process may be an etching process (such as a wet etching process, a dry etching process, or a similar process), an ashing process, a combination thereof, or a similar process.

As shown in FIG. 13 , the first hard mask structure 202 is removed. After removing the first mask structure 1104, the first hard mask structure 202 is removed. In some embodiments, the first hard mask structure 202 is selectively removed by a sixteenth etching process (such as a wet etching process, a dry etching process, or a similar process). In some embodiments, the sixteenth etching process recesses the first hard mask structure 202 instead of removing the first hard mask structure 202, so as to retain a portion of the first hard mask structure 202 on the second stack 705 of the semiconductor structure (to protect the fourth semiconductor structure 708 during the subsequent release process).

The third trench 1102 may be extended (along the y-direction, see FIG. 11 ) by removing (or recessing) the first hard mask structure 202. In some embodiments, the portion of the third trench 1102 may be extended (along the y-axis) by removing (or recessing) the first hard mask structure 202 at least partially undercutting (along the x-axis) the first sidewall spacer 702. In other embodiments, the sides (separated by the x-axis) of the portion of the third trench 1102 extended (along the y-axis) by removing (or recessing) the first hard mask structure 202 are at least partially defined by the sidewalls of the first etch stop layer 1002. In other embodiments, the sides (separated along the x-axis) of the portion of the third trench 1102 from which the first hard mask structure 202 is removed (or recessed) are at least partially defined by the sidewalls of the first hard mask structure 202 (e.g., the remaining portion of the first hard mask structure 202 remaining after the sixteenth etching process).

As shown in FIG. 13 , a plurality of nanostructure stacks 1302 are formed on the fins 210 . For example, the first nanostructure stack 1302a is formed on (e.g., directly formed on) the first fin 210a, the second nanostructure stack 1302b is formed on (e.g., directly formed on) the second fin 210b, the third nanostructure stack 1302c is formed on (e.g., directly formed on) the third fin 210c, the fourth nanostructure stack 1302d is formed on (e.g., directly formed on) the fourth fin 210d, the fifth nanostructure stack 1302e is formed on (e.g., directly formed on) the fifth fin 210e, and the sixth nanostructure stack 1302f is formed on (e.g., directly formed on) the sixth fin 210f. In some embodiments, the nanostructure stack 1302 is formed after removing the first hard mask structure 202.

The nanostructure stack 1302 is separated laterally (along the z-axis). The dielectric fin 502 can separate the nanostructure stack 1302 laterally (along the z-axis). In other words, the nanostructure stack 1302 is located on both sides of the dielectric fin 502. For example, the first nanostructure stack 1302a is located on the first side of the first dielectric fin 502a, and the second nanostructure stack 1302b is located on the second side (opposite to the first side) of the first dielectric fin 502a.

Each of the nanostructure stacks 1302 includes a plurality of nanostructures 1304 stacked vertically (along the y-axis), such as one directly on top of another. The nanostructures 1304 extend laterally (along the x-axis) on the fins 210 and are parallel to each other. The nanostructures 1304 of each nanostructure stack 1302 extend (along the x-axis) between a corresponding pair of source/drain regions. For example, the nanostructure 1304 of the first nanostructure stack 1302a extends (along the x-axis) between the first source/drain regions 902 of the first pair 902a (see FIG. 11 ), the nanostructure 1304 of the second nanostructure stack 1302b extends (along the x-axis) between the first source/drain regions 902 of the second pair 902b (see FIG. 11 ), and the nanostructure 1304 of the third nanostructure stack 1302c extends (along the x-axis) between the second source/drain regions 904 of the third pair 904a (see FIG. 11 ). ), the nanostructure 1304 of the fourth nanostructure stack 1302d extends (along the x-axis) between the second source/drain regions 904 of the fourth pair 904b (see FIG. 11 ), the nanostructure 1304 of the fifth nanostructure stack 1302e extends (along the x-axis) between the first source/drain regions 902 of the fifth pair 902c (see FIG. 11 ), and the nanostructure 1304 of the sixth nanostructure stack 1302f extends (along the x-axis) between the first source/drain regions 902 of the sixth pair 902d (see FIG. 11 ).

In some embodiments, the nanostructure stacks 1302 are separated from the fins 210 (along the y-axis). In some embodiments, the nanostructures 1304 of the nanostructure stacks 1302 are separated vertically (along the y-axis). For example, the first nanostructure stack 1302a is separated from the upper surface of the first fin 210a (along the y-axis), and the nanostructures 1304 of the first nanostructure stack 1302a are separated vertically (along the y-axis) from each other.

In some embodiments, nanostructure 1304 may have a rectangular profile, as shown in FIG. 13. In other embodiments, nanostructure 1304 may have a square profile, an oval profile, a stadium-shaped (e.g., oblong) profile, a hexagonal profile (e.g., a vertically separated hexagonal profile or a merged hexagonal profile), some other geometric profile, or a combination thereof. If nanostructure 1304 has a square profile, nanostructure 1304 may be considered a square nanowire. If nanostructure 1304 has an oval profile, nanostructure 1304 may be considered a nanoring. If nanostructure 1304 has a hexagonal profile or a stadium-shaped profile, nanostructure 1304 may be considered a horizontal nanosheet or a horizontal nanoplate. If the nanostructure 1304 has a hexagonal outline, the nanostructure 1304 can be regarded as a hexagonal nanowire.

In some embodiments, the process of forming the nanostructure stack 1302 includes removing the third semiconductor structure 706 and the capping structure 404 exposed by the third trench 1102 (such as the extended third trench 1102). By removing the third semiconductor structure 706 and the capping structure 404, the fourth semiconductor structure 708 can be released to form the nanostructure 1304. In other words, after removing the third semiconductor structure 706 and the capping structure 404, portions of the fourth semiconductor structure 708 can be retained as the nanostructure 1304.

The third semiconductor structure 706 and the capping structure 404 may be removed by a seventeenth etching process (such as a wet etching process, a dry etching process, or the like). Since the third semiconductor structure 706 and the capping structure 404 include the same semiconductor material (such as the first semiconductor material such as silicon germanium), the seventeenth etching process may selectively remove the third semiconductor structure 706 and the capping structure 404 to form the nanostructure 1304. In some embodiments, the seventeenth etching process may selectively remove the third semiconductor structure 706 and the capping structure 404, and a wet etching agent such as ammonium hydroxide, tetramethylammonium hydroxide solution, ethylenediamine catechol, potassium hydroxide solution, or the like may be used. In other embodiments, the seventeenth etching process may slightly etch the semiconductor material (e.g., the second semiconductor material such as silicon) of the fourth semiconductor structure 708, so that the cross-sectional area of the nanostructure 1304 is slightly smaller than the cross-sectional area of the fourth semiconductor structure 708. It should be understood that the seventeenth etching process may not release some portions of the nanostructure 1304 (e.g., the portion directly under the first sidewall spacer 702, see FIG. 11). Instead, the second sidewall spacer 802 surrounds these portions of the nanostructure 1304 (see FIG. 11).

As shown in FIG. 14 , an interface layer 1402 is formed around each nanostructure 1304. For example, the interface layer 1402 may be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), some other dielectric material, or a combination thereof. In some embodiments, the process of forming the interface layer 1402 includes depositing or growing the interface layer 1402 on a surface (e.g., an outer sidewall) of the nanostructure 1304, and the deposition or growth method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, some other deposition or growth process, or a combination thereof. In other embodiments, the interface layer 1402 is an oxide grown by a thermal oxidation process, so the interface layer 1402 is not formed on the dielectric fin 502 or the retained dielectric structure 704b/704d. Although not shown in FIG. 14, it should be understood that some embodiments may also form the interface layer 1402 on the upper surface of the fin 210 and the upper surface of the pad layer 302, such as the thermal oxidation process may grow the interface layer 1402 on the upper surface of the fin 210 and the upper surface of the pad layer 302.

As shown in FIG. 14 , a gate dielectric layer 1404 is formed around each nanostructure 1304. The gate dielectric layer 1404 is also formed around the interface layer 1402, on the fin 210, on the liner layer 302, on the dielectric fin 502, on the retained dielectric structure 704b/704d, and on the isolation structure 402. The gate dielectric layer 1404 can be or include a high dielectric constant dielectric layer such as bismuth oxide, zirconia, bismuth aluminum oxide, bismuth silicate, some other dielectric materials with a dielectric constant greater than 3.9, or a combination thereof.

The gate dielectric layer 1404 is formed after forming the interface layer 1402. In some embodiments, the process of forming the gate dielectric layer 1404 may include depositing the gate dielectric layer 1404 on the interface layer 1402, the fin 210, the liner layer 302, the dielectric fin 502, the remaining dielectric structure 704b/704d, and the surface of the isolation structure 402, as shown in Figure 14. For example, the deposition method of the gate dielectric layer 1404 may be atomic layer deposition, chemical vapor deposition, physical vapor deposition, some other deposition process, or a combination thereof. In other embodiments, a gate dielectric layer 1404 may be formed as a compliant layer.

As shown in FIG. 14 , a gate layer 1406 is formed on the gate dielectric layer 1404, the fin 210, the liner layer 302, the dielectric fin 502, the retained dielectric structure 704b/704d, the isolation structure 402, and the nanostructure stack 1302. In some embodiments, the gate layer 1406 is also formed around and between each nanostructure 1304, as shown in FIG. 14 .

In some embodiments, the process of forming the gate layer 1406 includes depositing a gate material in the third trench 1102 (e.g., the extended third trench 1102), on the gate dielectric layer 1404, on the fin 210, on the liner layer 302, on the dielectric fin 502, on the remaining dielectric structure 704b/704d, on the isolation structure 402, on the nanostructure stack 1302, and around and between each nanostructure 1304. The gate material is also deposited on the interlayer dielectric layer 1004, the first sidewall spacer 702, and the first etch stop layer 1002 (see FIG. 11). For example, the gate material may be or include polysilicon (such as doped polysilicon), a metal (such as aluminum, tungsten, or the like), titanium nitride, tantalum nitride, titanium aluminum carbide, titanium aluminum silicide, some other conductive material, or a combination thereof. The gate material may include multiple layers of gate material, such as a work function layer (such as titanium nitride, tantalum nitride, or the like), a metal fill layer (such as tungsten), and the like.

For example, the gate material may be deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, electrochemical plating, electroless plating, some other deposition process, or a combination thereof. After the gate material is deposited, a planarization process such as chemical mechanical polishing may be performed on the gate material to remove the upper portion of the gate material, thereby retaining the lower portion of the gate material as the gate layer 1406. For example, the gate layer 1406 may be or include polysilicon (e.g., doped polysilicon), a metal (e.g., aluminum, tungsten, or the like), titanium nitride, tantalum nitride, titanium aluminum carbide, titanium aluminum silicide, some other conductive material, or a combination thereof. The gate layer 1406 may include multiple layers, such as a work function layer (e.g., titanium nitride, tantalum nitride, or the like), a metal fill layer (e.g., tungsten), and the like. The planarization process can also remove the interlayer dielectric layer 1004, the first etch stop layer 1002, and the upper portion of the first sidewall spacer 702, so that the gate layer 1406, the interlayer dielectric layer 1004, the first etch stop layer 1002, and the upper surface of the first sidewall spacer 702 are coplanar.

As shown in FIG15 , a plurality of gate structures 1502 are formed on the fins 210, the liner layer 302, the dielectric fins 502, the isolation structures 402, and the nanostructure stack 1302. The corresponding dielectric fins 502 and the corresponding retained dielectric structures 704b/704d are laterally separated (along the z-axis) from the gate structures 1502. The upper surface of the gate structure 1502 is lower than the upper surface of the retained dielectric structures 704b/704d. In some embodiments, the upper surface of the gate structure 1502 is lower than the lower surface of the first sidewall spacer 702 (see FIG11 ). The gate structure 1502 is formed between source/drain regions of one or more of the corresponding pairs of source/drain regions. In some embodiments, the gate structure 1502 is formed around each nanostructure 1304 of one or more corresponding nanostructure stacks 1302.

For example, a first gate structure 1502a, a second gate structure 1502b, and a third gate structure 1502c are formed. The second dielectric structure 704b and the second dielectric fin 502b both laterally separate (along the z-axis) the first gate structure 1502a and the second gate structure 1502b, and the fourth dielectric structure 704d and the fourth dielectric fin 502d both laterally separate (along the z-axis) the second gate structure 1502b and the third gate structure 1502c. The upper surfaces of the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c are lower than the upper surfaces of the second dielectric structure 704b and the fourth dielectric structure 704d.

The first gate structure 1502a is formed between the first source/drain regions 902 of the first pair 902a and between the first source/drain regions 902 of the second pair 902b (see FIG. 11). The second gate structure 1502b is formed between the second source/drain regions 904 of the third pair 904a and between the second source/drain regions 904 of the fourth pair 904b (see FIG. 11). The third gate structure 1502c is formed between the first source/drain regions 902 of the fifth pair 902c and between the first source/drain regions 902 of the sixth pair 902d (see FIG. 11). In some embodiments, the upper surface of the first gate structure 1502a is lower than the lower surface of one of the first sidewall spacers 702 extending (along the z-axis) between the first source/drain regions 902 of the first pair 902a and the second pair 902b. In other embodiments, the upper surface of the second gate structure 1502b and/or the third gate structure 1502c is lower than the lower surface of one of the first sidewall spacers 702.

The first gate structure 1502a surrounds each nanostructure 1304 of the first nanostructure stack 1302a and each nanostructure 1304 of the second nanostructure stack 1302b. The second gate structure 1502b surrounds each nanostructure 1304 of the third nanostructure stack 1302c and each nanostructure 1304 of the fourth nanostructure stack 1302d. The third gate structure 1502c surrounds each nanostructure 1304 of the fifth nanostructure stack 1302e and each nanostructure 1304 of the sixth nanostructure stack 1302f.

It should be understood that the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c may surround each nanostructure 1304 of any number of nanostructure stacks 1302, depending on the intended function of the semiconductor device 1904. For example, the first gate structure 1502a may be formed around each nanostructure 1304 of one nanostructure stack 1302, around each nanostructure 1304 of two nanostructure stacks 1302 (as shown in FIG. 15 ), around each nanostructure 1304 of three nanostructure stacks 1302, or around each nanostructure 1304 of any other number of nanostructure stacks 1302. It should be understood that the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c can be formed around each nanostructure 1304 of the same number of nanostructure stacks 1302 (such as the two nanostructure stacks shown in FIG. 15), or the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c can be formed around each nanostructure 1304 of different numbers of nanostructure stacks 1302. It should be understood that the number of nanostructure stacks 1302 around which the gate structure 1502 is formed depends on the pattern of the first mask structure 1104 (see FIG. 12).

In some embodiments, the process of forming the gate structure 1502 includes recessing the gate layer 1406 (see FIG. 14 ) to below the upper surface of the retained dielectric structure 704b/704d. For example, the method of recessing the gate layer 1406 may be an etching process (such as a wet etching process, a dry etching process, or the like) that is selective to the gate layer 1406 (such as removing material of the gate layer 1406 without substantially attacking the gate dielectric layer 1404).

After the gate layer 1406 is recessed, the separated lower side portions of the gate layer are retained as the gate structure 1502. For example, after the gate layer 1406 is recessed, the second dielectric structure 704b and the fourth dielectric structure 704d separate the three lower side portions of the gate layer 1406, thereby forming the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c in a self-aligned manner.

The method described herein provides advantages over the reference cut metal gate process due to the self-aligned formation of the gate structure 1502. The reference cut metal gate process includes forming openings in the gate layer 1406 at this stage of the process and filling the openings with dielectric material to cut the gate layer 1406 into the gate structure 1502. As the structure size continues to shrink (e.g., 3nm or less), the reference cut metal gate process may have difficulty filling the openings due to the high aspect ratio of the openings. Improper filling of the openings may cause electrical shorts between the gate structures 1502 and may cause device failure. The improved method provided herein forms the gate structure 1502 in a self-aligned manner, thereby avoiding device failure and improving production capacity.

As shown in FIG. 15 , a second etch stop layer 1504 is formed on (e.g., directly on) the gate structure 1502. After the gate structure 1502 is formed, the second etch stop layer 1504 is formed. The upper surface of the second etch stop layer 1504 may be lower than the upper surface of the remaining dielectric structure 704b/704d. In some embodiments, the upper surface of the second etch stop layer 1504 is lower than the lower surface of the first sidewall spacer 702 (see FIG. 11 ). In other embodiments, the second etch stop layer 1504 may be a fluorine-free tungsten layer. The second etch stop layer 1504 may serve as an etch stop layer in a subsequent etching process and/or help reduce the resistance between the gate structure 1502 and a subsequently formed conductive contact (e.g., a metal contact electrically coupled to the gate structure 1502).

In some embodiments, the process of forming the second etch stop layer 1504 includes depositing the second etch stop layer 1504 on the gate structure 1502, and the deposition method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, electrochemical plating, electroless plating, some other deposition process, or a combination thereof. The second etch stop layer 1504 may be selectively deposited on the gate structure 1502 by a selective chemical vapor deposition process. The second etch stop layer 1504 is deposited after the gate structure 1502 is formed. In addition, the second etch stop layer 1504 is deposited in the trench (not shown) produced by the step of forming the gate structure 1502 (e.g., recessing the gate layer 1406). The trench formed by forming the gate structure 1502 extends vertically between the inner sidewalls of the first sidewall spacer 702, extends to the upper surface of the gate structure 1502, and extends to the surface of the gate dielectric layer 1404 (e.g., the upper surface and the sidewalls, which are higher than the upper surface of the gate structure 1502).

15 , a fourth dielectric layer 1506 is formed on (e.g., directly on) the remaining dielectric structures 704b/704d, the gate dielectric layer 1404, the gate structure 1502, the dielectric fin 502, and the second etch stop layer 1504. The fourth dielectric layer 1506 is formed after the second etch stop layer 1504 is formed. The fourth dielectric layer 1506 extends vertically (along the y-axis) between the inner sidewalls of the first sidewall spacers 702, to the upper surface of the second etch stop layer 1504, and to the surface of the gate dielectric layer 1404 (which is higher than the upper surface of the second etch stop layer 1504). In other words, the fourth dielectric layer 1506 is formed in the remaining portion of the trench formed when the gate structure 1502 is formed (such as the portion of the trench not filled by the second etch stop layer 1504). The fourth dielectric layer 1506 is formed so that the upper surface of the second dielectric structure 704b and the upper surface of the fourth dielectric structure 704d are between the uppermost surface and the lowermost surface of the fourth dielectric layer 1506, as shown in FIG. 15. In some embodiments, the uppermost surface of the fourth dielectric layer 1506 is substantially flat.

In some embodiments, the process of forming the fourth dielectric layer 1506 includes depositing a third dielectric material on the remaining dielectric structures 704b/704d, the gate dielectric layer 1404, the gate structure 1502, the dielectric fin 502, the second etch stop layer 1504, the first sidewall spacer 702, the first etch stop layer 1002, and the interlayer dielectric layer 1004. In other words, the third dielectric material is deposited on the upper surface of the first sidewall spacer 702, the upper surface of the first etch stop layer 1002, and the upper surface of the interlayer dielectric layer 1004 (see FIG. 11 ), and fills the remaining portion of the trench formed when forming the gate structure 1502 (e.g., the portion of the trench not filled by the second etch stop layer 1504). For example, the third dielectric material may be or include nitride (e.g., silicon nitride), carbonitride (e.g., silicon carbonitride), silicon oxycarbonitride, oxynitride (e.g., silicon oxynitride), metal oxide (e.g., aluminum oxide, yttrium oxide, zirconium oxide, or yttrium oxide), oxide (e.g., silicon oxide), some other dielectric material, or a combination thereof. The third dielectric material has a different chemical composition from the interlayer dielectric layer 1004, so the interlayer dielectric layer 1004 can be selectively etched in subsequent process steps (such as when forming source/drain contacts).

For example, the deposition method of the third dielectric material may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof. After the third dielectric material is deposited, a planarization process (such as chemical mechanical polishing) may be performed on the third dielectric material to remove the upper portion of the third dielectric material, thereby retaining the lower portion of the third dielectric material as the fourth dielectric layer 1506. The planarization process also removes the upper portion of the interlayer dielectric layer 1004, the first etch stop layer 1002, and the first sidewall spacer 702, so that the fourth dielectric layer 1506, the interlayer dielectric layer 1004, the first etch stop layer 1002, and the upper surface of the first sidewall spacer 702 are coplanar.

As shown in FIG. 16 , a first opening 1602 is formed in the fourth dielectric layer 1506. The first opening 1602 extends vertically (along the y-axis) between the inner sidewall of one of the first sidewall spacers 702 and the second etch stop layer 1504. The first opening 1602 at least partially overlaps with the second gate structure 1502b. The first opening 1602 partially overlaps with the second dielectric structure 704b and/or the fourth dielectric structure 704d.

In some embodiments, the first opening 1602 overlaps with the second gate structure 1502b, partially overlaps with the second dielectric structure 704b, and partially overlaps with the fourth dielectric structure 704d. In other words, the second gate structure 1502b is located between the sidewalls of the first opening 1602, the second dielectric structure 704b is partially located between the sidewalls of the first opening 1602, and the fourth dielectric structure 704d is partially located between the sidewalls of the first opening 1602. The first opening 1602 also overlaps with the third nanostructure stack 1302c, the fourth nanostructure stack 1302d, the third dielectric fin 502c, the third fin 210c, and the fourth fin 210d. In some embodiments, the inner sidewall of the fourth dielectric layer 1506, the inner sidewall of one of the first sidewall spacers 702, the upper surface of the second etch stop layer 1504, and the surface of the gate dielectric layer 1404 (such as the sidewall and the upper surface) may at least partially define the surface of the first opening 1602 (such as the sidewall and the lower surface).

In some embodiments, the process of forming the first opening 1602 includes forming a second mask structure 1604 on the fourth dielectric layer 1506. For example, the second mask structure 1604 may be or include positive photoresist and/or negative photoresist materials, hard mask materials, combinations thereof, or the like. In other embodiments, the process of forming the second mask structure 1604 includes depositing a mask material (such as positive photoresist and/or negative photoresist) on the upper surface of the fourth dielectric layer 1506. The mask material is then exposed to a pattern (for example, by a lithography process such as photolithography, extreme ultraviolet lithography, or the like) and the mask material is developed to form the second mask structure 1604 on the fourth dielectric layer 1506.

Then, an eighteenth etching process is performed on the fourth dielectric layer 1506 to remove the portion of the fourth dielectric layer 1506 not masked by the second mask structure 1604, thereby forming a first opening 1602 in the fourth dielectric layer 1506. In some embodiments, the eighteenth etching process stops on the second etch stop layer 1504. In other embodiments, the eighteenth etching process stops on the second etch stop layer 1504 and the gate dielectric layer 1404. The eighteenth etching process can be a dry etching process, a wet etching process, a reactive ion etching process, some other etching process, or a combination thereof.

Since the second dielectric structure 704b is located on the second dielectric fin 502b and the fourth dielectric structure 704d is located on the fourth dielectric fin 502d, the etching process tolerance of the first opening 1602 can be improved compared to the reference cutting metal gate process. In this process stage, the reference cutting metal gate process includes forming an opening in the gate layer 1406 and filling the opening with a dielectric material to cut the gate layer 1406 into the gate structure 1502. For example, the second dielectric structure 704b and the fourth dielectric structure 704d cause the first opening 1602 to have a larger size (due to lithography resolution limitations) and/or to be laterally offset from a predefined position (due to poor overlay control), while still ensuring that the first opening 1602 only overlaps with desired structures (e.g., the second gate structure 1502b). In contrast, if the opening of the reference cut metal gate process (e.g., the opening formed in the gate layer 1406 and filled with dielectric material to form the gate structure 1502) is too large and/or misaligned, the reference cut metal gate process may unintentionally remove portions of the gate layer 1406 (and/or unintentionally retain portions of the gate layer 1406), causing device failure and reduced productivity. Thus, as the structure size continues to shrink (e.g., 3nm or less), the methods described herein can avoid device failure and improve productivity.

As shown in FIG. 17 , the second mask structure 1604 is removed (e.g., stripped). As shown in FIG. 17 , a portion of the second etch stop layer 1504 exposed by the first opening 1602 is removed, and the second gate structure 1502b is removed. In some embodiments, the nineteenth etching process may remove the second gate structure 1502b and the portion of the second etch stop layer 1504 exposed by the first opening 1602. In other embodiments, before removing the second gate structure 1502b, the gate structure 1502 may be respectively regarded as a conductive gate structure (to distinguish between a functional gate structure present in the semiconductor device 1904 and a conductive gate structure removed when the semiconductor device 1904 is formed). For example, before removing the second gate structure 1502b, the first gate structure 1502a, the second gate structure 1502b, and the third gate structure 1502c can be regarded as the first conductive gate structure, the second conductive gate structure, and the third conductive gate structure, respectively.

The nineteenth etching process is anisotropic etching. The nineteenth etching process is selective to the second etch stop layer 1504 and the second gate structure 1502b, so the second gate structure 1502b and the portion of the second etch stop layer 1504 exposed by the first opening 1602 can be removed without removing a portion of the gate dielectric layer 1404 or the retained dielectric structure 704b/704d. The nineteenth etching process can be a dry etching process, a wet etching process, some other etching process, or a combination thereof.

Since the second dielectric structure 704b laterally separates the first gate structure 1502a from the second gate structure 1502b, and the fourth dielectric structure 704d laterally separates the second gate structure 1502b from the third gate structure 1502c, the second dielectric structure 704b and the fourth dielectric structure 704d can serve as a barrier, so that the nineteenth etching process can selectively remove the second gate structure 1502b. In other words, due to the location of the second dielectric structure 704b and the fourth dielectric structure 704d, and the second dielectric structure 704b and the fourth dielectric structure 704d extending on the upper surface of the gate structure 1502, the second dielectric structure 704b, and the fourth dielectric structure 704d as a barrier, the nineteenth etching process can be prevented from unintentionally removing portions of the first gate structure 1502a and the third gate structure 1502c. Therefore, as the structure size continues to shrink (e.g., 3nm or less), the method described herein can better avoid device failure and improve production capacity.

As shown in FIG. 18 , the second opening 1801 is formed in the boundary of the first opening 1602 (e.g., in the inner sidewall of the first opening 1602 ) and extends from the first opening 1602 toward the substrate 212 (along the y-axis). The first opening 1602 and the second opening 1801 are continuous regions of free space (e.g., a cavity of any material). In some embodiments, the process of forming the second opening 1801 includes performing a twentieth etching process on the structure shown in FIG. 17 . For example, the twentieth etching process may be a wet etching process, a dry etching process, a reactive ion etching process, some other etching process, or a combination thereof.

The twelfth etching process removes the structure exposed by (and/or under) the first opening 1602 (or recesses the structure). In some embodiments, the twelfth etching process is a highly directional etching process, which can vertically (e.g., downwardly) etch the structure exposed by (and/or under) the first opening 1602, but does not laterally (e.g., sideways) etch the structure exposed by (and/or under) the first opening 1602. In other embodiments, the twelfth etching process is selective to the structure exposed by (and/or under) the first opening 1602. In other words, the selectivity of the twelfth etching process to the structure exposed by (and/or under) the first opening 1602 is higher than the selectivity to the fourth dielectric layer 1506. Therefore, by performing the twelfth etching process on the structure shown in FIG. 17 , the twelfth etching process can selectively remove (or recess) the structure exposed by (and/or below) the first opening 1602. The contents of removing and recessing the structure exposed by (and/or below) the first opening 1602 (for example, by the twelfth etching process) are described in detail as follows.

The twelfth etching process may remove (e.g., completely remove) the nanostructure 1304 of the third nanostructure stack 1302c, the nanostructure 1304 of the fourth nanostructure stack 1302d, and a portion of the interface layer 1402 exposed by (and/or below) the first opening 1602. In addition, the twelfth etching process recesses the third dielectric fin 502c to form a recessed dielectric fin 1802. The upper surface of the recessed dielectric fin 1802 is lower than the upper surfaces of the first dielectric fin 502a, the second dielectric fin 502b, the fourth dielectric fin 502d, and the fifth dielectric fin 502e. As shown in FIG. 18 , the twelfth etching process removes two nanostructure stacks 1302 (such as the third nanostructure stack 1302c and the fourth nanostructure stack 1302d), but it should be understood that the twelfth etching process can remove any number of nanostructure stacks 1302. Specifically, the twelfth etching process can remove about 1 nanostructure stack to about 100 nanostructure stacks.

The twelfth etching process makes the third fin 210c recessed to form a recessed portion of the third fin 210c. The twelfth etching process makes the fourth fin 210d recessed to form a recessed portion of the fourth fin 210d. For the sake of clarity, the recessed portion of the third fin 210c can be regarded as the first recessed semiconductor fin 1804a, and the recessed portion of the fourth fin 210d can be regarded as the second recessed semiconductor fin 1804b, so as to more clearly distinguish the first recessed semiconductor fin 1804a of the third fin 210c and the second recessed semiconductor fin 1804b of the fourth fin 210d. However, it should be understood that the first recessed semiconductor fin 1804a can be regarded as a recessed portion of the third fin 210c (not all third fins 210c have unrecessed portions), and the second recessed semiconductor fin 1804b can be regarded as a recessed portion of the fourth fin 210d (not all fourth fins 210d have unrecessed portions).

In some embodiments, the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b are vertically located between the lower surface (e.g., the lowermost surface) and the upper surface (e.g., the uppermost surface) of the isolation structure 402. In other embodiments, the upper surfaces of the first recessed semiconductor fin 1804a and/or the second recessed semiconductor fin 1804b are lower than the lower surface of the isolation structure 402. The upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b may be rounded, as shown in FIG. 18 . In these embodiments, the upper surface of the first recessed semiconductor fin 1804a and the upper surface of the second recessed semiconductor fin 1804b may have a recessed shape. In other embodiments, the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b may be substantially flat.

The twelfth etching process recesses the portion of the liner layer 302 exposed by (and/or below) the first opening 1602. In some embodiments, the portion of the liner layer 302 exposed by (and/or below) the first opening 1602 is recessed, so that the upper surface of the liner layer 302 is substantially aligned with the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b. The upper surface of the liner layer 302 substantially aligned with the upper surfaces of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b can be rounded. In some embodiments, the curvature radius of the rounded upper surface of the pad layer 302 is the same as the curvature radius of the upper surface of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b. In other embodiments, the curvature radius of the rounded upper surface of the pad layer 302 is different from the curvature radius of the upper surface of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b. In other embodiments, the rounded upper surface of the pad layer 302 is connected to the sidewall of the corresponding isolation structure 402 in an arc shape from the substantially flat upper surface of the first recessed semiconductor fin 1804a and the second recessed semiconductor fin 1804b.

The twelfth etching process removes the remaining portion of the dielectric structure 704b/704d (see FIG. 17 ) to form a second plurality of dielectric structures 1806. For example, a portion of the second dielectric structure 704b exposed (and/or below) by the first opening 1602 is removed (see FIG. 17 ) to retain the remaining portion of the second dielectric structure 704b as a sixth dielectric structure 1806a, which is one of the dielectric structures of the second plurality of dielectric structures 1806. In addition, a portion of the fourth dielectric structure 704d exposed (and/or below) by the first opening 1602 is removed to retain the remaining portion of the fourth dielectric structure 704d as a seventh dielectric structure 1806b, which is another dielectric structure of the second plurality of dielectric structures 1806.

In some embodiments, the sixth dielectric structure 1806a has an L-shaped profile (e.g., along the section line A-A). In other embodiments, the seventh dielectric structure 1806b has an L-shaped profile (e.g., along the section line A-A). The L-shaped profile of the sixth dielectric structure 1806a and the L-shaped profile of the seventh dielectric structure 1806b face opposite directions. For example, the sixth dielectric structure 1806a has a first vertical portion (extending along the y-axis) and a first transverse portion (extending along the z-axis). The first transverse portion extends from the first vertical portion in a first direction (along the z-axis). The seventh dielectric structure 1806b has a second vertical portion (extending along the y-axis) and a second transverse portion (extending along the z-axis). The second transverse portion extends from the second vertical portion in a second direction (along the z-axis), and the second direction is opposite to the first direction.

The twelfth etching process may remove (e.g., completely remove) the portion of the gate dielectric layer 1404 exposed by (and/or below) the first opening 1602, thereby forming a plurality of gate dielectric structures 1808. For example, by removing the portion of the gate dielectric layer 1404 exposed by (and/or below) the first opening 1602, a first portion of the gate dielectric layer 1404 may be retained as a first gate dielectric structure 1808a, and a second portion of the gate dielectric layer 1404 may be retained as a second gate dielectric structure 1808b. The first gate dielectric structure 1808a separates the first gate structure 1502a and the first fin 210a, the second fin 210b, the liner layer 302, the isolation structure 402, the first dielectric fin 502a, the second dielectric fin 502b, the sixth dielectric structure 1806a, each nanostructure 1304 of the first nanostructure stack 1302a, and each nanostructure 1304 of the second nanostructure stack 1302b. The first gate dielectric structure 1808a also separates the sixth dielectric structure 1806a and the second etch stop layer 1504 and the fourth dielectric layer 1506.

The second gate dielectric structure 1808b separates the third gate structure 1502c and the fifth fin 210e, the sixth fin 210f, the liner layer 302, the isolation structure 402, the fourth dielectric fin 502d, the fifth dielectric fin 502e, the seventh dielectric structure 1806b, each nanostructure 1304 of the fifth nanostructure stack 1302e, and each nanostructure 1304 of the sixth nanostructure stack 1302f. The second gate dielectric structure 1808b also separates the seventh dielectric structure 1806b and the second etch stop layer 1504 from the fourth dielectric layer 1506.

Since the twelfth etching process is a highly directional etching, it can vertically etch the structure exposed by (and/or below) the first opening 1602, and various surfaces (such as sidewalls) of the structure shown in Figure 18 can be substantially aligned. For example, the first inner sidewall of the fourth dielectric layer 1506 is substantially aligned with the outer sidewall of the first gate dielectric structure 1808a, and the outer sidewall of the first gate dielectric structure 1808a is substantially aligned with the first sidewall of the sixth dielectric structure 1806a (such as the sidewall of the first vertical portion of the sixth dielectric structure 1806a). The second inner sidewall of the fourth dielectric layer 1506 (opposite to the first inner sidewall of the fourth dielectric layer 1506) is substantially aligned with the outer sidewall of the second gate dielectric structure 1808b, and the outer sidewall of the second gate dielectric structure 1808b is substantially aligned with the first sidewall of the seventh dielectric structure 1806b (e.g., the sidewall of the second vertical portion of the seventh dielectric structure 1806b). The second sidewall of the sixth dielectric structure 1806a (e.g., one sidewall of the first lateral portion of the sixth dielectric structure 1806a) is substantially aligned with the outer sidewall of the second dielectric fin 502b. The second sidewall of the seventh dielectric structure 1806b (e.g., one sidewall of the second lateral portion of the seventh dielectric structure 1806b) is substantially aligned with the outer sidewall of the fourth dielectric fin 502d.

In some embodiments, the outer sidewalls of the first gate dielectric structure 1808a, the outer sidewalls of the second gate dielectric structure 1808b, the surfaces (such as the sidewalls and the upper surface) of the second plurality of dielectric structures 1806, the outer sidewalls of the second dielectric fin 502b, the outer sidewalls of the fourth dielectric fin 502d, the recessed dielectric fin 1802 The surface (such as the sidewall and the upper surface) of the first opening 1601, the surface (such as the sidewall and the upper surface) of the isolation structure 402, the upper surface of the liner layer 302, the upper surface of the first recessed semiconductor fin 1804a, and the upper surface of the second recessed semiconductor fin 1804b can at least partially define the surface (such as the sidewall and the lower surface) of the second opening 1801. In other embodiments, since the process for forming the second opening (such as the twelfth etching process) removes the structure exposed (and/or below) the first opening 1602 (or recesses the structure), the process for forming the second opening can be regarded as a process for extending the depth (or height) of the first opening 1602.

As shown in FIG18 , the step of forming the second opening 1801 can form a plurality of nanostructure field effect transistors 1810. For example, the step of forming the second opening 1801 can form a first nanostructure field effect transistor 1810a on a first side of the second opening 1801, and form a second nanostructure field effect transistor 1810b on a second side of the second opening 1801, and the first side and the second side of the first opening 1801 are opposite to each other. The second opening 1801 laterally separates (along the z-axis) the first nanostructure field effect transistor 1810a and the second nanostructure field effect transistor 1810b. In some embodiments, the step of forming the gate dielectric structure 1808 completes the first nanostructure field effect transistor 1810a and the second nanostructure field effect transistor 1810b.

The first nanostructure field effect transistor 1810a includes a first gate structure 1502a, a first gate dielectric structure 1808a, a first nanostructure stack 1302a, a second nanostructure stack 1302b, a first source/drain region 902 of a first pair 902a (see FIG. 11 ), and a first source/drain region 902 of a second pair 902b (see FIG. 11 ). A first plurality of selective conductive channels (not shown) are respectively located in the nanostructure 1304 of the first nanostructure stack 1302a and the nanostructure 1304 of the second nanostructure stack 1302b. The selective conductive channel in the nanostructure 1304 of the first nanostructure stack 1302a can extend (along the x-axis) between the first source/drain regions 902 of the first pair 902a. The selective conductive channel in the nanostructure 1304 of the second nanostructure stack 1302b can extend (along the x-axis) between the first source/drain regions 902 of the second pair 902b. In addition to including two nanostructure stacks and corresponding two pairs of first source/drain regions 902, it should be understood that the first nanostructure field effect transistor 1810a can include any number of nanostructure stacks and any number of corresponding multiple pairs of first source/drain regions 902.

The second nanostructure field effect transistor 1810b includes a third gate structure 1502c, a second gate dielectric structure 1808b, a fifth nanostructure stack 1302e, a sixth nanostructure stack 1302f, a first source/drain region 902 of a fifth pair 902c (see FIG. 11 ), and a first source/drain region 902 of a sixth pair 902d (see FIG. 11 ). A second plurality of selective conductive channels (not shown) are respectively located in the nanostructure 1304 of the fifth nanostructure stack 1302e and the nanostructure 1304 of the sixth nanostructure stack 1302f. The selective conductive path in the nanostructure 1304 of the fifth nanostructure stack 1302e extends (along the x-axis) between the first source/drain regions 902 of the fifth pair 902c. The selective conductive path in the nanostructure 1304 of the sixth nanostructure stack 1302f extends (along the x-axis) between the first source/drain regions 902 of the sixth pair 902d. In addition to including two nanostructure stacks and two corresponding pairs of first source/drain regions 902, it should be understood that the second nanostructure field effect transistor 1810b may include any number of nanostructure stacks and any number of corresponding pairs of first source/drain regions 902. It should also be understood that the first nanostructure field effect transistor 1810a and the second nanostructure field effect transistor 1810b may include the same (or different) number of nanostructure stacks and corresponding multiple pairs of first source/drain regions 902.

As shown in FIG. 19 , the fifth dielectric layer 1902 is formed in (e.g., filled into) the first opening 1602 and the second opening 1801. The fifth dielectric layer 1902 is formed on the first recessed semiconductor fin 1804a, the second recessed semiconductor fin 1804b, the liner layer 302, the isolation structure 402, the recessed dielectric fin 1802, the dielectric fin 502, the second plurality of dielectric structures 1806, and the gate dielectric structure 1808. In some embodiments, the fifth dielectric layer 1902 has a flat upper surface.

In some embodiments, the process of forming the fifth dielectric layer 1902 includes depositing a fourth dielectric material on the first recessed semiconductor fin 1804a, the second recessed semiconductor fin 1804b, the liner layer 302, the isolation structure 402, the recessed dielectric fin 1802, the dielectric fin 502, the second plurality of dielectric structures 1806, the gate dielectric structure 1808, the gate structure 1502, the second etch stop layer 1504, the fourth dielectric layer 1506, the first sidewall spacer 702, the first etch stop layer 1002, and the interlayer dielectric layer 1004. In other words, the fourth dielectric material is formed on the upper surface of the fourth dielectric layer 1506, the upper surface of the first sidewall spacer 702, the upper surface of the first etch stop layer 1002, and the upper surface of the interlayer dielectric layer 1004 (see FIG. 11 ), and fills (e.g., completely fills) the second opening 1801 and the first opening 1602.

For example, the fourth dielectric material may be or include a nitride (such as silicon nitride), silicon carbonitride, silicon carbonitride oxide, nitride oxide (such as silicon oxynitride), metal oxide (such as aluminum oxide, yttrium oxide, zirconium oxide, or yttrium oxide), oxide (such as silicon oxide), some other dielectric material, or a combination thereof. The fourth dielectric material has a different chemical composition from the interlayer dielectric layer 1004, so the interlayer dielectric layer 1004 can be selectively etched in subsequent process steps (such as when forming source/drain contacts). In some embodiments, the fourth dielectric material has the same chemical composition as the third dielectric material, such as using the same dielectric material. In other embodiments, the fourth dielectric material has a different chemical composition from the third dielectric material, such as the third dielectric material and the fourth dielectric material are different dielectric materials.

For example, the deposition method of the fourth dielectric material can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, some other deposition process, or a combination thereof. After depositing the fourth dielectric material, a planarization process such as chemical mechanical polishing can be performed on the fourth dielectric material to remove the upper portion of the fourth dielectric material, thereby retaining the lower portion of the fourth dielectric material as the fifth dielectric layer 1902. The planarization process can also remove the interlayer dielectric layer 1004, the first etch stop layer 1002, the first sidewall spacer 702, and the upper portion of the fourth dielectric layer 1506, so that the fifth dielectric layer 1902, the interlayer dielectric layer 1004, the first etch stop layer 1002, the first sidewall spacer 702, and the upper surface of the fourth dielectric layer 1506 are coplanar.

The fifth dielectric layer 1902 separates the first nanostructure field effect transistor 1810a and the second nanostructure field effect transistor 1810b laterally (along the z-axis). In some embodiments, the fifth dielectric layer 1902 improves the electrical insulation between the first nanostructure field effect transistor 1810a and the second nanostructure field effect transistor 1810b, thereby improving device performance. For example, as the structure size continues to shrink (e.g., 3nm or less), the lateral space (along the z-axis) between the first nanostructure field effect transistor 1810a and the second nanostructure field effect transistor 1810b will shrink, which will cause leakage current of the first nanostructure field effect transistor 1810a and the second nanostructure field effect transistor 1810b. The fifth dielectric layer 1902 can reduce the leakage current, thereby improving the device performance of the first nanostructure field effect transistor 1810a and/or the second nanostructure field effect transistor 1810b.

Since the sixth dielectric structure 1806a is located on the second dielectric fin 502b and the seventh dielectric structure 1806b is located on the fourth dielectric fin 502d, the fifth dielectric layer 1902 is formed in a self-aligned manner. For example, when the fourth dielectric material is deposited, the fourth dielectric material will self-align the first sidewall of the sixth dielectric structure 1806a (e.g., the sidewall of the first vertical portion of the sixth dielectric structure 1806a) and the first sidewall of the seventh dielectric structure 1806b (e.g., the sidewall of the second vertical portion of the seventh dielectric structure 1806b). Therefore, the fifth dielectric layer 1902 is formed in a self-aligned manner to self-align the fifth dielectric layer (along the z-axis). Therefore, as the structure size continues to shrink (e.g., 3nm or less), the method described herein can improve the device performance of the first nanostructure field effect transistor 1810a and/or the second nanostructure field effect transistor 1810b.

Although not shown, it should be understood that the interconnect structure can be formed on the first nanostructure field effect transistor 1810a, the second nanostructure field effect transistor 1810b, the interlayer dielectric layer 1004, the fourth dielectric layer 1506, and the fifth dielectric layer 1902 to electrically couple various electronic devices of the semiconductor device 1904 (such as the first nanostructure field effect transistor 1810a, the second nanostructure field effect transistor 1810b, and similar electronic devices) in a predetermined manner. For example, the method for forming the interconnect structure may include: (1) forming a conductive source/drain contact (such as a metal contact) through the interlayer dielectric layer 1004 to the first source/drain region 902 and/or the second source/drain region 904; (2) forming a conductive gate contact (such as a metal contact) through the fourth dielectric layer 1506 and/or the fifth dielectric layer 1902 to the gate structure 1502; (3) forming an additional interlayer dielectric layer stacked on the interlayer dielectric layer; (4) forming conductive lines (such as metal lines) and conductive vias (such as metal vias) in the additional interlayer dielectric layer stack to electrically couple the various electronic devices (such as the first nanostructure field effect transistor 1810a, the second nanostructure field effect transistor 1810b, or the like) of the semiconductor device 1904 in a predetermined manner.

In some embodiments, the source/drain contacts may be formed by a self-aligned contact process. For example, the chemical composition of the fourth dielectric layer 1506 and the fifth dielectric layer 1902 is different from the chemical composition of the interlayer dielectric layer 1004 as described above, so the interlayer dielectric layer 1004 may be selectively etched. In addition, the fourth dielectric layer 1506 and the fifth dielectric layer 1902 cover the gate structure 1502 but not the interlayer dielectric layer 1004, as described above. Therefore, an etching process may be performed to selectively etch the interlayer dielectric layer 1004, thereby forming source/drain contact openings (and/or trenches) in the interlayer dielectric layer 1004 to expose the source/drain region. Thereafter, a conductive material such as tungsten, copper, or the like is filled into the source/drain contact openings (and/or trenches), and a planarization process is performed on the conductive material to level the conductive material as a source/drain region contact. It should be understood that before filling the source/drain contact openings (and/or trenches) with conductive material, a silicide process may be performed to form a silicide layer on the source/drain region exposed by the contact openings (and/or trenches).

Since the etching process selectively etches the interlayer dielectric layer 1004, the etching process will not expose the gate structure 1502 (for example, the fourth dielectric layer 1506 and the fifth dielectric layer 1902 will not be etched to expose the gate structure 1502). Therefore, if the source/drain contact opening (and/or trench) is too large and/or misaligned, the conductive material (or silicide layer) will not be deposited on the gate structure 1502, thereby avoiding electrical short circuit between the gate structure 1502 and the source/drain region (such as the first source/drain region 902 and/or the second source/drain region 904). Instead, a conductive material (and a silicide layer) may be deposited so that the conductive material self-aligns the source/drain region (e.g., the first source/drain region 902 and/or the second source/drain region 904). In summary, the fourth dielectric layer 1506 of some embodiments may be considered as a first self-aligned contact dielectric structure, and the fifth dielectric layer 1902 may be considered as a second self-aligned contact dielectric structure.

In some embodiments, the semiconductor device 1904 (e.g., an integrated circuit) is completed after the interconnect structure is formed. For at least the reasons described above, the space between the first nanostructure field effect transistor 1810a and the second nanostructure field effect transistor 1810b of the semiconductor device 1904 formed by the method described herein is reduced (e.g., the lateral space (along the z-axis) between the second nanostructure stack 1302b and the fifth nanostructure stack 1302e is less than 40nm). In summary, the method described herein can improve production capacity, avoid device failure, or improve device performance, etc. as the structure size continues to shrink (e.g., 3nm or less), as described in detail above.

20A to 20C are various diagrams of a semiconductor device 1904 with reduced space between nanostructure field effect transistors 1810 in some embodiments. FIG. 20A shows a perspective view of a semiconductor device 1904 with reduced space between nanostructure field effect transistors 1810 in some embodiments. FIG. 20B shows a cross-sectional view of the semiconductor device 1904 of FIG. 20A along the section line A-A of FIG. 20A. FIG. 20C shows a cross-sectional view of the semiconductor device 1904 of FIG. 20A along the section line B-B of FIG. 20A.

20A to 20C , the second plurality of dielectric structures 1806 extend laterally (along the x-axis) such that the second plurality of dielectric structures 1806 undercut the lower surface of the corresponding first sidewall spacers 702. For example, the sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) extend laterally (along the x-axis) such that the sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) undercut the lower surface of one of the first sidewall spacers 702 (e.g., the lower surface of one of the first sidewall spacers 702 extending (along the z-axis) between the first source/drain regions 902 of the first pair 902a, the second pair 902b, the fifth pair 902c, and the sixth pair 902d). In some embodiments, the sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) contacts (e.g., directly contacts) the lower surface of one of the first sidewall spacers 702. In other embodiments, the first gate structure 1502a (and the third gate structure 1502c), the second etch stop layer 1504, and the fourth dielectric layer 1506 may undercut the lower surface of one of the first sidewall spacers 702.

In some embodiments, the sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) extend laterally (along the x-axis) between opposing inner sidewalls of the first etch stop layer 1002. For example, the first etch stop layer 1002 has opposing first and second inner sidewalls 2002 and 2004. The first and second inner sidewalls 2002 and 2004 extend along both outer sidewalls of one of the first sidewall spacers 702 (along the y-axis). The sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) extend laterally (along the x-axis) between the first inner sidewall 2002 and the second inner sidewall 2004. In some embodiments, the sixth dielectric structure 1806a (and the seventh dielectric structure 1806b) contacts (such as directly contacts) the first inner sidewall 2002 and the second inner sidewall 2004.

FIG. 21 is a cross-sectional view of the semiconductor device of FIGS. 20A to 20C along the section line B-B of FIG. 20A in some embodiments. In order to make the figure clear, FIG. 21 does not include the labels of some structural features.

As shown in FIG. 21 , the fourth dielectric layer 1506 has a first height H ₁ . In some embodiments, the first height H ₁ is between about 5 nm and about 50 nm. The dielectric fin 502 has a second height H ₂ . The second height H ₂ may be between about 30 nm and about 80 nm. The nanostructure stack 1302 has a third height H ₃ (e.g., the distance between the uppermost surface of the uppermost nanostructure 1304 of the first nanostructure stack 1302a and the lowermost surface of the lowermost nanostructure 1304 of the first nanostructure stack 1302a). The third height H ₃ may be between about 30 nm and about 80 nm. In some embodiments, the third height H ₃ is substantially equal to the second height H ₂ . In some embodiments, the third height _H3 is different from the second height _H2 (eg, the third height _H3 is smaller than the second height _H2 ).

The second plurality of dielectric structures 1806 respectively have a vertical portion 2102 (extending along the y-axis) and a transverse portion 2104 (extending along the z-axis). For example, the sixth dielectric structure 1806a has a first vertical portion 2102a (extending along the y-axis) and a first transverse portion 2104a (extending along the z-axis). The first transverse portion 2104a extends from the first vertical portion 2102a in a first direction (along the z-axis). The seventh dielectric structure 1806b has a second vertical portion 2102b (extending along the y-axis) and a second transverse portion 2104b (extending along the z-axis). The second transverse portion 2104b extends from the second vertical portion 2102b in a second direction (along the z-axis), and the second direction is opposite to the first direction.

The second plurality of dielectric structures 1806 have a fourth height _H4 . The fourth height _H4 corresponds to the height of the vertical portion 2102 of the second plurality of dielectric structures 1806. In some embodiments, the fourth height _H4 is an overall height, such as the distance between the uppermost surface of the sixth dielectric structure 1806a and the lowermost surface of the sixth dielectric structure 1806a. In some embodiments, the ratio between the second height _H2 and the fourth height _H4 is between 3:5 and 16:1. In other embodiments, the ratio between the second height _H2 and the fourth height _H4 is between 8:5 and 6:1. In other embodiments, the fourth height _H4 is between about 5 nm and about 50 nm.

The second plurality of dielectric structures 1806 has a fifth height _H5 . The fifth height _H5 corresponds to the height of the lateral portion 2104 of the second plurality of dielectric structures 1806. In some embodiments, the difference between the fourth height _H4 and the fifth height _H5 is greater than or equal to 3 nm. In other embodiments, the difference between the fourth height _H4 and the fifth height _H5 is between about 3 nm and 47 nm. In other embodiments, the fifth height _H5 is between about 1 Å and about 47 nm.

Nanostructure 1304 has a first width _W1 . In some embodiments, first width _W1 is between about 50 nm and about 150 nm. Nanostructure 1304 has a sixth height _H6 . Sixth height _H6 may be between about 3 nm and about 10 nm. Nanostructures 1304 of nanostructure stack 1302 may be separated from each other by a first distance _D1 between about 3 nm and about 15 nm. In some embodiments, nanostructure stack 1302 may include about 2 to 10 nanostructures 1304.

The second plurality of dielectric structures 1806 have a second width _W2 . In some embodiments, the ratio of the second width _W2 to the fourth height _H4 is between 1:10 and 20:1. In other embodiments, the ratio of the second width _W2 to the first width _W1 is between 1:30 and 1:1. In other embodiments, the second width _W2 is between about 5 nm and about 100 nm.

The fifth dielectric layer 1902 extends (along the y-axis) a second distance _D2 from the lower surface of the recessed dielectric fin 1802 toward the semiconductor substrate 212. In other words, the second distance _D2 corresponds to the distance from the lowermost surface of the fifth dielectric layer 1902 to the lowermost surface of the recessed dielectric fin 1802. In some embodiments, the second distance _D2 is between about 20 nm and about 100 nm.

FIG. 22 is a perspective view of region 2106 of semiconductor device 1904 of FIG. 21 in some embodiments.

As shown in FIG. 22 , the first vertical portion 2102a extends from the second dielectric fin 502b (along the y-axis) to the first gate dielectric structure 1808a. The first lateral portion 2104a extends from the first vertical portion 2102a (along the z-axis). In some embodiments, the sixth dielectric structure 1806a has a first peripheral portion 2202 and a second peripheral portion 2204. The first peripheral portion 2202 is separated from the second peripheral portion 2204 (along the x-axis).

The first vertical portion 2102a extends (along the x-axis) between the first peripheral portion 2202 and the second peripheral portion 2204. The first transverse portion 2104a extends (along the x-axis) between the first peripheral portion 2202 and the second peripheral portion 2204. The first peripheral portion 2202 and the second peripheral portion 2204 are located (e.g., directly below) a lower surface of one of the first sidewall spacers 702. In some embodiments, an outer sidewall of the first peripheral portion 2202 and an outer sidewall of the second peripheral portion 2204 are respectively substantially aligned with an outer sidewall of one of the first sidewall spacers 702. In other embodiments, the outer sidewall of the first peripheral portion 2202 may contact (e.g., directly contact) the second inner sidewall 2004 of the first etch stop layer 1002 (see FIG. 20C ). In other embodiments, the outer sidewall of the second peripheral portion 2204 may contact (e.g., directly contact) the first inner sidewall 2002 of the first etch stop layer 1002 (see FIG. 20C ).

The sixth dielectric structure 1806a has a first upper surface 2208 and a second upper surface 2210. The first upper surface 2208 corresponds to the upper surface of the first vertical portion 2102a. The second upper surface 2210 corresponds to the upper surface of the first horizontal portion 2104a.

The first upper surface 2208 is located on the second upper surface 2210. In some embodiments, the first upper surface 2208 is the uppermost surface of the sixth dielectric structure 1806a. The second upper surface 2210 is located laterally (along the z-axis) between the first upper surface 2208 and the second dielectric fin 502b (see FIG. 21). The first upper surface 2208 is located laterally (along the z-axis) between the second upper surface 2210 and the first gate structure 1502a (see FIG. 21).

The first gate dielectric structure 1808a extends along the first upper surface 2208 of the sixth dielectric structure 1806a. In some embodiments, the first gate dielectric structure 1808a also extends along the first sidewall of the first gate dielectric structure 1808a, the first sidewall of the second dielectric fin 502b, the upper surface of the second fin 210b, the sidewall of the first dielectric fin 502a, the upper surface of the first dielectric fin 502a, and the upper surface of the first fin 210a (see FIG. 20B ). The first sidewall of the first gate dielectric structure 1808a extends vertically (along the y-axis) from the first upper surface 2208 to the second dielectric fin 502b. In some embodiments, the first sidewall of the first gate dielectric structure 1808a is substantially aligned with the first sidewall of the second dielectric fin 502b. In other embodiments, the first gate dielectric structure 1808a extends continuously along the first upper surface 2208, the sidewall of the first gate dielectric structure 1808a, the sidewall of the second dielectric fin 502b, the upper surface of the second fin 210b, the sidewall of the first dielectric fin 502a, the upper surface of the first dielectric fin 502a, and the upper surface of the first fin 210a.

The first gate dielectric structure 1808a has a first sidewall and a second sidewall on both sides. In other words, the second sidewall of the first gate dielectric structure 1808a is laterally separated from the first sidewall (along the z-axis). The second sidewall of the first gate dielectric structure 1808a extends vertically from the first upper surface 2208 to the second upper surface 2210 (along the y-axis). In some embodiments, the second sidewall of the first gate dielectric structure 1808a is substantially aligned with a sidewall of the first gate dielectric structure 1808a.

The third sidewall of the first gate dielectric structure 1808a is opposite to the first sidewall of the first gate dielectric structure 1808a. In other words, the third sidewall of the first gate dielectric structure 1808a is laterally separated from the first sidewall of the first gate dielectric structure 1808a (along the z-axis). The third sidewall of the first gate dielectric structure 1808a extends vertically (along the y-axis) from the second upper surface 2210 to the lower surface of the first gate dielectric structure 1808a (e.g., the lowermost surface of the first gate dielectric structure 1808a that contacts the upper surface of the second dielectric fin 502b). The second upper surface 2210 is laterally located (along the z-axis) between the second sidewall of the first gate dielectric structure 1808a and the third sidewall of the first gate dielectric structure 1808a. In some embodiments, the second upper surface 2210 extends from the third sidewall of the first gate dielectric structure 1808a to the second sidewall of the first gate dielectric structure 1808a. In other embodiments, the third sidewall of the first gate dielectric structure 1808a is substantially aligned with the second sidewall of the second dielectric fin 502b (opposite to the first sidewall of the second dielectric fin 502b), and the first sidewall of the second dielectric fin 502b is laterally separated from the second sidewall (along the z-axis).

In some embodiments, the first upper surface 2208 is higher than the upper surface of the first gate structure 1502a (such as the uppermost surface, see FIG. 21). In other embodiments, the second upper surface 2210 is lower than the upper surface of the first gate structure 1502a (see FIG. 21). The first upper surface 2208 may be higher than the second etch stop layer 1504. The second upper surface 2210 may be lower than the second etch stop layer 1504. Although FIG. 22 shows features (such as structural features) of the sixth dielectric structure 1806a, it should be understood that each of the plurality of dielectric structures may include substantially similar features.

FIG. 23 is a flowchart 2300 of a method for forming a semiconductor device with reduced space between nanostructured field effect transistors in some embodiments. Although the flowchart 2300 shown in FIG. 23 herein shows a series of actions or events, it should be understood that the order in which these actions or events are described is not intended to limit the embodiments. For example, some actions may be performed in a different order and/or some actions may occur with other actions or events other than those shown and/or described herein. In addition, one or more embodiments need not implement all of the actions described herein, and one or more actions described herein may be performed by one or more separate actions and/or methods.

In step 2302, a plurality of nanostructure stacks are formed on a plurality of semiconductor fins, wherein each of the plurality of nanostructure stacks includes a plurality of stacked nanostructures, wherein a plurality of dielectric fins separate the plurality of nanostructure stacks laterally, wherein a first dielectric structure is located on a first dielectric fin of the dielectric fins, and a second dielectric structure is located on a second dielectric fin of the dielectric fins, and wherein a third dielectric fin of the fins is laterally located between the first dielectric fin and the second dielectric fin, and laterally located between the first dielectric structure and the second dielectric structure. A series of diagrams of some embodiments shown in FIGS. 1-13 correspond to step 2302.

In step 2304, a plurality of conductive gate structures are formed on the nanostructure stack, on the semiconductor fin, and around the nanostructure of the nanostructure stack, wherein the first dielectric fin laterally separates the first conductive gate structure and the second conductive gate structure of the conductive gate structure, wherein the second dielectric fin laterally separates the third conductive gate structure and the second conductive gate structure of the conductive gate structure, and wherein the second conductive gate structure is laterally located between the first dielectric fin and the second dielectric fin. A series of cross-sectional views of some embodiments shown in FIGS. 14 and 15 correspond to step 2304.

In step 2306, a first dielectric layer is formed to cover the conductive gate structure, the first dielectric structure, and the second dielectric structure. The cross-sectional views of some embodiments shown in FIG. 15 correspond to step 2306.

In step 2308, a first opening is formed in the first dielectric layer, wherein the first opening overlaps with the second conductive gate structure, partially overlaps with the first dielectric structure, and partially overlaps with the second dielectric structure. The cross-sectional views of some embodiments shown in FIG. 16 correspond to step 2308.

In step 2310, the second conductive gate structure is removed. The cross-sectional views of some embodiments shown in FIG. 17 correspond to step 2310.

In step 2312, a portion of the first dielectric structure and a portion of the second dielectric structure under the first opening are removed to form a third dielectric structure on the first fin and a fourth dielectric structure on the second fin, respectively. The cross-sectional views of some embodiments shown in FIG. 18 correspond to step 2312.

In step 2314, the nanostructure stack under the first opening is removed and the semiconductor fin under the first opening is recessed to form a second opening under the first opening. The cross-sectional views of some embodiments shown in FIG. 18 correspond to step 2314.

In step 2316, a second dielectric layer is formed in the first opening and the second opening, wherein the second dielectric layer at least partially covers the third dielectric structure and the fourth dielectric structure. The cross-sectional views of some embodiments shown in FIG. 19 correspond to step 2316.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a semiconductor fin protruding vertically from a semiconductor substrate. A plurality of semiconductor nanostructures are directly located on the semiconductor fin and stacked vertically. A gate structure is located on the semiconductor fin and surrounds the semiconductor nanostructure. A dielectric fin is located on the semiconductor substrate, wherein the gate structure and the semiconductor nanostructure are located on a first side of the dielectric fin, and wherein the upper surface of the dielectric fin is lower than the upper surface of the gate structure. A dielectric structure is directly located on the dielectric fin, wherein the first upper surface of the dielectric structure is higher than the upper surface of the gate structure. A dielectric layer is at least partially disposed on a semiconductor substrate, wherein the dielectric layer is disposed on the second side of the dielectric fin, and the first side and the second side of the dielectric fin are opposite to each other, wherein the upper surface of the dielectric layer is higher than the upper surface of the gate structure and the first upper surface of the dielectric structure, and wherein the lower surface of the dielectric layer is lower than the upper surface of the dielectric fin.

In some embodiments, the dielectric structure has an L-shaped profile.

In some embodiments, the dielectric structure includes a second upper surface disposed between the first upper surface of the dielectric structure and the upper surface of the dielectric fin.

In some embodiments, the first upper surface of the dielectric structure is laterally located between the second upper surface of the dielectric structure and the gate structure.

In some embodiments, the semiconductor device further includes: a gate dielectric structure located between the gate structure and the semiconductor fin, wherein the gate dielectric structure separates the dielectric fin from the gate structure, and separates the dielectric structure from the gate structure.

In some embodiments, the gate dielectric structure extends continuously along the upper surface of the semiconductor fin, the first sidewall of the dielectric fin, the first sidewall of the dielectric structure, and the first upper surface of the dielectric structure.

In some embodiments, the second sidewall of the dielectric structure is opposite to the first sidewall of the dielectric structure and is substantially aligned with the sidewall of the gate dielectric structure.

In some embodiments, the dielectric structure includes a third sidewall, and the third sidewall of the dielectric structure is opposite to the first sidewall of the dielectric structure; and the second sidewall of the dielectric structure is laterally located between the first sidewall of the dielectric structure and the third sidewall of the dielectric structure.

In some embodiments, the second upper surface of the dielectric structure extends laterally from the third sidewall of the dielectric structure to the second sidewall of the dielectric structure; and the second upper surface of the dielectric structure is vertically located between the first upper surface of the dielectric structure and the upper surface of the dielectric fin.

In some embodiments, the third sidewall of the dielectric structure is substantially aligned with the second sidewall of the dielectric fin, and the second sidewall of the dielectric fin is opposite to the first sidewall of the dielectric fin.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a first semiconductor fin and a second semiconductor fin, which protrude vertically from a semiconductor substrate, wherein the second semiconductor fin is laterally separated from the first semiconductor fin in a first direction, wherein the first semiconductor fin and the second semiconductor fin extend laterally in a second direction and are parallel to each other, and wherein the second direction is substantially perpendicular to the first direction. A first gate structure is located on the first semiconductor fin. A second gate structure is located on the second semiconductor fin and is laterally separated from the first gate structure in the first direction. A first dielectric fin is disposed on the semiconductor substrate, wherein the first dielectric fin is disposed between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure. A second dielectric fin is disposed on the semiconductor substrate and is laterally separated from the first dielectric fin in a first direction, wherein the second dielectric fin is disposed between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure. A first dielectric structure is disposed on the first dielectric fin. A second dielectric structure is disposed on the second dielectric fin and is laterally separated from the first semiconductor fin in the first direction. A dielectric layer is at least partially disposed on a semiconductor substrate, wherein a first dielectric structure laterally separates the dielectric layer from a first portion of a first gate structure, and a second dielectric structure laterally separates the dielectric layer from a first portion of a second gate structure.

In some embodiments, the semiconductor device further includes: a fourth dielectric structure located on the first gate structure and partially covering the first dielectric structure; a fifth dielectric structure located on the second gate structure and partially covering the second dielectric structure, wherein: the dielectric layer is laterally located between the fourth dielectric structure and the fifth dielectric structure; the dielectric layer partially covers the first dielectric structure and the second dielectric structure; and the bottom surface of the dielectric layer is lower than the bottom surface of the fourth dielectric structure and the bottom surface of the fifth dielectric structure.

In some embodiments, the first dielectric structure has an L-shaped profile; and the second dielectric structure has an L-shaped profile.

In some embodiments, the first upper surface of the first dielectric structure is higher than the upper surface of the first gate structure; the second upper surface of the first dielectric structure is located between the first upper surface of the first dielectric structure and the upper surface of the first dielectric fin; the first upper surface of the second dielectric structure is higher than the upper surface of the second gate structure; the second upper surface of the second dielectric structure is located between the first upper surface of the second dielectric structure and the upper surface of the second dielectric fin; and the second upper surface of the first dielectric structure and the second upper surface of the second dielectric structure are laterally located between the first upper surface of the first dielectric structure and the first upper surface of the second dielectric structure.

In some embodiments, the semiconductor device further includes: a plurality of first semiconductor nanostructures stacked vertically, directly located on the first semiconductor fin, wherein the first semiconductor nanostructure extends from the first source/drain region to the second source/drain region in the second direction; and a plurality of second semiconductor nanostructures stacked vertically, directly located on the second semiconductor fin, wherein the second semiconductor nanostructure extends from the third source/drain region to the fourth source/drain region in the second direction, and wherein the third source/drain region and the fourth source/drain region are separated from the first source/drain region and the second source/drain region in the first direction.

In some embodiments, the first gate structure extends around the first semiconductor nanostructure, and the second gate structure extends around the second semiconductor nanostructure.

In some embodiments, the semiconductor device further includes: a third dielectric fin, located on the semiconductor substrate and laterally separated from the first dielectric fin and the second dielectric fin, wherein the third dielectric fin is located between the first dielectric fin and the second dielectric fin, and wherein the upper surface of the third dielectric fin is lower than the upper surface of the first dielectric fin and the upper surface of the second dielectric fin.

In some embodiments, the first dielectric structure extends vertically from the upper surface of the first dielectric fin; and the second dielectric structure extends vertically from the upper surface of the second dielectric fin.

In some embodiments, the dielectric layer covers the third dielectric fin; the first portion of the dielectric layer extends vertically toward the semiconductor substrate between the first dielectric fin and the third dielectric fin; the second portion of the dielectric layer extends vertically toward the semiconductor substrate between the second dielectric fin and the third dielectric fin; the lower surface of the first portion of the dielectric layer is rounded; and the lower surface of the second portion of the dielectric layer is rounded.

Some embodiments of the present invention provide a method for forming a semiconductor device. The method includes receiving a workpiece. The workpiece includes a first dielectric fin, located on a semiconductor substrate and laterally located between a first plurality of semiconductor nanostructures and a second plurality of semiconductor nanostructures; a second dielectric fin, located on the semiconductor substrate and laterally located between a third plurality of semiconductor nanostructures and the second plurality of semiconductor nanostructures; a first conductive gate structure, located on the semiconductor substrate and surrounding the first plurality of semiconductor nanostructures; a second conductive gate structure, located on the semiconductor substrate and surrounding the second plurality of semiconductor nanostructures; a third conductive gate structure, located on the semiconductor substrate and surrounding the first plurality of semiconductor nanostructures; The invention relates to a semiconductor nanostructure, wherein the second conductive gate structure is located between the first conductive gate structure and the third conductive gate structure and is laterally separated from the first conductive gate structure and the third conductive gate structure; the first dielectric structure is directly located on the first dielectric fin, wherein the first dielectric structure and the first dielectric fin laterally separate the first conductive gate structure and the second conductive gate structure; and the second dielectric structure is directly located on the second dielectric fin, wherein the second dielectric structure and the second dielectric fin laterally separate the third conductive gate structure and the second conductive gate structure. A first dielectric layer is formed on a first dielectric fin, a second dielectric fin, a first plurality of semiconductor nanostructures, a second plurality of semiconductor nanostructures, a third plurality of semiconductor nanostructures, a first dielectric structure, a second dielectric structure, a first conductive gate structure, a second conductive gate structure, and a third conductive gate structure. A first opening is formed in the first dielectric layer, wherein the first opening at least partially overlaps with the first dielectric structure, the second dielectric structure, and the second conductive gate structure. The second conductive gate structure is removed. A portion of the first dielectric structure under the first opening is removed to form a third dielectric structure directly on the first dielectric fin. A portion of the second dielectric structure under the first opening is removed to form a fourth dielectric structure directly on the second dielectric fin. The second plurality of semiconductor nanostructures are removed to form a second opening under the first opening. A second dielectric layer is formed in the first opening and the second opening, and at least partially covers the third dielectric structure and the fourth dielectric structure.

The features of the above embodiments are helpful for those with ordinary knowledge in the art to understand the present invention. Those with ordinary knowledge in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and/or the same advantages of the above embodiments. Those with ordinary knowledge in the art should also understand that these equivalent substitutions do not deviate from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

2300: Flowchart

2302,2304,2306,2308,2310,2312,2314,2316: Steps

Claims (10)

A semiconductor device includes: a semiconductor fin protruding vertically from a semiconductor substrate; a plurality of semiconductor nanostructures directly located on the semiconductor fin and stacked vertically; a gate structure located on the semiconductor fin and surrounding the semiconductor nanostructures; a dielectric fin located on the semiconductor substrate, wherein the gate structure and the semiconductor nanostructures are located on a first side of the dielectric fin, and wherein an upper surface of the dielectric fin is lower than an upper surface of the gate structure; A dielectric structure directly located on the dielectric fin, wherein the first upper surface of the dielectric structure is higher than the upper surface of the gate structure; and a dielectric layer at least partially located on the semiconductor substrate, wherein the dielectric layer is located on the second side of the dielectric fin, and the first side and the second side of the dielectric fin are opposite, wherein the upper surface of the dielectric layer is higher than the upper surface of the gate structure and the first upper surface of the dielectric structure, and wherein the lower surface of the dielectric layer is lower than the upper surface of the dielectric fin. A semiconductor device as claimed in claim 1, wherein the dielectric structure has an L-shaped profile. A semiconductor device comprises: a first semiconductor fin and a second semiconductor fin protruding vertically from a semiconductor substrate, wherein the second semiconductor fin is laterally separated from the first semiconductor fin in a first direction, wherein the first semiconductor fin and the second semiconductor fin extend laterally and parallel to each other in a second direction, and wherein the second direction is substantially perpendicular to the semiconductor substrate. the first direction; a first gate structure located on the first semiconductor fin; a second gate structure located on the second semiconductor fin and laterally separated from the first gate structure in the first direction; a first dielectric fin located on the semiconductor substrate, wherein the first dielectric fin is located between the first semiconductor fin and the second semiconductor fin, and the first a second dielectric fin disposed on the semiconductor substrate and laterally separated from the first dielectric fin in the first direction, wherein the second dielectric fin is disposed between the first semiconductor fin and the second semiconductor fin, and between the first gate structure and the second gate structure; a first dielectric structure disposed between the first dielectric fin and the second gate structure a second dielectric structure located on the second dielectric fin and laterally separated from the first semiconductor fin in the first direction; and a dielectric layer at least partially located on the semiconductor substrate, wherein the first dielectric structure laterally separates the dielectric layer from a first portion of the first gate structure, and the second dielectric structure laterally separates the dielectric layer from a first portion of the second gate structure. The semiconductor device of claim 3 further includes: a fourth dielectric structure located on the first gate structure and partially located on the first dielectric structure; a fifth dielectric structure located on the second gate structure and partially located on the second dielectric structure, wherein: the dielectric layer is laterally located between the fourth dielectric structure and the fifth dielectric structure; the dielectric layer is partially located on the first dielectric structure and the second dielectric structure; and the bottom surface of the dielectric layer is lower than the bottom surface of the fourth dielectric structure and the bottom surface of the fifth dielectric structure. A semiconductor device includes: a plurality of first semiconductor nanostructures located on a first semiconductor fin; a plurality of second semiconductor nanostructures located on a second semiconductor fin; a first gate structure located on the first semiconductor fin and around the first semiconductor nanostructures; a second gate structure located on the second semiconductor fin and around the second semiconductor nanostructures; The invention relates to a semiconductor nanostructure having a first dielectric fin disposed around the semiconductor nanostructure; a first dielectric fin disposed laterally between the first semiconductor nanostructure and the second semiconductor nanostructure; a second dielectric fin disposed laterally between the first semiconductor nanostructure and the second semiconductor nanostructure; a first dielectric structure disposed on the first dielectric fin, wherein the first dielectric structure has a first L-shaped profile; and a second a dielectric structure located on the second dielectric fin, wherein the second dielectric structure has a second L-shaped profile, and wherein the first L-shaped profile and the second L-shaped profile face opposite directions; and a dielectric layer laterally separating the first dielectric fin from the second dielectric fin, laterally separating the first gate structure from the second gate structure, and laterally separating the first dielectric structure from the second dielectric junction. The dielectric layer vertically extends from the lower surface of the dielectric layer to the upper surface of the dielectric layer, wherein the lower surface of the dielectric layer is lower than the upper surface of the first semiconductor fin, wherein the upper surface of the dielectric layer is higher than the first dielectric structure, and wherein the first dielectric structure laterally separates the dielectric layer and the first gate structure, and the second dielectric structure laterally separates the dielectric layer and the second gate structure. A method for forming a semiconductor device includes: receiving a workpiece, wherein the workpiece includes: a dielectric fin located on a semiconductor substrate and between a plurality of first semiconductor nanostructures and a plurality of second semiconductor nanostructures; a first conductive gate structure located on the semiconductor substrate and around the first semiconductor nanostructures; a second conductive gate structure located on the semiconductor substrate and around the second semiconductor nanostructures; and a dielectric fin cap located on the dielectric fin, wherein the dielectric fin cap and the dielectric fin are laterally located between the first conductive gate structure and the second conductive gate structure, and wherein the first conductive gate The upper surface of the first conductive gate structure and the upper surface of the second conductive gate structure are vertically located between the first upper surface of the dielectric fin cap and the semiconductor substrate; a dielectric layer is formed on the dielectric fin, the first semiconductor nanostructures, the second semiconductor nanostructures, the first conductive gate structure, the second conductive gate structure, and the dielectric fin cap; a first opening is formed in the dielectric layer, wherein the first opening is partially located on the dielectric fin cap and the second conductive gate structure; and a first etching process is performed to remove the second conductive gate structure, and the first etching process exposes the second conductive gate structure to a first etchant through the first opening. The method for forming a semiconductor device as claimed in claim 6 further includes: after removing the second conductive gate structure, performing a second etching process to remove the second semiconductor nanostructures, and the second etching process exposes the second semiconductor nanostructures to a second etchant through the first opening, wherein the second etching process removes the first portion of the dielectric fin cap, and wherein the second etching process forms a second opening within the outer boundary of the first opening. A method for forming a semiconductor device includes: forming a first stacked semiconductor structure on a first semiconductor fin; forming a second stacked semiconductor structure on a second semiconductor fin; forming a dielectric fin, which is laterally located between the first stacked semiconductor structure and the second stacked semiconductor structure; forming a dielectric tape structure on the dielectric fin, and the dielectric tape structure is laterally located between the first stacked semiconductor structure and the second stacked semiconductor structure; removing the dielectric tape structure; A portion of the first stacked semiconductor structure is removed to form a third stacked semiconductor structure; a portion of the second stacked semiconductor structure is removed to form a fourth stacked semiconductor structure; a portion of the dielectric tape structure is removed to form a dielectric structure on the dielectric fin, and the dielectric structure is laterally located between the third stacked semiconductor structure and the fourth stacked semiconductor structure; the third stacked semiconductor structure and the fourth stacked semiconductor structure are etched to form a first nanostructure stack The method further comprises forming a first gate structure on the first semiconductor fin, and forming a second nanostructure stack on the second semiconductor fin; forming a gate layer on the first semiconductor fin, on the second semiconductor fin, on the dielectric fin, on the dielectric structure, around the first nanostructure stack, and around the second nanostructure stack; making the gate layer recessed to a level lower than the upper surface of the dielectric structure to form a first gate structure around the first nanostructure stack and on the first side of the dielectric structure, and forming a A second gate structure is formed around the second nanostructure stack and on the second side of the dielectric structure, and the first side of the dielectric structure is opposite to the second side; a dielectric layer is formed on the first gate structure, the second gate structure, the dielectric fin, and the dielectric structure; an opening is formed in the dielectric layer, wherein the opening is located on the dielectric structure and the second gate structure; and after forming the opening in the dielectric layer, the second gate structure is removed, wherein the opening is used to remove the second gate structure. A method for forming a semiconductor device as claimed in claim 8, wherein the step of removing the second gate structure using the opening includes: performing an etching process that exposes the second gate structure to an etchant through the opening. A method for forming a semiconductor device includes: receiving a workpiece, wherein the workpiece includes: a first dielectric fin, located on a semiconductor substrate and laterally located between a plurality of first semiconductor nanostructures and a plurality of second semiconductor nanostructures; a second dielectric fin, located on the semiconductor substrate and laterally located between a plurality of third semiconductor nanostructures and the second semiconductor nanostructures; a first conductive gate structure, located on the semiconductor substrate and surrounding the first semiconductor nanostructures; a second conductive gate structure, located on the semiconductor substrate and surrounding the second semiconductor nanostructures; a third conductive gate structure located on the semiconductor substrate and surrounding the third semiconductor nanostructures, wherein the second conductive gate structure is located between the first conductive gate structure and the third conductive gate structure and is laterally separated from the first conductive gate structure and the third conductive gate structure; a first dielectric structure located on the first dielectric fin, wherein the first dielectric structure and the first dielectric fin laterally separate the first conductive gate structure and the second conductive gate structure; and a second dielectric structure located on the second dielectric fin, wherein the second The third conductive gate structure and the second conductive gate structure are laterally separated by the dielectric structure and the second dielectric fin; a first dielectric layer is formed on the first dielectric fin, the second dielectric fin, the first semiconductor nanostructures, the second semiconductor nanostructures, the third semiconductor nanostructures, the first dielectric structure, the second dielectric structure, the first conductive gate structure, the second conductive gate structure, and the third conductive gate structure; a first opening is formed in the first dielectric layer, wherein the first opening is at least partially located between the first dielectric structure, the second dielectric structure, and the third conductive gate structure. structure, and the second conductive gate structure; removing the second conductive gate structure; removing a portion of the first dielectric structure under the first opening to form a third dielectric structure on the first dielectric fin; removing a portion of the second dielectric structure under the first opening to form a fourth dielectric structure on the second dielectric fin; removing the second semiconductor nanostructures to form a second opening under the first opening; and forming a second dielectric layer in the first opening and the second opening, and at least partially on the third dielectric structure and the fourth dielectric structure.