TWI863851B - High Voltage Boost DC Converter with Dual On-Ratio Control - Google Patents

Abstract

A high step-up DC converter with dual conduction ratio control includes a first inductor, a second inductor, a first switch, a second switch, a third switch, a first diode, a second diode, a third diode, a fourth diode, a first capacitor, a second capacitor, and a third capacitor. The first switch and the second switch are controlled to be synchronously turned on or off. The third switch is controlled to be turned on or off. Through the circuit architecture of the present invention, in conjunction with the design of separately controlling the synchronous switching of the first switch and the second switch and controlling the third switch, the present invention can achieve high voltage gain with the design freedom of dual conduction ratios, thereby avoiding the disadvantages caused by operating at a high conduction ratio.

Description

High Voltage Boost DC Converter with Dual On-Ratio Control

The present invention relates to a voltage converter, in particular to a high voltage boost DC converter.

Figure 1 shows a conventional boost converter. Under ideal conditions, the voltage gain of the conventional boost converter is , _Vo is the output voltage, _Vin is the input voltage, and D is the switch duty ratio. In other words, as long as the known boost converter is operated at a very large duty ratio close to 1, a high voltage gain can be obtained.

However, in practice, due to the influence of parasitic elements, when the known boost converter operates at a conduction ratio of more than 0.9, the voltage gain decreases instead of increases, and it is difficult to achieve a voltage gain of 10 times. In addition, due to the large peak current of each power element, there is also the problem of large conduction loss. Therefore, how to develop a boost converter with high voltage gain without operating at a high conduction ratio is the direction that the industry is committed to researching.

Therefore, an object of the present invention is to provide a high boost DC converter with dual conduction ratio control that can improve at least one disadvantage of the prior art.

Therefore, the high boost DC converter with dual conduction ratio control of the present invention is suitable for boosting a DC input voltage to generate a DC output voltage, and includes a first inductor, a second inductor, a first switch, a second switch, a third switch, a first diode, a second diode, a third diode, a fourth diode, a first capacitor, a second capacitor, and a third capacitor.

The first inductor has a first end for receiving the DC input voltage, and a second end. The second inductor has a first end, and a second end connected to ground. The first switch has a first end electrically connected to the second end of the first inductor, a second end connected to ground, and a control end for receiving a first control signal, and the first switch is controlled by the first control signal to be turned on or off. The second switch has a first end electrically connected to the first end of the first inductor, a second end electrically connected to the first end of the second inductor, and a control end for receiving a second control signal that is the same as the first control signal, and the second switch is controlled by the second control signal to be turned on or off synchronously with the first switch. The third switch has a first end, a second end electrically connected to the first end of the second inductor, and a control end for receiving a third control signal, and the third switch is controlled by the third control signal to be turned on or off.

The first diode has an anode electrically connected to the second end of the first inductor, and a cathode. The second diode has an anode electrically connected to the cathode of the first diode, and a cathode. The third diode has an anode electrically connected to the cathode of the second diode, and a cathode. The fourth diode has an anode electrically connected to the second end of the first inductor, and a cathode electrically connected to the first end of the third switch. The first capacitor has a first end electrically connected to the cathode of the first diode and providing a first capacitor voltage, and a second end electrically connected to the first end of the second inductor. The second capacitor has a first end electrically connected to the cathode of the second diode, and a second end electrically connected to the anode of the first diode. The third capacitor has a first end electrically connected to the cathode of the third diode and providing a third capacitor voltage, and a second end electrically connected to the first end of the first capacitor. The sum of the first capacitor voltage and the third capacitor voltage is used as the DC output voltage.

The effect of the present invention is that through the circuit structure of the present invention, in conjunction with the design of separately controlling the synchronous switching of the first switch and the second switch and controlling the third switch, the present invention can achieve high voltage gain with the design freedom of dual conduction ratios, thereby avoiding the disadvantages caused by operating at a high conduction ratio.

Referring to FIG. 2 , an embodiment of the high boost DC converter with dual conduction ratio control of the present invention is suitable for receiving a DC input voltage V _i and boosting the DC input voltage V _i to generate a DC output voltage V _o , and outputting the DC output voltage V _o to a load R _o . The high boost DC converter with dual conduction ratio control includes a first inductor _L1 , a second inductor _{L2, a first switch S1 ,} a second switch S2, a third switch _S3 , a first diode _D1 , a second diode _D2 , a third diode _D3 , a fourth diode _{D4 ,} a first capacitor _C1 , a second capacitor _C2 , a third capacitor _C3 , and a control unit 2.

The first inductor _L1 has a first terminal for receiving the DC input voltage V _i and a second terminal. The second inductor _L2 has a first terminal and a second terminal connected to the ground.

The first switch _S1 has a first end electrically connected to the second end of the first inductor _L1 , a second end grounded, and a control end receiving a first control signal _Vgs1 . The first switch _S1 is controlled by the first control signal _Vgs1 to be turned on or off, and the conduction ratio of the first switch _S1 is _d1 . The second switch _S2 has a first end electrically connected to the first end of the first inductor _L1 , a second end electrically connected to the first end of the second inductor _L2 , and a control end receiving a second control signal _Vgs2 that is the same as the first control signal _Vgs1 . The second switch _S2 is controlled by the second control signal _Vgs2 to be turned on or off synchronously with the first switch _S1 , and the conduction ratio of the second switch _S2 is the same as the conduction ratio of the first switch _S1, both being _d1 .

The third switch _S3 has a first terminal, a second terminal electrically connected to the first terminal of the second inductor _L2 , and a control terminal receiving a third control signal _Vgs3 . The third switch _S3 is controlled by the third control signal _Vgs3 to be turned on or off. In this embodiment, the third switch _S3 starts to be turned on when the first switch _S1 and the second switch _S2 are turned off synchronously with each other, and the conduction ratio of the third switch _S3 is _d2 .

The first switch S ₁ , the second switch S ₂ , and the third switch S ₃ are each an N-type power semiconductor transistor, and the drain, source, and gate of the N-type power semiconductor transistor are the first end, the second end, and the control end of each of the first switch S ₁ , the second switch S ₂ , and the third switch S ₃ .

The first diode _D1 has an anode electrically connected to the second end of the first inductor _L1 , and a cathode. The second diode _D2 has an anode electrically connected to the cathode of the first diode _D1 , and a cathode. The third diode _D3 has an anode electrically connected to the cathode of the second diode _D2 , and a cathode. The fourth diode _D4 has an anode electrically connected to the second end of the first inductor _L1 , and a cathode electrically connected to the first end of the third switch _S3 .

The first capacitor _C1 has a first end electrically connected to the cathode of the first diode _D1 and providing a first capacitor voltage, and a second end electrically connected to the first end of the second inductor _L2 . The second capacitor _C2 has a first end electrically connected to the cathode of the second diode _D2 , and a second end electrically connected to the anode of the first diode _D1 . The third capacitor _C3 has a first end electrically connected to the cathode of the third diode _D3 and providing a third capacitor voltage, and a second end electrically connected to the first end of the first capacitor _C1 . The sum of the first capacitor voltage and the third capacitor voltage is used as the DC output voltage _V0 .

The control unit 2 generates a first control signal _Vgs1 for switching the first switch _S1 , a second control signal _Vgs2 for switching the second switch _S2 , and a third control signal _Vgs3 for switching the third switch _S3 . The first control signal _Vgs1 , the second control signal _Vgs2 , and the third control signal _Vgs3 have the same switching period _Ts . In this embodiment, a falling edge of each square wave of the first control signal _Vgs1 corresponds to a rising edge of each square wave of the third control signal _Vgs3 (FIG. 3, FIG. 4).

3 and 4, which are respectively operation timing diagrams of the present embodiment in continuous conduction mode (CCM) and discontinuous conduction mode (DCM), wherein parameters _Vgs1 , _Vgs2 , and _Vgs3 respectively represent the first to third control signals _Vgs1 - _Vgs3 for controlling whether the first switch _S1 , the second switch _S2, and the third switch _S3 are turned on, parameter _Ts is the switching period of the first control signal _Vgs1 , parameters _VL1 , _VL2 respectively represent the voltage across the first inductor _L1 and the second inductor _L2 , parameters _iL1 , _iL2 respectively represent the current flowing through the first inductor _L1 and the second inductor _L2 , parameters _VD1 , _VD2 , V _D3 represents the voltage across the first diode _D1 , the second diode _D2 and the third diode _D3, respectively. Parameters i _D1 , i _D2 and i _D3 represent the current flowing through the first diode _D1 , the second diode _D2 and the third diode _D3 , respectively. Parameter t represents time.

It should be noted that the following description is based on the following assumptions: 1. All power semiconductor components are considered ideal, that is, the conduction voltage drops of the first to third switches S ₁ ~S ₃ and the first to fourth diodes D ₁ ~D ₄ are all zero; 2. The capacitance of the first to third capacitors C ₁ ~C ₃ is large enough, and the voltage of each capacitor can be regarded as a constant in a switching cycle; 3. The inductance of the first inductor L ₁ and the second inductor L ₂ are the same (that is, L ₁₌ L ₂₌ L); 4. The first switch S ₁ and the second switch S ₂ operate synchronously, and the conduction ratio is d ₁ , and the third switch S ₃ starts to conduct when the first switch S ₁ and the second switch S ₂ are switched from conduction to non-conduction, and the conduction ratio of the third switch S ₃ is d ₂ .

Referring to FIG. 5 to FIG. 7 , the present embodiment operates cyclically from the first stage to the third stage in the continuous conduction mode. The circuit diagrams of FIG. 5 to FIG. 7 are similar to FIG. 2 , except that in FIG. 5 to FIG. 7 , the conducting components are drawn with solid lines, while the non-conducting components are drawn with dashed lines, and the actual current flow in the circuit is further illustrated with solid lines with arrows. The following describes each stage separately, and the parameter ON indicates that the component is conducting, and the parameter OFF indicates that the component is not conducting.

The first stage (time point: t ₀ ~t ₁ ):

3 and 5 , the first switch S ₁ : ON, the second switch S ₂ : ON, the third switch S ₃ : OFF, the first diode D ₁ : OFF, the second diode D ₂ : ON, the third diode D ₃ : OFF, and the fourth diode D ₄ : OFF.

In the first stage, the first switch _S1 and the second switch _S2 are both switched on, and the third switch _S3 is not switched on. At this time, the first inductor _L1 and the second inductor _L2 are connected in parallel and across the DC input voltage V _i , so that the currents i _L1 and i _L2 both rise linearly with a slope = V _i /L. From the energy point of view, the first inductor _L1 and the second inductor _L2 store energy in parallel in this stage. In addition, the DC input voltage V _i , the second switch S ₂ , the first capacitor C ₁ , the second diode D ₂ , the second capacitor C ₂ and the first switch S ₁ form a loop, so that the second capacitor C ₂ is charged, and the first capacitor C ₁ and the third capacitor C ₃ provide power to the load R _o . In this phase,

When t= _t1 , the first switch _S1 and the second switch _S2 are both switched to non-conducting state, and the third switch _S3 is switched to conducting state, and this phase ends.

The second stage (time point: t ₁ ~t ₂ ):

3 and 6 , the first switch S ₁ : OFF, the second switch S ₂ : OFF, the third switch S ₃ : ON, the first diode D ₁ : OFF, the second diode D ₂ : OFF, the third diode D ₃ : OFF, and the fourth diode D ₄ : ON.

In the second stage, the first switch _S1 and the second switch _S2 are both non-conductive, and the third switch _S3 remains conductive. At this time, the DC input voltage _Vi , the first inductor _L1 , the fourth diode _D4 , the third switch _S3 and the second inductor _L2 form a loop, so that the voltage _VL1 of the first inductor _L1 and the voltage _VL2 of the second inductor _L2 are both _Vi /2, so the currents _iL1 and _iL2 both rise linearly with a slope of _Vi /2L. From an energy point of view, the first inductor _L1 and the second inductor _L2 continue to store energy in series in this stage. In addition, the first capacitor _C1 and the third capacitor _C3 provide power to the load _Ro . In this stage,

When t= _t2 , the third switch _S3 is switched to non-conducting state, and this phase ends.

The third stage (time point: t ₂ ~t ₃ ):

3 and 7 , the first switch S ₁ is OFF, the second switch S ₂ is OFF, the third switch S ₃ is OFF, the first diode D ₁ is ON, the second diode D ₂ is OFF, the third diode D ₃ is ON, and the fourth diode D ₄ is OFF.

In the third stage, the first switch _S1 , the second switch _S2 and the third switch _S3 are all non-conductive. At this time, the DC input voltage V _i , the first inductor L ₁ , the first diode D ₁ , the first capacitor C ₁ and the second inductor L ₂ form a loop, so that the voltage V _L1 of the first inductor L ₁ and the voltage V _L2 of the second inductor L ₂ are both (V _i -V _C1 )/2, so the currents i _L1 and i _L2 both decrease linearly with a slope of (V _i -V _C1 )/2L. From the energy point of view, the first and second inductors L ₁ and L ₂ release energy in series in this stage, and the first capacitor C ₁ is charged. In this stage,

In addition, the DC input voltage V _i , the first inductor L ₁ , the second capacitor C ₂ , the third diode D ₃ , the third capacitor C ₃ , the first capacitor C ₁ and the second inductor L ₂ form a loop.

When t= _t3 , the first switch _S1 and the second switch _S2 are both switched on, and the third switch _S3 remains off, and this phase ends and enters the next switching cycle.

Referring to FIG. 5 to FIG. 8 , the present embodiment operates cyclically from the first stage to the fourth stage in the discontinuous conduction mode. The circuit diagrams of FIG. 5 to FIG. 8 are similar to FIG. 2 , except that in FIG. 5 to FIG. 8 , the conducting components are drawn with solid lines, while the non-conducting components are drawn with dashed lines, and the actual current flow in the circuit is further illustrated with solid lines with arrows. The following describes each stage separately, and the parameter ON indicates that the component is conducting, and the parameter OFF indicates that the component is not conducting.

The first stage (time point: t ₀ ~t ₁ ):

Referring to Figures 4 and 5, the operating principle of this stage is the same as the first stage in continuous conduction mode. In this stage,

When t= _t1 , the first switch _S1 and the second switch _S2 are both switched to non-conducting state, and the third switch _S3 is switched to conducting state, and this phase ends.

The second stage (time point: t ₁ ~t ₂ ):

Referring to Figure 4 and Figure 6, the operating principle of this stage is the same as the second stage in continuous conduction mode. In this stage,

When t= _t2 , the third switch _S3 is switched to non-conducting state, and this phase ends.

The third stage (time point: t ₂ ~t ₃ ):

Referring to FIG. 4 and FIG. 7 , the operating principle of this stage is the same as the third stage in the continuous conduction mode. In this stage, when t=t ₃ , the current i _L1 of the first inductor L ₁ and the current i _L2 of the second inductor L ₂ drop to 0, and the first diode D ₁ is turned off by zero current switching (ZCS), and this stage ends.

The fourth stage (time point: t ₃ ~t ₄ ):

4 and 8 , the first switch S ₁ : OFF, the second switch S ₂ : OFF, the third switch S ₃ : OFF, the first diode D ₁ : OFF, the second diode D ₂ : OFF, the third diode D ₃ : OFF, and the fourth diode D ₄ : OFF.

The current i _L1 of the first inductor L ₁ and the current i _L2 of the second inductor L ₂ are equal to 0. The first capacitor C ₁ and the third capacitor C ₃ are discharged to the load R _o , and the load current .

When t= _t4 , the first switch _S1 and the second switch _S2 are switched on, the current phase ends, and the next switching cycle begins.

《Voltage Gain Analysis in Continuous Conduction Mode》

Applying the volt-second balance principle to the first inductor _L1 and the second inductor _L2 , we can obtain:

,in, represents the inductor voltage in the first stage, represents the inductor voltage in the second stage, Represents the inductor voltage in the third stage.

Substitute the inductor voltage of each operating mode into

The voltages of the first capacitor C ₁ , the second capacitor C ₂ , and the third capacitor C ₃ are respectively as follows:

Another reason , can be obtained

Therefore, in continuous conduction mode, the voltage gain M _CCM is

From the above formula, it can be seen that the voltage gain M _CCM has two design freedoms of the conduction ratio d ₁ and d ₂ , and the operating condition is d ₁ +d ₂ <1. Referring to Figures 9 and 10, the voltage gain corresponds to the conduction ratio d ₁ and d ₂ when the embodiment operates in the continuous conduction mode. Figure 9 is a curve showing the relationship between the voltage gain M _CCM and the conduction ratio d ₂ when the conduction ratio d ₁ is at different constant values; on the other hand, Figure 10 is a curve showing the relationship between the voltage gain M _CCM and the conduction ratio d ₁ when the conduction ratio d ₂ is at different constant values.

《Voltage Gain Analysis in Discontinuous Conduction Mode》

Applying the volt-second balance theorem to the first inductor _L1 and the second inductor _L2 , we can obtain:

, where d ₃ is the time/switching period during which the first to third switches S ₁ ~S ₃ are simultaneously non-conductive, represents the inductor voltage in the first stage, represents the inductor voltage in the second stage, Represents the inductor voltage in the third stage.

Substitute the inductor voltage of each operating mode into

Arrangement available

(1)

From the analysis of the second stage of discontinuous conduction mode, we can get

In conjunction with FIG11 and using the node current method, the current i _D1 of the first diode _D1 can be obtained as

Apply the amp-second balance principle: In steady state, the average current of the capacitor is zero, that is, , we can get:

As shown in FIG11 , the average current i _D1 of the first diode _D1 is

Substitute into equation (1) and use the normalized inductor time constant: , we can get:

, and d ₁ +d ₂ ＜1.

From the above formula, it can be seen that when the present embodiment operates in the discontinuous conduction mode, the voltage gain is the normalized inductor time constant and the function of the conduction ratio _d1 and _d2 . If the following parameters are taken as an example, , , , through calculation, we can get , the voltage gain is determined by the conduction ratio _d1 and _d2 .

《Voltage Stress Analysis of Switches and Diodes》

According to the operating principle analysis in the continuous conduction mode, the voltage stress of the first switch S ₁ , the second switch S ₂ , and the third switch S ₃ is:

The voltage stress of the first diode D ₁ , the second diode D ₂ , and the third diode D ₃ is

The voltage stress of the power switch and diode of the conventional boost converter is the output voltage, while the voltage stress of the first to third switches _S1 - _S3 and the first to third diodes _D1 - _D3 of the present embodiment is less than the DC output voltage _V0 . In high output voltage applications, power semiconductor transistors with low rated withstand voltage and low RDS _(ON) can be used to reduce switch conduction loss. In addition, diodes with lower voltage stress can use diodes with lower conduction voltage drop, which can reduce conduction loss and improve conversion efficiency.

In summary, through the circuit architecture of the present invention, in conjunction with the design of separately controlling the synchronous switching of the first switch _S1 and the second switch _S2 , and controlling the third switch _S3 , the present invention can achieve high voltage gain with the design freedom of dual conduction ratios, thereby avoiding the disadvantages caused by operating at a high conduction ratio, and thus can truly achieve the purpose of the present invention.

In addition, since the voltage stress of the first to third switches S ₁ -S ₃ is much lower than the DC output voltage V _o , power semiconductor transistors with smaller on-resistance can be used to reduce conduction loss. In addition, since the voltage stress of the first to third diodes D ₁ -D ₃ is much lower than the DC output voltage V _o , diodes with smaller on-voltage drop can also be used to reduce conduction loss.

However, the above is only an embodiment of the present invention and should not be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the present patent.

_L1 : first inductor _L2 : second inductor _S1 : first switch _S2 : second switch _S3 : third switch _D1 : first diode _D2 : second diode _D3 : third diode _D4 : fourth diode _C1 : first capacitor _C2 : second capacitor _C3 : third capacitor R _o : load V _i : DC input voltage V _o : DC output voltage i _L1 : current of first inductor i _L2 : current of second inductor i _{D1: current of first diode i D2 :} current of second diode i _D3 : current of third diode V _gs1 : first control signal V _gs2 : second control signal V _gs3 : third control signal V _L1 : voltage of first inductor V _L2 : Voltage of the second inductor V _D1 : Voltage of the first diode V _D2 : Voltage of the second diode V _D3 : Voltage of the third diode t: Time t ₀ ~t ₄ : Time point T _s : Switching period d ₁ : Conductivity ratio of the first and second switches d ₂ : Conductivity ratio of the third switch 2: Control unit

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: FIG. 1 is a circuit diagram of a known boost converter; FIG. 2 is a circuit diagram illustrating an embodiment of the high boost DC converter with dual conduction ratio control of the present invention; FIG. 3 is a timing diagram illustrating the operation of the embodiment in continuous conduction mode; FIG. 4 is a timing diagram illustrating the operation of the embodiment in discontinuous conduction mode; FIGS. 5 to 8 are equivalent circuit diagrams illustrating the operation of the embodiment in the first stage to the fourth stage, respectively; FIG. 9 is a curve diagram illustrating the relationship between different conduction ratios and voltage gain when the embodiment operates in continuous conduction mode; FIG. 10 is a curve diagram illustrating the relationship between different conduction ratios and voltage gain when the embodiment operates in the continuous conduction mode; and FIG. 11 is a timing diagram illustrating the current waveform of a first diode when the embodiment operates in the discontinuous conduction mode.

L ₁ : First inductor

L ₂ : Second inductor

S ₁ : First switch

S ₂ : Second switch

S ₃ : The third switch

D ₁ : First diode

D ₂ : Second diode

D ₃ : The third diode

D ₄ : Fourth diode

C ₁ : First capacitor

C ₂ : Second capacitor

C ₃ : The third capacitor

R _o : Load

V _i : DC input voltage

V _o : DC output voltage

2: Control unit

Claims (6)

A high boost DC converter with dual conduction ratio control is suitable for boosting a DC input voltage to generate a DC output voltage, and includes: a first inductor having a first end for receiving the DC input voltage and a second end; a second inductor having a first end and a second end connected to ground; a first switch having a first end electrically connected to the second end of the first inductor, a second end connected to ground, and a control end for receiving a first control signal, the first switch being controlled by the first control signal to conduct or not conduct; a second switch having a first end electrically connected to the first end of the first inductor, a second end electrically connected to the first end of the second inductor, and a control end for receiving a second control signal identical to the first control signal, the second switch being controlled by the second control signal to conduct or not conduct synchronously with the first switch; A third switch having a first end, a second end electrically connected to the first end of the second inductor, and a control end receiving a third control signal, the third switch being controlled by the third control signal to be turned on or off; A first diode having an anode electrically connected to the second end of the first inductor, and a cathode; A second diode having an anode electrically connected to the cathode of the first diode, and a cathode; A third diode having an anode electrically connected to the cathode of the second diode, and a cathode; A fourth diode having an anode electrically connected to the second end of the first inductor, and a cathode electrically connected to the first end of the third switch; A first capacitor having a first end electrically connected to the cathode of the first diode and providing a first capacitor voltage, and a second end electrically connected to the first end of the second inductor; A second capacitor having a first end electrically connected to the cathode of the second diode, and a second end electrically connected to the anode of the first diode; and A third capacitor having a first end electrically connected to the cathode of the third diode and providing a third capacitor voltage, and a second end electrically connected to the first end of the first capacitor, the sum of the first capacitor voltage and the third capacitor voltage is used as the DC output voltage. A high boost DC converter with dual conduction ratio control as described in claim 1, wherein a falling edge of each square wave of the first control signal corresponds to a rising edge of each square wave of the third control signal. A high boost DC converter with dual conduction ratio control as described in claim 2, wherein a voltage gain of the high boost DC converter with dual conduction ratio control is (3+d ₁ -d ₂ )/(1-d ₁ -d ₂ ), d ₁ is the conduction ratio of the first and second switches, and d ₂ is the conduction ratio of the third switch. A high-voltage step-up DC converter with dual conduction ratio control as described in claim 1, wherein the first switch, the second switch and the third switch are each an N-type power semiconductor transistor. The high boost DC converter with dual conduction ratio control as described in claim 1 further includes a control unit, which can be controlled to generate the first control signal, the second control signal, and the third control signal, and the first control signal, the second control signal, and the third control signal have the same period. A high step-up DC converter with dual conduction ratio control as described in claim 1, wherein the inductance value of the first inductor is the same as the inductance value of the second inductor.

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