TWI863635B - Microcontroller circuit, control method and operating system - Google Patents

Abstract

A microcontroller circuit including a memory, an image processing circuit, a first register, a second register, a control circuit, and a display circuit is provided. The memory includes a first storage space and a second storage space. The image processing circuit writes first image data to the first storage space and writes second image data to the second storage space. The first register stores the initial address of one of the first and second storage spaces. The second register stores the initial address of the other of the first and second storage spaces. The control circuit exchanges the values of the first and second register according to a vertical synchronization signal. The display circuit accesses the first or second storage space according to the value of the first register.

Description

Microcontrol circuit, control method and operating system

The present invention relates to a microcontroller circuit, in particular to a microcontroller circuit that can provide image signals.

With the advancement of technology, the types and functions of electronic devices are increasing. Liquid crystal display is a new type of display device. Due to the advantages of thin size, light weight and low radiation, LCD has been widely used in recent years.

The present invention provides a microcontroller circuit, including a memory, an image processing circuit, a first register, a second register, a control circuit and a display circuit. The memory includes a first storage space and a second storage space. The image processing circuit writes a first image data into the first storage space and writes a second image data into the second storage space. The first register stores the starting address of one of the first and second storage spaces. The second register stores the starting address of the other of the first and second storage spaces. The control circuit exchanges the values of the first and second registers according to a vertical synchronization signal. The display circuit reads the image data of the first or second storage space according to the value of the first register.

The present invention further provides an operating system, including a display device and a microcontroller circuit. The display device presents a picture according to an image signal. The microcontroller circuit provides an image signal and includes a memory, an image processing circuit, a first register, a second register, a control circuit and a display circuit. The memory includes a first storage space and a second storage space. The image processing circuit writes a first image data into the first storage space and writes a second image data into the second storage space. The first register stores the starting address of one of the first and second storage spaces. The second register stores the starting address of the other of the first and second storage spaces. When a vertical synchronization signal is enabled and the value of a third register is a specific value, the control circuit exchanges the values of the first and second registers. When the value of the first register corresponds to the first storage space, the display circuit generates an image signal according to the first image data. When the value of the first register corresponds to the second storage space, the display circuit generates an image signal according to the second image data.

The present invention further provides a control method applicable to a microcontroller circuit. The microcontroller circuit includes a memory, a first register and a second register. The memory has a first storage space and a second storage space. The control method of the present invention includes: receiving a vertical synchronization signal; exchanging the values of the first and second registers according to the vertical synchronization signal; when the value of the first register corresponds to the first storage space, generating an image signal according to a first image data of the first storage space; when the value of the first register corresponds to the second storage space, generating an image signal according to a second image data of the second storage space.

The control method of the present invention can be implemented by the microcontroller circuit of the present invention, which is hardware or firmware that can execute specific functions, or can be recorded in a recording medium in the form of program code and implemented in combination with specific hardware. When the program code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a microcontroller circuit for implementing the present invention.

100, 300: Operating system

110, 310: Microcontroller circuit

120, 320: Display device

111, 311: Image processing circuit

112, 312: Memory

113, 313: Display circuit

114, 314: Control circuit

Reg_OnLine, Reg_OffLine, Reg_BufReady, Reg_BufWidth: temporary register

SIG: Image Signal

SA1, SA2: Storage space

VSYNC: vertical synchronization signal

S411~S415, S511~S519: Steps

Figure 1 is a schematic diagram of the operating system of the present invention.

Figure 2 is a schematic diagram of the operation of the operating system in Figure 1.

Figure 3 is another schematic diagram of the operating system of the present invention.

Figure 4 is a schematic diagram of the control method of the present invention.

Figure 5 is another schematic diagram of the control method of the present invention.

In order to make the purpose, features and advantages of the present invention more clearly understandable, the following examples are specifically cited and detailed descriptions are made in conjunction with the attached drawings. This invention specification provides different examples to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each component in the embodiment is for illustrative purposes and is not used to limit the present invention. In addition, the partial repetition of the figure numbers in the embodiment is for the purpose of simplifying the description and does not mean the correlation between different embodiments.

FIG. 1 is a schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 100 includes a microcontroller circuit 110 and a display device 120. The display device 120 displays a picture according to an image signal SIG. The present invention does not limit the type of the display device 120. In a possible embodiment, the display device 120 is a liquid crystal display (LCD).

The microcontroller circuit 110 provides an image signal SIG and includes an image processing circuit 111, a memory 112, a display circuit 113, a control circuit 114, registers Reg_OnLine and Reg_OffLine. The present invention does not limit the type of the microcontroller circuit 110. In a possible embodiment, the microcontroller circuit 110 is a microcontroller unit (MCU).

The memory 112 includes storage spaces SA1 and SA2. The present invention does not limit the amount of storage space. In one possible embodiment, the memory 112 has more storage space. In this embodiment, the storage spaces SA1 and SA2 are discontinuous storage spaces. The present invention does not limit the type of memory 112. In one possible embodiment, the memory 112 is a volatile memory, such as DRAM.

The image processing circuit 111 is used to write image data to the storage spaces SA1 and SA2. In one possible embodiment, the image processing circuit 111 writes a first image data to the storage space SA1 and writes a second image data to the storage space SA2. In this embodiment, the image processing circuit 111 updates the image data of the storage spaces SA1 and SA2 according to the value of the register Ref_OffLine.

For example, when the value of the register Ref_OffLine points to the storage space SA1, the image processing circuit 111 writes a third image data into the storage space SA1 to replace the first image data. In this example, the data amount of the third image data is the same as the data amount of the first image data. In another possible embodiment, the data amount of the third image data is less than the data amount of the first image data. In this example, the image processing circuit 111 uses the third image data to update part of the image data in the storage space SA1. When the value of the register Ref_OffLine points to the storage space SA2, the image processing circuit 111 writes a third image data into the storage space SA2 to replace the second image data. In this example, the data amount of the third image data is the same as the data amount of the second image data. In another possible embodiment, the data volume of the third image data is less than the data volume of the second image data. In this example, the image processing circuit 111 uses the third image data to update part of the image data in the storage space SA2. In other embodiments, the image processing circuit 111 uses a direct memory access (DMA) technology to access the memory 112.

The register Ref_OnLine stores a first access address. The register Ref_OffLine stores a second access address. In a possible embodiment, the first access address is the starting address of one of the storage spaces SA1 and SA2, and the second access address is the starting address of the other of the storage spaces SA1 and SA2. For example, the access address recorded in the register Ref_OnLine is the same as the starting address of the storage space SA1, and the access address recorded in the register Ref_OffLine is the same as the starting address of the storage space SA2.

In one possible embodiment, the register Ref_OffLine is integrated into the image processing circuit 111 or the memory 112. In another possible embodiment, the register Ref_OffLine is independent of the image processing circuit 111 and the memory 112. In other embodiments, the register Ref_OnLine is integrated into the display circuit 113 or the memory 112. In another possible embodiment, the register Ref_OnLine is independent of the display circuit 113 and the memory 112.

The control circuit 114 receives a vertical synchronization signal VSYNC, and exchanges the values stored in the register Ref_OnLine and the register Ref_OffLine according to the vertical synchronization signal VSYNC. For example, when the vertical synchronization signal VSYNC is enabled, the control circuit 114 copies the value stored in the register Ref_OnLine (such as 0x10000) to the register Ref_OffLine, and copies the value originally stored in the register Ref_OffLine (such as 0x20000) to the register Ref_OnLine.

The display circuit 113 reads the storage space SA1 or SA2 according to the value of the register Ref_OnLine. For example, when the value of the register Ref_OnLine points to the storage space SA1, the display circuit 113 generates an image signal SIG according to the image data of the storage space SA1. When the value of the register Ref_OnLine points to the storage space SA2, the display circuit 113 generates an image signal SIG according to the image data of the storage space SA2. In a possible embodiment, the display circuit 113 uses DMA technology to access the memory 112.

FIG. 2 is an operation diagram of the operating system of FIG. 1. At time point T1, the vertical synchronization signal VSYNC is enabled. Therefore, the control circuit 114 exchanges the values of the register Ref_OnLine and the register Ref_OffLine. For example, after the exchange, the value of the register Ref_OnLine corresponds to the starting address 0x10000 of the storage space SA1, and the value of the register Ref_OffLine corresponds to the starting address 0x20000 of the storage space SA2. Therefore, the display circuit 113 starts from the starting address 0x10000 of the storage space SA1 and reads the image data stored in the storage space SA1. The picture presented by the display device 120 corresponds to the image data of the storage space SA1.

In some embodiments, when the display circuit 113 reads the image data stored in the storage space SA1 according to the register Ref_OnLine, the image processing circuit 111 writes new image data starting from the starting address 0x20000 of the storage space SA2 according to the value stored in the register Ref_OffLine (such as 0x20000).

At time point T2, the vertical synchronization signal VSYNC is enabled again. Therefore, the control circuit 114 exchanges the values of the register Ref_OnLine and the register Ref_OffLine. For example, after the exchange, the value of the register Ref_OnLine corresponds to the starting address 0x20000 of the storage space SA2, and the value of the register Ref_OffLine corresponds to the starting address 0x10000 of the storage space SA1. Therefore, the display circuit 113 starts from the starting address 0x20000 of the storage space SA2 and reads the image data stored in the storage space SA2. At this time, the picture presented by the display device 120 corresponds to the image data of the storage space SA2.

In some embodiments, when the display circuit 113 reads the image data stored in the storage space SA2 according to the register Ref_OnLine, the image processing circuit 111 writes new image data starting from the starting address 0x10000 of the storage space SA1 according to the value stored in the register Ref_OffLine (such as 0x10000).

Before the vertical synchronization signal VSYNC is enabled, the image processing circuit 111 updates the image data corresponding to the storage space. Therefore, when the vertical synchronization signal VSYNC is enabled, the image circuit 113 can generate the image signal SIG according to the updated image data. Therefore, the display device 120 presents a correct picture without image tearing.

FIG. 3 is another schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 300 includes a microcontroller circuit 310 and a display device 320. The display device 320 displays the image according to the image signal SIG. Since the characteristics of the display device 320 are the same as those of the display device 120 in FIG. 1, they will not be described in detail.

The microcontroller circuit 310 includes an image processing circuit 311, a memory 312, a display circuit 313, a control circuit 314, registers Reg_OnLine, Reg_OffLine, and Reg_BufReady. Since the characteristics of the image processing circuit 311, the memory 312, the display circuit 313, the control circuit 314, the registers Reg_OnLine and Reg_OffLine are the same as those of the image processing circuit 111, the memory 112, the display circuit 113, the control circuit 114, the registers Reg_OnLine and Reg_OffLine in FIG. 1, they will not be described in detail.

When the value of register Reg_BufReady is equal to a specific value, it means that the image processing circuit 311 has updated the corresponding storage space according to register Reg_OffLine. Therefore, when the vertical synchronization signal VSYNC is enabled, the control circuit 314 exchanges the values of register Ref_OnLine and register Ref_OffLine. In a possible embodiment, after the control circuit 314 completes the exchange of the values of register Ref_OnLine and register Ref_OffLine, the control circuit 314 sets the value of register Reg_BufReady to be not equal to the specific value. At this time, the value of register Reg_BufReady may be 0.

When the value of the register Reg_BufReady is not equal to a specific value and the vertical synchronization signal VSYNC is not enabled, the image processing circuit 311 performs an update operation on the storage space SA1 or SA2 according to the value of the register Ref_OffLine. After completing the update operation, the image processing circuit 311 may set the value of the register Reg_BufReady to be equal to a specific value, such as the value 1.

In some embodiments, when the value of the register Reg_BufReady is not equal to a specific value, the image processing circuit 311 updates the image data of the memory 312 according to the value of the register Ref_OffLine. For example, when the value of the register Ref_OffLine points to the storage space SA1, the image processing circuit 311 writes new image data (or third image data) to the storage space SA1. When the value of the register Ref_OffLine points to the storage space SA2, the image processing circuit 311 writes the third image data to the storage space SA2.

The present invention does not limit the data volume of the third image data. In one possible embodiment, the data volume of the third image data is the same as the data volume of the image data in the storage spaces SA1 and SA2. For example, the storage spaces SA1 and SA2 each store 320*240*4 data. In this example, the data volume of the third image data is equal to 320*240*4. In another possible embodiment, the data volume of the third image data is less than the data volume of the storage spaces SA1 and SA2. In this example, the image processing circuit 311 uses the third image signal to update part of the image data in the storage spaces SA1 and SA2.

In some embodiments, when the value of the register Reg_BufReady is not equal to a specific value, it indicates that the image processing circuit 311 has not yet completed the update operation. At this time, if the vertical synchronization signal VSYNC is enabled, the display circuit 313 reads the image data of the corresponding storage space according to the value of the register Reg_OnLine. For example, assume that the value of the register Reg_OnLine corresponds to the storage space SA1, and the storage space SA1 stores the first image data. In a first period, when the value of the register Reg_BufReady is not equal to the specific value and the vertical synchronization signal VSYNC is enabled, the display circuit 313 generates the image signal SIG according to the first image data of the storage space SA1. At this time, the display device 320 presents a specific picture. Then, in a second period, when the value of the register Reg_BufReady is still not equal to the specific value and the vertical synchronization signal VSYNC is enabled again, the display circuit 313 generates the image signal SIG according to the first image data of the storage space SA1. At this time, the display device 320 presents the same specific picture. Since the display device 320 presents a large number of pictures in one second (may present 120 pictures in one second), even if the same picture is presented, it is not easy for the user to notice.

In addition, after the image processing circuit 311 completes the update operation, the control circuit 314 exchanges the values of the registers Reg_OnLine and Reg_OffLine, thereby ensuring that the storage space read by the display circuit 313 has complete image data. Therefore, the screen displayed by the display device 320 will not have tearing phenomenon.

In some embodiments, the microcontroller circuit 310 further includes a register Reg_BufWidth. The value of the register Reg_BufWidth is related to the resolution and image format of the display device 320. For example, assume that the resolution of the display device 320 is 320*240 and the image format is RGB888 format. In this example, the value stored in the register Reg_BufWidth is 320*240*4.

When the value of the register Reg_BufReady is not equal to the specific value, the image processing circuit 311 writes the new image data to the corresponding storage space according to the value of the register Ref_OffLine. In a possible embodiment, the image processing circuit 311 may use DMA technology to access the memory 312. After the write operation is completed, the value of the register Reg_BufReady is set to a specific value.

The present invention does not limit how to determine whether the write operation has been completed. In one possible embodiment, when the image data is written into the memory cell corresponding to a specific address of the memory 312, it indicates that the write operation has been completed. For example, assume that the value of the register Ref_OffLine is 0x10000 and the value of the register Reg_BufWidth is 0x05000. In this example, the image processing circuit 311 writes new image data starting from the address 0x10000 of the storage space SA1. When the memory cell corresponding to the address 0x14FFF (i.e., address 0x15000-1) of the storage space SA1 has updated the storage data, it indicates that all the image data has been written into the storage space SA1. Therefore, the image processing circuit 311 may set the value of the register Reg_BufReady to a specific value, such as 1.

Figure 4 is a flow chart of the control method of the present invention. The control method of the present invention may exist through program code. When the program code is loaded and executed by a machine, the machine becomes a microcontroller circuit for implementing the present invention. In one possible embodiment, the microcontroller circuit includes a memory, a first register, and a second register. The memory has a first storage space and a second storage space. In some embodiments, the first and second storage spaces store image data.

First, a vertical synchronization signal is received (step S411), and it is determined whether the vertical synchronization signal is enabled (step S412). In one possible embodiment, when the vertical synchronization signal is enabled, the vertical synchronization signal is at a low level. When the vertical synchronization signal is disabled (not enabled), the vertical synchronization signal is at a high level. In another possible embodiment, when the vertical synchronization signal is enabled, the vertical synchronization signal is at a high level. When the vertical synchronization signal is disabled, the vertical synchronization signal is at a low level.

When the vertical synchronization signal is enabled, the values of the first and second registers are exchanged (step S413). In a possible embodiment, the first register stores a first access address, and the second register stores a second access address. In this example, one of the first and second access addresses points to the first storage space, and the other of the first and second access addresses points to the second storage space. For example, the first access address is the starting address of the first storage space, such as 0x10000, and the second access address is the starting address of the second storage space, such as 0x20000. In this example, after step S413, the first access address of the first register is the starting address of the second storage space, i.e. 0x20000, and the second access address of the second register is the starting address of the first storage space, i.e. 0x10000.

When the vertical synchronization signal is not enabled, the values of the first and second registers are maintained (step S414). Assume that the first access address of the first register is equal to the starting address of the first storage space, such as 0x10000, and the second access address of the second register is equal to the starting address of the second storage space, such as 0x20000. After step S414, the first access address of the first register is still equal to the starting address of the first storage space, such as 0x10000, and the second access address of the second register still corresponds to the starting address of the second storage space, such as 0x20000.

According to the value of the first register, an image signal is generated (step S415). In one possible embodiment, when the first access address of the first register points to the first storage space, step S415 reads the image data of the first storage space and generates an image signal according to the image data. In another possible embodiment, when the first access address of the first register points to the second storage space, step S415 reads the image data of the second storage space and generates an image signal according to the image data.

FIG. 5 is another flow chart of the control method of the present invention. First, the values of the first and second registers are set (step S511). In one possible embodiment, the first access address of the first register points to the first storage space, and the second access address of the second register points to the second storage space. In some embodiments, the first access address of the first register is equal to the starting address of the first storage space, and the second access address of the second register is equal to the starting address of the second storage space.

In another possible example, step S511 further sets the value of a format register. In this example, the value of the format register is related to the resolution of a display device and the color format presented by the display device. For example, assuming that the resolution of the display device is 320*240, and the color format presented by the display device is RGB888. In this example, the value of the format register is 320*240*4.

Next, determine whether a vertical synchronization signal is enabled (step S512). In one possible embodiment, when the vertical synchronization signal is at a low level, it indicates that the vertical synchronization signal is enabled. When the vertical synchronization signal is enabled, determine whether the value of a third register is a first value (step S513). In one possible embodiment, the first value (or specific value) is 1.

When the value of the third register is not the first value, the image data of the corresponding storage space (such as the first storage space) is read according to the value of the first register (such as 0x10000) to generate an image signal (step S516). In a possible embodiment, the values of the first and second registers remain unchanged. Then, return to step S512 and wait for the vertical synchronization signal to be enabled again.

When the value of the third register is the first value, it means that the image data of the second storage space is ready. Therefore, the values of the first and second registers are exchanged (step S514). In a possible embodiment, before step S514, the value of the first register is 0x10000, and the value of the second register is 0x20000. After step S514, the value of the first register is 0x20000, and the value of the second register is 0x10000.

Next, the value of the third register is set to the second value (step S515). In a possible embodiment, the second value is 0. Then, according to the value of the first register (such as 0x20000), the image data of the corresponding storage space (such as the second storage space) is read to generate an image signal. Then, return to step S512 and wait for the vertical synchronization signal to be enabled again.

When the vertical synchronization signal is not enabled, determine whether the value of a third register is the second value (step S517). When the value of the third register is not the second value, read the image data of the corresponding storage space (such as the second storage space) according to the value of the first register (such as 0x20000) to generate an image signal (step S516).

When the value of the third register is the second value, an update operation is performed according to the value of the second register (such as 0x10000) (step S518). In a possible embodiment, the update operation is to update the image data of the storage space corresponding to the second register. For example, when the value of the second register points to the first storage space, step S518 updates the complete image data or part of the image data of the first storage space. When the value of the second register points to the second storage space, step S518 updates the complete image data or part of the image data of the second storage space.

Then, the value of the third register is set to the first value (step S519). At this time, the value of the third register may change from the value 0 (the second value) to the value 1 (the first value). Then, according to the value of the first register (such as 0x20000), the image data of the corresponding storage space (such as the second storage space) is read to generate an image signal (step S516). Then, return to step S512 to determine whether the vertical synchronization signal is enabled.

In this embodiment, when the value of the third register is a specific value (such as value 1) and the vertical synchronization signal is enabled, the values of the first and second registers are exchanged. Then, the corresponding image data is read according to the value of the first register after the exchange. In this example, when the value of the third register is not a specific value or the vertical synchronization signal is not enabled, the exchange of the values of the first and second registers is suspended. In a possible embodiment, after the values of the first and second registers are exchanged, the value of the third register is set not to a specific value. At this time, the value of the third register may change from value 1 to value 0.

In other embodiments, when the vertical synchronization signal is not enabled, if the value of the third register is not a specific value (such as a value of 1), the image data in the first or second storage space is updated according to the value of the second register. For example, if the value of the second register is equal to the starting address of the first storage space, the new image data (or the third image data) replaces the complete image data (or the first image data) originally stored in the first storage space, or replaces part of the image data in the first storage space. However, if the value of the second register is equal to the starting address of the second storage space, the new image data (or the third image data) replaces the complete image data (or the second image data) originally stored in the second storage space, or replaces part of the image data in the second storage space. In this example, after writing the new image data to the storage space specified by the second register, the value of the third register is set to a specific value.

In one possible embodiment, the data volume of the new image data is the same as the data volume of the first image data in the first storage space, and is also the same as the data volume of the second image data in the second storage space. For example, the data volume of the first to third image data is 320*240*4. In another possible embodiment, the data volume of the new image data is less than the data volume of the first image data in the first storage space, and is also less than the data volume of the second image data in the second storage space. In this example, the data volume of the first image data in the first storage space is the same as the data volume of the second image data in the second storage space.

It must be understood that when a component or layer is referred to as being "coupled" to another component or layer, it can be directly coupled or connected to the other component or layer, or have other components or layers interposed therebetween. Conversely, if a component or layer is "connected" to other components or layers, there will be no other components or layers interposed therebetween. In addition, enable shall mean changing the state of a Boolean signal. A Boolean signal can be enabled to be high or have a higher voltage, and a Boolean signal can be enabled to be low or have a lower voltage at the discretion of the circuit designer. Similarly, disable shall mean changing the state of a Boolean signal to a voltage level opposite to the enabled state.

The control method of the present invention, or a specific form or part thereof, may exist in the form of program code. The program code may be stored in a physical medium, such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product that is not limited to an external form, wherein when the program code is loaded and executed by a machine, such as a computer, the machine becomes a micro-control circuit for participating in the present invention. The program code may also be transmitted through some transmission media, such as wires or cables, optical fibers, or any transmission type, wherein when the program code is received, loaded and executed by a machine, such as a computer, the machine becomes a micro-control circuit for participating in the present invention. When implemented on a general-purpose processing unit, the code combines with the processing unit to provide a unique device that operates like an application-specific logic circuit.

Unless otherwise defined, all terms (including technical and scientific terms) herein are generally understood by those with ordinary knowledge in the technical field to which the present invention belongs. In addition, unless expressly stated, the definition of a term in a general dictionary should be interpreted as consistent with the meaning in the article in the relevant technical field, and should not be interpreted as an ideal state or overly formal language. Although terms such as "first" and "second" can be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention can be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Operating system

110: Microcontroller circuit

120: Display device

111: Image processing circuit

112: Memory

113: Display circuit

114: Control circuit

Reg_OnLine, Reg_OffLine: registers

SIG: Image Signal

SA1, SA2: Storage space

VSYNC: vertical synchronization signal

Claims (10)

A microcontroller circuit includes: a memory including a first storage space and a second storage space; an image processing circuit that writes a first image data into the first storage space and writes a second image data into the second storage space; a first register that stores the starting address of one of the first and second storage spaces; a second register that stores the starting address of the other of the first and second storage spaces; a control circuit that exchanges the values of the first and second registers according to a vertical synchronization signal; and a display circuit that reads the image data of the first or second storage space according to the value of the first register. The microcontrol circuit of claim 1 further includes: a third register, wherein when the value of the third register is equal to a specific value and the vertical synchronization signal is enabled, the control circuit exchanges the values of the first and second registers. For example, in the microcontroller circuit of claim 2, when the value of the third register is not equal to the specific value and the vertical synchronization signal is not enabled, the image processing circuit performs an update operation on the first or second image data according to the value of the second register. The microcontroller circuit of claim 3, wherein: When the value of the third register is not equal to the specific value and the value of the second register is the same as the starting address of the first storage space, the image processing circuit writes a third image data to the first storage space; when the value of the third register is not equal to the specific value and the value of the second register is the same as the starting address of the second storage space, the image processing circuit writes a third image data to the second storage space. As in the microcontroller circuit of claim 4, the data amounts of the first, second and third image data are the same. A microcontroller circuit as claimed in claim 1, wherein: when the value of the first register corresponds to the starting address of the first storage space, the display circuit reads the first image data; when the value of the first register corresponds to the starting address of the second storage space, the display circuit reads the second image data. A control method is applicable to a microcontroller circuit, the microcontroller circuit includes a memory, a first register and a second register, the memory has a first storage space and a second storage space, the control method includes: receiving a vertical synchronization signal; exchanging the values of the first and second registers according to the vertical synchronization signal; when the value of the first register corresponds to the first storage space, generating an image signal according to a first image data of the first storage space; and when the value of the first register corresponds to the second storage space, generating the image signal according to a second image data of the second storage space. The control method of claim 7 further includes: detecting the value of a third register; when the value of the third register is a specific value and the vertical synchronization signal is enabled, exchanging the values of the first and second registers. The control method of claim 8 further includes: after the values of the first and second registers are exchanged, the value of the third register is set not to be the specific value. An operating system includes: a display device that presents a picture according to an image signal; and a microcontroller circuit that includes: a memory that includes a first storage space and a second storage space; an image processing circuit that writes a first image data into the first storage space and writes a second image data into the second storage space; a first register that stores a starting address of one of the first and second storage spaces; a second register that stores a starting address of the first and second storage spaces; The first and second registers are configured to be a starting address of the other of the two storage spaces; a control circuit that exchanges the values of the first and second registers when a vertical synchronization signal is enabled and the value of a third register is a specific value; and a display circuit that generates the image signal according to the first image data when the value of the first register corresponds to the first storage space, and generates the image signal according to the second image data when the value of the first register corresponds to the second storage space.